Transistor and micro-nano manufacturing method thereof

Abstract

The invention provides a transistor and a micro-nano manufacturing method thereof, and the micro-nano manufacturing method of the transistor comprises the steps: combining photoetching, coating and etching technologies, employing atomic and / or nano-sized particles, and enabling the atomic and / or nano-sized particles to form any one or more of a carrier channel structure, a source electrode, a drain electrode, a grid electrode and a dielectric layer in a gas phase through a bottom-to-top 3D printing technology. Therefore, bottom-to-top printing of a carrier channel structure in a smaller source-drain gap can be realized, the printing is not limited by laser wavelength and the like, and material waste and redundant steps do not exist; and the purity and the nanoscale precision of the carrier channel structure are ensured through the 3D printing technology, so that the final performance of the nano transistor is ensured, and the requirement of the integration level of the device is met.

Description

Technical Field

[0001] The present invention relates to the field of device manufacturing, and in particular to a transistor and a micro-nano manufacturing method thereof. Background Art

[0002] To meet the growing demand for miniaturization and multifunctionality of integrated circuits, semiconductor nanomaterials have become indispensable building blocks, especially in transistor channels. Currently, transistor manufacturing technology to achieve nanoscale and three-dimensionalization mainly relies on top-down lithography methods. Lithography technology relies on large equipment and is expensive. Its minimum line width is limited by the laser wavelength and numerical aperture, and when the minimum line width reaches 50 nanometers, it faces a resolution bottleneck. The lithography method mainly uses a two-dimensional planar stacking design, which results in a large amount of material waste and redundant steps when used for future advanced transistor three-dimensional integrated manufacturing.

[0003] Existing bottom-up approaches enable on-demand, three-dimensional fabrication of transistors, primarily using inks as precursors and utilizing laser-induced or nozzle-directed writing fabrication strategies. However, these approaches inevitably suffer from ligand contamination of liquid precursors, which reduces transistor structural purity. Furthermore, limited by the assembly precision of the printing nozzle or induction source, the minimum linewidth cannot be less than 70 nm. Achieving resolution comparable to photolithography while maintaining material purity and architectural control remains a fundamental challenge. Existing methods typically rely on colloidal nanoparticle assembly in the liquid phase, which is plagued by ligand organic contamination and lacks the sub-10 nm precision achievable with photolithography. Even when semiconductor nanoparticles are fabricated, their arrangement requires nanoscale tools for size confinement to form nanostructures. Such tools can be adapted from physical nozzles used for material confinement or based on field-guided deposition. These physical nozzles lack nanoscale resolution, while laser / beam-based approaches face challenges in scalable manufacturing. Furthermore, after nanoparticle assembly, the persistence of organic stabilizers in the final structure degrades electronic switching performance.

[0004] Therefore, there is a need to provide a better method for manufacturing nanoscale transistors. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a transistor and a micro-nano manufacturing method thereof. Specifically, the present application provides a manufacturing method for constructing a nano-transistor by means of micro-nano printing from bottom to top in the gas phase, so as to solve the problems in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention is obtained by including the following technical solutions.

[0007] The first aspect of the present invention provides a micro-nano manufacturing method for nanotransistors, which combines photolithography, coating and etching techniques, uses atomic and / or nanoscale particles, and uses bottom-up 3D printing technology in the gas phase to form any one or more of a carrier channel structure, a source, a drain, a gate and a dielectric layer.

[0008] In the present application, the particles are selected from one or both of nanoscale and atomic scale.

[0009] In one embodiment, the temperature range of the 3D printing is not limited as long as it allows the existence of particles. Considering the specific cost and processing difficulty, the method of the present application can be carried out at room temperature.

[0010] In the present application, the pressure of the 3D printing is not limited. For example, in one embodiment, the 3D printing is performed under normal pressure, low pressure, or high pressure.

[0011] In one embodiment, the 3D printing to form a carrier channel structure, source, drain, gate or dielectric layer is: based on the action of an electric field, the directional migration of particles in the gas is manipulated so that the particles are stacked from bottom to top to form a carrier channel structure, source, drain, gate or dielectric layer.

[0012] In one embodiment, during 3D printing, the boundaries of the carrier channel structure, source, drain, gate, or dielectric layer are controlled by a self-alignment process.

[0013] In one embodiment, based on 3D printing technology, combined with photolithography, coating and etching technology, by switching the material type of particles, a column structure is formed by segmented printing from bottom to top. The middle of the column structure is a carrier channel structure, and the two ends are respectively a source and a drain.

[0014] In one embodiment, the carrier channel structure is a columnar or standing structure.

[0015] In one embodiment, the carrier channel structure is formed by printing a semiconductor material.

[0016] In one embodiment, the dielectric layer is formed by 3D printing using an insulating material.

[0017] In one embodiment, a conductive material is used to print and form an electrode layer of a source electrode, a drain electrode, or a gate electrode.

[0018] In one embodiment, the particle size is 20 nm or less.

[0019] In one embodiment, the semiconductor material is selected from one or more of indium oxide, zinc oxide, indium zinc oxide, gallium oxide, silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, gallium antimonide, lead sulfide, lead selenide, molybdenum disulfide, cadmium sulfide, cadmium selenide, cadmium telluride, barium titanate, strontium titanate, and CH3NH3PbI3.

[0020] In one embodiment, the particle size of the semiconductor material particles is 20 nm or less.

[0021] In another embodiment, the source, drain, and dielectric layer can be formed by photolithography and etching techniques based on 3D printing. For example, the source, drain, gate, dielectric layer, and carrier channel structure can be partially formed by 3D printing, while the rest can be formed by photolithography, coating, and etching techniques.

[0022] In another embodiment, the conductive material includes one or more of gold, silver, palladium, copper, nickel, titanium, chromium, silicon, germanium, aluminum, gold-silver alloy, nickel-titanium alloy, nickel-silicon alloy, indium oxide, zinc oxide, indium zinc oxide, silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide.

[0023] In yet another embodiment, the insulating material is selected from one or more of aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, silicon nitride, and boron nitride.

[0024] In another embodiment, one of the manufacturing methods comprises:

[0025] Provides a base layer;

[0026] forming a source electrode and a drain electrode on the base layer;

[0027] In the gap between the source and drain, a carrier channel structure is formed from bottom to top by 3D printing to form a bottom-gate transistor. Preferably, the process further includes forming a top-gate structure.

[0028] In a further embodiment, the method further includes forming a top gate dielectric layer and a top gate electrode layer on the bottom gate transistor for sealing the carrier channel structure.

[0029] In another embodiment, the manufacturing method includes:

[0030] Provides a base layer;

[0031] forming a source electrode and a drain electrode on the base layer;

[0032] forming a protective layer based on a photolithography technique to form exposed portions only on the source electrode and the drain electrode;

[0033] At the exposed parts of the source and drain, a bridge-shaped carrier channel structure is formed from bottom to top by 3D printing;

[0034] The protective layer is removed by etching technology. Preferably, the method further includes forming a top gate structure.

[0035] More preferably, the method further includes forming a top gate dielectric layer and a top gate electrode layer for closing the carrier channel structure.

[0036] In another embodiment, the manufacturing method comprises:

[0037] Provides a base layer;

[0038] forming a drain electrode on the base layer;

[0039] forming a pillar-type nano-sized carrier channel structure on the drain electrode from bottom to top by 3D printing;

[0040] forming a first preliminary dielectric layer for completely covering and sealing the carrier channel structure;

[0041] further forming a preliminary gate covering the carrier channel structure on the first preliminary dielectric layer;

[0042] forming a second preliminary dielectric layer completely covering the preliminary gate layer to isolate the gate and the source;

[0043] The second preliminary dielectric layer, the preliminary gate layer, and the first preliminary dielectric layer located at the top of the carrier channel structure are removed by self-alignment and directionally etching using a photolithography technique to expose the top of the carrier channel structure;

[0044] further forming a second dielectric layer for isolating the gate and the source;

[0045] Directional etching is performed to remove the second dielectric layer located near the top of the carrier channel structure to facilitate the formation of the source electrode;

[0046] A source electrode is formed at the top of the exposed carrier channel structure.

[0047] According to any of the above-mentioned micro-nano manufacturing methods, the photolithography is one or more of extreme ultraviolet lithography, maskless laser direct writing, stepper lithography and electron beam lithography.

[0048] According to any of the above-mentioned micro-nano manufacturing methods, the photoresist used in the photolithography is one or more selected from AZ5214, S1818, S1805, Lor5A and UV135G.

[0049] According to any of the above-mentioned micro-nano manufacturing methods, the base layer includes a silicon wafer substrate, and a single side of the silicon wafer substrate is polished and coated with a bottom gate dielectric layer.

[0050] According to any of the above-mentioned micro-nano manufacturing methods, a top gate dielectric layer and a top gate electrode layer are formed by photolithography and coating.

[0051] A second aspect of the present invention further provides a fin field-effect nanotransistor, comprising:

[0052] basal layer;

[0053] A metal pattern layer including a source electrode and a drain electrode: formed on the base layer, with a gap between the source electrode and the drain electrode;

[0054] Carrier channel structure: formed from the bottom up from the gap to the substrate, and connected to the source and drain;

[0055] Preferably, the top gate structure is further included. More preferably, the top gate structure includes a top gate dielectric layer and a top gate electrode layer for enclosing the carrier channel structure.

[0056] A third aspect of the present invention provides a field-effect nano-transistor with a bridge-type carrier channel structure, comprising:

[0057] basal layer;

[0058] Source and drain: formed on the base layer with a gap between them;

[0059] A bridge-shaped carrier channel structure is provided across the gap between the source and drain electrodes, with its ends formed on the source and drain electrodes, respectively. Preferably, it also includes a top gate structure. More preferably, the top gate structure includes a top gate dielectric layer and a top gate electrode layer: the top gate dielectric layer is formed on the metal pattern layer and surrounds the bridge-shaped carrier channel structure; the top gate electrode layer is formed on the top gate dielectric layer.

[0060] A fourth aspect of the present invention further provides a field-effect nano-transistor with a pillar-type carrier channel structure, comprising:

[0061] basal layer;

[0062] Drain: formed on the substrate layer;

[0063] Pillar carrier channel structure: formed on the drain, in a pillar-like shape;

[0064] The first dielectric layer is formed between the source and drain electrodes and is used to close the pillar-type carrier channel structure;

[0065] Source: formed at the top of the pillar-type carrier channel structure;

[0066] Gate: The gate is formed on the first dielectric layer and surrounds the columnar portion of the first dielectric layer;

[0067] Second dielectric layer: The second dielectric layer is formed on the gate electrode to isolate the gate electrode from the source electrode. Preferably, the second dielectric layer surrounds the columnar portion of the first dielectric layer.

[0068] In this application, semiconductor particles in the gas phase are used as the printed building blocks of the channel in printing a three-dimensional carrier channel structure. Through the printing method described above, not only can the transistor channel be constructed in the gas phase at room temperature and atmospheric pressure, but the semiconductor carrier channel can also be self-aligned from bottom to top based on the channel pattern layer.

[0069] The beneficial effects of the technical solution of the present invention are:

[0070] This invention provides a different approach to transistor construction than existing techniques. It uses semiconductor particles to form a carrier channel structure in a vapor phase through bottom-up 3D printing, thereby creating a nanotransistor. This method enables bottom-up printing of carrier channel structures within smaller source-drain gaps, without being constrained by laser wavelength or other factors, and without material waste or redundant steps. Furthermore, 3D printing ensures the purity and nanometer-level precision of the carrier channel structure, thereby ensuring the ultimate performance of the nanotransistor and meeting device integration requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figures 1 to 4 It shows a flow chart of a specific method in the technical solution of the present invention.

[0072] Figure 5 It is shown that the present invention forms Figure 3 The carrier channel structure shown corresponds to the photoresist aligned with the passivation layer.

[0073] Figure 6 Shown is a schematic flow chart of a method for manufacturing a transistor according to the present invention.

[0074] Figure 7 A schematic diagram showing the structure of the wafer layer and the bottom gate dielectric layer for forming a bridge transistor.

[0075] Figure 8 Shown is a schematic structural diagram of a metal pattern layer for forming a bridge transistor.

[0076] Figure 9 A schematic diagram showing the structure of a photoresist aligned with a passivation layer for forming a bridge transistor.

[0077] Figure 10 A schematic diagram showing a carrier channel structure forming a bridge transistor.

[0078] Figure 11Shown is a schematic diagram of a structure forming a bridge transistor.

[0079] Figure 12 Shown is a schematic diagram of the carrier channel structure of another type of bridge transistor.

[0080] Figure 13 Shown is a structural diagram of another bridge-connected transistor.

[0081] Figures 14 to 22 Schematic diagram showing the construction process of a standing transistor.

[0082] Figure 22 Shown is a schematic diagram of the structure of one type of standing transistor.

[0083] Figure 23 Shown is a schematic diagram of the metal pattern layer formed in Example 1.

[0084] Figure 24 Shown is a schematic structural diagram of the carrier channel in Example 1.

[0085] Figure 25 Shown is a TEM image of the top gate structure in Example 2.

[0086] Figure 26 Shown is the electrical test result of the transfer characteristic curve of the transistor in Example 1.

[0087] Figure 27 Shown is the electrical test result of the transfer characteristic curve of the transistor in Example 2.

[0088] Figure 28 A diagram showing the dimensions and results of one of the standing printed carrier channel structures constructed using the fifth method.

[0089] Figure 29 A diagram showing the effect of one of the bridge-type carrier channel structures constructed in the fourth method.

[0090] Figure 30 A schematic diagram showing the structure of another standing transistor constructed in the fifth way.

[0091] Description of component numbers in the accompanying drawings

[0092]

[0093] DETAILED DESCRIPTION

[0094] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0095] Before further describing the specific embodiments of the present invention, it should be understood that the scope of the present invention is not limited to the specific embodiments described below. It should also be understood that the terminology used in the examples is intended to describe specific embodiments and is not intended to limit the scope of the present invention. The experimental procedures in the following examples, where specific conditions are not specified, were generally performed under conventional conditions or according to the conditions recommended by the respective manufacturers.

[0096] When the embodiments provide numerical ranges, it should be understood that, unless otherwise specified in the present invention, both endpoints of each numerical range and any numerical value between the two endpoints may be selected. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those generally understood by those skilled in the art. In addition to the specific methods, equipment, and materials used in the embodiments, according to the understanding of the prior art by those skilled in the art and the description of the present invention, any methods, equipment, and materials of the prior art similar or equivalent to the methods, equipment, and materials described in the embodiments of the present invention may also be used to implement the present invention.

[0097] In this invention, the applicant utilizes "atomic and / or nanometer-sized particles to form a three-dimensional carrier channel structure via bottom-up 3D printing in the gas phase," thereby achieving bottom-up printing of carrier channel structures within smaller source-drain gaps. This approach is not limited by laser wavelength, and eliminates material waste and unnecessary steps. Furthermore, the 3D printing technology ensures the purity and nanometer-level precision of the carrier channel structure, thereby guaranteeing the ultimate performance of the nanotransistor and meeting device integration requirements. Other structures within the transistor can also be formed using photolithography, coating, and etching techniques.

[0098] With the help of this technical concept, a variety of transistors can be printed, such as planar field-effect transistors (Planar FETs), fin field-effect transistors (FinFETs) or all-around gate field-effect transistors (GAAFETs).

[0099] Furthermore, similar to the above technical concept, a source electrode, a drain electrode, or a gate electrode is formed based on 3D printing technology. For example, atomic and / or nano-sized particles are used to form a source electrode, a drain electrode, or a gate electrode through bottom-up 3D printing technology in the gas phase. In this way, the source electrode, a drain electrode, or a gate electrode can be directly formed based on 3D printing technology, without being limited to formation based on photolithography and etching technology in the pattern layer. At this time, a conductive material corresponding to the source electrode, drain electrode, or gate electrode is used for printing, and one or two of conductive nanoparticles and conductive atomic particles are further used for printing. Furthermore, the conductive particles are in a non-aggregated state. At the same time, conductive nanoparticles of a variety of materials can also be used to form a layered source electrode, drain electrode, or gate electrode.

[0100] Furthermore, similar to the above technical concept, a dielectric layer can be formed using insulating materials based on 3D printing technology. For example, corresponding insulating material nanoparticles or atomic-scale particles can be directly used and formed in the gas phase through 3D printing technology. If the corresponding particles are unavailable, a single substance can be first used to form a structure in the gas phase through 3D printing technology, and then an oxidation treatment can be performed to form a dielectric layer with the corresponding structure. Particles formed from insulating materials can only be controlled by an electric field if they carry an electric charge.

[0101] Furthermore, in this application, the raw materials for 3D printing are nanometer-scale and smaller particles of the corresponding materials, which are formed by spark discharge, or by other methods such as plasma or electrospray technology.

[0102] There is no particular limitation on the type, category, or chemical substance of the materials of each transistor structure in this application, as long as they are materials used or potentially used in the prior art.

[0103] For example, the semiconductor material is selected from one or more of indium oxide, zinc oxide, indium zinc oxide, gallium oxide, silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, gallium antimonide, lead sulfide, lead selenide, molybdenum disulfide, cadmium sulfide, cadmium selenide, cadmium telluride, barium titanate, strontium titanate, and CH3NH3PbI3.

[0104] For another example, the source, drain, and gate electrodes can be made of any conductive material, including metal materials and semiconductor materials. For example, the conductive material includes one or more of gold, silver, palladium, copper, nickel, titanium, chromium, silicon, germanium, aluminum, gold-silver alloy, nickel-titanium alloy, nickel-silicon alloy, indium oxide, zinc oxide, indium zinc oxide, silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide.

[0105] For another example, the dielectric layer may be made of an insulating material, such as one or more selected from aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, silicon nitride, and boron nitride.

[0106] The implementation scheme of the above technical concept in this application can be found in Figure 6 Schematic diagram of the process, which can integrate spark discharge particle formation and 3D printing technology, and then one or more of a carrier channel structure, a source, a drain, a gate and a dielectric layer can be formed on the substrate layer based on the device or process concept.

[0107] Furthermore, based on the above concept, the present invention further provides a technical solution for printing transistors by switching between different printing particles based on 3D printing technology, combined with photolithography, coating, and etching techniques. This solution is not only efficient and convenient, but also has high purity and precision, and a good degree of integration.

[0108] Ⅰ. Regarding particles used for printing to form carrier channel structures, particles used for printing to form source electrodes, particles used for printing to form drain electrodes, particles used for printing to form gate electrodes, and particles used for printing to form dielectric layers.

[0109] In this application, the particles used to print the carrier channel structure, the particles used to form the source and drain electrodes, the particles used to form the gate, and the particles used to form the dielectric layer are all raw materials for 3D printing. Generally speaking, they only need to meet the material type and semiconductor purity requirements, or as in this application, further meet the requirement of a particle size of 20nm or less. The preparation method and implementation method are not limited. For example, they can be obtained through spark discharge technology, plasma technology, and electrospray technology. The particles can be nanometer-sized or atomic-sized, such as atomic.

[0110] In one specific implementation, an oscillating discharge can be used to first sublimate and then desublimate the electrode material. This method achieves particles with controllable composition by controlling circuit parameters and electrode materials. By controlling circuit parameters, gas velocity, and particle residence time, semiconductor particles with controllable size and high uniformity are achieved, as well as particles for printing to form source electrodes, particles for printing to form drain electrodes, particles for printing to form dielectric layers, or particles for printing to form dielectric layer precursors (e.g., by first printing and forming the precursor and then further oxidizing it to form the dielectric layer).

[0111] Specifically, the preparation method of the semiconductor particles includes: forming two electrodes from the matrix material used to form the semiconductor particles, one end of the two electrodes are connected to the same resonant circuit, and the other ends of the two electrodes are arranged opposite to each other to form a gap. In a carrier gas atmosphere, the carrier gas in the gap between the two electrodes is broken down to generate an oscillating discharge current, and the matrix material in the electrodes is converted from gas to solid into the semiconductor particles.

[0112] Specifically, the preparation method for printing particles to form a source or drain includes: forming two electrodes from a matrix material for forming conductive material particles, one end of each of the two electrodes is connected to the same resonant circuit, and the other ends of the two electrodes are arranged opposite to each other to form a gap. In a carrier gas atmosphere, the carrier gas in the gap between the two electrodes is broken down to generate an oscillating discharge current, and the matrix material in the electrodes is converted from gas to solid into the conductive material particles.

[0113] Specifically, the preparation method of particles used to print and form a gate electrode layer includes: forming two electrodes from a matrix material used to form conductive material particles, one end of each of the two electrodes is connected to the same resonant circuit, and the other ends of the two electrodes are arranged opposite to each other to form a gap. In a carrier gas atmosphere, the carrier gas in the gap between the two electrodes is broken down to generate an oscillating discharge current, and the matrix material in the electrodes is converted from gas to solid into the conductive material particles.

[0114] Specifically, the preparation method of particles for printing to form a dielectric layer includes: forming two electrodes from a matrix material for forming corresponding insulating material particles, one end of each of the two electrodes is connected to the same resonant circuit, and the other ends of the two electrodes are arranged opposite to each other to form a gap. In a carrier gas atmosphere, the carrier gas in the gap between the two electrodes is broken down to generate an oscillating discharge current, and the matrix material in the electrodes is converted from gas to solid into the particles for printing to form the dielectric layer.

[0115] In the implementation of the present application, the selection of the matrix material for forming the particles can be made according to the specific circumstances. In the implementation of the present application, the selection of the matrix material for forming the semiconductor particles, that is, the electrode, can be made according to the specific circumstances. For example, when forming indium oxide, zinc oxide, and indium zinc oxide particles, metal rods and plates of indium and zinc can be used as electrodes, and a carrier gas containing oxygen can be used; or, rods and plates of indium oxide and zinc oxide can be directly used as electrodes. For example, when forming silicon and germanium particles, silicon or germanium rods or wafers containing these elements can be selected as electrode materials. For example, when forming gallium arsenide, gallium nitride, and silicon carbide particles, wafer blocks containing these elements can be selected.

[0116] In one specific embodiment, the gas-solid conversion process involves the sublimation of the matrix material and the completion of gas-phase mixing, followed by the condensation of the mixed vapor into the particles. An oscillating discharge causes the matrix material in the two electrodes to alternately sublime. During the discharge, the shock wave generated by the rapid expansion of the gas creates a low-pressure region in the gap between the two electrodes. The sublimated semiconductor vapor is then drawn in and uniformly mixed in the gas phase. The resulting mixed material vapor is cooled by the carrier gas and instantly condenses into particles of a corresponding mixing ratio, which are then transported to any desired location along with the carrier gas. In this application, the carrier gas is one or more of nitrogen, an inert gas, oxygen, and hydrogen.

[0117] Specifically, the semiconductor particles are selected from one or more of indium oxide, zinc oxide, indium zinc oxide, silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide.

[0118] Specifically, the above-mentioned semiconductor particles can be realized using the corresponding processes and parameters shown in Table 1 below.

[0119] Table 1

[0120]

[0121] As shown in Table 1, in the present application, when the particles are prepared, the carrier gas speed is 1 to 20 L / min, such as 5 L / min, 10 L / min, 15 L / min or 20 L / min.

[0122] As shown in Table 1, in the present application, the particles have a breakdown voltage of 0.1 to 10 kV during preparation, such as 0.1 kV, 1 kV, 1.5 kV, 2 kV, 2.5 kV, 3 kV, 3.5 kV, 4 kV, 4.5 kV, 5 kV, 5.5 kV, 6 kV, 6.5 kV, 7 kV, 7.5 kV, 8 kV, 8.5 kV, 9 kV, 9.5 kV or 10 kV.

[0123] As shown in Table 1, in the present application, the particles may be prepared at a frequency of 2 to 1000 Hz, such as 5 Hz, 10 Hz, 20 Hz, 30 Hz, 40 Hz, 50 Hz, 60 Hz, 70 Hz, 80 Hz, 90 Hz, 100 Hz, 110 Hz, 120 Hz, 130 Hz, 140 Hz, 150 Hz, 160 Hz, 170 Hz, 180 Hz, 190 Hz, 200 Hz, 220 Hz, 25 ...260 Hz, 270 Hz, 280 Hz, 290 Hz, 300 Hz, 310 Hz, 320 Hz, 330 Hz, 340 Hz, 350 Hz, 360 Hz, 370 Hz, 380 Hz, 390 Hz, 400 Hz, 410 Hz, 420 Hz, 430 Hz, 440 Hz, 450 Hz, 460 Hz, 470 Hz, 480 Hz, 490 Hz, 500 Hz, 510 Hz, 520 Hz, 530 Hz, 540 Hz, 550 Hz, 560 Hz, 570 Hz, 580 Hz, 590 Hz, 600 0Hz, 190Hz, 200Hz, 210Hz, 220Hz, 230Hz, 240Hz, 250Hz, 260Hz, 270Hz, 280Hz, 290Hz, 300Hz, 310Hz, 320Hz, 330Hz, 340Hz, 350H z, 360Hz, 370Hz, 380Hz, 390Hz, 400Hz, 450Hz, 500Hz, 550Hz, 600Hz, 650Hz, 700Hz, 750Hz, 800Hz, 850Hz, 900Hz, 950Hz or 1000Hz.

[0124] As shown in Table 1, in the present application, the particles have a capacitance of 0.1 to 10 nF during preparation, such as 1 nF, 2 nF, 3 nF, 4 nF, 5 nF, 6 nF, 7 nF, 8 nF, 9 nF or 10 nF.

[0125] The specific preparation parameters of the semiconductor particles used in the examples of this application are shown in Table 2 below.

[0126] Table 2

[0127]

[0128] Carrier gas type: Indium oxide, zinc oxide, and indium zinc oxide can use inert gas or inert / oxygen mixed gas; silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide can use hydrogen or inert gas.

[0129] Specifically, the particle size of the particles used for 3D printing is 20 nm or less, preferably 10 nm or less, such as 1 to 10 nm. In a more preferred embodiment, the particle size of the particles used for 3D printing is 3 to 7 nm, such as 3 nm, 4 nm, 5 nm, 6 nm, or 7 nm.

[0130] II. Regarding the formation of carrier channel structure, source or drain, gate, and dielectric layer using 3D printing technology.

[0131] In this application, the 3D printing technology used to form a carrier channel structure includes: manipulating the directional migration of semiconductor particles in a gas based on an electric field, causing the semiconductor particles to stack at corresponding locations to form the desired micro-nanostructure. The corresponding locations can form a pillar-like carrier channel structure in the gap between the source and drain electrodes, at the top surface of the source and drain electrodes, or directly on the drain electrode layer. Alternatively, by switching the material type of the particles, a pillar structure can be formed by segmented printing from bottom to top, with the carrier channel structure in the middle and the source and drain electrodes at either end.

[0132] In this application, forming a source electrode or a source, drain electrode, or gate electrode layer from bottom to top using 3D printing technology involves manipulating the directional migration of particles of corresponding materials in a gas based on an electric field, causing the particles to stack from bottom to top to form the source, drain, or gate electrode layer. Conductive material particles are used herein.

[0133] In this application, forming the dielectric layer by 3D printing technology includes: controlling the directional migration of particles of corresponding materials in the gas based on the action of an electric field, so that the particles are stacked from bottom to top to form the dielectric layer. Insulating material particles are used here.

[0134] Specifically, the 3D printing can be performed at room temperature and normal pressure. It can also be performed at 20 to 60°C, or at -20 to 20°C, depending on actual needs. It can also be performed at higher or lower pressures than atmospheric pressure.

[0135] Specifically, the particle size is 20 nm or less, preferably 10 nm or less, such as 1 to 10 nm. In a more preferred embodiment, the particle size is 3 to 7 nm, such as 3 nm, 4 nm, 5 nm, 6 nm, or 7 nm.

[0136] Specifically, during 3D printing, the electric field strength is 200-4000V / cm, and the printing time is 5-60 minutes. During the actual 3D printing process, the printed particles move along the electric field lines. The direction of the electric field lines depends on the polarity of the particles used for printing. For example, when printing with positively charged particles, the electric field lines must be directed toward the substrate.

[0137] In a specific embodiment of 3D printing, the electric field strength can be 200V / cm, 300V / cm, 400V / cm, 500V / cm, 600V / cm, 700V / cm, 800V / cm, 900V / cm, 1000V / cm, 1100V / cm, 1200V / cm, 1300V / cm, 1400V / cm, 1500V / cm, 1600V / cm, 1700V / cm, 1800V / cm, 1900V / cm, 2000V / cm, 2100V / cm, 2200V / cm, 2300V / cm, 2400V / cm, 2500V / cm, 2600V / cm, 2700V / cm, 2800V / cm, 2900V / cm, 3000V / c m, 3100V / cm, 3200V / cm, 3300V / cm, 3400V / cm, 3500V / cm, 3600V / cm, 3700V / cm, 3800V / cm, 3900V / cm or 4000V / cm.

[0138] In a specific embodiment of 3D printing, the printing time can be 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min or 60 min.

[0139] In a specific embodiment of 3D printing, the three-dimensional morphology of the channel structure is one or more selected from fins, pillars and lines.

[0140] In 3D printing, the morphology and size of the carrier channel structure, source, drain, gate and dielectric layer can be controlled by the size of the particles, the electric field strength, the printing time and the self-alignment process.

[0141] In this application, the self-alignment process during 3D printing is to automatically determine the relative positions of subsequent structures through a single key step (such as photolithography or etching), specifically forming a photoresist alignment passivation layer, which is removed after printing is completed.

[0142] Furthermore, the minimum line width of 3D printed semiconductor materials can be as low as 26nm or even lower.

[0143] Furthermore, the minimum line width of 3D printed metal materials can be as low as 14nm, or even lower.

[0144] III. One type of nano-transistor and its construction: a FinFET transistor, or fin field-effect transistor.

[0145] One embodiment of the present invention provides a Figures 1 to 3The method for preparing the nano-transistor shown is a bottom-gate controlled transistor, and mainly includes the following steps:

[0146] S11: Provide a base layer.

[0147] like Figure 1 As shown, the base layer is a wafer 1 , and a bottom gate dielectric layer 2 is formed on a single side of the wafer 1 by polishing or is further plated thereon after polishing.

[0148] In one embodiment, the material of the bottom gate dielectric layer 2 may be any one or more of aluminum oxide, hafnium oxide, titanium oxide, silicon nitride, and silicon oxide.

[0149] The thickness of the wafer can be set according to the needs of the actual transistor device. The wafer can be ultrasonically cleaned and dried.

[0150] In a more specific embodiment, the bottom gate dielectric layer 2 is a silicon oxide layer. Specifically, oxygen plasma can be used to bombard the silicon oxide surface to remove organic matter and change the surface roughness, which is conducive to complete and uniform coating of the photoresist.

[0151] S12: Form the source and drain, refer to Figure 2 .

[0152] A pattern layer for the source and drain electrodes is defined on the substrate layer by photolithography, and then plated and stripped to form a metal pattern layer 3; a gap 31 is formed between the source and drain electrodes. Alternatively, the source and drain electrodes are formed by 3D printing.

[0153] The bottom gate dielectric layer 2 is exposed in the gap 31 .

[0154] Among them, the gap 31 can be set according to the needs of the actual transistor device. Preferably, the gap between the source and the drain is 20 to 1000 nm. Since in the prior art, the smaller the gap, the more difficult it is to accurately control the formation of the channel structure or it cannot be achieved at a low cost; the micro-nano 3D printing method in this application can quickly and accurately realize the realization of the channel structure with a gap of 20 to 200 nm. More preferably, the gap is 20 to 150 nm. In a preferred embodiment, the gap in the metal pattern layer is 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm.

[0155] The pattern in the metal pattern layer can be an array periodic pattern or other arbitrary pattern. In a specific embodiment, the pattern feature size is 50nm to 10μm, and the array pitch is 50nm to 100μm. Specifically, the pattern feature size can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm or 10μm. As specifically, the array pitch can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm or 100μm.

[0156] In one embodiment of forming the metal pattern layer, the photolithography is one or more of extreme ultraviolet lithography, maskless laser writing (MLA), stepper lithography, and electron beam lithography.

[0157] In an embodiment of forming a metal pattern layer, the photoresist used in the photolithography is one or more selected from AZ5214, S1818, S1805, Lor5A and UV135G.

[0158] S13: A carrier channel structure 4 is formed from bottom to top by 3D printing to form a bottom-gate transistor. Figure 3 .

[0159] Specifically, a carrier channel structure is formed from bottom to top at the gap 31 of the metal pattern layer by 3D printing to form a bottom-gate transistor.

[0160] Specifically, the carrier channel structure 4 is formed by stacking and printing from bottom to top starting from the upper surface of the exposed bottom gate dielectric layer.

[0161] Specifically, the 3D printing is: based on the effect of the electric field, the directional migration of semiconductor particles in the gas is controlled, so that the semiconductor particles are stacked from bottom to top in the gap to form a carrier channel structure.

[0162] In one embodiment, the 3D printing boundary area can be defined by self-alignment technology. For example, a carrier channel structure protruding from the base layer is formed. In a more specific embodiment, in Figure 2 On the structure shown, a photoresist is further formed by photolithography to align the passivation layer, and the photoresist is aligned to the passivation layer to make the carrier channel only fill between the source and drain electrodes or further partially form on the source and drain metal layer after filling, but not form in other places. In a more specific embodiment, the following can be formed: Figure 5 The photoresist is aligned with the passivation layer structure so that the carrier channel structure can be formed at a specific location.

[0163] In a specific embodiment of the present application, the schematic diagram of forming a carrier channel is as follows: Figure 3 As shown in 4.

[0164] Furthermore, a top-gate transistor formed based on the above-mentioned bottom-gate transistor is provided, which specifically further includes the following steps.

[0165] S14: Further forming the top gate structure, refer to Figure 4 .

[0166] exist Figure 3 On this basis, a top gate dielectric layer 5 and a top gate electrode layer 6 are further formed.

[0167] The top gate dielectric layer 5 and the top gate electrode layer 6 can be formed by various processes or technical means, such as atomic layer deposition, magnetron sputtering, electron beam evaporation, and 3D printing.

[0168] The material of the top gate dielectric layer 5 can be any one or more of aluminum oxide, hafnium oxide, titanium oxide, silicon nitride, and silicon oxide. The dielectric layers in this application can all be made of the materials described herein.

[0169] The top gate dielectric layer 5 has a thickness of 1 to 200 nm. For example, the thickness may be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm.

[0170] The material of the top gate electrode layer 6 can be any one or more of gold, silver, copper, nickel, titanium, chromium, silicon, germanium, and aluminum. It can be a multi-layer metal layer, such as forming a titanium layer first and then a gold layer.

[0171] The thickness of the top gate electrode layer 6 is 1 to 200 nm.

[0172] The above descriptions concerning the materials and thicknesses of the various structures are applicable not only to FinFETs, but also to transistors with bridge-type carrier channel structures and transistors with pillar-type carrier channel structures.

[0173] IV. Another nano-transistor and its construction: This is a transistor with a bridge-type carrier channel structure.

[0174] The present invention provides another nano-transistor and a method for manufacturing the same, which mainly includes the following steps:

[0175] S21: Provide a base layer, such as Figure 7 The details are the same as S11.

[0176] S22: forming a source electrode and a drain electrode on the base layer, such as Figure 8 For details, please refer to S12.

[0177] S23: Forming a bridge-shaped carrier channel structure 4 from bottom to top through 3D printing to form a bottom-gate transistor.

[0178] Specifically, a protective layer is formed based on photolithography technology to form exposed areas only on the source and drain electrodes. At the exposed areas of the source and drain electrodes, a bridge-shaped carrier channel structure is formed from bottom to top by 3D printing to form a bottom-gate transistor. Figure 9 3D printing is performed from bottom to top at 71 and 72.

[0179] Specifically, self-alignment can be performed in combination with photolithography technology.

[0180] Specifically, the 3D printing is: based on the effect of the electric field, the directional migration of semiconductor particles in the gas is controlled, so that the semiconductor particles are stacked from bottom to top in the gap formed by the photoresist alignment passivation layer 7 on the upper surface of the source and drain to form a carrier channel structure.

[0181] In one embodiment, the Figure 8 On the structure shown, a photoresist alignment passivation layer 7 is further formed by photolithography. The photoresist alignment passivation layer 7 only forms gaps on the source and drain electrodes, respectively. The gaps expose the upper surfaces of the source and drain electrodes, and the gap between the source and drain electrodes is covered by the photoresist alignment passivation layer. As a result, the carrier channels formed by 3D printing are formed from bottom to top at 71 and 72 at the same time and gradually connected to form a bridge shape. In a more specific embodiment, the following can be formed: Figure 9 The photoresist is aligned with the passivation layer structure so that the carrier channel structure can be formed at a specific location.

[0182] In a specific embodiment of the present application, the schematic diagram of the formed carrier channel is as follows: Figure 10As shown in 4. Figure 6 The method flow shown in the figure is to print for 1 hour under the conditions of 1.5kV, 1nF; 380Hz+500V, and the indium oxide carrier channel formed is as follows Figure 29 shown.

[0183] Furthermore, a top-gate transistor formed based on the above-mentioned bottom-gate transistor is provided, which specifically further includes the following steps.

[0184] S24: Further forming a top gate structure, refer to Figure 11 .

[0185] exist Figure 10 On the basis of Figure 11 A top gate dielectric layer 5 and a top gate electrode layer 6 are shown.

[0186] The top gate dielectric layer 5 and the top gate electrode layer 6 can be formed by various processes or technical means, such as atomic layer deposition, magnetron sputtering, electron beam evaporation, and 3D printing.

[0187] In one embodiment of this process, Figure 11 The top gate dielectric layer 5 shown not only fills the gap between the source and drain, but also completely surrounds the carrier channel; the top gate electrode layer 6 is formed on the top gate dielectric layer 5 .

[0188] In another embodiment of the process, Figure 12 and Figure 13 The ring gate dielectric layer and the electrode layer are constructed as shown. Figure 12 As shown, the ring gate dielectric layer completely surrounds the carrier channel 4 and also fills the gap between the source and the drain. The difference is that it forms a ring structure or a bridge portion, and a gap 51 is formed under the bridge portion; further forming a top gate dielectric layer 6, which can be specifically as shown in FIG. Figure 13 As shown, the gap 51 may be filled, or the top gate dielectric bridge portion may be further surrounded.

[0189] V. Another nano-transistor and its construction: This is a standing transistor.

[0190] The present application also provides another method for preparing a nano-transistor, comprising:

[0191] S31: Provide a base layer. Refer to S11.

[0192] S32: forming a drain electrode or a drain electrode array on the base layer, such as Figure 1432. For example, the drain electrode layer may be formed by a metal coating method such as magnetron sputtering, electron beam evaporation, or 3D printing. Specifically, the drain electrode layer may have a size of 10-1000 nm. More specifically, the drain electrode may have a size of 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, or 1000 nm.

[0193] S33: forming a pillar-type nano-sized carrier channel structure or a columnar nano-sized carrier channel structure 4 from bottom to top on the drain electrode by 3D printing. Figure 14 shown.

[0194] Specifically, the carrier channel structure 4 only covers a portion of the drain layer, but not the entire drain layer, thereby forming an array of pillar carrier channel structures.

[0195] Specifically, the size of the carrier channel structure 4 can be controlled by 3D printing, and it can be a columnar structure as shown in the figure, distributed in an array, such as Figure 28 As shown. Its size can be 26 to 1000 nm. More specifically, its size can be 30 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm or 1000 nm. Figure 28 As shown, its line width is 26nm.

[0196] S34: further forming a first preliminary dielectric layer 8 that completely covers and closes the carrier channel structure; further forming a preliminary gate layer 9 that covers the carrier channel structure on the first preliminary dielectric layer. Figure 15 shown.

[0197] Specifically, the materials for forming the first preliminary dielectric layer 8 and the preliminary gate layer 9 are the same as those for forming the FinFET transistor described above. Specific formation techniques include electroplating, atomic layer deposition, magnetron sputtering, electron beam evaporation, and other coating methods, or 3D printing technology can be used.

[0198] Specifically, the thickness of the first preliminary dielectric layer 8 is 1 to 1000 nm, such as 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm or 1000 nm.

[0199] Specifically, the thickness of the preliminary gate layer 9 is 1-1000 nm, such as 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm or 1000 nm.

[0200] Specifically, the first preliminary dielectric layer 8 forms a complete covering layer, completely covering the pillar-type carrier channel structure, and the drain is not exposed.

[0201] Specifically, at the edge of the preliminary gate layer 9, the first preliminary dielectric layer 8 may be exposed. Figure 15 shown.

[0202] In the following, the second preliminary dielectric layer, the preliminary gate layer and the first preliminary dielectric layer located at the top of the carrier channel structure are removed in sequence by self-alignment through photolithography technology and qualitative etching to expose the top of the carrier channel structure.

[0203] S35: Further forming a second preliminary dielectric layer 10 covering the preliminary gate layer 9 and the exposed portion of the first preliminary dielectric layer 8; then forming a photoresist alignment passivation layer by photolithography or etching technology, which covers the second preliminary dielectric layer 10 and exposes the second preliminary dielectric layer at the carrier channel structure 4. Figure 16 shown.

[0204] Specifically, this process may adopt RIE etching technology.

[0205] Specifically, the thickness of the second preliminary dielectric layer 10 is 1-1000 nm, such as 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm or 1000 nm.

[0206] Specifically, due to the carrier channel structure, the second preliminary dielectric layer 10 is convex at the corresponding position. The second preliminary dielectric layer 10 at the convex position is exposed by photolithography or etching technology (eg, Figure 16 ). Among them, Figure 16 In the figure, 73 is a photoresist layer.

[0207] S36: Directional etching exposes the preliminary gate layer located at the carrier channel structure. The specific structure is as follows Figure 17 shown.

[0208] Specifically, only a portion of the second preliminary dielectric layer 10 located at the carrier channel structure 4 is etched away, so that the preliminary gate layer 9 located at the protruding carrier channel structure 4 is exposed.

[0209] Specifically, the etching technology may be ion dry etching and chemical wet etching.

[0210] S37: Remove the prepared gate layer at the carrier channel structure by etching in a direction to expose a portion of the first prepared dielectric layer at the carrier channel structure; further remove the first prepared dielectric layer at the carrier channel structure by directional etching to expose a portion of the carrier channel structure 4. The specific structure is as follows: Figure 18 shown.

[0211] Specifically, the etching may be ion dry etching or chemical wet etching.

[0212] Figure 18 In the figure, 74 is a photoresist protection layer. After this process is completed, 74 can be removed.

[0213] S38: forming a continuous and complete dielectric layer on the top surface. Figure 19 shown.

[0214] The specific formation technologies or means are: atomic layer deposition, magnetron sputtering, electron beam evaporation and other coating methods.

[0215] S38: Etching to expose the top of the carrier channel structure to facilitate the formation of the source. Figure 20 shown.

[0216] S39: forming a source electrode to cover the exposed portion of the carrier channel structure. Figure 21 shown.

[0217] The final transistor structure is as follows Figure 22 shown.

[0218] Compared to transistors constructed using methods III and IV, the benefits of using method V are as follows: The vertical transistors formed using this method can fully utilize three-dimensional space, enabling the fabrication of higher-density transistors and improving chip performance. The following illustrates the innovative nature of this application's technical solutions and technical effects through more specific examples and performance data.

[0219] Furthermore, as in the above process, it is also possible to form Figure 30 Another standing transistor is shown, in which the source, carrier channel structure, and drain form a pillar from bottom to top, with the source and drain located at either end of the pillar, and the carrier channel structure in the middle, connecting the source and drain. In this structure, the source, carrier channel structure, and drain can all be formed by 3D printing, simply by switching the particle material. This structure, combined with printing speed control, further reduces the length of the semiconductor's carrier channel structure, allowing it to be reduced to the nanometer scale (e.g., less than 20nm or less).

[0220] Example 1

[0221] This embodiment provides a bottom-gate transistor constructed using method III, which mainly includes the following steps:

[0222] Step 1: Provide a base layer.

[0223] A single-side polished silicon wafer with a thickness of 500 μm was selected and cleaned.

[0224] Cleaning was performed in a megasonic cleaning machine with an ultrasonic power of 1.08 kW. The silicon wafers were first ultrasonically cleaned in an acetone solution for 5 minutes, then in an isopropyl alcohol solution for 5 minutes, and finally in deionized water for 3 minutes. After removal, the wafer surface was purged and dried using a nitrogen gun.

[0225] Before the coating process, the silicon oxide surface was bombarded with oxygen plasma for 1.5 seconds to remove organic matter and change the surface roughness, which was conducive to the complete coating of the photoresist. The oxygen flow rate was 50 sccm and the RF power was 500 W.

[0226] Step 2: forming a metal pattern layer including a source electrode and a drain electrode: defining a pattern layer for the source electrode and the drain electrode on the base layer by photolithography, coating and stripping to form a metal pattern layer 3 with a gap 31 between the source electrode and the drain electrode.

[0227] Specifically, photoresist is coated on the surface of the substrate, and the selected photoresist model is UV135G0.9, and exposure and development processes are completed in sequence.

[0228] 1) The coating process is completed by spin coating with an automatic coating developer, and the coating thickness is 900nm. 2) The exposure process is completed in a stepper lithography machine. The pattern of the mask needs to include 4 cross marks for subsequent channel layer alignment. The laser light source is 248nm deep ultraviolet light, and the exposure dose is 20.5mj / cm 2 3) AZ300MIF developer was used for the development process, and the development time was 60 seconds.

[0229] The metal electrode is coated by electron beam evaporation (E-beam), and then the metal is stripped to complete the metal pattern preparation. Among them: 1) The coating process first deposits an 8nm layer of titanium to improve metal adhesion, and then deposits a 72nm layer of gold as an electrode. 2) The stripping process is completed in an ultrasonic cleaning machine with an ultrasonic power of 1.08kW. First, place the substrate in an acetone solution and ultrasonicate for 30 minutes. Take it out and wash it with ultrapure water and then ultrasonicate for 10 minutes. Repeat this three times, then take it out and use a nitrogen gun to blow dry the substrate surface.

[0230] Specifically, the width of the gap 31 is 150 nm.

[0231] The metal pattern layer 3 is formed as follows Figure 23 shown.

[0232] Step 3: further forming a photoresist aligned with a passivation layer by photolithography technology; the photoresist aligned with the passivation layer is used to ensure that the carrier channel is only filled between the source and drain electrodes or is further partially formed on the source and drain metal layer after filling, and is not formed elsewhere.

[0233] Specifically, a photoresist, Lor5A and S1805, was applied to the substrate surface, and the exposure and development processes were completed sequentially. 1) The coating process was completed by spin coating with a 500nm thickness per layer. 2) The exposure process was completed in an MLA, using four cross marks on the metal layer for alignment. The laser source was 405nm UV light, and the exposure metering was 65mj / cm 2 3) AZ300MIF developer was used for the development process, and the development time was 45 seconds.

[0234] Step 4: Print three-dimensional indium oxide semiconductor particles from bottom to top on the processed substrate through 3D printing to form a carrier channel structure and complete the preparation of the bottom-gate transistor. Its spatial configuration is shown in the attached figure. Figure 4 As shown, it is a Fin (fin type), and the transistor finally formed is a FinFET.

[0235] Specifically, the selected indium oxide semiconductor particles are produced by 3D printing. The particle size of the indium oxide semiconductor particles is 3 to 7 nm.

[0236] Specifically, the 3D printing is performed at room temperature and normal pressure.

[0237] Specifically, the 3D printing process involves manipulating the directional migration of semiconductor particles in a gas using an electric field, causing them to stack in gaps to form carrier channel structures. The electric field strength was 1000 V / cm, and the printing time was 30 minutes.

[0238] The final carrier channel structure is as follows Figure 24 As shown, see specifically Figure 24 The white portion is formed in the gap and further formed on the source and drain electrodes.

[0239] Example 2

[0240] Based on Example 1, an atomic layer deposition system was used to deposit 80 nm of aluminum oxide as the top gate dielectric layer, and magnetron sputtering was used to deposit 15 / 85 nm of chromium and gold respectively as the top gate electrode layer. The TEM image of the specific top gate is shown in FIG. Figure 25 shown. Figure 25 From bottom to top in the middle are indium oxide layer, aluminum oxide layer (white part), chromium layer and gold layer.

[0241] The transistors finally formed in Example 1 and Example 2 were subjected to transfer characteristic curve electrical testing using a semiconductor analysis tester. The test results are shown in FIG. Figure 26 (Results of Example 1) and Figure 27 (Results of Example 2) are shown.

[0242] The test method is: fix the voltage applied to the source and drain (V ds ), by changing the gate voltage (V g ), observe the source-drain current (I ds ) switch changes.

[0243] Depend on Figure 26 It can be seen that when the bottom-gate transistor in Example 1 is tested, the source-drain voltage is fixed at 2V. Under the control of the gate voltage from -20V to 20V, the ratio of the maximum value to the minimum value of the source-drain circuit is 100-1000, that is, the switching of transistors 100-1000 is achieved.

[0244] Depend on Figure 27 It can be seen that when the top-gate transistor in Example 2 is tested, the source-drain voltage is fixed at 6V, and the ratio of the maximum value to the minimum value of the source-drain circuit is greater than 10 when the gate voltage is controlled from -10V to 10V. 3 , that is, to realize transistor 10 3 switch.

[0245] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A micro-nano manufacturing method for nano transistors, characterized in that: Combining photolithography, coating and etching techniques, atomic and / or nanoscale particles are used and printed from bottom to top in the gas phase through 3D printing technology to form any one or more of the carrier channel structure, source, drain, gate and dielectric layer.

2. The micro-nano manufacturing method according to claim 1, characterized in that: The material of the particles is selected from one or more of insulating materials, semiconductor materials and conductive materials; the 3D printing forms the carrier channel structure, source, drain, gate or dielectric layer by: based on the action of the electric field, controlling the directional migration of particles in the gas, so that the particles are stacked from bottom to top to form the carrier channel structure, source, drain, gate or dielectric layer; and / or, during 3D printing, controlling the boundaries of the carrier channel structure, source, drain, gate or dielectric layer through a self-alignment process; and / or, based on 3D printing technology, combined with photolithography, coating and etching technology, printing out transistors by switching different printing particles; and / or, by switching the material type of the particles, printing in segments from bottom to top to form a column structure, the middle of the column structure is the carrier channel structure, and the two ends are the source and drain respectively; and / or, the carrier channel structure is in a columnar or standing type.

3. The micro-nano manufacturing method according to claim 2, characterized in that: Semiconductor materials are used for printing to form carrier channel structures; and / or, insulating materials are used for 3D printing to form dielectric layers; and / or, conductive materials are used for printing to form electrode layers of source, drain, or gate; and / or, the particle size is less than 20 nm.

4. The micro-nano manufacturing method according to claim 3, characterized in that: The semiconductor material is selected from one or more of indium oxide, zinc oxide, indium zinc oxide, gallium oxide, silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, gallium antimonide, lead sulfide, lead selenide, molybdenum disulfide, cadmium sulfide, cadmium selenide, cadmium telluride, barium titanate, strontium titanate, and CH3NH3PbI3; and / or the particle size of the semiconductor material is less than 20 nm; and / or, during 3D printing, the printing process of the carrier channel structure, source, drain, gate or dielectric layer is controlled according to the particle size, electric field strength and printing time; and / or the insulating material is selected from one or more of aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, silicon nitride, and boron nitride; and / or the conductive material includes one or more of gold, silver, palladium, copper, nickel, titanium, chromium, silicon, germanium, aluminum, gold-silver alloy, nickel-titanium alloy, nickel-silicon alloy, indium oxide, zinc oxide, indium zinc oxide, silicon, germanium, gallium arsenide, gallium nitride, and silicon carbide.

5. The manufacturing method according to claim 1, characterized in that The manufacturing method comprises: Provides a base layer; forming a source electrode and a drain electrode on the base layer; In the gap between the source and the drain, a carrier channel structure is formed from bottom to top by 3D printing to form a bottom-gate transistor; preferably, it also includes further forming a top-gate structure.

6. The manufacturing method according to claim 1, characterized in that The manufacturing method comprises: Provides a base layer; forming a source electrode and a drain electrode on the base layer; forming a protective layer based on a photolithography technique to form exposed portions only on the source electrode and the drain electrode; At the exposed parts of the source and drain, a bridge-shaped carrier channel structure is formed from bottom to top by 3D printing; Removing the protective layer by etching technology; Preferably, the method further includes forming a top gate structure.

7. The manufacturing method according to claim 1, characterized in that The manufacturing method comprises: Provides a base layer; forming a drain electrode on the base layer; forming a pillar-type nano-sized carrier channel structure on the drain electrode from bottom to top by 3D printing; forming a first preliminary dielectric layer for completely covering and sealing the carrier channel structure; further forming a preliminary gate layer covering the carrier channel structure on the first preliminary dielectric layer; forming a second preliminary dielectric layer completely covering the preliminary gate layer to isolate the gate and the source; The second preliminary dielectric layer, the preliminary gate layer, and the first preliminary dielectric layer located at the top of the carrier channel structure are removed by self-alignment and directionally etching using a photolithography technique to expose the top of the carrier channel structure; further forming a second dielectric layer for isolating the gate and the source; Directional etching is performed to remove the second dielectric layer located near the top of the carrier channel structure to facilitate the formation of the source electrode; A source electrode is formed at the top of the exposed carrier channel structure.

8. A fin field effect nanotransistor, characterized in that: include: basal layer; A metal pattern layer including a source electrode and a drain electrode: formed on the base layer, with a gap between the source electrode and the drain electrode; Carrier channel structure: formed from the bottom up from the gap to the substrate, and connected to the source and drain; Preferably, a top gate structure is also included.

9. A field-effect nano-transistor with a bridge-type carrier channel structure, characterized in that: include: basal layer; Source and drain: formed on the base layer with a gap between them; Bridge-shaped carrier channel structure: spans the gap between the source and drain, with both ends formed on the source and drain respectively; Preferably, a top gate structure is also included.

10. A pillar-type carrier channel junction field effect nano-transistor, characterized in that: include: basal layer; Drain: formed on the base layer; Pillar carrier channel structure: formed on the drain, in a pillar-like shape; The first dielectric layer is formed between the source and drain electrodes and is used to close the pillar-type carrier channel structure; Source: formed at the top of the pillar-type carrier channel structure; Gate: The gate is formed on the first dielectric layer and surrounds the columnar portion of the first dielectric layer; Second dielectric layer: The second dielectric layer is formed on the gate electrode and is used to isolate the gate electrode from the source electrode.

Images