Photonic integrated circuits and methods of forming same

Abstract

A photonic integrated circuit may include a first waveguide optically coupled to a second waveguide and a third waveguide. The first waveguide and the second waveguide are manufactured to have different side wall angles. In particular, the first waveguide may be manufactured to have a larger sidewall angle than the second waveguide. The smaller sidewall angle of the second waveguide results in a greater sidewall taper of the second waveguide, which enables high gap filling performance around the second waveguide. The larger sidewall angle of the first waveguide results in the first waveguide having a smaller amount of sidewall taper (e.g., a more vertical sidewall), which provides a larger amount of surface area at the top of the first waveguide for coupling an input optical signal from the third coupling waveguide to the first waveguide.

Description

Technical Field

[0001] The present invention relates to a photonic integrated circuit and a method for forming the same. Background Art

[0002] A photonic integrated circuit may include a polarization splitter and rotator (PSR) waveguide. The polarization splitter and rotator waveguide may be configured to receive an input optical signal and split the input optical signal into two orthogonal polarization optical signals: a transverse electric (TE) polarization optical signal and a transverse magnetic (TM) polarization optical signal. The polarization splitter and rotator waveguide then rotates one of the polarization optical signals so that two separated transverse electric polarization optical signals or two separated transverse magnetic polarization optical signals are output from the polarization splitter and rotator waveguide. The polarization splitter and rotator waveguide has various use cases, including wavelength division multiplexing (WDM) of the input optical signal, mitigating polarization-induced effects in the input optical signal, and / or polarization-based sensing, among other examples. Summary of the Invention

[0003] Some embodiments described herein provide a method for forming a photonic integrated circuit. The method includes performing one or more first etching operations to form a first waveguide in a semiconductor layer of a semiconductor device. The method includes performing one or more second etching operations to form a second waveguide in the semiconductor layer, wherein a first end of the first waveguide is physically coupled to the second waveguide. The method includes forming a third waveguide in a dielectric layer such that a portion of the third waveguide is located above a second end of the first waveguide opposite the first end, wherein a first angle of a portion of the first waveguide below the third waveguide portion (the angle between a sidewall of the portion of the first waveguide and a bottom surface of the portion of the first waveguide) and a second angle between a sidewall of the second waveguide and the bottom surface of the second waveguide are different angles.

[0004] Some embodiments described herein provide a method for forming a photonic integrated circuit. The method includes etching a semiconductor layer of a semiconductor device to form a first waveguide and a second waveguide, each waveguide having a first thickness, wherein a first end of the first waveguide is physically coupled to the second waveguide. The method includes forming one or more first mask layers over at least a portion of a tapered portion of a second end of the first waveguide opposite the first end. The method includes performing one or more first etching operations to etch the semiconductor layer while the one or more first mask layers cover at least the portion of the tapered portion of the first waveguide, thereby increasing the thickness of the second waveguide from the first thickness to a second thickness. The method includes forming a second mask layer over the second waveguide after performing the one or more first etching operations. The method includes performing a second etching operation while the second mask layer covers the second waveguide, thereby increasing the thickness of the first waveguide from the first thickness to the second thickness.

[0005] Some embodiments described herein provide a photonic integrated circuit. The photonic integrated circuit includes a first waveguide. A semiconductor device includes a second waveguide physically coupled to a first end of the first waveguide. The semiconductor device includes a third waveguide located above a second end of the first waveguide opposite the first end, wherein a first sidewall angle of the first waveguide at the second end is greater than a second sidewall angle of a portion of the second waveguide not physically contacting the first waveguide. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration.

[0007] Figures 1A to 1C is a diagram of an example of the photonic integrated circuit described in this article.

[0008] Figures 2A to 2QQ is a diagram of an embodiment forming an example of a photonic integrated circuit described herein.

[0009] Figures 3A to 3C is a diagram of an example of the photonic integrated circuit described in this article.

[0010] Figures 4A to 4L is a diagram of an embodiment forming an example of a photonic integrated circuit described herein.

[0011] 5A to 5I is a diagram of an embodiment forming an example of a photonic integrated circuit described herein.

[0012] Figure 6 is a flow chart of an example process associated with forming the photonic integrated circuits described herein.

[0013] Figure 7 is a flow chart of an example process associated with forming the photonic integrated circuits described herein. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature is in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the sake of brevity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to facilitate describing the relationship of one component or feature to another component or feature as depicted in a figure. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] In some cases, a polarization splitter and rotator (PSR) waveguide in a photonic integrated circuit is optically coupled to an edge coupler waveguide via a coupling waveguide. The edge coupler waveguide can receive an input optical signal, such as from an external optical fiber, and provide it to the polarization splitter and rotator waveguide for signal processing via the coupling waveguide.

[0017] The polarization-splitting rotator waveguide can be fabricated with a specific sidewall angle to achieve high gap-filling performance when a dielectric layer is formed above the polarization-splitting rotator waveguide. The polarization-splitting rotator waveguide and the coupling waveguide can be fabricated from the same semiconductor layer, so the coupling waveguide can be fabricated with the same sidewall angle as the polarization-splitting rotator waveguide, enabling efficient process integration and low process complexity in fabricating the polarization-splitting rotator waveguide and the coupling waveguide.

[0018] If the edge coupler waveguide is located in a dielectric layer above the coupling waveguide, the input optical signal is coupled from the edge coupler waveguide to the coupling waveguide through the top of the coupling waveguide. The polarization splitting rotator waveguide sidewall angle selected to achieve high gap-filling performance around the polarization splitting rotator waveguide can result in low optical coupling efficiency and increased optical signal loss for the input optical signal coupling from the edge coupler waveguide to the coupling waveguide through the top of the coupling waveguide. In particular, the sidewall angle selected for the polarization splitting rotator waveguide can result in the polarization splitting rotator waveguide sidewall having a high amount of taper to achieve high gap-filling performance around the polarization splitting rotator waveguide, while the high amount of taper on the coupling waveguide sidewall can result in a reduced surface area at the top of the coupling waveguide, thereby reducing the area where the input optical signal can be coupled from the edge coupler waveguide to the coupling waveguide.

[0019] In certain embodiments described herein, a photonic integrated circuit of a semiconductor device is fabricated to include a polarization-splitting rotator waveguide, an edge coupler waveguide, and a coupling waveguide optically coupled to the polarization-splitting rotator waveguide and the edge coupler waveguide. The polarization-splitting rotator waveguide and the coupling waveguide are fabricated to have different sidewall angles. Specifically, the polarization-splitting rotator waveguide can be fabricated to have a smaller sidewall angle than the coupling waveguide, while the coupling waveguide can be fabricated to have a larger sidewall angle than the polarization-splitting rotator waveguide. The smaller sidewall angle of the polarization-splitting rotator waveguide sidewalls allows the polarization-splitting rotator waveguide to have a greater degree of sidewall taper, which enables high gap-filling performance when a dielectric layer is formed above the polarization-splitting rotator waveguide. The larger sidewall angle of the coupling waveguide sidewalls results in the coupling waveguide having a lesser degree of sidewall taper (e.g., a more vertical sidewall), which provides a larger surface area on top of the coupling waveguide to improve coupling efficiency and reduce optical signal loss from the input optical signal coupled from the edge coupler waveguide to the coupling waveguide.

[0020] As described herein, the coupled waveguides can be fabricated with a larger sidewall angle for only a portion of the coupled waveguide below the edge coupler waveguide, or for a larger portion of the coupled waveguide. The polarization-splitting rotator waveguide and the coupled waveguides can be fabricated from the same semiconductor layer using a series of masking and etching operations, allowing the process of forming the polarization-splitting rotator waveguide and the coupled waveguides to be integrated with other complementary metal-oxide-semiconductor (CMOS) processes for semiconductor devices.

[0021] Figures 1A to 1Cis a diagram of an example 100 of a photonic integrated circuit 102 described herein. The photonic integrated circuit 102 may include an optical coupling circuit including an edge coupler waveguide 104, a polarization-splitting rotator waveguide 106, and a coupling waveguide 108 that optically couples the edge coupler waveguide 104 and the polarization-splitting rotator waveguide 106. In some embodiments, the photonic integrated circuit 102 may be included in a semiconductor device, such as the semiconductor device 202 described herein.

[0022] Figure 1A A top view of the photonic integrated circuit 102 along the xy plane will be described. Figure 1B Instructions along the Figure 1A A cross-sectional view of the photonic integrated circuit 102 taken along line AA in the x-direction. Figure 1C illustrate Figure 1A Multiple cross-sections in the y direction, such as along Figure 1A Cross-sectional view of the photonic integrated circuit 102 along line BB, Figure 1A Cross-sectional view of the photonic integrated circuit 102 along line CC, Figure 1A The cross-sectional view of the photonic integrated circuit 102 along the DD line, and Figure 1A A cross-sectional view of the photonic integrated circuit 102 taken along line EE.

[0023] like Figure 1A As shown, the edge coupler waveguide 104, the polarization splitting rotator waveguide 106, and the coupling waveguide 108 can each extend along the x-direction within the photonic integrated circuit 102. The edge coupler waveguide 104 can include a tapered portion 110, a tapered portion 112, and a transition portion 114 located between the tapered portions 110 and 112. The tapered portion 110 can be optically coupled to an optical fiber, an optical fiber cable, and / or other types of external optical inputs. The edge coupler waveguide 104 can be configured to receive an input optical signal from the external optical input and provide the input optical signal to the coupling waveguide 108. The input optical signal can propagate through the edge coupler waveguide 104 along the x-direction.

[0024] like Figure 1A As further shown, the polarization splitting rotator waveguide 106 may include a through segment 116 and a cross segment 118 extending in the x-direction along the through segment 116. The through segment 116 may include a tapered portion 120, a transition portion 122, a bi-tapered portion 124, a transition portion 126, a tapered portion 128, and / or an output portion 130, among others. The through segment 116 may include different types of portions and / or different arrangements of portions. The cross segment 118 may include a tapered portion 132 and an output portion 134.

[0025] The tapered portion 120 of the through-section 116 of the polarization-splitting rotator waveguide 106 can be optically and physically coupled to the coupling waveguide 108, such that an input optical signal is received by the polarization-splitting rotator waveguide 106 at the tapered portion 120. The input optical signal (e.g., an unpolarized input optical signal) can propagate from the tapered portion 120 through the transition portion 122 to the dual-tapered portion 124, where the input optical signal is split into a transverse electric (TE) polarized optical signal and a transverse magnetic (TM) polarized optical signal. Therefore, the dual-tapered portion 124 can be referred to as a splitter portion of the polarization-splitting rotator waveguide 106.

[0026] The transverse electric polarization optical signal and the transverse magnetic polarization optical signal propagate through the tapered portion 128, where one of the transverse electric polarization optical signal or the transverse magnetic polarization optical signal is coupled to the tapered portion 132 of the cross-section 118 and rotated. Optical signals not coupled to the cross-section 118 continue to propagate unmodulated through the output portion 130. For example, a transverse electric polarization optical signal can be coupled from the tapered portion 128 to the tapered portion 132 and rotated in the cross-section 118 to become another transverse magnetic polarization optical signal, while the transverse magnetic polarization optical signal can remain in the through-section 116 and propagate to the output portion 130. As another example, a transverse magnetic polarization optical signal can be coupled from the tapered portion 128 to the tapered portion 132 and rotated in the cross-section 118 to become another transverse electric polarization optical signal, while the transverse electric polarization optical signal can remain in the through-section 116 and propagate to the output portion 130.

[0027] like Figure 1A As further shown, the coupling waveguide 108 may include a tapered portion 136 at a first end of the coupling waveguide 108, a tapered portion 138 at a second end of the coupling waveguide 108 opposite the first end, and a transition portion 140 between the tapered portion 136 and the tapered portion 138. The coupling waveguide 108 may be located between the edge coupler waveguide 104 and the polarization splitting rotator waveguide 106 in the x-direction.

[0028] like Figure 1A and 1B As shown, the edge coupler waveguide 104 and the coupling waveguide 108 at least partially overlap in a coupling region 142 of the photonic integrated circuit 102. In the coupling region 142, the tapered portion 136 at the first end of the coupling waveguide 108 may be at least partially overlapped by the tapered portion 112 at an end of the edge coupler waveguide 104 that is optically coupled to an external optical input relative to the end of the edge coupler waveguide 104. The coupling region 142 is where an input optical signal is converted between the edge coupler waveguide 104 and the coupling waveguide 108.

[0029] like Figure 1Aand 1B As further shown, the polarization-splitting rotator waveguide 106 and the coupling waveguide 108 at least partially overlap in another coupling region 144 of the photonic integrated circuit 102. In the coupling region 144, the tapered portion 138 at the second end of the coupling waveguide 108 can be at least partially overlapped by the tapered portion 120 at an end of the polarization-splitting rotator waveguide 106 opposite the end of the polarization-splitting rotator waveguide 106 where the output portions 130 and 134 are located. The coupling region 144 is where the input optical signal is converted between the polarization-splitting rotator waveguide 106 and the coupling waveguide 108.

[0030] like Figure 1B As shown, the edge coupler waveguide 104 can be located at a higher or greater vertical (z-direction) position in the photonic integrated circuit 102 than the polarization separating rotator waveguide 106 and the coupling waveguide 108 because the edge coupler waveguide 104 is formed in a dielectric layer above the polarization separating rotator waveguide 106 and the coupling waveguide 108. The edge coupler waveguide 104 can include a dielectric waveguide including one or more dielectric materials, while the polarization separating rotator waveguide 106 and the coupling waveguide 108 can each include a semiconductor waveguide including one or more semiconductor materials. Examples of dielectric materials that the edge coupler waveguide 104 can include include silicon nitride materials (SiN). x N y , such as Si3N4), alumina materials (Al x O y , such as Al2O3), aluminum nitride materials (AlN), hafnium oxide materials (HfO x , such as HfO2), titanium oxide materials (TiO x , such as TiO2), zinc oxide materials (ZnO) and / or germanium oxide materials (GeO x , such as GeO 2 ), etc. Examples of semiconductor materials that the polarization separation rotator waveguide 106 and the coupling waveguide 108 may include include silicon (Si), germanium (Ge), and / or other semiconductor materials.

[0031] The higher vertical position of the edge coupler waveguide 104 causes the tapered portion 112 of the edge coupler waveguide 104 to be positioned above and / or over the tapered portion 136 of the coupling waveguide 108 in the coupling region 142. In the coupling region 142, the tapered portion 112 of the edge coupler waveguide 104 and the tapered portion 136 of the coupling waveguide 108 can be spaced apart from each other in the z-direction such that the edge coupler waveguide 104 and the coupling waveguide 108 do not physically contact each other. An input optical signal can propagate downwardly along the z-direction from the edge coupler waveguide 104 to the coupling waveguide 108 in the coupling region 142.

[0032] like Figure 1BAs further shown, the bottom surfaces of the polarization splitting rotator waveguide 106 and the coupling waveguide 108 can be located at approximately the same height or vertical (z-direction) position in the photonic integrated circuit 102 because the polarization splitting rotator waveguide 106 and the coupling waveguide 108 are formed from the same semiconductor layer. Figure 1B As shown, the polarization-splitting rotator waveguide 106 can have a greater vertical (z-direction) thickness than the coupling waveguide 108. In the coupling region 144, the tapered portion 138 of the coupling waveguide 108 and the tapered portion 120 of the polarization-splitting rotator waveguide 106 can be physically coupled (e.g., can be in direct physical contact) and also optically coupled. An input optical signal can propagate upward in the z-direction from the coupling waveguide 108 to the polarization-splitting rotator waveguide 106 in the coupling region 144.

[0033] like Figure 1C As shown, the edge coupler waveguide 104, the polarization splitting rotator waveguide 106, and the coupling waveguide 108 may each include a strip waveguide cross-sectional profile, except that in the coupling region 144, the combination of the polarization splitting rotator waveguide 106 and the coupling waveguide 108 corresponds to a slab waveguide cross-sectional profile. Figure 1C As shown in the cross section formed by the CC lines in , the slab waveguide cross-sectional profile appears because the polarization splitting rotator waveguide 106 is located on top of (and in physical contact with) the coupling waveguide 108 in the coupling region 144 .

[0034] like Figure 1C As further shown, at the cross-sectional position formed by line BB, the cross-sectional width of the edge coupler waveguide 104 in the y-direction is greater than the cross-sectional width of the coupled waveguide 108 in the y-direction, while at the cross-sectional position formed by line AA, the cross-sectional width of the edge coupler waveguide 104 in the y-direction is less than the cross-sectional width of the coupled waveguide 108 in the y-direction. This is because the cross-sectional widths of the edge coupler waveguide 104 and the cross-sectional widths of the coupled waveguide 108 decrease in opposite directions along the x-direction in the coupling region 142.

[0035] like Figure 1C As further shown, at the cross-sectional location formed by line BB in the coupling region 142, the tapered portion 136 of the coupling waveguide 108 may have a sidewall angle (at Figure 1C At the location of the cross section formed by line CC in the coupling region 142, the tapered portion 136 of the coupling waveguide 108 may have another sidewall angle (at Figure 1C At the cross-sectional location formed by line DD in the coupling region 144, the tapered portion 138 of the coupling waveguide 108 may have a sidewall angle (at Figure 1CAt the cross-sectional location where the EE line is formed (e.g., in the coupling region between the through section 116 and the cross section 118 of the polarization splitting rotator waveguide 106), the tapered portion 128 of the polarization splitting rotator waveguide 106 may have a sidewall angle (at Figure 1C At the cross-sectional location where the EE line is formed (e.g., in the coupling region between the through section 116 and the cross section 118 of the polarization splitting rotator waveguide 106), the tapered portion 132 of the polarization splitting rotator waveguide 106 may have a sidewall angle (at Figure 1C Dimension D5 is indicated in the figure.

[0036] The sidewall angle described herein refers to the angle between the bottom surface of the waveguide and the sidewall of the waveguide in the y-direction. Therefore, a smaller sidewall angle results in a greater degree of tapering between the opposing sidewalls in the z-direction, meaning that the sidewalls in the y-direction converge faster from the bottom to the top of the waveguide than with a larger sidewall angle.

[0037] The polarization-splitting rotator waveguide 106 and the coupling waveguide 108 can be fabricated from semiconductor layers using the techniques described herein such that one or more portions of the coupling waveguide 108 have different sidewall angles in the y-direction than the polarization-splitting rotator waveguide 106. For example, the coupling waveguide 108 can be fabricated such that its tapered portion 136 in the coupling region 142 has a larger sidewall angle than the polarization-splitting rotator waveguide. In other words, the coupling waveguide 108 can be fabricated such that dimensions D1 and D2 are larger than dimensions D4 and D5. Conversely, the polarization-splitting rotator waveguide 106 can be fabricated such that its sidewall angles are smaller than those of the tapered portion 136 of the coupling waveguide 108. In other words, the polarization-splitting rotator waveguide 106 can be fabricated such that dimensions D4 and D5 are smaller than dimensions D1 and D2.

[0038] The tapered portion 136 of the coupling waveguide 108 has a larger sidewall angle, resulting in a lesser degree of sidewall taper in the tapered portion 136 of the coupling waveguide 108, and therefore a more vertical sidewall. In the coupling region 142, the greater verticality of the sidewalls of the tapered portion 136 of the coupling waveguide 108 provides a larger surface area at the top of the coupling waveguide 108. This provides a larger surface area of ​​the coupling waveguide 108 for the input optical signal to propagate from the edge coupler waveguide 104 in the coupling region 142. This enables high coupling efficiency and low optical signal loss for coupling the input optical signal from the edge coupler waveguide 104 to the coupling waveguide 108 in the coupling region 142.

[0039] The sidewalls of the polarization-splitting rotator waveguide 106 have a smaller sidewall angle, resulting in a greater degree of sidewall taper for the polarization-splitting rotator waveguide 106. The greater degree of sidewall taper of the sidewalls of the polarization-splitting rotator waveguide 106 allows dielectric material to be more easily deposited around the sidewalls of the polarization-splitting rotator waveguide 106, particularly at locations between the tapered portion 128 of the through-section 116 and the tapered portion 132 of the cross-section 118. This enables high gap-filling performance to be achieved when forming a dielectric layer over the polarization-splitting rotator waveguide 106.

[0040] In some embodiments, dimension D1 and dimension D2 can each be within a range of about 86 degrees to about 88 degrees to achieve high coupling efficiency and low optical signal loss in coupling the input optical signal from the edge coupler waveguide 104 to the coupling waveguide 108 in the coupling region 142. However, other values ​​and ranges for dimension D1 and dimension D2 are also within the scope of the present disclosure. In some embodiments, dimension D4 and dimension D5 can each be within a range of about 80 degrees to about 85 degrees to achieve high gap filling performance when a dielectric layer is formed above the polarization splitting rotator waveguide 106. However, other values ​​and ranges for dimension D4 and dimension D5 are also within the scope of the present disclosure.

[0041] Dimension D3 may also be included in the range of about 80 degrees to about 85 degrees because Figures 2A to 2QQ As described above, the tapered portion 138 of the coupling waveguide 108 may be formed together with the tapered portion 120 of the polarization splitting rotator waveguide 106. Alternatively, the tapered portion 138 may be formed to have another sidewall angle.

[0042] As described above, providing Figures 1A to 1C As an example. Other examples can be found in the Figures 1A to 1C Different than described.

[0043] Figures 2A to 2QQ To form Figures 1A to 1C Schematic diagram of an embodiment 200 of the example 100 of the photonic integrated circuit 102. In some embodiments, one or more semiconductor process tools may be used to perform Figures 2A to 2QQ The one or more semiconductor process operations, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools and / or wafer / die transfer tools, etc. Figures 2A to 2QQ One or more of the graphs is from Figure 1A Top view of Figure 1B Section along line AA and / or Figure 1C The cross-sections along lines BB, CC, DD and EE are drawn.

[0044] refer to Figures 2A to 2C , a semiconductor device 202 may be provided. The semiconductor device 202 may be provided as a substrate 204, which may include a silicon on insulator (SOI) substrate (or an SOI wafer) and / or other types of substrates. The substrate 204 may include a semiconductor substrate 206 (e.g., a silicon (Si) substrate and / or other types of semiconductor substrates), a dielectric layer 208 (e.g., a buried oxide or bottom oxide (BOX) layer and / or other types of insulating layers) located above and / or on the semiconductor substrate 206, and a semiconductor layer 210 (e.g., a silicon (Si) layer and / or other types of semiconductor layers) located above and / or on the dielectric layer 208.

[0045] Alternatively, semiconductor substrate 206 may be provided as a semiconductor wafer, dielectric layer 208 may be formed over and / or on semiconductor substrate 206 using a deposition tool, and semiconductor layer 210 may be formed over and / or on dielectric layer 208 using a deposition tool. Dielectric layer 208 may be formed using a deposition tool by chemical vapor deposition (CVD), physical vapor deposition (PVD), oxidation (e.g., thermal oxidation), and / or other types of deposition techniques. Semiconductor layer 210 may be formed using a deposition tool by chemical vapor deposition, physical vapor deposition, epitaxy, and / or other types of deposition techniques.

[0046] like Figures 2A to 2C As further shown, a mask layer 212 is formed over and / or on the semiconductor layer 210. The mask layer 212 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SiXNy), silicon oxynitride (SiON), and / or other suitable dielectric materials. The mask layer 212 may be formed using a deposition tool using chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition (ALD) techniques, oxidation techniques (e.g., thermal oxidation techniques), and / or other types of deposition techniques.

[0047] like Figures 2D to 2FAs shown, a patterned mask layer 214 (e.g., a patterned photoresist layer) may be formed on the mask layer 212. In some embodiments, a deposition tool may be used to form the photoresist layer on the mask layer 212 using a spin coating technique and / or other suitable types of deposition techniques. An exposure tool may be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern, thereby forming the patterned mask layer 214.

[0048] like Figures 2G to 2I As shown, the pattern in the patterned mask layer 214 can be used to etch the mask layer 212 so that the pattern in the patterned mask layer 214 is transferred to the mask layer 212. An etching tool can be used to etch the mask layer 212 to transfer the pattern from the patterned mask layer 214 to the mask layer 212. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the patterned mask layer 214 (for example, using a chemical stripper, plasma ashing, and / or other techniques).

[0049] like Figures 2J to 2L As shown, the semiconductor layer 210 may be etched according to the pattern in the mask layer 212. An etching tool may be used to etch the semiconductor layer 210 to form the polarization separation rotator waveguide 106 and the coupling waveguide 108, each etched to a first depth corresponding to the first thickness (at Figure 2L In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations.

[0050] like Figures 2M to 2O As shown, another patterned mask layer 216 (e.g., a patterned photoresist layer) is formed over a portion of the semiconductor layer 210 and a portion of the coupling waveguide 108. For example, the patterned mask layer 216 may be formed over the tapered portion 136 of the coupling waveguide 108. The tapered portion 138 and the transition portion 140 of the coupling waveguide 108, as well as the polarization splitting rotator waveguide 106, may be exposed through the patterned mask layer 216.

[0051] In some embodiments, a deposition tool may be used to form a photoresist layer on the polarization splitting rotator waveguide 106, the coupling waveguide 108, and the semiconductor layer 210 using a spin coating technique and / or other suitable types of deposition techniques. An exposure tool may be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer from the polarization splitting rotator waveguide 106, the tapered portion 138 and the transition portion 140 of the coupling waveguide 108, and portions of the semiconductor layer 210 to expose the pattern, thereby forming a patterned mask layer 216.

[0052] like Figure 2P to Figure 2R As shown, the portion of the semiconductor layer 210 that exposes the patterned mask layer 216 can be etched. An etching tool can be used to perform the etching operation to etch the portion of the semiconductor layer 210 surrounding the polarization splitting rotator waveguide 106 and the portion of the semiconductor layer 210 surrounding the tapered portion 138 and the transition portion 140 of the coupling waveguide 108. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations.

[0053] An etching operation may be performed to etch through the semiconductor layer 210 to the dielectric layer 208, increasing the thickness of the polarization splitting rotator waveguide 106 and the tapered portion 138 and transition portion 140 of the coupling waveguide 108 to a second thickness (at Figure 2R Dimension D7 is indicated in the figure. The mask layer 212 on the polarization-splitting rotator waveguide 106 and on the tapered portion 138 and transition portion 140 of the coupling waveguide 108 protects the top surface of the polarization-splitting rotator waveguide 106 and the top surfaces of the tapered portion 138 and transition portion 140 of the coupling waveguide 108 from being etched during the etching operation. The patterned mask layer 216 protects the tapered portion 136 of the coupling waveguide 108 from being etched during the etching operation. As a result, the tapered portion 136 of the coupling waveguide 108 remains at the first depth, corresponding to the first thickness (dimension D6), in the semiconductor layer 210 after the etching operation.

[0054] like Figure 2R As further shown, the etching operation causes the tapered portion 138 of the coupling waveguide 108, the through-section 116 of the polarization-splitting rotator waveguide 106, and the cross-section 118 of the polarization-splitting rotator waveguide 106 to have sidewall angles corresponding to dimensions D3, D4, and D5, respectively. In some embodiments, dimensions D3, D4, and D5 are each within a range of about 80 degrees to about 85 degrees. However, other ranges are also within the scope of the present disclosure.

[0055] like Figures 2S to 2U As shown, in Figure 2P to Figure 2R After the etching operation described above, the remaining portion of the patterned mask layer 216 may be removed. The remaining portion of the patterned mask layer 216 may be removed using a photoresist removal tool, chemical strippers, plasma ashing, and / or other techniques.

[0056] like Figures 2S to 2U As further shown, after removing the remaining portions of the patterned mask layer 216, another patterned mask layer 218 (e.g., a patterned photoresist layer) may be formed over the polarization splitting rotator waveguide 106 and over the tapered portion 138 and transition portion 140 of the coupling waveguide 108. The tapered portion 136 of the coupling waveguide 108 may be exposed through the patterned mask layer 218.

[0057] In some embodiments, a deposition tool may be used to form a photoresist layer on the polarization separation rotator waveguide 106, the coupling waveguide 108, and the remaining portion of the semiconductor layer 210 using a spin coating technique and / or other suitable types of deposition techniques. An exposure tool may be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer on the tapered portion 136 of the coupling waveguide 108 and the remaining portion of the semiconductor layer 210 to expose the pattern, thereby forming a patterned mask layer 218.

[0058] like Figure 2V to Figure 2X As shown, the portion of the remaining semiconductor layer 210 exposed by the patterned mask layer 218 can be etched. An etching operation can be performed using an etching tool to etch the remaining portion of the semiconductor layer 210 around the tapered portion 136 of the coupling waveguide 108. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations.

[0059] An etching operation may be performed to etch through the semiconductor layer 210 to the dielectric layer 208 to increase the thickness of the tapered portion 136 of the coupling waveguide 108 to a second thickness (at Figure 2X The mask layer 212 on the tapered portion 136 of the coupling waveguide 108 protects the top surface of the tapered portion 136 of the coupling waveguide 108 from being etched during the etching operation. The patterned mask layer 218 protects the polarization splitting rotator waveguide 106 and protects the tapered portion 138 and the transition portion 140 of the coupling waveguide 108 from being etched during the etching operation.

[0060] In this manner, a first set of masking and etching operations (e.g. Figures 2M to 2RThe tapered portion 138 of the coupling waveguide 108 at the cross-sectional position formed by the DD line, the through-segment 116 of the polarization splitting rotator waveguide 106 at the cross-sectional position formed by the EE line, and the cross-segment 118 of the polarization splitting rotator waveguide 106 at the cross-sectional position formed by the EE line are formed so that they each have a sidewall angle corresponding to the dimension D3, the dimension D4, and the dimension D5. A second set of masking and etching operations (such as Figures 2S to 2X The tapered portion 136 of the coupling waveguide 108 is formed at the cross-sectional position defined by line BB and the cross-sectional position defined by line CC, so as to have sidewall angles corresponding to dimension D1 and dimension D2, respectively. In this manner, the tapered portion 136 can be etched such that the sidewall angle of the tapered portion 136 is greater than the sidewall angle of the polarization splitting rotator waveguide 106. In some embodiments, dimension D1 and dimension D2 are each within a range of approximately 86 degrees to approximately 88 degrees. However, other ranges are also within the scope of the present disclosure.

[0061] A first set of mask and etch operations (e.g. Figures 2M to 2R as described) and a second set of masking and etching operations (as Figures 2S to 2X For example, different etching parameters can be used for the first set of mask and etching operations (such as Figures 2M to 2R as described) and a second set of masking and etching operations (as Figures 2S to 2X The method) uses different plasma-based etching parameter sets to achieve different sidewall angles.

[0062] In some embodiments, the first set of mask and etch operations (e.g. Figures 2M to 2R A lower plasma bias is used in the embodiment described above to achieve smaller sidewall angles of the tapered portion 138 of the coupling waveguide 108 at the cross-sectional position formed by the DD line, the through-segment 116 of the polarization splitting rotator waveguide 106 at the cross-sectional position formed by the EE line, and the cross-segment 118 of the polarization splitting rotator waveguide 106 at the cross-sectional position formed by the EE line. In the second set of masking and etching operations (such as Figures 2S to 2X ) can be used in a manner that is greater than the first set of mask and etch operations (e.g. Figures 2M to 2R The higher plasma bias voltage is used to generate the second set of mask and etch operations (such as Figures 2S to 2X A more vertical etch is performed in the second set of mask and etch operations (as described above), thereby achieving a larger sidewall angle of the tapered portion 136 of the coupling waveguide 108 at the cross-sectional location formed by line BB and the cross-sectional location formed by line CC. A higher plasma bias can result in a second set of mask and etch operations (as described above). Figures 2S to 2XThe ion bombardment is more vertical in the cross section of the coupling waveguide 108, so that the tapered portion 136 of the coupling waveguide 108 at the cross section formed by the BB line and the cross section formed by the CC line has a larger sidewall angle. In some embodiments, the first set of mask and etching operations (such as Figures 2M to 2R A lower chamber pressure is used in the embodiment described above to achieve smaller sidewall angles of the tapered portion 138 of the coupling waveguide 108 at the cross-sectional position formed by the DD line, the through-segment 116 of the polarization splitting rotator waveguide 106 at the cross-sectional position formed by the EE line, and the cross-segment 118 of the polarization splitting rotator waveguide 106 at the cross-sectional position formed by the EE line. In the second set of masking and etching operations (such as Figures 2S to 2X ) can be used in a manner that is greater than the first set of mask and etch operations (e.g. Figures 2M to 2R The higher chamber pressure (described above) is used to perform the second set of mask and etch operations (e.g. Figures 2S to 2X A more vertical etch is performed in the second set of mask and etch operations (e.g., FIG. 1 ), thereby achieving a larger sidewall angle of the tapered portion 136 of the coupling waveguide 108 at the cross-sectional location formed by line BB and the cross-sectional location formed by line CC. A higher chamber pressure can facilitate the second set of mask and etch operations (e.g., FIG. 1 ). Figures 2S to 2X The flow and directionality of ion bombardment are better controlled in the embodiment described above, so that the tapered portion 136 of the coupling waveguide 108 at the cross-sectional position formed by the BB line and the cross-sectional position formed by the CC line has a larger sidewall angle.

[0063] like Figures 2Y to 2AA As shown, when executing Figure 2V to Figure 2X After the associated etching operation, the remaining portion of the patterned mask layer 216 may be removed. The remaining portion of the patterned mask layer 216 may be removed using a photoresist removal tool, chemical strippers, plasma ashing, and / or other techniques.

[0064] like Figures 2Y to 2AA As further shown, a dielectric layer 220 may be formed around the polarization separation rotator waveguide 106 and around the coupling waveguide 108. The dielectric layer 220 may be referred to as a shallow trench isolation (STI) layer. In some embodiments, before forming the dielectric layer 220, a shallow trench isolation liner layer is first deposited on the sidewalls of the polarization separation rotator waveguide 106 and the sidewalls of the coupling waveguide 108. The dielectric layer 220 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), carbon-doped silicon oxide and / or other dielectric materials.

[0065] The dielectric layer 220 can be deposited using a deposition tool using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques. In some embodiments, after depositing the dielectric layer 220, a planarization tool is used to planarize the dielectric layer 220. In some embodiments, the dielectric layer 220 can be planarized so that the top surface of the dielectric layer 220 is substantially coplanar with the top surface of the mask layer 212.

[0066] like Figures 2BB to 2DD As shown, a patterned mask layer 222 (e.g., a patterned photoresist layer) can be formed over the dielectric layer 220 and over and / or on the polarization splitting rotator waveguide 106. The patterned mask layer 222 is formed such that the coupling waveguide 108 is exposed through the patterned mask layer 222. In some embodiments, portions of the dielectric layer 220 surrounding the coupling waveguide 108 are also exposed through the patterned mask layer 222.

[0067] In some embodiments, a deposition tool may be used to form a photoresist layer on the polarization separation rotator waveguide 106, the coupling waveguide 108, and the dielectric layer 220 by spin coating and / or other suitable types of deposition techniques. An exposure tool may be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development tool may be used to develop and remove the portion of the photoresist layer on the coupling waveguide 108 to expose the pattern, thereby forming a patterned mask layer 222.

[0068] like Figures 2EE to 2GG As shown, the coupling waveguide 108 can be etched based on the patterned mask layer 218. An etching operation can be performed using an etching tool to etch the coupling waveguide 108, thereby reducing the thickness of the coupling waveguide 108 in the z-direction. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations.

[0069] like Figure 2FF As shown, this etching operation results in the formation of a coupling region 144 between the coupling waveguide 108 and the polarization splitting rotator waveguide 106. Figure 2GGAs shown, the etching operation reduces the thickness of the coupling waveguide 108 from the second thickness (dimension D7) to the third thickness (dimension D8). Figure 2GG The patterned mask layer 218 protects the polarization splitting rotator waveguide 106 from being etched during the etching operation. Therefore, after the etching operation, the polarization splitting rotator waveguide 106 still maintains the second thickness (dimension D7).

[0070] like Figures 2HH to 2JJ As shown, in Figures 2EE to 2GG After the associated etching operation, the dielectric layer 220 (eg, shallow trench isolation layer) is rebuilt. Additional material for the dielectric layer 220 may be deposited using a deposition tool by chemical vapor deposition techniques, physical vapor deposition techniques, oxidation techniques (eg, thermal oxidation techniques), and / or other types of deposition techniques.

[0071] like Figures 2HH to 2JJ As further shown, after depositing the additional material of the dielectric layer 220, a planarization operation is performed using a planarization tool to planarize the dielectric layer 220. During the planarization operation, the remaining portion of the mask layer 212 may also be removed. In some embodiments, the dielectric layer 220 may be planarized such that the top surface of the dielectric layer 220 is substantially coplanar with the top surface of the polarization-splitting rotator waveguide 106. Because the thickness of the polarization-splitting rotator waveguide 106 in the z-direction is greater than the thickness of the coupling waveguide 108 in the z-direction, the coupling waveguide 108 may be encapsulated in the dielectric layer 220.

[0072] like Figures 2KK to 2MM As shown, another dielectric layer 224 (e.g., an interlayer dielectric (ILD) layer) is formed over and / or on the dielectric layer 220, over and / or on the polarization separation rotator waveguide 106, and / or over the coupling waveguide 108. The dielectric layer 224 can be deposited using a deposition tool by chemical vapor deposition techniques, physical vapor deposition techniques, oxidation techniques (e.g., thermal oxidation techniques), and / or other types of deposition techniques. In some embodiments, after depositing the dielectric layer 224, a planarization operation is performed using a planarization tool to planarize the dielectric layer 224. The dielectric layer 224 can include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinatedsilicate glass (FSG), carbon-doped silicon oxide and / or other dielectric materials.

[0073] like Figures 2KK to 2MM As further shown, another dielectric layer 226 is formed over and / or on the dielectric layer 224. The dielectric layer 226 may be deposited using a deposition tool using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques. In some embodiments, after depositing the dielectric layer 226, a planarization operation is performed using a planarization tool to planarize the dielectric layer 226. The edge coupler waveguide 104 may be formed from the dielectric layer 226. Thus, the dielectric layer 226 may include one or more dielectric materials, such as silicon nitride (SiN) materials. x N y , such as Si3N4), alumina materials (Al x O y , such as Al2O3), aluminum nitride materials (AlN), hafnium oxide materials (HfO x , such as HfO2), titanium oxide materials (TiO x , such as TiO2), zinc oxide materials (ZnO) and / or germanium oxide materials (GeO x , such as GeO2) etc.

[0074] like Figures 2NN to 2PP As shown, a patterned mask layer 228 (e.g., a patterned photoresist layer) can be used to etch the dielectric layer 226 to form the edge coupler waveguide 104 from the dielectric layer 226. In some embodiments, a deposition tool can be used to form a photoresist layer on the dielectric layer 226 using a spin coating technique and / or other suitable types of deposition techniques. An exposure tool can be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to reveal the pattern, thereby forming the patterned mask layer 228. The dielectric layer 226 can then be etched according to the pattern in the mask layer 218 to form the edge coupler waveguide 104. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. The dielectric layer 226 is etched such that the tapered portion 112 of the edge coupler waveguide 104 is formed over a portion of the coupling waveguide 108 (eg, the tapered portion 136 of the coupling waveguide 108 ), which results in the formation of a coupling region 142 between the edge coupler waveguide 104 and the coupling waveguide 108 .

[0075] like Figure 2QQ As shown, additional material for the dielectric layer 224 is deposited. The additional material for the dielectric layer 224 can be deposited using a deposition tool using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques. After depositing the additional material for the dielectric layer 224, a planarization operation is performed using a planarization tool to planarize the dielectric layer 224. After depositing the additional material for the dielectric layer 224, the edge coupler waveguide 104 can be encapsulated in the dielectric layer 224.

[0076] like Figure 2QQ As further shown, the interconnect layer of the semiconductor device 202 is formed above the dielectric layer 224. The interconnect layer may be referred to as the back end region or back end of line (BEOL) region of the semiconductor device 202. The interconnect layer includes a dielectric region 230, which may include a plurality of dielectric layers arranged along the z-direction. These dielectric layers may include interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etch stop layers (ESLs), and / or other types of dielectric layers. The dielectric layers in the dielectric region 230 may each include an oxide (e.g., silicon oxide (SiO x ) and / or other oxide materials), undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG) and / or other suitable dielectric materials. In some embodiments, the dielectric layer in the dielectric region 230 includes an extremely low dielectric constant (ELK) dielectric material having a dielectric constant less than about 2.5. In some embodiments, the dielectric layer in the dielectric region 230 may include silicon nitride (Si x N y ), silicon carbide (SiC), silicon oxynitride (SiON) and / or other suitable dielectric materials.

[0077] The interconnect layer may further include a plurality of conductive interconnects 232 located in the dielectric layer of the dielectric region 230. These conductive interconnects may include a combination of conductive structures (e.g., trenches, conductive lines) interconnected by interconnect structures (e.g., vias). The conductive interconnects 232 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0078] The conductive interconnects 232 of the interconnect layer can be arranged vertically (e.g., along the z-direction) in the dielectric region 230 to facilitate routing of electrical signals and / or power through the dielectric region 230. The conductive interconnects 232 can be arranged in an alternating pattern of metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer can include one or more conductive interconnects 232 arranged transversely in the xy plane of the dielectric region 230, while each via layer can include one or more conductive interconnects 232 arranged transversely in the xy plane of the dielectric region 230. For example, a metal-0 (M0) layer (including one or more conductive interconnects 232) may be formed at the bottom of the dielectric region 230, a via-1 (V1) layer (including one or more conductive interconnects 232) may be formed above and coupled to the M1 layer in the dielectric region 230, a metal-1 (M1) layer may be formed above and coupled to the V1 layer in the dielectric region 230, a via-2 (V2) layer may be formed above and coupled to the M1 layer in the dielectric region 230, a metal-2 (M2) layer may be formed above and electrically coupled to the V2 layer in the dielectric region 230, and so on.

[0079] As described above, Figures 2A to 2QQ This is provided as an example only. Other examples can be found in the Figures 2A to 2QQ Different than described.

[0080] Figures 3A to 3C is a diagram of an example 300 of a photonic integrated circuit 102 described herein. The photonic integrated circuit 102 may include an optical coupling circuit including an edge coupler waveguide 104, a polarization-splitting rotator waveguide 106, and a coupling waveguide 108 optically coupled to the edge coupler waveguide 104 and the polarization-splitting rotator waveguide 106. In some embodiments, the photonic integrated circuit 102 may be included in a semiconductor device, such as the semiconductor device 202 described herein.

[0081] like Figures 3A to 3C As shown, an example 300 of the photonic integrated circuit 102 includes Figures 1A to 1C The example 100 of the photonic integrated circuit 102 is similar in component combination and arrangement. However, in Figures 3A to 3CIn the example 300 of the photonic integrated circuit 102, the tapered portion 138 of the coupling waveguide 108 has a sidewall angle (at Figure 3C The sidewall angle is approximately equal to the dimension D1 and the dimension D2. For example, the dimension D9 may also be in the range of about 86 degrees to about 88 degrees because the tapered portion 138 of the coupling waveguide 108 may be formed together with the tapered portion 136 of the coupling waveguide 108, as shown in FIG. Figures 4A to 4L Described in .

[0082] As mentioned above, Figures 3A to 3C is provided as an example. Other examples can be found in the Figures 3A to 3C Different than described.

[0083] Figures 4A to 4L is formed Figures 3A to 3C 100 of an exemplary embodiment 400 of the photonic integrated circuit 102 described in

[0028] In some embodiments, Figures 4A to 4L The relevant one or more semiconductor process operations can be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools and / or wafer / die transfer tools. Figures 4A to 4L One or more of the diagrams is from Figure 3A Top view of Figure 3B A cross-section along line AA, and / or Figure 3C The cross-sections along the BB, CC, DD and EE lines are drawn.

[0084] like Figures 4A to 4C As shown, the executable Figures 2A to 2L Related operations are performed to form the polarization splitting rotator waveguide 106 and the coupling waveguide 108 in the semiconductor layer 210, each waveguide being formed to a first depth corresponding to a first thickness (dimension D6).

[0085] like Figures 4A to 4C As further shown, the patterned mask layer 216 is formed in the same manner as Figures 2M to 2O , but in embodiment 400, the patterned mask layer 216 is also formed on the tapered portion 138 and the transition portion 140 of the coupling waveguide 108. Figure 4C As shown, a portion of the polarization splitting rotator waveguide 106 located above the tapered portion 138 of the coupling waveguide 108 is covered by the patterned mask layer 216. Other portions of the polarization splitting rotator waveguide 106 are exposed through the patterned mask layer 216.

[0086] like Figures 4D to 4FAs shown, the portion of the semiconductor layer 210 exposed through the patterned mask layer 216 can be etched. An etching operation can be performed using an etching tool to etch the portion of the semiconductor layer 210 surrounding the exposed portion of the polarization splitting rotator waveguide 106. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations.

[0087] The etching operation can be performed through the semiconductor layer 210 and into the dielectric layer 208 to increase the exposed portion of the polarization-splitting rotator waveguide 106 to a second thickness (dimension D7). The patterned mask layer 216 protects the coupling waveguide 108 and the portion of the polarization-splitting rotator waveguide 106 located above the tapered portion 138 of the coupling waveguide 108 from being etched during the etching operation. Therefore, after the etching operation, the coupling waveguide 108 and the portion of the polarization-splitting rotator waveguide 106 located above the tapered portion 138 of the coupling waveguide 108 remain within the semiconductor layer 210 at a first depth corresponding to the first thickness (dimension D6). Furthermore, the etching operation causes the exposed portion of the polarization-splitting rotator waveguide 106, including the through-segment 116 of the polarization-splitting rotator waveguide 106 at the cross-sectional location formed by the EE line and the cross-segment 118 of the polarization-splitting rotator waveguide 106 at the cross-sectional location formed by the EE line, to have sidewall angles corresponding to dimensions D4 and D5, respectively. In some embodiments, dimension D4 and dimension D5 are each within a range of about 80 degrees to about 85 degrees. However, other ranges of values ​​are also within the scope of the present disclosure.

[0088] like Figures 4G to 4I As shown, when executing Figures 4D to 4F After the relevant etching operation, the remaining portion of the patterned mask layer 216 can be removed. Figures 4G to 4I As further shown, in the execution Figures 4D to 4F A patterned mask layer 218 is formed over the portions of the polarization splitting rotator waveguide 106 that were etched during the associated etching operation.

[0089] like Figures 4J to 4L As shown, the portion of the remaining semiconductor layer 210 exposed by the patterned mask layer 218 can be etched. An etching operation can be performed using an etching tool to etch the portion of the remaining semiconductor layer 210 surrounding the coupling waveguide 108. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. The etching operation can be performed to penetrate the semiconductor layer 210 and reach the dielectric layer 208 to increase the thickness of the coupling waveguide 108 to a second thickness (dimension D7). The patterned mask layer 218 protects the polarization splitting rotator waveguide 106 from being etched during the etching operation.

[0090] In this manner, a first set of masking and etching operations (e.g. Figures 4A to 4F) to form the polarization splitting rotator waveguide 106, and performing a second set of masking and etching operations (as Figures 4G to 4L The coupling waveguide 108 is etched to form the tapered portion 136, the tapered portion 138, and the transition portion 140 of the coupling waveguide 106. Thus, the coupling waveguide 108 can be etched in such a manner that the sidewall angle of the coupling waveguide 108 is greater than the sidewall angle of the polarization splitting rotator waveguide 106. In some embodiments, dimension D1, dimension D2, and dimension D9 of the coupling waveguide 108 are each within a range of approximately 86 degrees to approximately 88 degrees. However, other ranges are also within the scope of the present disclosure.

[0091] As mentioned above, Figures 4A to 4L The system is provided as an example. Other examples can be found in the reference Figures 4A to 4L The ones described are different.

[0092] 5A to 5I To form and Figures 1A to 1C Schematic diagram of an embodiment 500 of an example 100 of a photonic integrated circuit 102 described in the related art. In some embodiments, 5A to 5I One or more semiconductor process operations described herein may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools, and / or wafer / die transfer tools. 5A to 5I One or more diagrams in Figure 1C Cross-sectional views of lines BB, CC, DD and EE.

[0093] and 5A to 5I The operations described can be used as Figures 2M to 2R An alternative process to the operations described above for etching the semiconductor layer 210 to form the polarization splitting rotator waveguide 106 is performed. In particular, 5A to 5I The illustrated embodiment 500 includes performing multiple mask and etch cycles to gradually etch the semiconductor layer 210 to form the polarization splitting rotator waveguide 106. 5A to 5I The order of operations described herein is an example, including an example number of mask and etch cycles (e.g., 3 mask and etch cycles). However, other numbers of mask and etch cycles may be performed using the same 5A to 5I Similar techniques as described above are used to gradually etch the semiconductor layer 210 to form the polarization separation rotator waveguide 106. Additionally and / or alternatively, 5A to 5I The related described techniques can be used to gradually etch the semiconductor layer 210 to Figures 3A to 3C The example 300 of the photonic integrated circuit 102 described above forms a polarization splitting rotator waveguide 106 .

[0094] like Figure 5AAs shown, a first patterned mask layer 216a may be formed over the coupling waveguide 108, including the tapered portion 136. In some embodiments, the first patterned mask layer 216a is also formed over the tapered portion 138 and / or the transition portion 140 of the coupling waveguide 108.

[0095] like Figure 5B As shown, the semiconductor layer 210 surrounding the polarization splitting rotator waveguide 106 may be etched while the first patterned mask layer 216a protects the coupling waveguide 108 to increase the thickness of the polarization splitting rotator waveguide 106 from a first thickness (dimension D6) to a first intermediate thickness (at Figure 5B Indicated as dimension D10).

[0096] like Figure 5C As shown, the remaining portions of the first patterned mask layer 216a may be removed using a photoresist removal tool, chemical strippers, plasma ashing, and / or other techniques. Figures 5A to 5C May correspond to the first mask and etch cycle.

[0097] like Figure 5D As shown, a second patterned mask layer 216b may be formed over the coupling waveguide 108, including the tapered portion 136. In some embodiments, the second patterned mask layer 216b is also formed over the tapered portion 138 and / or the transition portion 140 of the coupling waveguide 108.

[0098] like Figure 5E As shown, the semiconductor layer 210 surrounding the polarization splitting rotator waveguide 106 can be etched while the second patterned mask layer 216b protects the coupling waveguide 108 to increase the thickness of the polarization splitting rotator waveguide 106 from a first intermediate thickness (dimension D10) to a second intermediate thickness (dimension D10). Figure 5E Indicated as dimension D11).

[0099] like Figure 5F As shown, the remaining portion of the second patterned mask layer 216b may be removed using a photoresist removal tool, chemical strippers, plasma ashing, and / or other techniques. Figures 5D to 5F May correspond to the second mask and etch cycle.

[0100] like Figure 5G As shown, a third patterned mask layer 216c may be formed over the coupling waveguide 108, including the tapered portion 136. In some embodiments, the third patterned mask layer 216c is also formed over the tapered portion 138 and / or the transition portion 140 of the coupling waveguide 108.

[0101] like Figure 5HAs shown, the semiconductor layer 210 surrounding the polarization splitting rotator waveguide 106 may be etched while the second patterned mask layer 216b protects the coupling waveguide 108 to etch through the semiconductor layer 210 and increase the thickness of the polarization splitting rotator waveguide 106 from the second intermediate thickness (dimension D11) to the second thickness (dimension D7).

[0102] like Figure 5I As shown, the remaining portion of the third patterned mask layer 216c can be removed using a photoresist removal tool by chemical strippers, plasma ashing, and / or other techniques. Figures 5G to 5I May correspond to the third mask and etch cycle.

[0103] As indicated above, 5A to 5I Provided as an example. Other examples may differ from those regarding 5A to 5I The content described.

[0104] Figure 6 is a flow chart of an example process 600 associated with forming the photonic integrated circuit 102 described herein. In some embodiments, one or more semiconductor process tools are used to perform Figure 6 One or more process blocks, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools and / or other types of semiconductor process tools.

[0105] like Figure 6 As shown, process 600 may include performing one or more first etching operations to form a first waveguide in a semiconductor layer of semiconductor device 202 (block 610). For example, one or more semiconductor process tools may be used to perform the one or more first etching operations to form a first waveguide (e.g., coupling waveguide 108) in a semiconductor layer (e.g., semiconductor layer 210) of semiconductor device 202 (as described herein).

[0106] like Figure 6 As further shown in FIG6 , process 600 may include performing one or more second etching operations to form a second waveguide in the semiconductor layer (block 620). For example, one or more semiconductor process tools may be used to perform the one or more second etching operations to form a second waveguide (e.g., polarization splitting rotator waveguide 106) in the semiconductor layer, as described herein. In some embodiments, the first end of the first waveguide is physically coupled to the second waveguide.

[0107] like Figure 6As further shown in FIG6 , process 600 may include forming a third waveguide in a dielectric layer such that a portion of the third waveguide is positioned above a second end of the first waveguide opposite the first end (block 630). For example, a third waveguide (e.g., edge coupler waveguide 104) may be formed in a dielectric layer (e.g., dielectric layer 220) using one or more semiconductor process tools such that a portion of the third waveguide (e.g., tapered portion 112) is positioned above a second end of the first waveguide opposite the first end, as described herein. In some embodiments, a first angle (e.g., dimension D1, dimension D2) of a portion of the first waveguide below the third waveguide portion (e.g., tapered portion 136) between a sidewall of the first waveguide portion and a bottom surface of the first waveguide portion and a second angle (e.g., dimension D4, dimension D5) between a sidewall of the second waveguide and a bottom surface of the second waveguide are different angles.

[0108] Process 600 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0109] In the first embodiment, the first angle is greater than the second angle.

[0110] In a second embodiment, alone or in combination with the first embodiment, the first angle is contained within a range of about 86 degrees to about 88 degrees, and the second angle is contained within a range of about 80 degrees to about 85 degrees.

[0111] In a third embodiment, alone or in combination with one or more of the first and second embodiments, performing the one or more second etching operations includes performing the one or more second etching operations after performing the one or more first etching operations.

[0112] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, a third angle (e.g., dimension D9) at which the first waveguide is physically coupled to another portion of the second waveguide (e.g., the tapered portion 138) (the angle being between a sidewall of the other portion of the first waveguide and a bottom surface of the other portion of the first waveguide), and the second angle, are different angles.

[0113] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the third angle is greater than the second angle.

[0114] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 600 includes performing a third etching operation to begin forming the first waveguide and the third waveguide in the semiconductor layer 210 before performing the one or more first etching operations and the one or more second etching operations.

[0115] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, performing one or more first etching operations includes performing the one or more first etching operations using a first set of plasma-based etching parameters, and performing one or more second etching operations includes performing the one or more second etching operations using a second set of plasma-based etching parameters, and the first set of plasma-based etching parameters is different from the second set of plasma-based etching parameters.

[0116] In an eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, the first set of plasma-based etching parameters includes a first plasma bias, the second set of plasma-based etching parameters includes a second plasma bias, and the first plasma bias is greater than the second plasma bias.

[0117] although Figure 6 Several example blocks of process 600 are shown, but in some embodiments, process 600 includes Figure 6 The blocks shown may be more blocks, fewer blocks, different blocks, or blocks in a different arrangement. Additionally or alternatively, two or more blocks of process 600 may be performed in parallel.

[0118] Figure 7 is a flow chart of an example process 700 associated with forming the photonic integrated circuit 102 described herein. In some embodiments, Figure 7 One or more process blocks are performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0119] like Figure 7 As shown, process 700 may include etching the semiconductor layer 210 of the semiconductor device 202 to form a first waveguide and a second waveguide, each having a first thickness (block 710). For example, one or more semiconductor process tools may be used to etch the semiconductor layer 210 of the semiconductor device 202 to form a first waveguide (e.g., the coupling waveguide 108) and a second waveguide (e.g., the polarization splitting rotator waveguide 106), each having a first thickness (e.g., dimension D6), as described herein. In some embodiments, a first end (e.g., the tapered portion 138) of the first waveguide is physically coupled to the second waveguide.

[0120] like Figure 7As further shown, the process 700 may include forming one or more first mask layers over at least a portion of the tapered portion at the second end (opposite the first end) of the first waveguide (block 720). For example, one or more first mask layers (e.g., patterned mask layer 216, patterned mask layer 216a, patterned mask layer 216b, patterned mask layer 216c) may be formed over at least a portion of the tapered portion (e.g., tapered portion 136) at the second end (opposite the first end) of the first waveguide using one or more semiconductor processing tools, as described herein.

[0121] like Figure 7 As further shown, the process 700 may include performing one or more first etching operations to etch the semiconductor layer 210 while the one or more first mask layers are positioned over at least a portion of the tapered portion of the first waveguide to increase the thickness of the second waveguide from the first thickness to a second thickness (block 730). For example, one or more semiconductor process tools may be used to perform one or more first etching operations to etch the semiconductor layer 210 while the one or more first mask layers are positioned over at least a portion of the tapered portion of the first waveguide to increase the thickness of the second waveguide from the first thickness to a second thickness (e.g., dimension D7), as described herein.

[0122] like Figure 7 As further shown, the process 700 may include forming a second mask layer over the second waveguide after performing the one or more first etching operations (block 740). For example, the second mask layer (e.g., patterned mask layer 218) may be formed over the second waveguide after performing the one or more first etching operations using one or more semiconductor processing tools, as described herein.

[0123] like Figure 7 As further shown, the process 700 may include performing a second etching operation while the second mask layer is positioned over the second waveguide to etch the semiconductor layer 210 to increase the thickness of the first waveguide from the first thickness to the second thickness (block 750). For example, the second etching operation may be performed using one or more semiconductor processing tools while the second mask layer is positioned over the second waveguide to etch the semiconductor layer 210 to increase the thickness of the first waveguide from the first thickness to the second thickness, as described herein.

[0124] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0125] In a first embodiment, process 700 includes removing one or more first mask layers before forming the second mask layer.

[0126] In a second embodiment, either alone or in combination with the first embodiment, a first angle (e.g., dimension D1, dimension D2) between a sidewall of the tapered portion of the first waveguide and a bottom surface of the tapered portion of the first waveguide is greater than a second angle (e.g., dimension D4, dimension D5) between a sidewall of the second waveguide and a bottom surface of the second waveguide.

[0127] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming one or more first mask layers and performing one or more first etching operations include: forming a first photoresist layer (e.g., patterned mask layer 216a) in one or more first mask layers over at least a portion of the tapered portion of the first waveguide; performing a first trench etching operation in one or more first etching operations simultaneously with the first photoresist layer over at least a portion of the tapered portion of the first waveguide to etch the semiconductor layer 210 to increase the thickness of the second waveguide; forming a second photoresist layer (e.g., patterned mask layer 216b, patterned mask layer 216c) in one or more first mask layers over at least a portion of the tapered portion of the first waveguide; and performing a second trench etching operation in one or more first etching operations simultaneously with the second photoresist layer over at least a portion of the tapered portion of the first waveguide to etch the semiconductor layer 210 to increase the thickness of the second waveguide.

[0128] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 700 includes removing the first photoresist layer before forming the second photoresist layer.

[0129] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 700 includes: forming a third photoresist layer (e.g., patterned mask layer 216c) in one or more first mask layers above at least a portion of the tapered portion of the first waveguide; and performing a third trench etching operation in one or more first etching operations while the third photoresist layer is positioned above at least a portion of the tapered portion of the first waveguide to etch the semiconductor layer 210 to increase the thickness of the second waveguide.

[0130] Although Figure 7 Example blocks of process 700 are shown, but in some implementations, process 700 may include Figure 7 7. Additionally or alternatively, two or more blocks of process 700 may be performed in parallel.

[0131] In this manner, a photonic integrated circuit of a semiconductor device is fabricated to include a polarization-splitting rotator waveguide, an edge coupler waveguide, and a coupling waveguide, wherein the coupling waveguide is optically coupled to the polarization-splitting rotator waveguide and the edge coupler waveguide. The polarization-splitting rotator waveguide and the coupling waveguide are fabricated to have different sidewall angles. Specifically, the polarization-splitting rotator waveguide can be fabricated to have a smaller sidewall angle than the coupling waveguide, while the coupling waveguide can be fabricated to have a larger sidewall angle than the polarization-splitting rotator waveguide. The smaller sidewall angle of the polarization-splitting rotator waveguide sidewall results in the polarization-splitting rotator waveguide having a greater amount of sidewall taper, which enables high gap-filling performance when a dielectric layer is formed above the polarization-splitting rotator waveguide. The larger sidewall angle of the coupling waveguide sidewall results in the coupling waveguide having a smaller sidewall taper (e.g., a more vertical sidewall), which provides a larger surface area on top of the coupling waveguide to increase coupling efficiency and reduce optical signal loss from coupling an input optical signal from the edge coupler waveguide to the coupling waveguide.

[0132] As described in more detail above, some embodiments described herein provide a method for forming a photonic integrated circuit. The method includes performing one or more first etching operations to form a first waveguide in a semiconductor layer of a semiconductor device. The method includes performing one or more second etching operations to form a second waveguide in the semiconductor layer, wherein a first end of the first waveguide is physically coupled to the second waveguide. The method includes forming a third waveguide in a dielectric layer such that a portion of the third waveguide is located above a second end of the first waveguide opposite the first end, wherein a first angle of a portion of the first waveguide below the third waveguide portion (the angle between a sidewall of the portion of the first waveguide and a bottom surface of the portion of the first waveguide) and a second angle between a sidewall of the second waveguide and the bottom surface of the second waveguide are different angles.

[0133] As described in more detail above, some embodiments described herein provide a method for forming a photonic integrated circuit. The method includes etching a semiconductor layer of a semiconductor device to form a first waveguide and a second waveguide, each waveguide having a first thickness, wherein a first end of the first waveguide is physically coupled to the second waveguide. The method includes forming one or more first mask layers over at least a portion of a tapered portion of a second end of the first waveguide opposite the first end. The method includes performing one or more first etching operations to etch the semiconductor layer while the one or more first mask layers cover at least the portion of the tapered portion of the first waveguide, thereby increasing the thickness of the second waveguide from the first thickness to a second thickness. The method includes forming a second mask layer over the second waveguide after performing the one or more first etching operations. The method includes performing a second etching operation to etch the semiconductor layer while the second mask layer covers the second waveguide, thereby increasing the thickness of the first waveguide from the first thickness to the second thickness.

[0134] As described in more detail above, some embodiments described herein provide a photonic integrated circuit. The photonic integrated circuit includes a first waveguide. A semiconductor device includes a second waveguide physically coupled to a first end of the first waveguide. The semiconductor device includes a third waveguide located above a second end of the first waveguide opposite the first end, wherein a first sidewall angle of the first waveguide at the second end is greater than a second sidewall angle of a portion of the second waveguide not physically contacting the first waveguide.

[0135] The terms "approximately" and "substantially" may indicate that the numerical value of a given quantity varies within 5% of the numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the numerical value). These numerical values ​​are merely examples and are not limiting. It should be understood that the terms "approximately" and "substantially" may refer to a percentage of the numerical value of a given quantity according to the present disclosure.

[0136] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a photonic integrated circuit, characterized in that: include: performing one or more first etching operations to form a first waveguide in a semiconductor layer of the semiconductor device; performing one or more second etching operations to form a second waveguide in the semiconductor layer, wherein the first end of the first waveguide is physically coupled to the second waveguide; and forming a third waveguide in the dielectric layer such that a portion of the third waveguide is located above a second end of the first waveguide opposite the first end, wherein the portion of the first waveguide below the portion of the third waveguide has a first angle between a sidewall of the portion of the first waveguide and a bottom surface of the portion of the first waveguide, wherein the second waveguide has a second angle, the second angle being located between a sidewall of the second waveguide and a bottom surface of the second waveguide, and The first angle and the second angle are different angles.

2. The method according to claim 1, characterized in that The first angle is greater than the second angle.

3. The method according to claim 1, characterized in that A third angle of the other portion of the first waveguide physically coupled to the second waveguide and the second angle are different angles, the third angle being located between a sidewall of the other portion of the first waveguide and a bottom surface of the other portion of the first waveguide.

4. A method for forming a photonic integrated circuit, characterized in that: include: etching a semiconductor layer of the semiconductor device to form a first waveguide and a second waveguide, each having a first thickness, wherein the first end of the first waveguide is physically coupled to the second waveguide; forming one or more first mask layers over at least a portion of the tapered portion of the first waveguide at a second end of the second waveguide opposite the first end; performing one or more first etching operations to etch the semiconductor layer to increase the thickness of the second waveguide from the first thickness to a second thickness while the one or more first mask layers are positioned over the at least a portion of the tapered portion of the first waveguide; forming a second mask layer over the second waveguide after performing the one or more first etching operations; and When the second mask layer is located above the second waveguide, a second etching operation is performed to etch the semiconductor layer to increase the thickness of the first waveguide from the first thickness to the second thickness.

5. The method according to claim 4, characterized in that A first angle between a sidewall of the tapered portion of the first waveguide and a bottom surface of the tapered portion of the first waveguide is greater than a second angle between a sidewall of the second waveguide and a bottom surface of the second waveguide.

6. A photonic integrated circuit, characterized in that: include: First Waveguide; a second waveguide physically coupled to the first end of the first waveguide; as well as a third waveguide located on a second end of the first waveguide opposite to the first end, A first sidewall angle of the first waveguide at the second end is greater than a second sidewall angle of a portion of the second waveguide spaced apart from the first waveguide.

7. The photonic integrated circuit according to claim 6, wherein: wherein the first waveguide comprises a first semiconductor waveguide; wherein the second waveguide comprises a second semiconductor waveguide; and Wherein, the third waveguide includes a dielectric waveguide.

8. The photonic integrated circuit according to claim 6, wherein: The first sidewall angle is within a range of about 86 degrees to about 88 degrees.

9. The photonic integrated circuit according to claim 6, wherein: The first waveguide comprises: a first tapered portion located at said second end of said first waveguide, wherein the first tapered portion is located below a portion of the third waveguide; and a second tapered portion located at said first end of said first waveguide, The second tapered portion is physically coupled to the second waveguide.

10. The photonic integrated circuit according to claim 7, wherein: wherein the first waveguide comprises a coupled waveguide; wherein the second waveguide comprises a polarization splitting rotator waveguide; and Wherein, the third waveguide comprises an edge coupler waveguide.

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