Processing method and electronic equipment

Abstract

The invention provides a processing method and electronic equipment, and the method comprises the steps: responding to the operation of a first system, and determining first information of a plurality of processing cores of a target processor; the first information is used for reflecting the processing performance of the corresponding processing core; in response to execution of the target task in the second system, determining at least one target processing core based on the first information of each processing core, so as to execute the target task based on the at least one target processing core; wherein the first system is different from the second system, and the first system is used for guiding the second system.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a processing method and electronic device. Background Art

[0002] In the related art, a multi-core processor cannot fully utilize the potential of multiple processing cores of the multi-core processor when processing tasks, resulting in low task execution efficiency. Summary of the Invention

[0003] The present disclosure provides a processing method and an electronic device.

[0004] According to one aspect of the present disclosure, a processing method is provided, comprising: in response to operation of a first system, determining first information of multiple processing cores of a target processor; the first information being used to reflect processing performance of the corresponding processing cores; and in response to executing a target task in a second system, determining at least one target processing core based on the first information of each processing core, so as to execute the target task based on the at least one target processing core; wherein the first system is different from the second system, and the first system is used to guide the second system.

[0005] According to an embodiment of the present disclosure, in response to the operation of the first system, first information of multiple processing cores of the target processor is determined, including: in response to the operation of the first system, enabling the target function; in response to the enabling of the target function, restarting the electronic device and running the target function to divide the multiple processing cores into at least one first processing core and at least one second processing core; wherein the first information includes the division of the processing cores, and the frequency of the first processing core is higher than the frequency of the second processing core.

[0006] According to an embodiment of the present disclosure, running a target function to divide a plurality of processing cores into at least one first processing core and at least one second processing core includes: reading second information of the plurality of processing cores; the second information is obtained by testing the physical capabilities of the processing cores, including one or more of electrical characteristics under different loads, leakage rate, heat dissipation capability, and frequency adjustment capability in different temperature ranges; and setting the frequency of each processing core based on the second information to obtain at least one first processing core and at least one second processing core.

[0007] According to an embodiment of the present disclosure, in response to executing a target task in a second system, at least one target processing core is determined based on first information of each processing core, including: determining task characteristics of the target task; based on the task characteristics, determining a setting strategy; based on the setting strategy, determining at least one target processing core from at least one first processing core and / or at least one second processing core; the target processing core includes the first processing core and / or the second processing core.

[0008] According to an embodiment of the present disclosure, a setting strategy is determined based on task characteristics, and based on the setting strategy, at least one target processing core is determined from at least one first processing core and / or at least one second processing core, including: determining a first setting strategy in response to executing a target task having a first task characteristic; the first task characteristic characterizing that the task requires parallel computing using multiple processing cores; when at least one first processing core can meet the requirements for running the target task, determining multiple processing cores from at least one first processing core as target processing cores; when at least one first processing core cannot meet the requirements for running the target task, processing at least one first processing core and at least one second processing core to determine at least one target processing core.

[0009] According to an embodiment of the present disclosure, at least one first processing core and at least one second processing core are processed to determine at least one target processing core, including: in response to the frequency of the at least one second processing core being unable to change, all the first processing cores are used as target processing cores, and a first number of second processing cores are determined from the at least one second processing core as target processing cores; in response to the frequency of the at least one second processing core being able to change, all the first processing cores are used as target processing cores, and the frequency of the second processing cores whose frequency can be changed is reduced to increase the frequency of the at least one first processing core.

[0010] According to an embodiment of the present disclosure, it also includes: obtaining operating parameters of at least one second processing core; if the operating parameters indicate that all second processing cores are loaded with tasks, determining that the frequency of at least one second processing core cannot be changed; if the operating parameters indicate that all second processing cores are loaded with tasks but there is a task whose second processing core load meets a first condition, determining that the frequency of at least one second processing core can be changed; the first condition indicates that the task priority is lower than the target task.

[0011] According to an embodiment of the present disclosure, a setting strategy is determined based on task characteristics, and based on the setting strategy, at least one target processing core is determined from at least one first processing core and / or at least one second processing core, including: determining a second setting strategy in response to executing a target task with a second task characteristic; the second task characteristic characterizing that the task needs to be calculated using a single processing core; and determining a target processing core from at least one first processing core based on the second setting strategy.

[0012] According to an embodiment of the present disclosure, a setting strategy is determined based on task characteristics, and based on the setting strategy, at least one target processing core is determined from at least one first processing core and / or at least one second processing core, including: determining a third setting strategy in response to executing a target task with a third task characteristic; the third task characteristic characterizes that the task requires the use of multiple processing cores for parallel computing, and requires the processor's main frequency to meet a second condition; adjusting the main frequency of the target processor to be greater than a target threshold, and determining a number of processing cores greater than the second number from at least one first processing core and / or at least one second processing core as target processing cores.

[0013] Another aspect of the present disclosure provides an electronic device, comprising: a first system, a second system, at least one processor, and a memory communicatively connected to the at least one processor; wherein the at least one processor has multiple processing cores; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement: in response to the operation of the first system, determining first information of multiple processing cores of a target processor; the first information is used to reflect the processing performance of the corresponding processing cores; in response to executing a target task in the second system, determining at least one target processing core based on the first information of each processing core, so as to execute the target task based on the at least one target processing core.

[0014] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0016] Figure 1 is a flowchart of a processing method according to an embodiment of the present disclosure;

[0017] Figure 2 is a flowchart of a processing method according to another embodiment of the present disclosure;

[0018] Figure 3 is a flowchart of a processing method according to another embodiment of the present disclosure;

[0019] Figure 4 is a structural diagram of an electronic device according to an embodiment of the present disclosure; and

[0020] Figure 5 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0022] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision, disclosure and application of the data involved (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, take necessary confidentiality measures, and do not violate public order and good morals.

[0023] In some cases, the default operating system scheduling policy in multi-core processors is inadequate. Tasks are randomly assigned to processing cores without distinguishing between the processing performance of different cores, such as performance cores (P-Cores) and energy-efficiency cores (E-Cores). For example, the real-time modeling thread of industrial modeling software may be assigned to an E-Core, resulting in increased response latency. For example, tasks are randomly assigned to processing cores without distinguishing between the performance cores (P-Cores) and energy-efficiency cores (E-Cores). For example, the real-time modeling thread of industrial software SolidWorks may be assigned to an E-Core, resulting in increased response latency.

[0024] It can be seen that in some examples, the multi-core processor cannot fully utilize the potential of multiple processing cores of the multi-core processor when processing tasks, resulting in low task execution efficiency.

[0025] Figure 1 is a flowchart of a processing method according to an embodiment of the present disclosure.

[0026] like Figure 1 As shown, the processing method of this embodiment includes operations S110-S120.

[0027] In operation S110 , in response to the operation of the first system, first information of a plurality of processing cores of a target processor is determined; the first information is used to reflect the processing performance of the corresponding processing cores.

[0028] In the embodiments of the present disclosure, the target processor is provided in an electronic device. The electronic device may be a computer, such as a laptop or desktop computer. The electronic device may be a mobile device, such as a smartphone or tablet computer. The electronic device may be a gaming device, such as a game console or handheld game console. The electronic device may be an embedded dedicated device, such as a network device or smart home device. The electronic device may also be a server or data center device, such as a server or storage device.

[0029] In the embodiments of the present disclosure, the target processor includes multiple processing cores. The target processor integrates multiple independent computing units (processing cores) on a single physical chip. All processing cores of the target processor are located on the same silicon die or interconnected through advanced packaging. Each processing core is an independent unit with full instruction execution capabilities and can independently run operating system threads.

[0030] In an embodiment of the present disclosure, the first system may be the first system executed by the electronic device after power-on. The first system may be used to initialize the hardware of the electronic device, load some functions of the electronic device, or guide the loading of the second system.

[0031] For example, the first system may be a Basic Input / Output System (BIOS).

[0032] In an embodiment of the present disclosure, first information about multiple processing cores of a target processor is determined. The first information is used to reflect the processing performance of the corresponding processing core. For example, the first information may reflect the strength of the processing performance of the corresponding processing core. Processing cores with high processing performance can handle tasks with high real-time requirements and intensive computations (such as game rendering, 3D modeling, and scientific computing). Processing cores with low processing performance can handle background tasks, low-priority tasks, or periodic tasks (such as file downloads, data synchronization, and push notifications).

[0033] In the embodiments of the present disclosure, the processing performance of a processing core refers to the comprehensive ability of a single processing core to execute computing tasks. Essentially, it reflects the efficiency with which a hardware unit converts electrical energy into effective computing output. This performance can include computational throughput (the number of instructions completed per unit time), task response speed (the end-to-end latency from instruction fetch to result output), and energy efficiency conversion rate (the amount of effective computing generated per watt of power consumption).

[0034] In the embodiments of the present disclosure, the processing efficiency of the processing core may be measured by indicators in multiple dimensions.

[0035] For example, frequency can be used to measure the processing performance of a processing core. The higher the frequency, the more instructions the processing core executes per unit time, and the stronger the processing performance of the processing core.

[0036] For example, the number of instructions per cycle can be used to measure the processing performance of a processing core. The number of instructions per cycle refers to the number of instructions that can be executed in each clock cycle. The higher the number of instructions per cycle of a processing core, the stronger the processing performance of the processing core.

[0037] For example, cache size and latency can be used to measure the processing performance of a processing core. A processing core with higher processing performance typically has a larger private cache, which can reduce the latency of accessing memory and increase data access speed.

[0038] For example, the energy efficiency ratio can be used to measure the processing performance of a processing core. A processing core with strong processing performance has a higher energy efficiency ratio (performance per watt) than a processing core with weak processing performance.

[0039] In operation S120 , in response to executing the target task in the second system, at least one target processing core is determined based on the first information of each processing core to execute the target task based on the at least one target processing core, wherein the first system is different from the second system and the first system is used to guide the second system.

[0040] In embodiments of the present disclosure, the second system may be the operating system (OS) of the electronic device. After the first system (BIOS) completes hardware initialization, it transfers control to the second system (OS), which then takes full control of the hardware resources. The second system is the system software responsible for managing both hardware and software resources within the electronic device.

[0041] In an embodiment of the present disclosure, in response to executing a target task in a second system, at least one target processing core is determined based on first information about each processing core, so that the target task is executed based on the at least one target processing core. The at least one target processing core is the optimal processing core for executing the target task. The number of processing cores to execute the target task and their corresponding performance can be determined based on the target task.

[0042] For example, when a target task requires a processing core with higher processing performance, a target processing core with satisfactory processing performance can be determined based on the first information of each processing core. For example, when a target task requires multiple processing cores with lower processing performance, multiple target processing cores with satisfactory processing performance can be determined based on the first information of each processing core.

[0043] Through the embodiments of the present disclosure, first information of multiple processing cores is determined when the first system is running. Since the first information can reflect the processing performance of each processing core, when executing a target task in the second system, at least one target processing core that can efficiently process the target task can be determined based on the first information of each processing core. By executing the target task based on at least one target processing core, the potential of multiple processing cores of the multi-core processor can be fully utilized, the execution efficiency of the target processor can be improved, and the power consumption can be reduced.

[0044] Figure 2 is a flowchart of a processing method according to another embodiment of the present disclosure.

[0045] like Figure 2As shown, in some embodiments of the present disclosure, in response to the operation of the first system, first information of multiple processing cores of the target processor is determined, including operations S210-S220.

[0046] In operation S210 , in response to the operation of the first system, a target function is enabled.

[0047] In operation S220, in response to enabling the target function, the electronic device is restarted and the target function is run to divide the multiple processing cores into at least one first processing core and at least one second processing core; wherein the first information includes the division of the processing cores, and the frequency of the first processing core is higher than the frequency of the second processing core.

[0048] In an embodiment of the present disclosure, the target function may be a function for dividing the processing performance of a plurality of processing cores of a target processor.

[0049] For example, the target function may be the core power dynamic allocation function (Intel Speed ​​Select: CorePower, SST-CP).

[0050] In an embodiment of the present disclosure, after enabling a target function, the electronic device is restarted and the target function is run to divide the multiple processing cores into at least one first processing core and at least one second processing core. The first information includes the division of the processing cores, that is, the first information includes whether each of the multiple processing cores of the target processor is the first processing core or the second processing core.

[0051] In the embodiments of the present disclosure, the frequency of the first processing core is higher than the frequency of the second processing core. Frequency can be used to measure the processing performance of a processing core. The higher the frequency, the more instructions the processing core executes per unit time, and the stronger the processing performance of the processing core. Therefore, the processing performance of the first processing core is stronger than that of the second processing core.

[0052] In an embodiment of the present disclosure, the first processing core may be a performance core, and the second processing core may be an energy efficiency core, wherein the processing performance of the performance core is stronger than that of the energy efficiency core. The first information is used to characterize whether the corresponding processing core is a performance core or an energy efficiency core.

[0053] According to the embodiments of the present disclosure, by dividing the processing core into a first processing core and a second processing core, the convenience of determining the target processing core based on the target task can be improved, thereby improving the accuracy and reliability of the processing method of this embodiment.

[0054] In some embodiments of the present disclosure, running a target function to divide multiple processing cores into at least one first processing core and at least one second processing core includes: reading second information of the multiple processing cores; the second information is obtained by testing the physical capabilities of the processing cores, including one or more of electrical characteristics, leakage rate, heat dissipation capability, and frequency adjustment capability in different temperature ranges under different loads; and setting the frequency of each processing core based on the second information to obtain at least one first processing core and at least one second processing core.

[0055] In an embodiment of the present disclosure, the second information is obtained by testing the physical capabilities of the processing core, and the second information includes physical capability test data of the processing core. The second information may be obtained based on factory test data of the electronic device. The second information may also be obtained by testing the processing core while the target function is running in response to activation of the target function.

[0056] In an embodiment of the present disclosure, the processor core physical characteristic dataset may be obtained through wafer-level testing. The second information may include one or more of electrical characteristics under different loads, leakage rate, heat dissipation capability, and frequency adjustment capability in different temperature ranges.

[0057] For example, the electrical characteristics may be obtained by measuring the maximum stable frequency at different voltages (0.5-1.3V) using a wafer test probe, where the maximum stable frequency of the first processing core is higher than the maximum stable frequency of the second processing core.

[0058] For example, the leakage rate may be obtained by recording the static current of the processing cores in a high temperature chamber, where the leakage rate of the first processing core is lower than the leakage rate of the second processing core.

[0059] For example, the heat dissipation capability can be obtained by measuring the temperature rise slope per unit power consumption using an infrared thermal imager. The temperature rise of the first processing core per unit power consumption is lower than the temperature rise of the second processing core per unit power consumption.

[0060] For example, the frequency adjustment capability in different temperature ranges can be obtained by obtaining the frequency reduction thresholds at different temperature points through stress testing. The first processing core can run at a higher frequency than the second processing core at the same temperature.

[0061] In an embodiment of the present disclosure, the frequency of each processing core is set based on the second information, resulting in at least one first processing core and at least one second processing core. Based on the second information, a processing core among the multiple processing cores of the electronic device that is more suitable for serving as the first processing core can be determined. After determining the processing core that is more suitable for serving as the first processing core, the frequency of the processing core can be adjusted to determine the first processing core. After determining the processing core that is more suitable for serving as the second processing core, the frequency of the processing core can be adjusted to determine the second processing core. The frequency of the first processing core is higher than the frequency of the second processing core.

[0062] In the embodiments of the present disclosure, setting the frequency of each processing core may include setting a base frequency, a maximum turbo frequency limit, and other frequencies for the processing core. By setting different frequencies for the first processing core and the second processing core, the power consumption allocation for the first processing core can be increased. Because the first processing core has the highest power efficiency and processing performance, increasing the power consumption allocation for the first processing core, while maintaining the same total power consumption, can improve the processing efficiency of the target processor.

[0063] For example, the base frequency refers to the lowest sustainable operating frequency of the processing core under standard heat dissipation conditions. The base frequency of the first processing core may be set higher than the base frequency of the second processing core.

[0064] For example, the maximum turbo frequency upper limit refers to the instantaneous maximum frequency of the processing core within the power consumption / temperature allowable range. The maximum turbo frequency upper limit of the first processing core can be set to be higher than the maximum turbo frequency upper limit of the second processing core.

[0065] Through the embodiments of the present disclosure, by classifying each processing core based on its physical capabilities, the physical characteristics of each processing core can be accurately identified, thereby accurately determining which processing cores are suitable for being designated as the first processing core and which processing cores are suitable for being designated as the second processing core among the multiple processing cores of the target processor. By setting a higher frequency for the first processing core, the performance of the first processing core can be maximized while maintaining the same total power consumption, thereby improving the efficiency and reliability of the processing method of this embodiment.

[0066] Figure 3 is a flowchart of a processing method according to another embodiment of the present disclosure.

[0067] like Figure 3 As shown, in some embodiments of the present disclosure, in response to executing a target task in the second system, at least one target processing core is determined based on first information of each processing core, including operations S310-S330.

[0068] In operation S310 , task characteristics of a target task are determined.

[0069] In operation S320 , a setting strategy is determined based on the task characteristics.

[0070] In operation S330 , at least one target processing core is determined from the at least one first processing core and / or the at least one second processing core based on the setting policy; the target processing core includes the first processing core and / or the second processing core.

[0071] In embodiments of the present disclosure, task characteristics may represent characteristics of a target task during execution. For example, task characteristics may include the frequency requirement of a processing core during execution of a target temperature. Task characteristics may also include the number of processing cores required during execution of a target temperature.

[0072] In an embodiment of the present disclosure, a setting strategy is determined based on task characteristics. The setting strategy may include the optimal type and number of processing cores required to execute the target task. Based on the setting strategy, at least one target processing core is determined from the at least one first processing core and / or the at least one second processing core.

[0073] For example, it may be determined based on a setting policy that a high-performance processing core is required to execute the target task, and therefore, a first processing core may be determined from the at least one first processing core as the target processing core.

[0074] For example, it may be determined based on a setting policy that executing a target task requires multiple processing cores to execute in parallel. Therefore, multiple target processing cores may be determined from at least one first processing core and / or at least one second processing core.

[0075] Through the embodiments of the present disclosure, setting strategies are determined based on task characteristics, and target processing cores are determined based on the setting strategies, which can improve the accuracy of the determined target processing cores, thereby improving the accuracy and reliability of the processing method of this embodiment.

[0076] In some embodiments of the present disclosure, a setting strategy is determined based on task characteristics, and based on the setting strategy, at least one target processing core is determined from at least one first processing core and / or at least one second processing core, including: determining a first setting strategy in response to executing a target task having a first task characteristic; the first task characteristic characterizing that the task requires parallel computing using multiple processing cores; when at least one first processing core can meet the target task operation, determining multiple processing cores from at least one first processing core as target processing cores; when at least one first processing core cannot meet the target task operation, processing at least one first processing core and at least one second processing core to determine at least one target processing core.

[0077] In an embodiment of the present disclosure, the first task feature characterization task requires parallel computing using multiple processing cores. The target task can be split into highly independent subtasks, supporting large-scale parallel processing. For example, the performance improvement of processing the target task can be positively correlated with the number of processing cores.

[0078] In an embodiment of the present disclosure, a first setting policy is determined in response to executing a target task having a first task characteristic. The number of processing cores required to execute the target task can be determined based on the first task characteristic of the target task. For example, if the target task can be split into n subtasks, each of which can be executed independently by a processing core, the first setting policy is to utilize n processing cores to execute the target task.

[0079] In an embodiment of the present disclosure, if at least one first processing core is capable of running a target task, that is, if the number of first processing cores in the target processor's multiple processing cores is sufficient to run the target task, n idle processing cores can be determined from the at least one first processing core as target processing cores. Prioritizing the first processing core with higher processing performance to execute the target task can improve the processing efficiency of the target task.

[0080] In an embodiment of the present disclosure, when at least one first processing core cannot meet the requirements for running the target task, that is, the number of first processing cores among the multiple processing cores of the target processor cannot meet the requirements for running the target task, at least one first processing core and at least one second processing core can be processed to determine at least one target processing core.

[0081] Through the embodiments of the present disclosure, when at least one first processing core is capable of meeting the target task operation, at least one first processing core is preferentially called to execute the target task, which can effectively improve the processing efficiency of the target task and thereby improve the efficiency of the processing method of this embodiment.

[0082] In some embodiments of the present disclosure, at least one first processing core and at least one second processing core are processed to determine at least one target processing core, including: in response to the frequency of the at least one second processing core being unable to change, taking all the first processing cores as target processing cores, and determining a first number of second processing cores from the at least one second processing core as target processing cores; in response to the frequency of the at least one second processing core being able to change, taking all the first processing cores as target processing cores, reducing the frequency of the second processing cores whose frequency can be changed to increase the frequency of the at least one first processing core.

[0083] In an embodiment of the present disclosure, when at least one first processing core cannot meet the requirements for executing a target task, and in response to the frequency of at least one second processing core being unable to change, at least one second processing core is called upon to execute a portion of the target task to meet the requirements for executing the target task. All first processing cores are used as target processing cores, and a first number of second processing cores are determined from the at least one second processing core as target processing cores.

[0084] For example, if a target task can be split into n subtasks, each of which can be independently executed by a processing core, the first setting strategy is to call n processing cores to execute the target task. The target processing cores ultimately determined include all first processing cores capable of executing the subtasks of the target task and a first number of second processing cores. If the number of first processing cores capable of executing all subtasks of the target task is a, and the first number is b, then a + b = n.

[0085] In an embodiment of the present disclosure, when at least one first processing core is unable to meet the target task operation, the frequency of at least one second processing core can be changed. In this case, the frequency of the first processing core can be affected by changing the frequency of the second processing core. All first processing cores are used as target processing cores, and the frequency of the second processing cores that can change the frequency is reduced to increase the frequency of at least one first processing core. Under the condition of the same total power consumption, by reducing the frequency of the second processing cores that can change the frequency, the power consumption allocation quota of the first processing core can be increased, the frequency of the first processing core can be increased, and the processing capability of the first processing core can be improved.

[0086] For example, the target task can be divided into n subtasks, each of which can be executed independently by a processing core, and some subtasks require the execution frequency of the processing core to reach the target frequency. The first setting strategy is to call n processing cores to execute the target task. When at least one first processing core cannot meet the target task operation, it may be that the number of processing cores in the first processing core that can execute the target task has reached n, but the frequency of some first processing cores cannot reach the target frequency. At this time, the frequency of at least one first processing core can be increased by reducing the frequency of the second processing core that can change the frequency, so that the frequency of some first processing cores can reach the target frequency, thereby meeting the operation of the target task.

[0087] According to the embodiments of the present disclosure, when the first processing core cannot meet the target task operation requirements, the target processing core is determined according to the frequency of the second processing core, which can further improve the accuracy of the determined target processing core.

[0088] In some embodiments of the present disclosure, the method further includes: obtaining operating parameters of at least one second processing core; if the operating parameters indicate that all second processing cores are loaded with tasks, determining that the frequency of at least one second processing core cannot be changed; if the operating parameters indicate that all second processing cores are loaded with tasks but there is a task whose second processing core load satisfies a first condition, determining that the frequency of at least one second processing core can be changed; the first condition indicates that the task priority is lower than the target task.

[0089] In an embodiment of the present disclosure, if the operating parameters indicate that all second processing cores are loaded with tasks, since the second processing cores need to execute corresponding tasks (for example, background tasks, download tasks, etc.), in order not to interrupt the tasks executed by the second processing cores, it is determined that the frequency of at least one second processing core cannot be changed.

[0090] In an embodiment of the present disclosure, if the operating parameters indicate that all second processing cores are loaded with tasks, but there is a task on the second processing core that satisfies a first condition, it is determined that the frequency of at least one second processing core can be changed. Because the priority of the task that satisfies the first condition is lower than the target task, the frequency of the second processing core can be reduced by pausing or slowing down the execution of the task that satisfies the first condition, thereby increasing the frequency of the first processing core.

[0091] In an embodiment of the present disclosure, if the operating parameter indicates that all the second processing cores are not loaded with tasks, it is determined that the frequency of at least one of the second processing cores can be changed.

[0092] According to the embodiments of the present disclosure, the state of the second processing core is determined according to the operating parameters of the second processing core, which can improve the accuracy of determining whether the frequency of the second processing core can be changed, thereby improving the accuracy and reliability of the processing method of this embodiment.

[0093] In some embodiments of the present disclosure, a setting strategy is determined based on task characteristics, and based on the setting strategy, at least one target processing core is determined from at least one first processing core and / or at least one second processing core, including: determining a second setting strategy in response to executing a target task with a second task characteristic; the second task characteristic characterizing that the task requires calculation using a single processing core; and determining a target processing core from at least one first processing core based on the second setting strategy.

[0094] In the embodiments of the present disclosure, the second task characteristic indicates that the task requires computation on a single processing core. In other words, the target task strongly relies on single-threaded execution capabilities, and the execution efficiency and performance of the target task are strongly correlated with the main frequency of the processing core. The higher the frequency of the processing core executing the target task, the greater the processing performance and the higher the processing efficiency of the target task.

[0095] In an embodiment of the present disclosure, the second setting strategy may include determining one of the first processing cores as the target processing core. Therefore, based on the second setting strategy, one target processing core is determined from the at least one first processing core.

[0096] Through the embodiments of the present disclosure, for target tasks that require calculation using a single processing core, the first processing core with stronger processing performance is preferentially determined as the target processing core, which can effectively improve the processing efficiency of the target task and thereby improve the efficiency of the processing method of this embodiment.

[0097] In some embodiments of the present disclosure, a setting strategy is determined based on task characteristics, and based on the setting strategy, at least one target processing core is determined from at least one first processing core and / or at least one second processing core, including: determining a third setting strategy in response to executing a target task with a third task characteristic; the third task characteristic characterizing that the task requires the use of multiple processing cores for parallel computing, and requires the processor's main frequency to meet a second condition; adjusting the main frequency of the target processor to be greater than a target threshold, and determining a number of processing cores greater than the second number from at least one first processing core and / or at least one second processing core as target processing cores.

[0098] In the embodiments of this disclosure, the processor's main frequency refers to the fundamental tick rate of the processor core, measured in Hertz (Hz). The main frequency determines the upper limit on the number of basic operations the processor can perform per second. The processor's performance is positively correlated with the main frequency.

[0099] In an embodiment of the present disclosure, the third task characteristic characterization task requires the use of multiple processing cores for parallel computing, and requires the main frequency of the processor to meet the second condition. That is, the main frequency of the target processor required to execute the target task can be greater than the target threshold, and the target task requires multiple processing cores for parallel computing. Therefore, the main frequency of the target processor is adjusted to be greater than the target threshold, and processing cores greater than the second number are determined from at least one first processing core and / or at least one second processing core as target processing cores. Here, greater than the second number refers to the condition of the number of processing cores required to execute the target task.

[0100] Through the embodiments of the present disclosure, for target tasks that require parallel computing using multiple processing cores and require the processor's main frequency to meet the second condition, by adjusting the main frequency of the target processor and selecting processing cores greater than the second number as target processing cores, the processing efficiency of the target task can be effectively improved, thereby improving the reliability of the processing method of this embodiment.

[0101] Figure 4 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

[0102] In an embodiment of the present disclosure, the electronic device 400 includes: a first system, a second system, at least one processor 420, and a memory 410 communicatively connected to the at least one processor 420; wherein, the at least one processor 420 has multiple processing cores; the memory 410 stores instructions that can be executed by the at least one processor 420, and the instructions are executed by the at least one processor 420 to achieve: in response to the operation of the first system, determining first information of multiple processing cores of the target processor; the first information is used to reflect the processing performance of the corresponding processing core; in response to executing a target task in the second system, determining at least one target processing core based on the first information of each processing core, so as to execute the target task based on the at least one target processing core.

[0103] In the embodiment of the present disclosure, the processor 420 may execute the processing method described above.

[0104] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0105] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement the methods of embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0106] like Figure 5 As shown, device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. RAM 503 may also store various programs and data required for the operation of device 500. Computing unit 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0107] Various components in device 500 are connected to I / O interface 505, including: an input unit 506, such as a keyboard, mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, optical disk, etc.; and a communication unit 509, such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0108] The computing unit 501 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as the processing method. For example, in some embodiments, the processing method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed onto the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the processing method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the processing method by any other suitable means (e.g., via firmware).

[0109] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-a-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0112] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: an electronic device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0113] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0114] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. This client-server relationship is established by computer programs running on the respective computers, establishing a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a host product within the cloud computing service ecosystem, addressing the management difficulties and limited scalability of traditional physical hosts and VPS ("Virtual Private Server") services. The server may also be a server in a distributed system or a server integrated with blockchain.

[0115] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0116] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A processing method comprising: In response to the operation of the first system, determining first information of a plurality of processing cores of a target processor; The first information is used to reflect the processing performance of the corresponding processing core; In response to executing a target task in the second system, determining at least one target processing core based on the first information of each processing core, so as to execute the target task based on the at least one target processing core; The first system is different from the second system, and the first system is used to guide the second system.

2. The method according to claim 1, wherein determining first information of a plurality of processing cores of a target processor in response to the operation of the first system comprises: In response to the operation of the first system, enabling a target function; In response to enabling the target function, restarting the electronic device and running the target function to divide the plurality of processing cores into at least one first processing core and at least one second processing core; The first information includes the division of processing cores, and the frequency of the first processing core is higher than the frequency of the second processing core.

3. The method according to claim 2, wherein running the target function to divide the plurality of processing cores into at least one first processing core and at least one second processing core comprises: reading second information of the plurality of processing cores; The second information is obtained by testing the physical capabilities of the processing core, including one or more of electrical characteristics under different loads, leakage rate, heat dissipation capability, and frequency adjustment capability in different temperature ranges; The frequency of each processing core is set based on the second information to obtain at least one first processing core and at least one second processing core.

4. The method according to claim 2, wherein, in response to executing the target task in the second system, determining at least one target processing core based on the first information of each processing core comprises: Determining the task characteristics of the target task; Determining a setting strategy based on the task characteristics; determining at least one target processing core from the at least one first processing core and / or the at least one second processing core based on the setting policy; The target processing core includes the first processing core and / or the second processing core.

5. The method according to claim 4, wherein determining a setting strategy based on the task characteristics, and determining at least one target processing core from the at least one first processing core and / or the at least one second processing core based on the setting strategy, comprises: In response to performing the target task having the first task characteristic, determining a first setting strategy; The first task feature characterization task requires parallel computing using multiple processing cores; In a case where the at least one first processing core can meet the requirements for running the target task, determining a plurality of processing cores from the at least one first processing core as the target processing cores; In a case where the at least one first processing core cannot meet the target task execution requirements, the at least one first processing core and the at least one second processing core are processed to determine at least one target processing core.

6. The method according to claim 5, wherein processing the at least one first processing core and the at least one second processing core to determine at least one target processing core comprises: In response to the frequency of the at least one second processing core being unable to change, all of the first processing cores are used as the target processing cores, and a first number of second processing cores are determined from the at least one second processing core as the target processing cores; In response to the frequency of the at least one second processing core being changeable, all first processing cores are used as the target processing cores, and the frequencies of the second processing cores capable of changing frequencies are reduced to increase the frequency of the at least one first processing core.

7. The method according to claim 6, further comprising: obtaining operating parameters of the at least one second processing core; If the operating parameter indicates that all the second processing cores are loaded with tasks, determining that the frequency of the at least one second processing core cannot be changed; If the operating parameter indicates that all second processing cores are loaded with tasks but there is a task whose second processing core load satisfies a first condition, it is determined that the frequency of the at least one second processing core can be changed; the first condition indicates that the task priority is lower than the target task.

8. The method according to claim 4, wherein determining a setting strategy based on the task characteristics, and determining at least one target processing core from the at least one first processing core and / or the at least one second processing core based on the setting strategy, comprises: determining a second setting strategy in response to executing the target task having a second task characteristic; The second task feature characterization task needs to be calculated using a single processing core; Based on the second setting strategy, a target processing core is determined from the at least one first processing core.

9. The method according to claim 4, wherein determining a setting strategy based on the task characteristics, and determining at least one target processing core from the at least one first processing core and / or the at least one second processing core based on the setting strategy, comprises: determining a third setting strategy in response to executing the target task having a third task characteristic; The third task feature characterization task requires parallel computing using multiple processing cores, and the processor's main frequency must meet the second condition; The main frequency of the target processor is adjusted to be greater than a target threshold, and processing cores greater than a second number are determined from the at least one first processing core and / or the at least one second processing core as target processing cores.

10. An electronic device comprising: A first system, a second system, at least one processor, and a memory communicatively connected to the at least one processor; wherein, At least one of the processors has multiple processing cores; The memory stores instructions that can be executed by at least one of the processors, and the instructions are executed by at least one of the processors to implement: In response to the operation of the first system, determining first information of a plurality of processing cores of a target processor, wherein the first information is used to reflect the processing performance of the corresponding processing cores; In response to executing the target task in the second system, at least one target processing core is determined based on the first information of each processing core, so as to execute the target task based on the at least one target processing core.

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