Cache replacement method, processor and chip

Abstract

The invention discloses a cache replacement method, a processor and a chip, and belongs to the technical field of processors, and the method comprises the following steps: when a target cache line in a cache region needs to be replaced in the process of executing a memory access instruction, replacing original data in the target cache line with data corresponding to a memory access address, writing the original data into a replacement buffer area as replacement candidate data; detecting whether a re-access operation on the replacement candidate data exists in a preset clock period or not; if the re-access operation exists, writing the replacement candidate data back to the cache region from the replacement buffer region; and if the re-access operation does not exist, writing the replacement candidate data back to the memory from the replacement buffer area or clearing the replacement candidate data, thereby realizing the delayed replacement function of the replaced cache data, effectively reducing the frequency of re-reading the recently replaced cache data from the memory, and improving the execution efficiency of the memory access instruction.

Description

Technical Field

[0001] The present application belongs to the field of processor technology, and in particular relates to a cache replacement method, a processor, and a chip. Background Art

[0002] Cache is a temporary storage device located between the central processing unit (CPU) and memory. Its capacity is much smaller than that of memory. Cache acts as a CPU-side backup for some data in memory, shifting memory access interactions between the CPU pipeline and memory to interactions with the cache. This resolves the mismatch between CPU processing speed and memory read / write speed, accelerating CPU read speeds.

[0003] Due to cache capacity limitations, it's not guaranteed that all data exists within the cache. During the execution of memory access instructions by the CPU pipeline, cache hits and cache misses may occur. A cache hit indicates that the cache contains the required data, while a cache miss indicates that the cache does not contain the required data. Due to the temporal and spatial locality of data access, the currently accessed data is likely to be accessed again within a period of time, and data near the currently accessed data is likely to be accessed within a period of time. Therefore, some replacement algorithms are needed to select a way in the cache to store the cache line where the currently accessed data resides. If the selected way is not idle, the existing data will be replaced. However, although there are many types of existing replacement algorithms, none of them can guarantee that the data selected for replacement will not be accessed first later. Once it is accessed later, the data will have to be retrieved from memory again and replaced with the data in the original way, greatly reducing the execution efficiency of memory access instructions. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a cache replacement method, processor, and chip that can reduce the frequency of re-reading replaced cache data from the memory and improve the execution efficiency of memory access instructions.

[0005] In a first aspect, the present application provides a cache replacement method, comprising:

[0006] When a target cache line in the cache area needs to be replaced during the execution of a memory access instruction, the original data in the target cache line is replaced with data corresponding to the memory access address, and the original data is written into the replacement buffer as replacement candidate data;

[0007] detecting whether there is a re-access operation on the replacement candidate data within a preset clock cycle;

[0008] If there is a re-access operation, writing the replacement candidate data from the replacement buffer back to the cache area;

[0009] If there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer.

[0010] In some embodiments, the cache replacement method further includes:

[0011] During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area;

[0012] When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

[0013] In some embodiments, the step of determining whether there is a target cache line requiring a replacement operation in the cache area based on the usage status of all cache lines corresponding to the memory access address in the cache area includes:

[0014] When the usage status indicates that all corresponding cache lines are in an occupied state, determining that there is a target cache line that needs to be replaced in the cache area, and the target cache line is one of the cache lines in an occupied state;

[0015] When the usage status indicates that at least one of the cache lines is in an idle state, it is determined that no target cache line requiring replacement exists in the cache area, and the data corresponding to the memory access address is directly written into one of the cache lines in an idle state.

[0016] In some embodiments, after determining that a target cache line requiring a replacement operation exists in the cache area, the cache replacement method further includes:

[0017] Reading dirty bit information of the target cache line, and writing the dirty bit information into the replacement buffer;

[0018] Writing the replacement candidate data from the replacement buffer back to the memory or clearing it includes: writing the replacement candidate data from the replacement buffer back to the memory or clearing it according to the written dirty bit information.

[0019] In some embodiments, the step of writing the replacement candidate data back to the memory or clearing it from the replacement buffer according to the written dirty bit information includes:

[0020] When the written dirty bit information indicates a dirty state, writing the replacement candidate data from the replacement buffer back to the memory;

[0021] When the written dirty bit information indicates a clean state, the replacement candidate data is cleared from the replacement buffer.

[0022] In some embodiments, the step of writing the replacement candidate data from the replacement buffer back to the memory includes:

[0023] When it is detected that the bus is idle, the replacement candidate data is written back to the memory from the replacement buffer through the bus.

[0024] In some embodiments, the replacement buffer includes at least one entry, the entry including a data area and a dirty bit flag area, and the step of writing the original data as replacement candidate data into the replacement buffer includes:

[0025] Writing the original data as replacement candidate data into the data area of ​​one of the entries;

[0026] Writing the dirty bit information into the replacement buffer includes: writing the dirty bit information into the dirty bit mark area of ​​the entry where the original data is located.

[0027] In some embodiments, before replacing the original data in the target cache line with the data corresponding to the memory access address and writing the original data as replacement candidate data into the replacement buffer, the cache replacement method further includes:

[0028] Reading dirty bit information of the target cache line;

[0029] When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with the data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data;

[0030] When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

[0031] In some embodiments, the step of writing the replacement candidate data back to the memory or clearing it from the replacement buffer includes:

[0032] The replacement candidate data is written back to the memory from the replacement buffer.

[0033] In some embodiments, when the memory access address is a load address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer, the cache replacement method further includes:

[0034] If a hit event occurs, a correct location is selected from the cache area, the replacement buffer, the backfill buffer or the storage buffer that is hit to read the data corresponding to the load address.

[0035] In some embodiments, when the memory access address is a storage address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer, the cache replacement method further includes:

[0036] If a hit event occurs in the cache area, the data corresponding to the storage address is written into the cache area;

[0037] If a hit event occurs in the replacement buffer, writing the data corresponding to the storage address into the replacement buffer by merging;

[0038] If a hit event occurs in the backfill buffer, the data corresponding to the storage address is written into the backfill buffer in a merging manner.

[0039] In a second aspect, the present application provides a processor configured to execute the cache replacement method as described in the first aspect above.

[0040] In a third aspect, the present application provides a chip for executing a computer program, which, when executed by the chip, implements the cache replacement method described in the first aspect.

[0041] In a fourth aspect, the present application provides a cache replacement device, comprising:

[0042] a replacement unit, configured to replace original data in the target cache line with data corresponding to the memory access address when a target cache line in the cache area needs to be replaced during the execution of a memory access instruction, and write the original data into a replacement buffer as replacement candidate data;

[0043] A detection unit, configured to detect whether there is a re-access operation on the replacement candidate data within a preset clock cycle;

[0044] A write-back unit is configured to write the replacement candidate data from the replacement buffer back to the cache area if a re-access operation occurs; and to write the replacement candidate data from the replacement buffer back to the memory or clear the data if no re-access operation occurs.

[0045] In some embodiments, the cache replacement device further includes a judgment unit configured to:

[0046] During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area;

[0047] When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

[0048] In some embodiments, the judgment unit is specifically configured to:

[0049] When the usage status indicates that all corresponding cache lines are in an occupied state, determining that there is a target cache line that needs to be replaced in the cache area, and the target cache line is one of the cache lines in an occupied state;

[0050] When the usage status indicates that at least one of the cache lines is in an idle state, it is determined that no target cache line requiring replacement exists in the cache area, and the data corresponding to the memory access address is directly written into one of the cache lines in an idle state.

[0051] In some embodiments, the replacement unit is further configured to:

[0052] Reading dirty bit information of the target cache line, and writing the dirty bit information into the replacement buffer;

[0053] At this time, the write-back unit is used to write the replacement candidate data back to the memory or clear it from the replacement buffer according to the written dirty bit information.

[0054] In some embodiments, the write-back unit is configured to:

[0055] When the written dirty bit information indicates a dirty state, writing the replacement candidate data from the replacement buffer back to the memory;

[0056] When the written dirty bit information indicates a clean state, the replacement candidate data is cleared from the replacement buffer.

[0057] In some embodiments, the write-back unit is configured to:

[0058] When it is detected that the bus is idle, the replacement candidate data is written back to the memory from the replacement buffer through the bus.

[0059] In some embodiments, the replacement buffer includes at least one entry, the entry including a data area and a dirty bit mark area, and the write-back unit is configured to:

[0060] Writing the original data as replacement candidate data into the data area of ​​one of the entries;

[0061] At this time, the replacement unit is specifically configured to write the dirty bit information into the dirty bit mark area of ​​the entry where the original data is located.

[0062] In some embodiments, before replacing the original data in the target cache line with the data corresponding to the access address and writing the original data as replacement candidate data into the replacement buffer, the replacement unit is further configured to:

[0063] Reading dirty bit information of the target cache line;

[0064] When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with the data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data;

[0065] When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

[0066] In some embodiments, if there is no re-access operation, the replacement unit is specifically configured to:

[0067] The replacement candidate data is written back to the memory from the replacement buffer.

[0068] In some embodiments, when the memory access address is a load address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer, the determination unit is further configured to:

[0069] If a hit event occurs, a correct location is selected from the cache area, the replacement buffer, the backfill buffer or the storage buffer that is hit to read the data corresponding to the load address.

[0070] In some embodiments, when the memory access address is a storage address, after determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area, the determination unit is further configured to:

[0071] If a hit event occurs in the cache area, the data corresponding to the storage address is written into the cache area;

[0072] If a hit event occurs in the replacement buffer, writing the data corresponding to the storage address into the replacement buffer by merging;

[0073] If a hit event occurs in the backfill buffer, the data corresponding to the storage address is written into the backfill buffer in a merging manner.

[0074] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the cache replacement method described in any one of the above items is implemented.

[0075] In a sixth aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the cache replacement methods described above when executing the computer program.

[0076] In a seventh aspect, the present application provides a computer program product, comprising a computer program, which implements any of the above-mentioned cache replacement methods when executed by a processor.

[0077] The cache replacement method, processor, chip, cache replacement device, storage medium, electronic device and computer program product provided by the embodiments of the present application, when it is necessary to replace the target cache line in the cache area during the execution of a memory access instruction, the original data in the target cache line is replaced with the data corresponding to the memory access address, and the original data is written into the replacement buffer as the replacement candidate data; it is detected whether there is a re-access operation on the replacement candidate data within a preset clock cycle; if there is a re-access operation, the replacement candidate data is written back to the cache area from the replacement buffer; if there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer, that is, the original data replaced in the cache is written into the replacement buffer, and the data in the replacement buffer is written back to the cache according to the re-access operation on the data in the replacement buffer in a short time, so that when the replaced data in the cache is re-accessed, there is no need to read the data from the memory, thereby realizing the delayed replacement function of the cache replaced data, thereby effectively reducing the frequency of re-reading the recently replaced cache data from the memory, and improving the execution efficiency of the memory access instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the description of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0079] Figure 1 Schematic diagram of the process of the cache replacement method provided in the embodiment of the present application;

[0080] Figure 2This is a schematic diagram of the framework of the cache replacement process provided by the embodiment of the present application;

[0081] Figure 3 is a schematic structural diagram of a cache replacement device provided in an embodiment of the present application;

[0082] Figure 4 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0083] Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0084] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0085] To solve at least one of the above technical problems, embodiments of the present application provide a cache replacement method, apparatus, storage medium, electronic device, and computer program product.

[0086] See Figure 1 , Figure 1 101-104, wherein:

[0087] 101. When a target cache line in a cache area needs to be replaced during execution of a memory access instruction, the original data in the target cache line is replaced with data corresponding to the memory access address, and the original data is written into a replacement buffer as replacement candidate data.

[0088] 102. Detect whether there is a re-access operation to the replacement candidate data within a preset clock cycle;

[0089] 103. If a re-access operation exists, writing the replacement candidate data from the replacement buffer back to the cache area;

[0090] 104. If there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer.

[0091] Memory access instructions primarily involve the transfer of data between memory and the processor, including load and store instructions. The cache area is a storage area provided by the CPU cache. In a computer system, the cache is used to store copies of the most recently or most frequently accessed data, as well as copies of data in adjacent areas, to accelerate data read and write operations. The cache is typically a multi-way set-associative structure, where each memory address can be mapped to the same set address on different ways. The cache contains multiple cache lines. A cache line is a block of data in the cache and is the basic unit of data exchange between the CPU and memory. A cache line typically contains a certain number of consecutive bytes of data (e.g., 32 bytes, 64 bytes, etc.) and may also include additional information such as tags and status bits (such as valid and dirty bits). The replacement buffer is a temporary storage area used to temporarily store cache line data that has been replaced in the cache.

[0092] When the CPU pipeline is executing a memory access instruction, if it is necessary to replace the data of a cache line in the cache (that is, the new data corresponding to the memory access instruction replaces the original data in the cache line), the original data in the cache line can be written into the replacement buffer as replacement candidate data while the replacement operation is being performed, and the timer is started. If there is no re-access to the cache line data within a certain clock cycle, and the cache line data is dirty data, it can be written back to the memory from the replacement buffer. If the cache line data is clean data, it can be directly overwritten with the newly entered replacement candidate data to achieve clearing. If there is a re-access to the cache line data within a certain clock cycle, the cache line data will be refilled from the replacement buffer back to the cache, avoiding re-reading the data from the memory to fill it back into the cache, thereby realizing the delayed replacement function of the data, effectively reducing the frequency of re-reading the recently replaced cache data from the memory, and improving the execution efficiency of the memory access instruction.

[0093] Furthermore, steps 101-104 will be described in detail below.

[0094] 101. When a target cache line in a cache area needs to be replaced during execution of a memory access instruction, the original data in the target cache line is replaced with data corresponding to the memory access address, and the original data is written into a replacement buffer as replacement candidate data.

[0095] In some embodiments, the cache replacement method further includes:

[0096] During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area;

[0097] When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

[0098] Specifically, when the CPU pipeline executes a memory access instruction, it calculates the memory address to be accessed (i.e., the memory access address), and first searches the cache and some temporary storage areas based on the memory access address to see if there is a hit. For example, when executing a load instruction, the CPU needs to load data from the specified memory address to the register or other computing unit. During this process, if the required data already exists in the cache (i.e., the data corresponding to the memory address has been loaded into the cache), a cache hit event occurs. At this time, the CPU can quickly read the data directly from the cache without accessing the slower memory (main memory). For example, when executing a store instruction, the CPU needs to write data to the specified memory address. In this case, if the data corresponding to the memory address to be written already exists in the cache, a cache hit event occurs. At this time, the update process will first occur at the cache level, that is, the data needs to be written to the cache location corresponding to the memory address first.

[0099] For details, see Figure 2 , Figure 2 This is a schematic diagram of the framework of the cache replacement process provided by an embodiment of the present application. The execution process of the cache replacement process involves multiple modules, including a CACHE RAM module, a load search control module, an Stb module, a backfill control module and a replacement control module. The CACHE RAM module is the storage entity of the cache (i.e., the cache area). The Stb module performs the search operation of the storage instruction and provides a storage buffer (storebuffer). The load search control module performs the search operation of the load instruction. The backfill control module provides a backfill buffer, and the replacement control module provides a replacement buffer. The replacement buffer can be a register, a random access memory (RAM), etc., and the data therein supports all types of memory access. The replacement buffer is a fully associative structure. When searching the CACHE RAM, it is necessary to search the replacement buffer synchronously.

[0100] For example, when the CPU pipeline executes a load instruction, the load search control module searches the cache RAM module based on the load address. It also searches the backfill buffer, replacement buffer, and store buffer to see if there's a hit. That is, whether the data corresponding to the load instruction's address (load address) can be found in the cache and these buffers. If so, a hit occurs; otherwise, no hit occurs. When the CPU pipeline executes a store instruction, the Stb module searches the cache RAM module, backfill buffer, and replacement buffer. If the data corresponding to the store instruction's address (store address) can be found in any of these buffers, a hit occurs; otherwise, no hit occurs.

[0101] When no hit event occurs, in some embodiments, the step of “determining whether there is a target cache line requiring a replacement operation in the cache area based on the usage status of all cache lines corresponding to the memory access address in the cache area” specifically includes:

[0102] When the usage status indicates that all corresponding cache lines are in an occupied state, determining that there is a target cache line that needs to be replaced in the cache area, and the target cache line is one of the cache lines in an occupied state;

[0103] When the usage status indicates that at least one cache line is in an idle state, it is determined that there is no target cache line requiring a replacement operation in the cache area, and the data corresponding to the memory access address is directly written into one of the cache lines in the idle state.

[0104] Among them, the usage status includes the occupied state and the idle state, and the target cache line refers to the cache line corresponding to the selected way. If no hit event occurs, it is necessary to read the usage status of all ways in the group corresponding to the memory access address in the CACHE RAM module. If all ways are in the occupied state, the replacement mechanism can be triggered to select one of these ways for data replacement. For example, for a load instruction, data replacement means replacing the original data in the selected way with the data read from the specified memory address this time. For a store instruction, data replacement means replacing the original data in the selected way with the data to be written to the specified memory address this time. If there is at least one way in the idle state, the data corresponding to the memory access address can be directly written into one of the idle ways.

[0105] For details, please refer to Figure 2The backfill control module will receive the backfill request generated by the load search control module and the Stb module after no hit event occurs. The backfill request will be accompanied by information about whether all the ways corresponding to the memory access address in the cache are occupied. Next, the backfill control module sends a data access request for the bus to the outside to obtain the data corresponding to the memory access address. If there is currently an idle way, the backfill control module will directly write the data returned by the bus back to the idle way. If there is currently no idle way, the backfill control module will send a replacement request to the replacement control module to trigger the replacement mechanism. When the replacement control module receives the replacement request, it selects one of the occupied ways as the way to be backfilled by the backfill control module through the set replacement algorithm for data replacement. In this embodiment, the replacement algorithm can adopt, for example, a random replacement algorithm, or a first-in-first-out (FIFO) algorithm or other algorithms, which are not limited here.

[0106] In some embodiments, when the memory access address is a load address, after executing the above step of "determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer", the cache replacement method further includes:

[0107] If a hit event occurs, a correct location is selected from the hit cache area, the replacement buffer, the backfill buffer or the storage buffer to read the data corresponding to the load address.

[0108] That is, when executing a load instruction, if the load search control module finds the data corresponding to the load instruction address from any of the CACHE RAM, backfill buffer, replacement buffer and storage buffer, it is determined that a hit event has occurred. At this time, the load search control module only needs to read the data of the load instruction directly from it without reading it from the memory.

[0109] In some embodiments, when the memory access address is a storage address, after performing the above step of "determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area", the cache replacement method further includes:

[0110] If a hit event occurs in the cache area, the data corresponding to the storage address is written into the cache area;

[0111] If a hit event occurs in the replacement buffer, the data corresponding to the storage address is written into the replacement buffer by merging;

[0112] If a hit event occurs in the backfill buffer, the data corresponding to the storage address is written into the backfill buffer in a merging manner.

[0113] That is, when executing a storage instruction, if the storage module finds the data corresponding to the storage instruction address from any one of the CACHE RAM, the backfill buffer and the replacement buffer, it is determined that a hit event has occurred. At this time, if the hitter is the CACHE RAM, the data to be written by the storage instruction is written into the cache RAM (for example, a path corresponding to the storage instruction address is selected from the CACHE RAM to write the data, and when it is an idle path, it is written directly, and when it is a non-idle path, it is written by data replacement); if the hitter is the backfill buffer, the data to be written by the data storage instruction and the original data corresponding to the storage instruction address in the backfill buffer are merged, and the merged data are subsequently written into the CACHE RAM by the backfill control module; if the hitter is the replacement buffer, the data to be written by the data storage instruction and the original data corresponding to the storage instruction address in the replacement buffer are merged, and subsequently, no matter the data in the replacement buffer is to be refilled into the CACHE RAM or written back to the memory through the bus, the data of the storage instruction will be written together.

[0114] Furthermore, when it is determined that a target cache line in the cache area needs to be replaced, the replacement control module replaces the original data in the target cache line with the data corresponding to the memory access address, completing the replacement operation. To prevent the replaced original data from being re-accessed in the short term and requiring it to be re-read from memory, the original data can be written to the replacement buffer as replacement candidate data for temporary storage while the data replacement operation is in progress, rather than being directly cleared.

[0115] In some embodiments, for the original data written into the replacement buffer, the operation of writing it back to the memory or clearing it can be triggered based on the timer timing and the dirty bit information of the data to release resources of the replacement buffer. In this case, after determining that there is a target cache line that needs to be replaced in the cache area, the cache replacement method further includes:

[0116] The dirty bit information of the target cache line is read and written into the replacement buffer.

[0117] The dirty bit flag of the target cache line may be stored in a tag random access memory (Tag RAM) or stored separately.

[0118] Furthermore, the replacement buffer includes at least one entry, and the entry includes a data area and a dirty bit flag area. The step 101 of "writing the original data as the replacement candidate data into the replacement buffer" includes: writing the original data as the replacement candidate data into the data area of ​​one of the entries;

[0119] At this time, the above step of "writing the dirty bit information into the replacement buffer" includes: writing the dirty bit information into the dirty bit mark area of ​​the entry where the original data is located.

[0120] The data in the replacement buffer is stored in the form of entries, each entry corresponds to a cache line, and the number of entries in the replacement buffer can be any value, for example, 4. Each entry includes a data area, an address area, a counter area, a dirty bit mark area, and a valid bit area. The data area is used to store the actual data content, the address area is used to store the address of the data, the counter area is used to store the timing value, and the dirty bit mark area is used to store the dirty bit mark of the data. The dirty bit mark can be represented by the values ​​0 and 1. 0 means that the data is consistent with the memory and the data is clean data. 1 means that the data is inconsistent with the memory and the data is dirty data, and the current entry is the latest data. The entry can also include a to-be-refilled mark area, which is used to store the to-be-refilled mark. The value of the to-be-refilled mark can include 0 and 1. 0 means that there is no need to refill the data, and 1 means that a refill operation to refill the data back into the replacement buffer needs to be triggered.

[0121] Specifically, after reading the dirty bit flag of the target cache line from the tag random access memory, it is stored in the dirty bit flag area of ​​the entry allocated by the replacement control module for the current replacement request. The address read from the tag random access memory and the tag index are used together to calculate the data address corresponding to the current way. The data address is then stored in the address area of ​​the entry, and the actual data content read is stored in the data area of ​​the entry. The counter is reset to a fixed value, for example, the counter can be set to 10'b1111111111, that is, to detect whether there is a reaccess within 1024 clock cycles. Initially, the pending refill flag is set to 0.

[0122] 102. Detect whether there is a re-access operation to the replacement candidate data within a preset clock cycle.

[0123] 103. If there is a re-access operation, the replacement candidate data is written back to the cache area from the replacement buffer.

[0124] 104. If there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer.

[0125] The value in the counter area is decremented by 1 each cycle according to the normal process. If a load instruction or store instruction is detected within 1024 clock cycles that re-accesses the data of an entry in the replacement buffer, it indicates that the previously selected replacement way from the cache by the replacement algorithm was inaccurate. In this case, a new way can be selected in the cache to exchange the data of the entry in the replacement buffer (that is, the data of the previously selected replacement way), thus correcting the replacement of the previously replaced way.

[0126] For example, if a load instruction is detected within 1024 cycles re-accessing the data of the entry in the replacement buffer, the pending refill flag for that entry is set to 1, triggering a refill operation. The refill operation includes: finding a way in the cache based on the current load instruction, exchanging the data of the entry in the replacement buffer with the data of the selected way, as well as information such as the corresponding address and dirty bit, completing the refill operation, setting the pending refill flag to 0, and resetting the counter to 10'b1111111111. If the data of the current entry is accessed again before the counter reaches 0, the pending refill flag for the current entry is set to 1, triggering the refill operation again. This cycle continues until the counter reaches 0, indicating that the current entry needs to be released. At this time, if the dirty bit of the current entry is marked as 1, a bus write operation is triggered. If the dirty bit of the current entry is marked as 0, when the replacement control module receives a new replacement request, the new replacement data can be used to overwrite the data in the current entry to clear the original data.

[0127] When a store instruction is detected accessing the data of the entry in the replacement buffer within 1024 cycles, the data required by the store instruction is merged into the data area of ​​the entry, and the dirty bit flag in the entry is set to 1. The subsequent operations are similar to the steps of the above-mentioned load instruction accessing the replacement buffer, and the timer timing and dirty bit information are used to decide when to refill the data back to the cache or clear it.

[0128] If, however, the value in the counter area decreases to 0 (after 1024 cycles), no re-access to the data in the entry has been detected, this indicates that the way previously selected for replacement from the cache by the replacement algorithm was relatively accurate. In this case, the dirty bit flag is used to determine whether the data in the previously selected way (i.e., the data in the entry) should be written back to the memory or cleared. That is, the "writing the candidate data from the replacement buffer back to the memory or clearing it" in step 104 specifically includes:

[0129] The replacement candidate data is written back to the memory or cleared from the replacement buffer according to the written dirty bit information.

[0130] Furthermore, the above step of “writing the candidate replacement data back to the memory or clearing it from the replacement buffer according to the written dirty bit information” specifically includes:

[0131] When the written dirty bit information indicates a dirty state, the replacement candidate data is written back to the memory from the replacement buffer;

[0132] When the written dirty bit information indicates a clean state, the replacement candidate data is cleared from the replacement buffer.

[0133] Furthermore, the above step of "writing the replacement candidate data from the replacement buffer back to the memory" specifically includes:

[0134] When the bus is detected to be idle, the replacement candidate data is written back to the memory through the bus from the replacement buffer.

[0135] Among them, when the counter value in the entry is 0, if the dirty bit is marked as 1 (dirty state), the write bus action is triggered. At this time, the replacement control module can wait for the bus to be idle to write the data in the entry back to the memory, thereby reducing bus conflicts, improving bus utilization, and thus improving instruction execution efficiency. If the dirty bit is marked as 0, it is considered that the current entry is an allocable entry. If a replacement request is subsequently received, the original data in the current entry can be overwritten with new replacement data. When the number of allocable entries is less than or equal to a certain set value (such as 1), the replacement control module can select the entry with the smallest counter value from the entries with non-zero counter values ​​as the entry to be released in the near future. When the dirty bit of the entry is marked as 0, if a replacement request is subsequently received, the data in the entry is directly overwritten with new data. If the dirty bit of the entry is marked as 1, the write bus action is directly triggered.

[0136] In other embodiments, in addition to storing the data of the cache way selected for replacement and its dirty bit flag in the replacement buffer and subsequently performing a replacement correction on the replaced way based on the timer timing and the dirty bit flag, it is also possible to not write the dirty bit flag in the replacement buffer, but instead perform a dirty bit flag check before storing the data of the replaced way in the replacement buffer. Specifically, before "replacing the original data in the target cache line with the data corresponding to the access address and writing the original data as replacement candidate data into the replacement buffer" in step 101 above, the cache replacement method may further include:

[0137] Read the dirty bit information of the target cache line;

[0138] When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data;

[0139] When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

[0140] At this time, the step 104 of “writing the candidate replacement data from the replacement buffer back to the memory or clearing it” specifically includes: writing the candidate replacement data from the replacement buffer back to the memory.

[0141] That is, when it is determined that the data in the target cache line in the cache area (i.e., the occupied way) needs to be replaced, the dirty bit flag of the selected way is read. If the dirty bit flag is 0 (indicating that the data in the cache is consistent with the data in the memory, and the data in the memory is the latest value), only the original data in the selected way is replaced with the data corresponding to the memory access address to complete the replacement operation. If the dirty bit flag is 1 (indicating that the data in the memory is not the latest value), in addition to completing the replacement operation, the original data in the selected way must also be written as replacement candidate data into the entry of the replacement buffer for temporary storage. Subsequently, if the timer value in the entry is reduced to 0 and no re-access operation for the data is detected, it will be directly written back to the memory. If a re-access operation is detected, the data will be refilled back to the cache to achieve replacement correction of the previously replaced way.

[0142] As can be seen from the above, the cache replacement method provided by the embodiment of the present application, when it is necessary to replace the target cache line in the cache area during the execution of a memory access instruction, replaces the original data in the target cache line with the data corresponding to the memory access address, and writes the original data into the replacement buffer as replacement candidate data; detects whether there is a re-access operation on the replacement candidate data within a preset clock cycle; if there is a re-access operation, writes the replacement candidate data back to the cache area from the replacement buffer; if there is no re-access operation, writes the replacement candidate data back to the memory or clears it from the replacement buffer, that is, writes the original data replaced in the cache into the replacement buffer, and writes it back to the cache according to the re-access operation of the data in the replacement buffer in a short time, so that when the replaced data in the cache is re-accessed, there is no need to read the data from the memory, thereby realizing the delayed replacement function of the cache replaced data, thereby effectively reducing the frequency of re-reading the recently replaced cache data from the memory, and improving the execution efficiency of the memory access instruction.

[0143] According to the method described in the above embodiment, the present application also provides a cache replacement device for executing the steps in the above cache replacement method. Figure 3 , Figure 3 Schematic diagram of the structure of a cache replacement device provided in an embodiment of the present application. The cache replacement device 200 can be implemented as an electronic device, and the steps of the cache replacement method can be performed by a functional module or functional entity in the electronic device. Specifically, the cache replacement device 200 includes a replacement unit 201, a detection unit 202, and a write-back unit 203, wherein:

[0144] The replacement unit 201 is configured to replace the original data in the target cache line with the data corresponding to the memory access address when a target cache line in the cache area needs to be replaced during the execution of a memory access instruction, and write the original data into the replacement buffer as replacement candidate data;

[0145] The detection unit 202 is used to detect whether there is a re-access operation to the replacement candidate data within a preset clock cycle;

[0146] The write-back unit 203 is configured to write the replacement candidate data from the replacement buffer back to the cache area if a re-access operation occurs; and to write the replacement candidate data from the replacement buffer back to the memory or clear the data if no re-access operation occurs.

[0147] In some embodiments, the cache replacement device further includes a determination unit configured to:

[0148] During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area;

[0149] When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

[0150] In some embodiments, the judgment unit is specifically configured to:

[0151] When the usage status indicates that all corresponding cache lines are in an occupied state, determining that there is a target cache line that needs to be replaced in the cache area, and the target cache line is one of the cache lines in an occupied state;

[0152] When the usage status indicates that at least one cache line is in an idle state, it is determined that there is no target cache line requiring a replacement operation in the cache area, and the data corresponding to the memory access address is directly written into one of the cache lines in the idle state.

[0153] In some embodiments, the replacement unit 201 is further configured to:

[0154] Reading dirty bit information of the target cache line and writing the dirty bit information into the replacement buffer;

[0155] At this time, the write-back unit 203 is used to write the replacement candidate data from the replacement buffer back to the memory or clear it according to the written dirty bit information.

[0156] In some embodiments, the write-back unit 203 is configured to:

[0157] When the written dirty bit information indicates a dirty state, writing the replacement candidate data from the replacement buffer back to the memory;

[0158] When the written dirty bit information indicates a clean state, the replacement candidate data is cleared from the replacement buffer.

[0159] In some embodiments, the write-back unit 203 is configured to:

[0160] When the bus is detected to be idle, the replacement candidate data is written back to the memory from the replacement buffer through the bus.

[0161] In some embodiments, the replacement buffer includes at least one entry, the entry including a data area and a dirty bit mark area, and the write-back unit 203 is configured to:

[0162] Writing the original data as replacement candidate data into one of the data areas of the entry;

[0163] At this time, the replacement unit 201 is specifically configured to write the dirty bit information into the dirty bit mark area of ​​the entry where the original data is located.

[0164] In some embodiments, before replacing the original data in the target cache line with the data corresponding to the access address and writing the original data as replacement candidate data into the replacement buffer, the replacement unit 201 is further configured to:

[0165] Read the dirty bit information of the target cache line;

[0166] When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data;

[0167] When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

[0168] In some embodiments, if there is no re-access operation, the replacement unit 201 is specifically configured to:

[0169] The replacement candidate data is written back to the memory from the replacement buffer.

[0170] In some embodiments, when the memory access address is a load address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer, the determination unit is further configured to:

[0171] If a hit event occurs, a correct location is selected from the hit cache area, the replacement buffer, the backfill buffer or the storage buffer to read the data corresponding to the load address.

[0172] In some embodiments, when the memory access address is a storage address, after determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area, the determination unit is further configured to:

[0173] If a hit event occurs in the cache area, the data corresponding to the storage address is written into the cache area;

[0174] If a hit event occurs in the replacement buffer, the data corresponding to the storage address is written into the replacement buffer by merging;

[0175] If a hit event occurs in the backfill buffer, the data corresponding to the storage address is written into the backfill buffer in a merging manner.

[0176] It should be noted that the specific details of each module unit in the cache replacement device 200 have been described in detail in the embodiment of the cache replacement method, and will not be repeated here.

[0177] As can be seen from the above, the cache replacement device 200 provided by the embodiment of the present application, when it is necessary to replace the target cache line in the cache area during the execution of a memory access instruction, the replacement unit 201 replaces the original data in the target cache line with the data corresponding to the memory access address, and writes the original data as replacement candidate data into the replacement buffer; the detection unit 202 detects whether there is a re-access operation on the replacement candidate data within a preset clock cycle; if there is a re-access operation, the write-back unit 203 writes the replacement candidate data from the replacement buffer back to the cache area; if there is no re-access operation, the write-back unit 203 writes the replacement candidate data from the replacement buffer back to the memory or clears it, that is, the original data replaced in the cache is written to the replacement buffer, and is written back to the cache according to the re-access operation of the data in the replacement buffer in a short time, so that when the replaced data in the cache is re-accessed, there is no need to read the data from the memory, thereby realizing the delayed replacement function of the cache replaced data, thereby effectively reducing the frequency of re-reading the recently replaced cache data from the memory, and improving the execution efficiency of the memory access instruction.

[0178] The cache replacement device in the embodiments of the present application can be an electronic device or a component of an electronic device, such as an integrated circuit or chip. The electronic device can be a terminal or other device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a mobile internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA). It can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine (ATM), or a self-service machine, etc., and the embodiments of the present application do not specifically limit this.

[0179] In some embodiments, the present application also provides a processor configured to execute the above-mentioned cache replacement method.

[0180] In some embodiments, the embodiments of the present application further provide a chip for executing a computer program, which implements the above-mentioned cache replacement method when executed by the chip.

[0181] In some embodiments, as Figure 4 As shown, an embodiment of the present application also provides an electronic device 400, including a processor 401, a memory 402, and a computer program stored in the memory 402 and executable on the processor 401. When the program is executed by the processor 401, the various processes of the above-mentioned cache replacement method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0182] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0183] Figure 5 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0184] like Figure 5As shown, the electronic device 500 includes but is not limited to: a radio frequency unit 501, a network module 502, an audio output unit 503, an input unit 504, a sensor 505, a display unit 506, a user input unit 507, an interface unit 508, a memory 509 and a processor 510 and other components.

[0185] Those skilled in the art will understand that the electronic device 500 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 510 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 5 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0186] The processor 510 is configured to:

[0187] When a target cache line in the cache area needs to be replaced during the execution of a memory access instruction, the original data in the target cache line is replaced with the data corresponding to the memory access address, and the original data is written into the replacement buffer as replacement candidate data;

[0188] detecting whether there is a re-access operation to the replacement candidate data within a preset clock cycle;

[0189] If there is a re-access operation, the replacement candidate data is written back to the cache area from the replacement buffer;

[0190] If there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer.

[0191] In some embodiments, the processor 510 is further configured to:

[0192] During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area;

[0193] When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

[0194] In some embodiments, the processor 510 is configured to:

[0195] When the usage status indicates that all corresponding cache lines are in an occupied state, determining that there is a target cache line that needs to be replaced in the cache area, and the target cache line is one of the cache lines in an occupied state;

[0196] When the usage status indicates that at least one cache line is in an idle state, it is determined that there is no target cache line requiring a replacement operation in the cache area, and the data corresponding to the memory access address is directly written into one of the cache lines in the idle state.

[0197] In some embodiments, after determining that a target cache line requiring a replacement operation exists in the cache area, the processor 510 is further configured to:

[0198] Reading dirty bit information of the target cache line and writing the dirty bit information into the replacement buffer;

[0199] Writing the replacement candidate data from the replacement buffer back to the memory or clearing it includes: writing the replacement candidate data from the replacement buffer back to the memory or clearing it according to the written dirty bit information.

[0200] In some embodiments, the processor 510 is configured to:

[0201] When the written dirty bit information indicates a dirty state, writing the replacement candidate data from the replacement buffer back to the memory;

[0202] When the written dirty bit information indicates a clean state, the replacement candidate data is cleared from the replacement buffer.

[0203] In some embodiments, the processor 510 is configured to:

[0204] When the bus is detected to be idle, the replacement candidate data is written back to the memory from the replacement buffer through the bus.

[0205] In some embodiments, the replacement buffer includes at least one entry, the entry including a data area and a dirty bit flag area, and the processor 510 is configured to:

[0206] Writing the original data as replacement candidate data into one of the data areas of the entry;

[0207] Writing the dirty bit information into the replacement buffer includes: writing the dirty bit information into a dirty bit mark area of ​​the entry where the original data is located.

[0208] In some embodiments, the processor 510 is configured to:

[0209] Read the dirty bit information of the target cache line;

[0210] When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data;

[0211] When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

[0212] In some embodiments, the processor 510 is configured to:

[0213] The replacement candidate data is written back to the memory from the replacement buffer.

[0214] In some embodiments, when the memory access address is a load address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer, the processor 510 is further configured to:

[0215] If a hit event occurs, data corresponding to the load address is read from the hit cache area, the replacement buffer, the backfill buffer or the storage buffer.

[0216] In some embodiments, when the memory access address is a storage address, after determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer, the backfill buffer, and the storage buffer, the processor 510 is further configured to:

[0217] If a hit event occurs in the cache area, the data corresponding to the storage address is written into the cache area;

[0218] If a hit event occurs in the replacement buffer, the data corresponding to the storage address is written into the replacement buffer by merging;

[0219] If a hit event occurs in the backfill buffer, the data corresponding to the storage address is written into the backfill buffer in a merging manner.

[0220] It should be understood that in an embodiment of the present application, the input unit 504 may include a graphics processing unit (GPU) 5041 and a microphone 5042, and the graphics processor 5041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 506 may include a display panel 5061, and the display panel 5061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 507 includes a touch panel 5071 and at least one of other input devices 5072. The touch panel 5071 is also called a touch screen. The touch panel 5071 may include two parts: a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0221] The memory 509 can be used to store software programs and various data. The memory 509 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 509 may include a volatile memory or a non-volatile memory, or the memory 509 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (DRRAM). The memory 509 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0222] Processor 510 may include one or more processing units. Processor 510 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 510.

[0223] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the above-mentioned cache replacement method.

[0224] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the various processes of the above-mentioned cache replacement method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0225] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0226] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned cache replacement method when executed by a processor.

[0227] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0228] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0229] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0230] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0231] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0232] In the description of this application, “plurality” means two or more.

[0233] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0234] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A cache replacement method, characterized in that: include: When a target cache line in the cache area needs to be replaced during the execution of a memory access instruction, the original data in the target cache line is replaced with data corresponding to the memory access address, and the original data is written into the replacement buffer as replacement candidate data; detecting whether there is a re-access operation on the replacement candidate data within a preset clock cycle; If there is a re-access operation, writing the replacement candidate data from the replacement buffer back to the cache area; If there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer.

2. The cache replacement method according to claim 1, wherein: The cache replacement method further includes: During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area; When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

3. The cache replacement method according to claim 2, wherein: The step of determining whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area comprises: When the usage status indicates that all corresponding cache lines are in an occupied state, determining that there is a target cache line that needs to be replaced in the cache area, and the target cache line is one of the cache lines in an occupied state; When the usage status indicates that at least one of the cache lines is in an idle state, it is determined that no target cache line requiring replacement exists in the cache area, and the data corresponding to the memory access address is directly written into one of the cache lines in an idle state.

4. The cache replacement method according to claim 3, wherein: After determining that a target cache line requiring a replacement operation exists in the cache area, the cache replacement method further includes: Reading dirty bit information of the target cache line, and writing the dirty bit information into the replacement buffer; Writing the replacement candidate data from the replacement buffer back to the memory or clearing it includes: writing the replacement candidate data from the replacement buffer back to the memory or clearing it according to the written dirty bit information.

5. The cache replacement method according to claim 4, wherein: The step of writing the replacement candidate data back to the memory or clearing it from the replacement buffer according to the written dirty bit information includes: When the written dirty bit information indicates a dirty state, writing the replacement candidate data from the replacement buffer back to the memory; When the written dirty bit information indicates a clean state, the replacement candidate data is cleared from the replacement buffer.

6. The cache replacement method according to claim 5, wherein: The step of writing the replacement candidate data from the replacement buffer back to the memory comprises: When it is detected that the bus is idle, the replacement candidate data is written back to the memory from the replacement buffer through the bus.

7. The cache replacement method according to claim 4, wherein: The replacement buffer includes at least one entry, the entry including a data area and a dirty bit flag area, and the step of writing the original data as replacement candidate data into the replacement buffer includes: Writing the original data as replacement candidate data into the data area of ​​one of the entries; Writing the dirty bit information into the replacement buffer includes: writing the dirty bit information into the dirty bit mark area of ​​the entry where the original data is located.

8. The cache replacement method according to claim 1, wherein: Before replacing the original data in the target cache line with the data corresponding to the memory access address and writing the original data as replacement candidate data into the replacement buffer, the cache replacement method further includes: Reading dirty bit information of the target cache line; When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with the data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data; When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

9. The cache replacement method according to claim 8, wherein: The step of writing the replacement candidate data back to the memory or clearing it from the replacement buffer comprises: The replacement candidate data is written back to the memory from the replacement buffer.

10. The cache replacement method according to any one of claims 2 to 9, characterized in that: When the memory access address is a load address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area, the cache replacement method further includes: If a hit event occurs, a correct location is selected from the cache area, the replacement buffer, the backfill buffer or the storage buffer that is hit to read the data corresponding to the load address.

11. The cache replacement method according to any one of claims 2 to 9, characterized in that: When the memory access address is a storage address, after determining whether a hit event corresponding to the memory access address occurs based on data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area, the cache replacement method further includes: If a hit event occurs in the cache area, the data corresponding to the storage address is written into the cache area; If a hit event occurs in the replacement buffer, writing the data corresponding to the storage address into the replacement buffer by merging; If a hit event occurs in the backfill buffer, the data corresponding to the storage address is written into the backfill buffer in a merging manner.

12. A processor, characterized in that: The method is configured to execute the cache replacement method according to any one of claims 1 to 11.

13. A chip, characterized in that: Used to execute a computer program, which, when executed by the chip, implements the cache replacement method described in any one of claims 1 to 11.

14. A cache replacement device, characterized in that: include: a replacement unit, configured to replace original data in the target cache line with data corresponding to the memory access address when a target cache line in the cache area needs to be replaced during the execution of a memory access instruction, and write the original data into a replacement buffer as replacement candidate data; A detection unit, configured to detect whether there is a re-access operation on the replacement candidate data within a preset clock cycle; a write-back unit, configured to write the replacement candidate data from the replacement buffer back to the cache area if a re-access operation occurs; If there is no re-access operation, the replacement candidate data is written back to the memory or cleared from the replacement buffer.

15. The cache replacement device according to claim 14, wherein: It also includes a judgment unit, which is used to: During the execution of a memory access instruction, determining whether a hit event corresponding to the memory access address occurs based on the data stored in the cache area, the replacement buffer area, the backfill buffer area, and the storage buffer area; When no hit event occurs, it is determined whether there is a target cache line requiring a replacement operation in the cache area according to the usage status of all cache lines corresponding to the memory access address in the cache area.

16. The cache replacement device according to claim 14, wherein: Before replacing the original data in the target cache line with the data corresponding to the memory access address and writing the original data as replacement candidate data into the replacement buffer, the replacement unit is further configured to: Reading dirty bit information of the target cache line; When the dirty bit information indicates a dirty state, performing the step of replacing the original data in the target cache line with the data corresponding to the memory access address, and writing the original data into the replacement buffer as replacement candidate data; When the dirty bit information indicates a clean state, the original data in the target cache line is replaced with data corresponding to the memory access address.

17. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the cache replacement method according to any one of claims 1 to 11 is implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the cache replacement method according to any one of claims 1 to 11 is implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the cache replacement method according to any one of claims 1 to 11 is implemented.

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