Modularized mainboard expansion framework based on chipset

Abstract

The invention relates to a modular mainboard architecture technology, and discloses a modular mainboard expansion architecture based on a chipset. The modular mainboard expansion architecture comprises a substrate, at least two pluggable chip modules and a programmable silicon intermediary module, wherein the pluggable chip module is in detachable physical connection with the substrate through the magnetic suction interface module; the magnetic suction interface adopts a Halbach permanent magnet array in 15-degree spiral layout, and is matched with an electromagnetic compensation coil to realize rapid demagnetization and adhesion prevention; the programmable silicon intermediary module is composed of a basic routing layer and a protocol conversion layer, the basic routing layer is integrated on the substrate, the protocol conversion layer is integrated with a pluggable chip module, the pluggable chip module generates an unclonable PUF function and is used for chip identity authentication, the substrate sends a verification request and a generated unique signature through the PUF function, and the verification request and the generated unique signature are sent to the substrate. And the protocol conversion layer loads a module configuration file to support dynamic protocol conversion and topology reconstruction.

Description

Technical Field

[0001] The present invention relates to modular motherboard architecture technology, and in particular to a chipset-based modular motherboard expansion architecture. Background Art

[0002] Embedded systems are widely used in various fields. As an important component of embedded systems, the performance and reliability of single-board computers are crucial to the operation of the entire system.

[0003] Existing technologies include a single-board computer motherboard based on the VPX architecture, such as the one proposed in Chinese patent application CN112380162A. In this patent, the processor module is connected to a first interface module, a GPU module, an MXM graphics card module, and a storage module. The processor module is connected to the motherboard expansion chipset via PCIE signal lines. The processor module and motherboard expansion chipset are each connected to a VPX connector module. Providing multiple interfaces on the motherboard can meet different needs and improve compatibility.

[0004] However, most current motherboard architectures have several key technical bottlenecks, which limit their performance in complex and changing application scenarios.

[0005] Traditional single-board computers (SBCs) have a fixed motherboard structure, making it difficult to support flexible expansion and hot-swappable operations for heterogeneous computing modules such as CPUs, FPGAs (Field Programmable Gate Arrays), and NPUs (Neural Processing Units). This hardware staticity significantly limits the system's adaptability and maintainability. Any system upgrade or component replacement requires downtime, complete disassembly, and replacement of the entire device. Serial transmission, decompression, and reconstruction are then required. Furthermore, dynamic compatibility issues with heterogeneous protocols must be addressed.

[0006] This not only increases maintenance costs but also leads to long service interruptions. Especially in critical application scenarios such as automotive, military, and aerospace, any service interruption can have serious consequences. Summary of the Invention

[0007] Based on the above technical problems, the present invention proposes a modular motherboard expansion architecture based on a chipset.

[0008] The technical solution of the present invention is achieved as follows: A chipset-based modular motherboard expansion architecture, comprising: substrate, Pluggable chip modules, A programmable silicon intermediary module, which is composed of a basic routing layer and a protocol conversion layer; The pluggable chip module is detachably connected to the substrate by a magnetic interface module, the basic routing layer is integrated on the substrate, and the protocol conversion layer is integrated with the pluggable chip module. The pluggable chip module generates an unclonable PUF function for chip identity authentication. The substrate sends a verification request through the PUF function, generates a unique signature, and then the protocol conversion layer loads the module configuration file to reconstruct the substrate signal topology.

[0009] In the present invention, the pluggable chip module consists of a liquid cooling interface, a quantum contact layer, a functional chip layer and an electromagnetic locking layer. The substrate integrated liquid cooling system is connected to a liquid cooling interface, which is a plurality of copper micro-tubes for conducting heat away from the functional chip layer.

[0010] In the present invention, the quantum contact layer is used to provide power supply, wherein the quantum contact layer includes: Multiple power contacts; Multiple high-speed signal contacts for high-speed data communication transmission; PUF identity contacts, which generate physically unclonable PUF functions based on quantum dot arrays for chip identity authentication; Functional chip layer; The electromagnetic locking layer is used for the detachable insertion and removal of pluggable chip modules.

[0011] In the present invention, the electromagnetic locking layer includes an electromagnetic lock and an anti-misinsertion guide key.

[0012] In the present invention, the magnetic interface module is composed of a contact layer, a soft magnetic guide layer, a permanent magnet array and an electromagnetic compensation coil. The soft magnetic guide layer is used to guide and focus the magnetic flux lines. The permanent magnet array is arranged in a 15° spiral layout, and the electromagnetic compensation coil is arranged around the permanent magnet array.

[0013] In the present invention, the protocol conversion layer includes TSV silicon vias, a clock tree grid and a protocol bridge IP core. The TSV silicon vias are vertically interconnected with the functional chip layer, and the protocol bridge IP core implements dynamic adjustment of the protocol by RTL code.

[0014] In the present invention, the basic routing layer includes: Multiple independent power supply areas, Overcurrent fuse, used to cut off the power path due to overcurrent; A clock buffer is used to drive a clock signal to multiple load terminals; Signal paths are divided into main path, backup path and detection path; PUF verification unit, which generates a unique identity and key based on the physically unclonable PUF function; The topology preset unit controls the connection topology and operation mode switching inside the substrate.

[0015] In the present invention, the substrate further includes a CAN bus, a Gigabit Ethernet, a BMC management network port, a USB2.0, an HDMI1.0, a LVDS, a SATA storage, and a power status interface.

[0016] In the present invention, the substrate further includes Gigabit Ethernet, USB3.0, RS232 debugging serial port, RS422 serial port, DVI-D, SATA storage, CPCI expansion slot, XMC expansion slot, RTC clock, and status indicator light.

[0017] In the present invention, the substrate also includes a 10G optical port, a 1G electrical port, a PCIe4.0 slot, an MXM graphics card slot, a USB3.0, a multi-protocol serial port, a video output interface, a BMC debugging interface, and SATA storage.

[0018] The implementation of the chipset-based modular motherboard expansion architecture of the present invention has the following beneficial effects: 1. By introducing pluggable chip modules and magnetic interface modules, the system supports fast hot-swap operations. Users can flexibly replace computing chip modules such as FPGA, NPU, and CPU according to actual needs, improving system adaptability and scalability to meet the computing needs of different application scenarios.

[0019] 2. The pluggable chip module integrates a liquid cooling port with a copper micro-tube heat conduction structure, efficiently dissipating heat generated during chip operation. The liquid cooling port automatically seals during insertion and removal to prevent coolant leakage, ensuring system stability and safety under high load operation.

[0020] 3. The power contacts in the quantum contact layer adopt a triple redundant design, which can maintain normal power supply even if some contacts fail, significantly improving the stability and fault tolerance of the system power supply, and reducing performance degradation or system interruption caused by power fluctuations.

[0021] 4. High-speed signal contacts support large-scale parallel data transmission, have good anti-electromagnetic interference capabilities, ensure data integrity and low bit error rate in high-speed communication between chips, and are suitable for high-bandwidth, low-latency computing scenarios.

[0022] 5. PUF identity contacts generate a unique physically unclonable function to authenticate the chip module and prevent unauthorized access to the system. Simultaneously, the PUF verification unit generates a 256-bit quantum-grade key for device authentication and data encryption, enhancing system security. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the structure of the modular motherboard expansion architecture of the present invention; Figure 2 This is a schematic structural diagram of the modular motherboard expansion architecture of the present invention from another angle; Figure 3 This is a block diagram of the modular motherboard expansion architecture of the present invention; Figure 4 This is a cross-sectional structural block diagram of the pluggable chip module of the present invention; Figure 5 This is a cross-sectional structural diagram of the magnetic interface module of the present invention; Figure 6 This is a cross-sectional structural block diagram of the basic routing layer of the present invention; Figure 7 This is a flowchart of the modular motherboard expansion architecture of the present invention; Figure 8 This is a flowchart of the modular motherboard expansion architecture of the present invention.

[0024] The accompanying drawings are denoted by the following symbols: 10-substrate, 20-pluggable chip module, 21-liquid cooling interface, 22-quantum contact layer, 221-power contact, 222-high-speed signal contact, 223-PUF identity contact, 23-functional chip layer, 24-electromagnetic locking layer, 241-electromagnetic lock, 242-anti-misinsertion guide key, 30-programmable silicon interposer module, 31-basic routing layer, 311-independent power supply area, 312-overcurrent fuse, 313-clock buffer, 314-signal path, 315-PUF verification unit, 316-topology preset unit, 32-protocol conversion layer, 321-TSV silicon through-hole, 322-clock tree grid, 323-protocol bridge IP core, 40-magnetic interface module, 41-contact layer, 42-soft magnetic guide layer, 43-permanent magnet array, 44-electromagnetic compensation coil. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] Reference Figures 1 to 8 As shown, this embodiment provides a chipset-based modular motherboard expansion architecture including a baseboard 10, at least two pluggable chip modules 20, and a programmable silicon interposer module 30. The pluggable chip modules 20 are physically and detachably connected to the baseboard 10 via a magnetic interface module 40. The programmable silicon interposer module 30 is composed of a basic routing layer 31 and a protocol conversion layer 32. The basic routing layer 31 is integrated on the baseboard 10, and the protocol conversion layer 32 is integrated with the pluggable chip modules 20.

[0027] In one embodiment, the substrate 10 includes 8 CAN2.0 buses with a rate of 250kbps~1Mbps and an isolation of 2500Vrms; 4 Gigabit Ethernets, 100 / 1000Mbps; 1 BMC management network port, supporting the IPMI protocol; 2 USB2.0s, standard Type-A; 1 HDMI1.0 for video output; 1 LVDS for display interface; 1 SATA storage with a capacity ≥1TB and a read / write speed ≥100MB / s; and 1 power / status interface with an aperture switch, specifically white / green / yellow / red status indication.

[0028] In one embodiment, the substrate 10 includes 4 Gigabit Ethernet ports, 2 front-exit RJ45 ports, and 2 rear-exit J3 interfaces; 2 USB3.0 ports, front-exit Type-A ports; 1 RS232 debug serial port, front-exit RJ45 port, baud rate 115200; 4 RS422 serial ports, rear-exit J5 interface ports; 1 DVI-D port, front-exit, supporting 1920×1080; 3 SATA storage ports, specifically 1 nSATA port + 2 rear-exit SATA ports; at least 4 CPCI expansion slots, 32-bit / 33MHz; 1 XMC expansion slot, with reserved installation space; 1 RTC clock, motherboard integrated battery holder; 2 status indicator lights, specifically a power light + a hard disk light; and 1 reset button.

[0029] In one embodiment, the substrate 10 includes 4 10 Gigabit optical ports, SFP+; 4 Gigabit electrical ports, RJ45; 4 PCIe4.0 slots; 1 MXM graphics card slot, PCIe4.0×8 signal; 6 USB3.0; 6 multi-protocol serial ports, specifically RS232×2+RS422×2+RS485×2; 3 video outputs, specifically 2 HDMI+1 VGA; 1 BMC debug interface, specifically 2 VGA+1 RS232+1 network port; 2 SATA storage; 6 fan controls, specifically 4 chassis fans + 2 CPU fans; 5 front panel controls, specifically power button + reset button + 3 status indicator lights.

[0030] Refer again Figures 4 and 5 As shown, the pluggable chip module 20 consists of a liquid cooling interface 21, a quantum contact layer 22, a functional chip layer 23, and an electromagnetic locking layer 24. The substrate 10 integrates a liquid cooling system connected to the liquid cooling interface 21. The liquid cooling interface 21 consists of multiple copper microtubes that are used to quickly conduct heat away from the functional chip layer 23. During rapid plugging and unplugging, the liquid cooling interface 21 automatically seals to prevent coolant leakage and ensure stable system operation.

[0031] The quantum contact layer 22 is used to provide a stable power supply for the chip, wherein the quantum contact layer 22 includes: Power contact 221: The power contact 221 adopts a triple redundancy design. Even if one or two contacts fail, the system can still operate normally, reducing the impact of power fluctuations on chip performance; 32 pairs of differential high-speed signal contacts 222 transmit high-speed differential signals and support high-speed data communication between chips. 32 pairs of differential signals support large-scale parallel data transmission, and differential signals have good suppression capabilities against low-noise electromagnetic interference; The PUF identity contact 223 generates a physically unclonable PUF function based on a quantum dot matrix for chip identity authentication. The PUF of each chip is unique, preventing unauthorized chips from accessing the system.

[0032] The functional chip layer 23 is a computing chip such as FPGA / NPU / CPU.

[0033] The electromagnetic locking layer 24 is used to quickly insert and remove the pluggable chip module 20. The electromagnetic locking layer 24 includes an electromagnetic lock 241 and an anti-misinsertion guide key 242. When the power is off, the electromagnetic lock 241 automatically opens and releases to prevent damage to the pluggable chip module 20. The anti-misinsertion guide key 242 ensures that the pluggable chip module 20 is correctly inserted and prevents misinsertion.

[0034] Furthermore, the magnetic interface module 40 is composed of a contact layer 41, a soft magnetic guide layer 42, a permanent magnet array 43, and an electromagnetic compensation coil 44. The contact layer 41 is a gold-palladium alloy with an alloy ratio of Au:Pd of 90:10, providing a low-resistance, high-stability electrical contact interface, maintaining low wear rate and long-term conductivity during the plug-in and unplug process. The soft magnetic guide layer 42 is a Permalloy alloy, which is used to guide and focus the magnetic flux lines, improve the magnetic attraction efficiency, reduce edge leakage, and enhance the ability to resist external magnetic field interference. During the docking process, the soft magnetic guide layer 42 is guided by magnetic self-alignment.

[0035] The permanent magnet array 43 is a Halbach permanent magnet array with a 15° spiral layout. The alternating north and south poles enhance the magnetic field on one side and offset it on the other. The 15° spiral layout achieves a four-dimensional magnetic force distribution: axial, circumferential, radial, and spiral. The magnetic attraction reaches 45N at the center and 12N at the edges, enabling gradient adsorption control.

[0036] The electromagnetic compensation coil 44 is arranged around the permanent magnet array, typically as a multi-layer winding made of highly conductive copper wire or high-temperature superconducting coils. This enhances the magnetic attraction when powered on, and reverses the current applied when the power is turned off, rapidly demagnetizing the magnet and preventing residual magnetism from sticking after disconnection.

[0037] In this embodiment, again referring to Figure 7As shown, before a hot-swap operation, the management system first issues an uninstall command, and the substrate 10 activates a state preservation mechanism, including freezing the data stream, flushing the cache, and backing up the register state to the non-volatile dual in-line memory module (NVDIMM). Subsequently, the quantum contact layer 22 is controlled to quickly drop to a safe threshold, and the liquid cooling interface 21 is switched to bypass mode to ensure safety during the hot-swap process.

[0038] This stage involves manual operation, which is prevented by electromagnetic lock 241 and anti-misinsertion guide key 242. The anti-misinsertion guide key 242 has an angle tolerance within ±0.5°, and when a pull-out force exceeding 8N is applied, the electromagnetic lock 241 automatically pops open.

[0039] After the physical replacement is completed, the activation phase is entered through the protocol conversion layer 32. The protocol conversion layer 32 includes TSV silicon vias 321, a clock tree grid 322, and a protocol bridge IP core 323. The TSV silicon vias 321 use a 2.5D package with a diameter of 5μm, and are vertically interconnected with the functional chip layer 23 through the TSV silicon vias 321. The clock tree grid 322 is a copper pillar array that provides precise clock synchronization signals to ensure that the modules inside the functional chip layer 23 operate synchronously. The protocol bridge IP core 323 implements dynamic adjustment of the protocol through RTL code to achieve conversion between different protocols. The substrate 10 sends verification through the PUF identity contact 223 and returns a response signature to confirm the module identity. The signal topology is then reconstructed according to the loaded module configuration file, and the microkernel driver is injected into the functional chip, and the BIST self-test process is executed, and the self-test results are finally fed back to the substrate 10.

[0040] Refer again Figure 6 As shown, the basic routing layer 31 includes: Independent power supply area 311 divides the substrate 10 into multiple independent power supply areas, and sets the voltage (0.8V, 1.2V, 1.8V) for each area as needed to achieve voltage domain management; Overcurrent fuse 312, which quickly cuts off the power path to protect the circuit when an overcurrent or short circuit fault occurs; A clock buffer 313 is used to drive the clock signal to multiple load terminals to maintain signal integrity; The signal path 314 is divided into a primary path, a backup path, and a detection path to achieve redundancy and fault tolerance of signal transmission, and to enable failover and error detection mechanisms; PUF verification unit 315, generates a unique identity and key based on the physically unclonable PUF function to achieve hardware-level security authentication; The topology preset unit 316 presets 16 modes and controls the connection topology and operation mode switching inside the substrate 10 .

[0041] Refer again Figure 8 As shown, signal path 314 comprises a hardwired redundant structure with three channels: primary, backup, and detection. The primary path uses 8μm line width to optimize latency, while the backup path uses 12μm line width to enhance noise immunity. The delay difference is controlled within ±5ps. Vertical signal interconnection is achieved, and differential pair routing is used to ensure high-frequency signal integrity.

[0042] When the signal quality monitoring module detects that the CRC error exceeds the set threshold, it triggers the redundant path switching process: starting the backup path, shutting down the primary path, completing the route switching, and updating the route status to the NVDIMM to maintain topology consistency.

[0043] At the same time, the PUF verification unit generates a 256-bit quantum-level key for device authentication and data encryption to prevent unauthorized access.

[0044] In summary, the physical connection security and identity authentication issues are resolved through the magnetic interface 40 and the PUF authentication 223. When inserting a pluggable chip module for replacement, relying solely on the topology preset unit 316, it is unable to dynamically adapt to protocol differences, resulting in incompatibility.

[0045] Furthermore, in one embodiment, the protocol bridge IP core 323 implements dynamic protocol adjustment through RTL code to achieve conversion between different protocols. The specific steps include the following: Step 1: Analyze the input data stream in real time and identify the current communication protocol.

[0046] The preamble is extracted from the first 64 bits of the input stream to preliminarily determine the protocol type.

[0047] The subsequent 64 bits of data are extracted and their information entropy feature vectors are calculated to reflect the data distribution characteristics. The topology preset unit 316 pre-stores configuration bit streams and parameters corresponding to various protocols.

[0048] The input feature vector Vector with agreement signature Perform double index matching, specifically, with the pre-stored protocol signature vector Perform Hamming Distance and Cosine Similarity matching.

[0049] Protocol matching calculation:

[0050] Where S is the cosine similarity between the input signal and the protocol signature, ranging from 0 to 1. Larger values ​​indicate greater similarity. n is the number of dimensions of the feature vector, typically 64 or 128. is the eigenvalue of the i-th dimension of the input data stream, forming the input feature vector . The i-th dimension reference eigenvalue of the pre-stored protocol signature constitutes the protocol signature vector When S>0.95 and the Hamming distance is less than the threshold, the protocol is confirmed to be matched and the matching target protocol type is output.

[0051] Step 2: According to the matched target protocol type, the corresponding bit stream is loaded from the topology preset unit 316, a partial reconfiguration is performed on the specific logic area, and a specific data packet format conversion is performed.

[0052] Model the reconfiguration time:

[0053] in, The total time required to complete one RTL reconfiguration. This is the basic reconfiguration overhead time, which is a fixed value, typically 100 ns. The incremental latency introduced by each logical unit change, It is the delay coefficient caused by the change of clock frequency. The value is 2 ns, The value is 5 ns / MHz. The number of logic units that changed in this reconfiguration. The difference between the source and target protocol operating clock frequencies.

[0054] According to the above reconfiguration time model, the reconfiguration time is proportional to the logic change amount and the frequency jump amplitude.

[0055] Adopting a reconfigurable finite state machine architecture, it supports loading state migration logic of different protocols at runtime. The migration time model is:

[0056] in, The time required for state migration. is the current working clock frequency, is the total number of states that need to be migrated, is the number of pipeline stages.

[0057] Migration time is affected by clock cycles and pipeline efficiency, further reducing switching latency. Data flow interruption time during protocol switching is less than 1 μs, meeting high-real-time requirements in military and automotive applications.

[0058] Specifically, protocol conversion is essentially a linear transformation process of mapping input data packet I to output data packet O.

[0059] Data packet format conversion: .in, O is the output protocol packet vector, a 64-dimensional floating-point or integer vector. W is the protocol conversion weight matrix, a 64×64 matrix, which stores address mapping, command encoding rules, etc. I is the input protocol packet vector, and B is the bias vector, which adds fixed fields such as the packet header, CRC, and virtual channel identifier.

[0060] Weight matrix dynamic fusion formula:

[0061] in, is the new weight matrix for practical application, is the protocol similarity factor. is the dedicated transformation matrix for the target protocol, obtained through pre-training or configuration. The default basic conversion matrix is ​​used for unknown protocols or fault tolerance.

[0062] A sudden change in the format of the old and new packets can cause CRC check failures or field loss, leading to communication interruption. In this embodiment, a gradual transition of packet formats is ensured. A basic conversion matrix provides basic compatibility with unknown protocols, preventing packet loss or format errors during protocol switching and ensuring communication continuity. Furthermore, to ensure the stability of cross-clock domain operations, path delay differences are compensated.

[0063] Step 3: Establish a distributed clock network between the clock buffer 313 of the basic routing layer 31 and the clock tree grid 322 of the protocol conversion layer 32. Dynamic compensation of path delays is used to eliminate clock skew in signal transmission and ensure synchronization of operations across clock domains.

[0064] Mathematical constraints:

[0065] in, is the maximum skew of each path in the clock network. For example: =5GHz, <20ps. The maximum skew across each path in a traditional clock network exceeds 3 GHz, easily leading to setup / hold time violations. This can lead to soaring data transmission errors across clock domains, dynamic reconfiguration timing conflicts, and clock frequency jumps during protocol switching, making the traditional clock network unable to adaptively compensate for delays.

[0066] Traditional solutions require serial bitstream transmission, decompression, and reconstruction, resulting in high latency. Hot-swapping causes service interruptions and cannot meet the needs of high-speed switching.

[0067] Reconfiguration time optimization model:

[0068] in, is the total time taken for actual reconfiguration, is the compressed bitstream size, DMA transfer bandwidth. The time required for decompression, Refer to the above formula.

[0069] transmission and decompression Execute in parallel and prioritize the steps that take longer time.

[0070] The transmission time and decompression time are maximized to balance the compression ratio and decompression speed.

[0071] Traditional protocol switching requires downtime to load firmware, serial transmission, decompression, and reconstruction, which is time-consuming and cannot meet the real-time requirements of automotive and military scenarios. This embodiment completes heterogeneous protocol recognition, clock synchronization, and gradual data packet format conversion within μs, ensuring zero data loss and uninterrupted service during hot plugging.

[0072] Extract entropy feature vectors of input data streams in real time , calculate and pre-store signatures When S>0.95, load the target protocol, otherwise enable the basic conversion matrix Provide a safety net to resolve unknown protocol compatibility issues.

[0073] Using weight fusion formula With linear transformation , automatically fill in CRC and other fields through the bias vector B, and use the protocol similarity factor Dynamically adjust conversion rules to eliminate packet loss caused by format mutations.

[0074] The transmission and decompression stages are performed in parallel, compressing the reconstruction delay by 60% and the interruption time by <1μs. A distributed network is established between the clock buffer 313 and the clock tree grid 322 to constrain the path offset, for example, <20ps at 5GHz, eliminating timing violations during high-frequency switching.

[0075] Protocol matching provides matrix gradient Adjustment basis, Ensure that basic communications are not interrupted under unknown protocols; parallel reconstruction and clock compensation work together to ensure μs-level switching timeliness, and the weight fusion mechanism maintains data packet continuity; ultimately achieve zero data loss during the hot plug process, μs-level completion of protocol switching, and basic compatibility with unknown modules.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A modular motherboard expansion architecture based on a chipset, characterized in that: include: substrate, Pluggable chip modules, A programmable silicon intermediary module, which is composed of a basic routing layer and a protocol conversion layer; The pluggable chip module is detachably connected to the substrate by a magnetic interface module, the basic routing layer is integrated on the substrate, and the protocol conversion layer is integrated with the pluggable chip module. The pluggable chip module generates an unclonable PUF function for chip identity authentication. The substrate sends a verification request through the PUF function, generates a unique signature, and then the protocol conversion layer loads the module configuration file to reconstruct the substrate signal topology.

2. The modular motherboard expansion architecture according to claim 1, wherein: The pluggable chip module consists of a liquid cooling interface, a quantum contact layer, a functional chip layer and an electromagnetic locking layer. The substrate integrated liquid cooling system is connected to a liquid cooling interface, which is a plurality of copper micro-tubes for conducting heat away from the functional chip layer.

3. The modular motherboard expansion architecture according to claim 2, wherein: The quantum contact layer is used to provide power supply, wherein the quantum contact layer includes: Multiple power contacts; Multiple high-speed signal contacts for high-speed data communication transmission; PUF identity contacts, which generate physically unclonable PUF functions based on quantum dot arrays for chip identity authentication; Functional chip layer; The electromagnetic locking layer is used for the detachable insertion and removal of pluggable chip modules.

4. The modular motherboard expansion architecture according to claim 3, wherein: The electromagnetic locking layer includes an electromagnetic lock and an anti-misinsertion guide key.

5. The modular motherboard expansion architecture according to claim 1, wherein: The magnetic interface module consists of a contact layer, a soft magnetic guide layer, a permanent magnet array and an electromagnetic compensation coil. The soft magnetic guide layer is used to guide and focus the magnetic flux lines. The permanent magnet array is arranged in a 15° spiral layout, and the electromagnetic compensation coil is arranged around the permanent magnet array.

6. The modular motherboard expansion architecture according to claim 2, wherein: The protocol conversion layer includes TSV silicon vias, a clock tree grid, and a protocol bridge IP core. The TSV silicon vias are vertically interconnected with the functional chip layer. The protocol bridge IP core implements dynamic adjustment of the protocol through RTL code.

7. The modular motherboard expansion architecture according to claim 1, wherein: The basic routing layer includes: Multiple independent power supply areas, Overcurrent fuse, used to cut off the power path due to overcurrent; A clock buffer is used to drive a clock signal to multiple load terminals; Signal paths are divided into main path, backup path and detection path; PUF verification unit, which generates a unique identity and key based on the physically unclonable PUF function; The topology preset unit controls the connection topology and operation mode switching inside the substrate.

8. The modular motherboard expansion architecture according to claim 1, wherein: The substrate also includes a CAN bus, a Gigabit Ethernet, a BMC management network port, a USB2.0, an HDMI1.0, a LVDS, a SATA storage, and a power status interface.

9. The modular motherboard expansion architecture according to claim 1, wherein: The base plate also includes Gigabit Ethernet, USB3.0, RS232 debugging serial port, RS422 serial port, DVI-D, SATA storage, CPCI expansion slot, XMC expansion slot, RTC clock, and status indicator light.

10. The modular motherboard expansion architecture according to claim 1, wherein: The substrate also includes a 10G optical port, a 1G electrical port, a PCIe4.0 slot, an MXM graphics card slot, a USB3.0, a multi-protocol serial port, a video output interface, a BMC debugging interface, and SATA storage.

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