Self-bias, transient boost, low quiescent power level shift circuit and control method

Abstract

The present disclosure provides a self-biased, transient-enhanced, low quiescent power level shifter circuit and control method. The level shifter circuit includes a first cross-coupled circuit provided with a first transistor and a second transistor, whose sources are connected to a first power supply voltage, whose drains are connected to corresponding first and second nodes via first and second isolation devices, respectively, and whose gates are connected to corresponding second and first nodes, respectively; an input circuit provided between an output node and ground; and the input circuit is provided with a first input terminal and a second input terminal and pull-up and pull-down circuits. The level shifter circuit provided by the embodiments of the present disclosure can shorten the transient time delay during the conversion between the low voltage domain and the high voltage domain, while only consuming nanampere level of static current.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to self-biasing, transient enhancement, low static power level shifting circuits and control methods. Background Technology

[0002] As integrated circuit process dimensions continue to shrink, the circuit structure of System-on-Chip (SoC) becomes increasingly complex. To reduce circuit power consumption, the most direct and effective way is to reduce the power supply voltage. Level shifters (LS) are generally used to connect signals in different voltage domains, thereby meeting the different amplitude signal requirements of various circuit modules within the SoC.

[0003] Currently, typical level shifting circuits, when there is a significant difference between the low-voltage high level (VDDL) and the high-voltage high level (VDDH), cause the drain-source voltage withstand value of the low-voltage transistor to be exceeded during logic level switching, resulting in transistor breakdown and damage, affecting the normal operation of the circuit. Furthermore, some level shifting circuits use current mirrors, replacing the cross-coupling circuit with a current mirror composed of two PMOS transistors. Due to the presence of the current mirror structure, the entire level shifting circuit generates significant static power consumption when the input is low, thus failing to meet the low-power application requirements of SOC design.

[0004] Therefore, existing technologies still need to be improved and enhanced.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes a self-biased transient-enhanced low static power level shifting circuit that enables level switching between low and high voltage domains in integrated circuits, while further reducing the transient time delay problem in the switching process between low and high voltage domains in existing level shifting circuits.

[0007] In a first aspect of this disclosure, a self-biased transient enhancement low quiescent power level shifting circuit is proposed. The level shifting circuit is disposed between a first power supply voltage VDDH and ground GND. The level shifting circuit includes: a first cross-coupling circuit comprising a first transistor HVPM1 and a second transistor HVPM2, the source of which is simultaneously connected to the first power supply voltage VDDH, the drain of which is connected to the corresponding first node A and the corresponding second node B via a first isolation device HVNM5 and a second isolation device HVNM6, respectively, and the gate of which is connected to the corresponding second node B and the corresponding first node A; and an input circuit disposed between an output node and ground GND, the output node being configured to be connected to the first... Node A and the aforementioned second node B constitute the input circuit. The input circuit is provided with a first input terminal inp and a second input terminal inn, as well as pull-up and pull-down circuits. The pull-up and pull-down circuits are located between the second power supply voltage VDDL and ground GND and are respectively connected to the first input terminal inp and the second input terminal inn, and respectively connected to the first clamping node C and the second clamping node D. When the first input terminal inp is set to the second power supply voltage VDDL, the first clamping node C is adjusted to be connected to ground GND. When the first input terminal inp is set to be connected to ground GND, the first clamping node C is adjusted to be connected to the second power supply voltage VDDL. The first power supply voltage VDDH is higher than the second power supply voltage VDDL.

[0008] Furthermore, in some embodiments, the level shifting circuit is further provided with a second cross-coupling circuit, which is disposed between the first power supply voltage VDDH and the output node.

[0009] Furthermore, in some embodiments, the second cross-coupling circuit is configured to include: a third transistor HVPM5 and a fourth transistor HVPM6, the sources of which are simultaneously connected to the first power supply voltage VDDH, the drains of which are respectively connected to the corresponding first node A and the second node B, and the gates of which are respectively connected to the drains of the second transistor HVPM2 and the first transistor HVPM1.

[0010] Furthermore, in some embodiments, the level shifting circuit further includes diodes and / or transistors configured to block loop interference, wherein the first isolation device HVNM5 and / or the second isolation device HVNM6 are configured to block loop interference.

[0011] Furthermore, in some embodiments, the input circuit is provided with a first input transistor LVNM1 and a second input transistor LVNM2, as well as a first protection transistor HVNM1_native and a second protection transistor HVNM2_native; the first input transistor LVNM1 is configured such that its gate is connected to the first input terminal inp, its drain is connected to the source of the first protection transistor HVNM1_native, and its source is connected to ground GND; the second input transistor LVNM2 is configured such that its gate is connected to the second input terminal inn, and its drain is connected to the first input terminal inp. The source of the second protection transistor HVNM2_native is connected to ground (GND); the gate of the first protection transistor HVNM1_native is connected to the gate of the first input transistor LVNM1, and its drain is connected to the first node A; its source is connected to the drain of the first input transistor LVNM1; the gate of the second protection transistor HVNM2_native is connected to the gate of the second input transistor LVNM2, its drain is connected to the second node B, and its source is connected to the drain of the second input transistor LVNM2.

[0012] Furthermore, in some embodiments, the pull-up / pull-down circuit is configured to consist of a fifth transistor LVPM1, a sixth transistor LVPM2, a seventh transistor LVNM3, and an eighth transistor LVNM4; the fifth transistor LVPM1 is configured such that its gate is connected to the gate of the first input transistor LVNM1, its drain is connected to the first clamping node C, and its source is connected to the second power supply voltage VDDL; the sixth transistor LVPM2 is configured such that its gate is connected to the gate of the second input transistor LVNM2, its drain is connected to the second clamping node D, and its source is connected to the second power supply voltage VDDL; the seventh transistor LVNM3 is configured such that its gate is connected to the gate of the first input transistor LVNM1, its drain is connected to the first clamping node C, and its source is connected to ground GND; the eighth transistor LVNM4 is configured such that its gate is connected to the gate of the second input transistor LVNM2, its drain is connected to the second clamping node D, and its source is connected to ground GND.

[0013] Furthermore, in some embodiments, the level shifting circuit further includes an output inverting unit for inverting the voltages of the first node A and the second node B to obtain a secondary output signal.

[0014] Furthermore, in some embodiments, the aforementioned output inverting unit is provided with a first output inverting unit and a second output inverting unit; the aforementioned first output inverting unit is composed of a first inverting transistor HVPM3 and a second inverting transistor HVNM3; the aforementioned first inverting transistor HVPM3 is configured such that its gate is connected to the aforementioned first node A and the gate of the aforementioned second inverting transistor HVNM3, its source is connected to the aforementioned first power supply voltage VDDH, and its drain is connected to the first output terminal out and the drain of the aforementioned second inverting transistor HVNM3; the aforementioned second inverting transistor... The source of transistor HVNM3 is connected to ground (GND); the second output inverting unit is composed of a third inverting transistor HVPM4 and a fourth inverting transistor HVNM4; the gate of the third inverting transistor HVPM4 is connected to the gate of the second node B and the fourth inverting transistor HVNM4, its source is connected to the first power supply voltage VDDH, and its drain is connected to the second output terminal outb and the drain of the fourth inverting transistor HVNM4; the source of the fourth inverting transistor HVNM4 is connected to ground (GND).

[0015] Furthermore, in some embodiments, the level shifting circuit further includes an input conversion unit for generating two corresponding differential output signals from the primary input signal to serve as input signals for the first input terminal inp and the second input terminal inn.

[0016] In a second aspect of this disclosure, a control method for the level shifting circuit as described above is also provided. The method includes: in response to a first input signal, when the first input terminal inp is set to a low-voltage high-level second power supply voltage VDDL; the first clamping node C is adjusted to a low level connected to ground GND; when the first input terminal inp is set to a low level connected to ground GND, the first clamping node C is adjusted to a low-voltage high-level second power supply voltage VDDL; and in response to a second input signal that is inverse of the first input signal, when the second input terminal inn is set to a low-voltage high-level second power supply voltage VDDL; the second clamping node D is adjusted to a low level connected to ground GND; when the second input terminal inn is set to a low level connected to ground GND, the second clamping node D is adjusted to a low-voltage high-level second power supply voltage VDDL.

[0017] This disclosure has the following advantages over the prior art:

[0018] (1) In some embodiments, intrinsic transistors, such as native NMOS transistors, are used instead of ordinary NMOS transistors. They use the input differential signal to complete the biasing of the selection clamp protection circuit, eliminating the need for additional bias circuits, reducing circuit complexity, and simplifying the layout and routing of subsequent circuits. (2) Furthermore, in some embodiments, the input signal also serves as the control signal for the selection clamp circuit, eliminating the need for additional control logic and accelerating the corresponding node to a low-voltage high level VDDL or GND. (3) Further still, in some embodiments, a dual positive feedback loop is used to accelerate the establishment process of the high-voltage high level VDDH and GND at the output terminal, enhancing the transient response of the level shifter (LS) circuit. (4) Further still, in some embodiments, nanoampere-level static current power consumption is achieved, making it suitable for low-power application scenarios. Attached Figure Description

[0019] The above and other features, advantages and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description, wherein:

[0020] Figure 1 The schematic diagram of a level shifting circuit employing cross-coupled pairs is shown according to some examples;

[0021] Figure 2 A schematic diagram of a level shifting circuit employing a current mirror is shown, based on some examples.

[0022] Figure 3 A schematic diagram of a self-biased, transient-enhanced, low-static-power level shifting circuit according to some embodiments of the present disclosure is shown.

[0023] Figure 4 It shows Figure 3 A schematic diagram of the positive feedback loop one of the level shifting circuit in the embodiment;

[0024] Figure 5 It shows Figure 3 A schematic diagram of the second positive feedback loop of the level shifting circuit in the embodiment;

[0025] Figure 6 It shows Figure 3 The input signal of the level shifting circuit in the embodiment is a schematic diagram of the signal changes at each node of the circuit at the rising edge;

[0026] Figure 7 It shows Figure 3 The schematic diagram of the signal changes at each node of the circuit when the input signal of the level shift circuit in the embodiment is the falling edge;

[0027] Figure 8 It shows Figure 3 The static current power consumption simulation results of the level shifting circuit in the embodiment are shown in the figure.

[0028] Figure 9 It shows Figure 3 Another simulation result diagram of the level shifting circuit in the embodiment;

[0029] Figure 10 It shows Figure 3 Another simulation result diagram of the level shifting circuit in the embodiment;

[0030] Figure 11 A schematic diagram of a self-biased, transient-enhanced, low-static-power level shift circuit according to other embodiments of the present disclosure is shown.

[0031] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0032] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0033] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0034] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first state may also be referred to as a second state, and similarly, a second state may also be referred to as a first state. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0035] It should be understood that in some instances, a typical level shifter (LS) circuit is provided, such as... Figure 1 As shown, it employs a cross-coupled level shifter (CCLS) circuit, with a high-voltage transistor on the upper layer and a low-voltage transistor on the lower layer. When the input terminal in is at a low-voltage high level VDDL, the inb terminal is at a low level. At this time, NMOS transistor LVNM1 is turned on, LVNM2 is turned off, and the voltage at point A is pulled down to a low level, causing PMOS transistor HVPM2 to turn on. The voltage at point B is pulled up to a high-voltage high level VDDH, and after passing through an inverter, the output terminal out is at a high-voltage high level VDDH. The opposite occurs when the input terminal in is at a low level. When the difference between the low-voltage high level VDDL and the high-voltage high level VDDH is large, during the logic level switching process, the voltages at points A and B may exceed the withstand voltage of the drain-source voltage of the low-voltage transistor, causing transistor breakdown and damage, affecting the normal operation of the circuit.

[0036] Furthermore, in other instances, for example, the following methods were employed: Figure 2 The current mirror level shift circuit (CMLS) shown replaces the cross-coupled circuit with a current mirror formed by PMOS transistors HNPM1 and HVPM2. When the input terminal in is low, the inb terminal is VDDL. At this time, NMOS transistor LVNM1 is cut off, LVNM2 is turned on, and the upper PMOS transistor HVPM2 forms a gate-drain short connection, operating in the saturation region and generating a large static current. Because LVNM1 is cut off, the voltage at point C is pulled up to a high voltage level VDDH. After passing through the inverter, the output terminal out is low. When the input terminal in is a low voltage high level VDDL, NMOS transistor LVNM1 is turned on. Because LVNM1 is cut off, the voltage at point C is pulled down to a low level. After passing through the inverter, the output terminal out is a high voltage high level VDDH. Due to the presence of the current mirror structure, when the input terminal in is low, the entire level shift circuit generates a large static power consumption, thus failing to meet the low power consumption application requirements of SOC design.

[0037] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes a self-biased, transient-enhanced, low-static-power level shifting circuit, which will be described below in conjunction with the accompanying drawings and specific embodiments.

[0038] Figure 3A schematic diagram of a self-biased, transient-enhanced, low quiescent-power level shifter circuit according to some embodiments of the present disclosure is shown. In this illustrated embodiment, a self-biased, transient-enhanced, low quiescent-power level shifter circuit is shown, disposed between a first power supply voltage VDDH and ground GND. The level shifter circuit includes: a first cross-coupled circuit, incorporating a first transistor HVPM1 and a second transistor HVPM2. The sources of the first transistor HVPM1 and the second transistor HVPM2 are simultaneously connected to the first power supply voltage VDDH. The drains of the first transistor HVPM1 and the second transistor HVPM2 are respectively connected to a first node A and a second node B via a first isolation device HVNM5 and a second isolation device HVNM6. The gates of the first transistor HVPM1 and the second transistor HVPM2 are respectively connected to a second node B and a first node A. Furthermore, the level shifting circuit also includes: an input circuit disposed between the output node and ground GND, wherein the output node can be configured to consist of the first node A and the second node B; and the input circuit is configured with a first input terminal inp and a second input terminal inn (which can be differential inputs). The level shifting circuit further includes: pull-up / pull-down circuits disposed between the second power supply voltage VDDL and ground GND and connected to the first input terminal inp and the second input terminal inn respectively, and connected to the first clamping node C and the second clamping node D respectively. It should be understood that when the first input terminal inp is set to the second power supply voltage VDDL, the first clamping node C is adjusted to be connected to ground GND; when the first input terminal inp is set to be connected to ground GND, the first clamping node C is adjusted to be connected to the second power supply voltage VDDL; wherein the first power supply voltage VDDH is higher than the second power supply voltage VDDL. This should be understood as follows: the pull-up and pull-down circuits are composed of the four transistors LVPM1, LVNM3 and LVPM2, LVNM4 shown in the diagram. Taking LVPM1 and LVNM3 as an example, when inp is high (VDDL), LVNM3 is turned on, and point C is pulled down to ground (GND) for pull-down. When inp is ground (GND), LVPM1 is turned on, and point C is pulled up to high (VDDL) for pull-up. Therefore, this circuit that can both pull up and pull down is called a pull-up and pull-down circuit.

[0039] Furthermore, in some embodiments, the level shifting circuit is further provided with a second cross-coupling circuit, which is disposed between the first power supply voltage VDDH and the output node. Further, the second cross-coupling circuit is configured to include, as shown in the figure, a third transistor HVPM5 and a fourth transistor HVPM6, the sources of the third transistor HVPM5 and the fourth transistor HVPM6 being simultaneously connected to the first power supply voltage VDDH, the drains of the third transistor HVPM5 and the fourth transistor HVPM6 being respectively connected to the corresponding first node A and the second node B, and the gates of the third transistor HVPM5 and the fourth transistor HVPM6 being respectively connected to the drains of the second transistor HVPM2 and the first transistor HVPM1.

[0040] Furthermore, in some embodiments, the level shifting circuit further includes a first isolation device HVNM5 and a second isolation device HVNM6. It should be understood that the first isolation device HVNM5 and the second isolation device HVNM6 can be diodes or corresponding transistors used to block loop interference. It should be understood that the isolation devices HVNM5 and HVNM6 effectively isolate points A and B from the gates of transistors HVPM5 and HVPM6. If these isolation devices are removed, the two positive feedback loops would be directly connected, resulting in chaotic mutual interference.

[0041] Furthermore, in some embodiments, the input circuit may also include a first input transistor LVNM1 and a second input transistor LVNM2, as well as a first protection transistor HVNM1_native and a second protection transistor HVNM2_native. The first input transistor LVNM1 is configured such that its gate is connected to the first input terminal inp, its drain is connected to the source of the first protection transistor HVNM1_native, and its source is connected to ground GND. Correspondingly, the second input transistor LVNM2 is configured such that its gate is connected to the second input terminal inn, its drain is connected to the source of the second protection transistor HVNM2_native, and its source is connected to ground GND. The first protection transistor HVNM1_native is connected to the gate of the first input transistor LVNM1, and its drain is connected to the first node A. The source of the first protection transistor HVNM1_native is connected to the drain of the first input transistor LVNM1 (i.e., connected to the first clamping node C in the figure). The second protection transistor HVNM2_native is connected to the gate of the second input transistor LVNM2, and its drain is connected to the second node B. The source of the second protection transistor HVNM2_native is connected to the drain of the second input transistor LVNM2 (i.e., connected to the second clamping node D in the figure). It should also be understood that both the first protection transistor HVNM1_native and the second protection transistor HVNM2_native can be intrinsic transistors, for example, both are intrinsic NMOS transistors. It should also be understood that using native NMOS transistors instead of ordinary NMOS transistors allows the selection clamping protection circuit to be biased using a differential input signal, eliminating the need for additional biasing circuitry, reducing circuit complexity, and simplifying subsequent circuit layout and routing. It should be understood that transistors HVNM1_native1 and 2 are used to protect the underlying first input transistor LVNM1 and second input transistor LVNM2; since the voltage at points A and B can reach up to VDDH, without these two transistors, the underlying first input transistor LVNM1 and second input transistor LVNM2 would be damaged.

[0042] Furthermore, in some embodiments, the pull-up / pull-down circuit is configured to consist of a fifth transistor LVPM1, a sixth transistor LVPM2, a seventh transistor LVNM3, and an eighth transistor LVNM4; the fifth transistor LVPM1 is configured such that its gate is connected to the gate of the first input transistor LVNM1, its drain is connected to the first clamping node C, and its source is connected to the second power supply voltage VDDL; the sixth transistor LVPM2 is configured such that its gate is connected to the gate of the second input transistor LVNM2, and the sixth transistor LVPM2... The drain of the sixth transistor LVNM2 is connected to the second clamping node D; the source of the sixth transistor LVNM2 is connected to the second power supply voltage VDDL; the gate of the seventh transistor LVNM3 is configured to be connected to the gate of the first input transistor LVNM1; the drain of the seventh transistor LVNM3 is connected to the first clamping node C; the source of the seventh transistor LVNM3 is connected to ground GND; the gate of the eighth transistor LVNM4 is configured to be connected to the gate of the second input transistor LVNM2; the drain of the eighth transistor LVNM4 is connected to the second clamping node D; and the source of the eighth transistor LVNM4 is connected to ground GND.

[0043] It should be understood that, regarding Figure 3 The example implementation can be understood as follows. Figure 3 In the illustrated example embodiment, the level shifting circuit includes: an input circuit, a gating clamp protection circuit, a cross-coupled shifting circuit, and an output buffer circuit. The input circuit receives a set of differential input signals at each of its two input terminals and is connected to the gating clamp protection circuit. The gating clamp protection circuit uses the input differential signals for simultaneous biasing, and its output is connected to the cross-coupled shifting circuit. When the input signal is low, the key component of the gating clamp protection circuit, the native NMOS, can be correctly biased. Simultaneously, the input signal also serves as the gating control signal for the gating clamp protection circuit, clamping the sources of the two native NMOS transistors to a low-voltage high-level VDDL or GND. The cross-coupled shifting circuit performs level shifting on the signal passing through the gating clamp protection circuit, raising the high level from the low voltage VDDL to the high voltage VDDH. Simultaneously, a positive feedback loop accelerates the signal transient setup process. The output buffer circuit buffers the level-shifted signal, enhancing its driving capability. It should be understood that in some embodiments of this disclosure, the gate clamping protection circuit, i.e., transistors HVNM1_native1 and 2, is included as part of the input circuit. In some embodiments of this disclosure, the output buffer circuit is configured as an output inverting unit. In some embodiments of this disclosure, the cross-coupled shift circuit includes not only a first cross-coupled circuit but also a second cross-coupled circuit.

[0044] It should also be understood that, based on the above Figure 3Example implementation, in conjunction with Figure 4 and Figure 5 The schematic diagram illustrates the working principle of this level shifting circuit as follows: When the input terminal in is a low-voltage high-level VDDL, after passing through the inverter, the output terminal inp is a low-voltage high-level VDDL. NMOS transistors LVNM1 and LVNM3 are turned on, and the voltage at point C is accelerated to GND. At this time, NMOS transistor HVNM1_native is also turned on, discharging point A and causing the voltage at point A to start to drop. After passing through the gate input and drain output of PMOS transistor HVPM2, the first common-source amplification is completed. Then, after passing through the gate input and drain output of PMOS transistor HVPM5, the second common-source amplification is completed. The two common-source amplifications form a positive feedback loop. Finally, the voltage at point A is accelerated down to GND, and the PMOS transistor HVNM3 of the output buffer circuit is turned on, and the output terminal out is a high-voltage high-level VDDH. Simultaneously, the low-voltage high-level VDDL at the input terminal in becomes GND after passing through the inverter. NMOS transistors LVNM2 and LVNM4 are turned off, while PMOS transistor LVPM2 is turned on. The voltage at point D is pulled up to VDDL. Because NMOS transistor HVNM2_native cannot be completely turned off, it charges point B, causing its voltage to rise. This voltage then passes through the gate input and drain output of PMOS transistor HVPM1, completing the first common-source amplification. It then passes through the gate input and drain output of PMOS transistor HVPM6, completing the second common-source amplification. These two common-source amplifications form a positive feedback loop, ultimately accelerating the voltage at point B to the high-voltage high-level VDDH. The NMOS transistor HVNM4 in the output buffer circuit turns on, and the output terminal outb becomes GND. The opposite occurs when the input terminal in is at the low-voltage high-level VDDL. Therefore, regardless of whether the input terminal in is low or at a low-voltage high level VDDL, one of the NMOS transistors LVNM1 and LVNM2 in the two branches will be in the off state. The leakage current of the native NMOS cannot flow to GND, avoiding leakage caused by the native NMOS not being completely turned off by the gate voltage. This allows the level shifter (LS) circuit to still work normally. At the same time, the gating clamp protection circuit accelerates signal establishment under the low-voltage high level VDDL voltage domain, and the positive feedback loop accelerates signal establishment under the high-voltage high level VDDH voltage domain. The two are superimposed and jointly enhance the transient response of the level shifter (LS) circuit.

[0045] It should be noted that Figure 4 It shows Figure 3 A schematic diagram of the positive feedback loop one of the level shifting circuit in the embodiment. Figure 4In the diagram, positive feedback loop one is drawn with thick lines. The loop includes the gate of transistor HVPM2 to node A, then to the drain of transistor HVPM5, and after passing through transistor HVPM5, it runs from the gate of transistor HVPM5 to the drain of transistor HVPM2, forming loop one as shown by the thick lines. Correspondingly, Figure 5 It shows Figure 3 A schematic diagram of the second positive feedback loop of the level shifting circuit in the embodiment. Figure 5 In the diagram, positive feedback loop two is also drawn with thick lines. This loop includes the gate of transistor HVPM1 to node B, then to the drain of transistor HVPM6, and finally back to the drain of transistor HVPM1, forming loop two as shown in the thick lines. It should be understood that these two loops can be used to accelerate the setup speed in the VDDH voltage domain, while the gating clamping circuit below (i.e., transistors HVNM1_native1 and 2) is used to accelerate the setup speed in the VDDL voltage domain. The two parts are superimposed to enhance the transient response of the circuit.

[0046] Furthermore, in some embodiments, the level shifting circuit further includes an output inverting unit for inverting the voltages of the first node A and the second node B to obtain a secondary output signal.

[0047] Furthermore, in some embodiments, the aforementioned output inverting unit is provided with a first output inverting unit and a second output inverting unit; the aforementioned first output inverting unit is composed of a first inverting transistor HVPM3 and a second inverting transistor HVNM3; the aforementioned first inverting transistor HVPM3 is configured such that its gate is connected to the aforementioned first node A and the gate of the aforementioned second inverting transistor HVNM3, its source is connected to the aforementioned first power supply voltage VDDH, and its drain is connected to the first output terminal out and the drain of the aforementioned second inverting transistor HVNM3; the aforementioned second inverting transistor... The source of transistor HVNM3 is connected to ground (GND); the second output inverting unit is composed of a third inverting transistor HVPM4 and a fourth inverting transistor HVNM4; the gate of the third inverting transistor HVPM4 is connected to the gate of the second node B and the fourth inverting transistor HVNM4, its source is connected to the first power supply voltage VDDH, and its drain is connected to the second output terminal outb and the drain of the fourth inverting transistor HVNM4; the source of the fourth inverting transistor HVNM4 is connected to ground (GND).

[0048] Furthermore, in some embodiments, the level shifting circuit further includes an input conversion unit for generating two corresponding differential output signals from the primary input signal to serve as input signals for the first input terminal inp and the second input terminal inn.

[0049] It should also be understood that, Figure 3 In example implementations, the near-zero threshold voltage of an intrinsic NMOS transistor can be used to replace a normal NMOS transistor. A differential input signal is used to perform the biasing and gating control of the gating clamp protection circuit, eliminating the need for additional biasing circuitry and gating control logic. Furthermore, the constructed dual positive feedback loop enhances the overall transient response of the level shifting circuit. Further, in some embodiments, the gating clamp protection circuit based on an intrinsic NMOS transistor uses an intrinsic NMOS transistor with a near-zero threshold voltage instead of a conventional NMOS transistor, achieving self-biasing through an input differential signal. Even further, by utilizing the gating clamp protection circuit, the input signal serves as the gating control signal, eliminating the need for additional control logic and simplifying the overall circuit architecture. Even further, in some embodiments, by employing the gating clamp protection circuit, the gating clamp pulls the corresponding node to a low-voltage high level VDDL or GND, accelerating the establishment process of the electrically low VDDL voltage domain. Furthermore, in the cross-coupled shift circuit, the constructed dual positive feedback loop accelerates the establishment process of the high-level VDDH voltage domain, enhancing the transient response of the level shift circuit.

[0050] It should also be understood that, Figure 6-7 In the example embodiment, the changes in the signals (voltages) of each node are shown according to different input signals, wherein the signal changes from low level (GND) to high level (VDDL or VDDH) on the rising edge, and the signal changes from high level (VDDL or VDDH) to low level on the falling edge; for example, with Figure 6 Taking the left half as an example, when the input terminal in is a rising edge, the inn terminal is a falling edge, the signal at point D becomes a rising edge, the signal at point B also becomes a rising edge, and finally the outb terminal outputs a falling edge. Correspondingly, Figure 7 Signal changes and Figure 6 on the contrary.

[0051] Furthermore, in some embodiments, a control method for the level shift circuit as described above is also provided. This method includes: in response to a first input signal, when the first input terminal inp is set to a low-voltage high-level second power supply voltage VDDL; the first clamping node C is adjusted to a low level connected to ground GND; when the first input terminal inp is set to a low level connected to ground GND, the first clamping node C is adjusted to a low-voltage high-level second power supply voltage VDDL; and in response to a second input signal that is inverse of the first input signal, when the second input terminal inn is set to a low-voltage high-level second power supply voltage VDDL; the second clamping node D is adjusted to a low level connected to ground GND; when the second input terminal inn is set to a low level connected to ground GND, the second clamping node D is adjusted to a low-voltage high-level second power supply voltage VDDL.

[0052] It should also be understood that Figure 8 It shows in Figure 3 In the circuit of the example embodiment, after one level shift of the input signal, the circuit consumes only 1.9nA of static current.

[0053] Furthermore, Figure 9 It shows Figure 3 The simulation results of the level shifting circuit in the embodiment at the rising edge of the input signal are shown in the figure; correspondingly, Figure 10 It shows Figure 3 The simulation results of the level shifting circuit in the embodiment at the falling edge of the input signal are shown in the figure. It should also be understood that, according to... Figure 9 , 10 The simulation results, at the rising edge output, are as follows: Figure 9 As shown, Figure 3 The circuit in the example embodiment (labeled as this solution in the diagram for convenience) has an output delay of approximately 170 ps, ​​which is about 597 ps shorter than the output delay of the conventional solution. Correspondingly, at the falling edge output, i.e., as... Figure 10 As shown, Figure 3 The circuit in the example embodiment (labeled as this solution in the diagram for convenience) has an output delay of approximately 186 ps, which is about 579 ps shorter than the output delay of the conventional solution. Therefore, participating... Figure 9 , 10 The simulation results fully demonstrate Figure 3 The circuit in the example embodiment significantly reduces output delay and accelerates the transient response of level shift.

[0054] It should also be understood that in some other embodiments, Figure 3In the example embodiment, the first isolation device HVNM5 and / or the second isolation device HVNM6 are respectively replaced with two diodes, i.e., as shown below. Figure 9 The first diode DIO1 and the second diode DIO2 are shown; the two diodes serve to... Figure 3 The transistors HVNM5 and HVNM6 have the same function.

[0055] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0056] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A self-biased transient enhancement low static power level shifting circuit, characterized in that, The level shifting circuit is disposed between the first power supply voltage VDDH and ground GND, and the level shifting circuit includes: The first cross-coupled circuit is provided with a first transistor HVPM1 and a second transistor HVPM2. Its source is configured to be connected to the first power supply voltage VDDH at the same time. Its drain is configured to be connected to the corresponding first node A and the corresponding second node B via the first isolation device HVNM5 and the second isolation device HVNM6 respectively. Its gate is configured to be connected to the corresponding second node B and the first node A respectively. An input circuit is disposed between an output node and ground GND. The output node is configured to consist of a first node A and a second node B. The input circuit is provided with a first input terminal inp and a second input terminal inn, as well as pull-up / pull-down circuits. The pull-up / pull-down circuits are disposed between a second power supply voltage VDDL and ground GND and are respectively connected to the first input terminal inp and the second input terminal inn, and respectively connected to a first clamping node C and a second clamping node D. When the first input terminal inp is set to the second power supply voltage VDDL, the first clamping node C is adjusted to be connected to ground GND. When the first input terminal inp is set to be connected to ground GND, the first clamping node C is adjusted to be connected to the second power supply voltage VDDL. The first power supply voltage VDDH is higher than the second power supply voltage VDDL.

2. The level shifting circuit according to claim 1, characterized in that, The level shifting circuit is also provided with: A second cross-coupling circuit is disposed between the first power supply voltage VDDH and the output node.

3. The level shifting circuit according to claim 2, characterized in that, The second cross-coupling circuit is configured to include: The sources of the third transistor HVPM5 and the fourth transistor HVPM6 are configured to be connected to the first power supply voltage VDDH, the drains are configured to be connected to the corresponding first node A and the second node B, respectively, and the gates are configured to be connected to the drains of the second transistor HVPM2 and the first transistor HVPM1, respectively.

4. The level shifting circuit according to claim 1, characterized in that, The level shifting circuit also includes: The first isolation device HVNM5 and / or the second isolation device HVNM6 are configured as diodes and / or transistors to block loop interference.

5. The level shifting circuit according to claim 1, characterized in that, The input circuit is provided with a first input transistor LVNM1 and a second input transistor LVNM2, as well as a first protection transistor HVNM1_native and a second protection transistor HVNM2_native; The first input transistor LVNM1 is configured such that its gate is connected to the first input terminal inp, its drain is connected to the source of the first protection transistor HVNM1_native, and its source is connected to ground GND. The second input transistor LVNM2 is configured such that its gate is connected to the second input terminal inn, its drain is connected to the source of the second protection transistor HVNM2_native, and its source is connected to ground GND. The first protection transistor HVNM1_native is configured such that its gate is connected to the gate of the first input transistor LVNM1, and its drain is connected to the first node A; The second protection transistor HVNM2_native is configured such that its gate is connected to the gate of the second input transistor LVNM2, and its drain is connected to the second node B.

6. The level shifting circuit according to claim 5, characterized in that, The pull-up and pull-down circuits are configured to consist of a fifth transistor LVPM1, a sixth transistor LVPM2, a seventh transistor LVNM3, and an eighth transistor LVNM4. The fifth transistor LVPM1 is configured such that its gate is connected to the gate of the first input transistor LVNM1, its drain is connected to the first clamping node C, and its source is connected to the second power supply voltage VDDL. The sixth transistor LVPM2 is configured such that its gate is connected to the gate of the second input transistor LVNM2, its drain is connected to the second clamping node D, and its source is connected to the second power supply voltage VDDL. The seventh transistor LVNM3 is configured such that its gate is connected to the gate of the first input transistor LVNM1, its drain is connected to the first clamping node C, and its source is connected to ground GND. The eighth transistor LVNM4 is configured such that its gate is connected to the gate of the second input transistor LVNM2, its drain is connected to the second clamping node D, and its source is connected to ground GND.

7. The level shifting circuit according to claim 1, characterized in that, Also includes: The output inverting unit is used to invert the voltages of the first node A and the second node B to obtain the secondary output signal.

8. The level shifting circuit according to claim 7, characterized in that, The output inverting unit is provided with a first output inverting unit and a second output inverting unit; The first output inverting unit is composed of a first inverting transistor HVPM3 and a second inverting transistor HVNM3; the gate of the first inverting transistor HVPM3 is configured such that its gate is connected to the first node A and the gate of the second inverting transistor HVNM3, its source is connected to the first power supply voltage VDDH, and its drain is connected to the first output terminal out and the drain of the second inverting transistor HVNM3; the source of the second inverting transistor HVNM3 is configured to be connected to ground GND; The second output inverting unit is composed of a third inverting transistor HVPM4 and a fourth inverting transistor HVNM4; the third inverting transistor HVPM4 is configured such that its gate is connected to the second node B and the gate of the fourth inverting transistor HVNM4, its source is connected to the first power supply voltage VDDH, and its drain is connected to the second output terminal outb and the drain of the fourth inverting transistor HVNM4; the source of the fourth inverting transistor HVNM4 is configured to be connected to ground GND.

9. The level shifting circuit according to claim 1, characterized in that, Also includes: The input conversion unit is used to generate two corresponding differential output signals from the primary input signal as input signals for the first input terminal inp and the second input terminal inn.

10. A control method for a level shifting circuit as described in claim 6, characterized in that, include: In response to the first input signal, when the first input terminal inp is set to the low-voltage high level of the second power supply voltage VDDL; the first clamping node C is adjusted to a low level connected to ground GND; when the first input terminal inp is set to a low level connected to ground GND, the first clamping node C is adjusted to a low-voltage high level of the second power supply voltage VDDL; and In response to a second input signal that is inverse of the first input signal, when the second input terminal inn is set to the second power supply voltage VDDL at a low-voltage high level; the second clamping node D is adjusted to a low level connected to ground GND; when the second input terminal inn is set to a low level connected to ground GND, the second clamping node D is adjusted to the low-voltage high level of the second power supply voltage VDDL.

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