Flip conductor patch lamination for ultrafine wire substrate formation

Abstract

A laminated circuit board structure includes a printed circuit board substrate (16) having conductive routing traces (not shown) on at least a first routing face, a prepreg layer (18) formed over the first routing face, and a patch (10) having an area of less than 1,000 mm2. The patch includes conductive routing traces (14a-14d) formed on a routing face and is laminated to the printed circuit board substrate over the prepreg layer, the patch being oriented such that the routing face is in contact with the prepreg layer and pressed into the prepreg layer. A portion of the pre-preg layer fills gaps between the conductive routing traces.

Description

[0001] This invention patent application is a divisional application of the invention patent application with international application number PCT / EP2019 / 070889, international application date August 2, 2019, application number 201980064869.3 entering the Chinese national phase, and name “Flip conductor patch lamination for ultra-fine wire substrate formation”. Technical Field

[0002] The present invention relates to circuit assembly substrates. More particularly, the present invention relates to a laminate structure providing a layer of very fine conductive tracks for use on printed circuit board substrates. Background Art

[0003] As die shrink (but typically with increasing pin counts), package interconnect technologies need to be developed to interface with these dies as they evolve, but to accommodate the size reduction demands themselves. Wirebond die pads to a carrier substrate have been the preferred interface method, but recently chip-scale packages (CSP dies or "flip chips") are more often connected directly to the substrate, shifting the "fan-out" problem of the tracks to the printed circuit board (PCB) substrate.

[0004] Etched fine line tracks / gaps on PCBs have become a problem primarily because as the width of the conductive tracks becomes smaller, etching reaches its process limits and the adhesion of the copper tracks and connection pads to the substrate is greatly reduced.

[0005] Some PCB and die packaging companies have developed methods with very fine trace layers on the outside of their substrates. PCB and IC companies such as Kyocera, Toshiba, and Cicor have developed processes to add ultra-fine line capabilities to their IC and PCB laminate structures and products. These methods are generally expensive and do not provide the flexibility needed for designs that combine different elements of a design, such as die, SMT components, and PCBs, which are typically purchased separately and not necessarily from the same source.

[0006] As the die began to be integrated into the substrate itself, the process became less straightforward as substrate design, manufacturing, and assembly became complex (and often proprietary) activities requiring approaches different from simply providing a PCB and assembling components onto it. These activities often involved proprietary additive processes rather than subtractive etching processes, but were still limited in where and how these processes could be introduced into the design (usually at external layers).

[0007] One problem is the ability to include ultra-fine tracking layers in PCB laminate structures, where such tracking layers are not part of the normal PCB build. Another problem is the difficulty in providing small through-holes in laminated PCB structures. Yet another problem is minimizing the lateral area required to establish connections between lower and upper layers of a laminated PCB assembly. Yet another problem is that layers laminated to a PCB substrate experience nonlinear and uncontrolled stretching, making layer registration difficult. Summary of the Invention

[0008] According to one aspect of the present invention, a laminated circuit board structure includes a printed circuit board substrate having wiring traces on at least a first wiring surface thereof, a prepreg layer formed above the first wiring surface of the printed circuit board substrate, and a patch formed of a non-conductive substrate and having wiring traces formed on the wiring surface of the non-conductive substrate, the patch being laminated to the printed circuit board substrate above the prepreg layer, the patch being oriented with its wiring surface in contact with the prepreg layer and pressed into the prepreg layer, with portions of the prepreg layer filling gaps between the wiring traces on the patch.

[0009] According to one aspect of the present invention, the laminated circuit board structure also includes at least one opening formed through the non-conductive substrate of the patch and connected to at least one wiring trace on the wiring surface of the patch, and a conductive material arranged in each of the at least one opening and electrically contacting at least one wiring trace on the wiring surface of the patch.

[0010] According to one aspect of the present invention, the conductive material disposed in each of the at least one opening and in contact with the exposed at least one wiring trace is a solder bump.

[0011] According to one aspect of the present invention, the conductive material disposed in each of the at least one opening and in contact with the exposed at least one wiring trace is a conductive ink layer.

[0012] According to one aspect of the present invention, the laminated circuit board structure also includes solder bumps arranged on the wiring traces on the patch, solder bumps arranged on the wiring traces on the first wiring surface of the printed circuit board substrate in a position aligned with the solder bumps on the wiring traces arranged on the patch, and a z-axis tape layer arranged between the printed circuit board substrate and the patch, at least between the solder bumps arranged on the patch and the solder bumps arranged on the printed circuit board substrate.

[0013] According to one aspect of the present invention, the laminated circuit board structure further includes solder bumps disposed on routing traces on a patch, an integrated circuit die having at least one connection pad aligned with the solder bumps on the routing traces on the patch, and a z-axis tape layer disposed between the integrated circuit die and the patch, at least between the solder bumps disposed on the patch and the connection pads disposed on the solder-bumped integrated circuit die. The at least one connection pad may be a solder bump.

[0014] According to one aspect of the present invention, the laminated circuit board structure further includes a conductive trace on the second wiring side of the printed circuit board substrate, a first conductive via formed through the printed circuit board substrate to establish electrical contact between one of the wiring traces on the first wiring side of the printed circuit board substrate and one of the wiring traces on the second wiring side of the printed circuit board substrate, and a second conductive via formed through the prepreg layer and electrically contacting the wiring trace on the patch. The second conductive via is in electrical contact with the wiring trace on the first wiring side of the printed circuit board substrate. The laminated circuit board structure may also include an upper prepreg layer disposed above the solder bump integrated circuit die, and a top printed circuit board disposed above the upper prepreg layer.

[0015] According to one aspect of the present invention, the laminated circuit board structure also includes a plurality of preformed openings in the patch, each preformed opening being connected to at least one wiring trace on the wiring surface of the patch; a solder printing area formed in the preformed openings; and at least one surface mount component electrically connected to the solder printing area formed in the preformed openings.

[0016] According to one aspect of the present invention, the non-conductive substrate of the patch is formed from polyimide.

[0017] According to one aspect of the present invention, the patch has a diameter less than 1000 mm. 2 area.

[0018] According to one aspect of the present invention, a method for forming a patch of a laminated circuit board structure includes providing a non-conductive material layer having a conductive electroplating seed layer formed on its surface; applying a photoresist layer over the surface of the conductive electroplating seed layer; defining a wiring channel in the photoresist layer using photolithography and etching processes; electroplating a first layer of conductive material in the wiring channel; electroplating a second layer of conductive material over the first layer in the wiring channel; adhering a non-conductive layer over the photoresist layer and the plated conductive material in the wiring channel; and removing the non-conductive layer and the conductive electroplating seed layer.

[0019] According to one aspect of the present invention, providing a non-conductive material layer having a conductive plating seed layer formed on a surface thereof includes providing a polyester material layer having a conductive plating seed layer formed on a surface thereof.

[0020] According to one aspect of the invention, electroplating the first layer includes electroplating a gold layer in the wiring channel.

[0021] According to one aspect of the invention, electroplating the second layer includes electroplating a nickel layer over the first layer in the wiring channel.

[0022] According to one aspect of the invention, laminating a non-conductive layer over the photoresist layer and the plated layer of conductive material in the routing channels includes attaching a layer of one of polyester or polyimide over the photoresist layer and the plated conductive material in the routing channels using a transfer adhesive.

[0023] According to one aspect of the present invention, the patch comprises a patch having a diameter less than 1000 mm. 2 A non-conductive thin substrate having an area of ​​??. The non-conductive flexible substrate has a wiring surface. A conductive material layer is formed on the wiring surface of the non-conductive substrate, and regions of the conductive material layer are etched away to define a plurality of wiring traces on the wiring surface of the non-conductive flexible substrate, at least some of the wiring traces having a width no wider than 50 μm.

[0024] According to one aspect of the invention, regions of conductive material are etched away to form regions of conductive material disposed between and insulated from routing traces. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The invention will now be explained in more detail with reference to embodiments and the accompanying drawings, in which:

[0026] Figures 1A to 1I is a cross-sectional schematic diagram illustrating formation of a chip circuit component structure according to an exemplary embodiment of the present invention;

[0027] Figure 2 is a schematic diagram showing a top view of an exemplary patch according to the present invention;

[0028] Figures 3A to 3E are cross-sectional and top views of an exemplary embodiment of the present invention in which the patch can be folded to provide a bottom-to-top connection of the laminate structure; and

[0029] Figures 4A to 4G is a schematic cross-sectional view illustrating formation of a patch according to other exemplary embodiments of the present invention. DETAILED DESCRIPTION

[0030] Those skilled in the art will recognize that the following description is illustrative only and not limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0031] See first Figure 1A, a cross-sectional view shows a substrate "patch" 10 that can be used to provide an extremely fine conductive track layer for use on a printed circuit board substrate. According to one aspect of the invention, the patch can be formed from a flexible material. A non-conductive substrate 12 is shown that is formed from a layer of material that can withstand the temperatures encountered during the PCB lamination process, such as a polyimide layer, and a conductive layer 14 is formed over the wiring surface of the non-conductive substrate 12 by a known process such as deposition or etching. In one aspect of the invention, the conductive layer 14 is a copper layer. According to one aspect of the invention, the non-conductive substrate 12 is relatively "thin". According to the invention, the "thin" non-conductive substrate 12 has a thickness of less than about 100 μm and preferably between about 10 μm and about 50 μm. According to one aspect of the invention, portions of the conductive layer 14 are etched away using conventional photolithography and etching techniques to form a pattern of conductive wiring traces, including as Figure 1B According to one aspect of the present invention, at least some of the routing traces have a width no wider than 50 μm.

[0032] A non-conductive substrate 12 having defined conductive traces 14a, 14b, 14c, and 14d is oriented with the conductive traces 14a, 14b, 14c, and 14d facing downward and placed on the surface of a PCB substrate 16, over which a prepreg layer 18 has been formed. A prepreg layer (short for "prepreg") is a substrate fabric, such as fiberglass, that has been impregnated with a resin (an example of which is the NEMA grade designation FR4). The resin is pre-dried but not hardened, so when the resin is heated under pressure during the lamination process, it flows, adheres to, and covers the conductive traces 14a, 14b, 14c, and 14d, filling any gaps between the conductive traces 14a, 14b, 14c, and 14d.

[0033] As previously noted, etched fine line tracks / gaps on prior art PCBs become a problem primarily due to the greatly reduced adhesion of the copper tracks / pads to the substrate as the line width of the tracks becomes smaller and etching reaches its process limits. A typical conductive trace used in the present invention may be about 24 μm wide and about 12 μm high. It is contemplated that the present invention may be implemented using conductive traces having a width as small as about 1 μm and a thickness of about 1 μm. During the lamination process, a prepreg layer 18 is formed around the conductive traces 14a, 14b, 14c, and 14d and provides dimensional stability to these conductive traces, filling any gaps between them.

[0034] Figure 1Cis a schematic cross-sectional view of a laminate structure showing the structure obtained after patch 10 including a non-conductive substrate 12 having conductive traces 14a, 14b, 14c and 14d has been laminated to a PCB substrate 16 and prepreg layer 18 by pressing and heating to laminate prepreg layer 18 as is known in the art. Figure 1C Conductive traces 14a, 14b, 14c and 14d are shown securely embedded in a prepreg layer 18 of a hybrid laminate substrate comprising a PCB substrate 16 and patch 10 comprising a non-conductive substrate 12 and conductive traces 14a, 14b, 14c and 14d.

[0035] Now see Figure 1D , which shows a schematic cross-sectional view of the laminate structure after a small hole 18 (e.g., down to about 20 μm or less in diameter) has been formed in the non-conductive substrate 12. This can be done using, for example, laser ablation. Larger holes (e.g., hole 20) for surface mount technology (SMT) components (e.g., 0201 size and above), which would be more time-consuming to form by laser ablation, can be formed in the non-conductive substrate 12, for example, as laser-cut openings through which Sn / Cu paste can be printed and subsequently sintered according to conventional surface mount technology (SMT) solder attach assembly processes. Figure 1D The laminate structure is shown after holes 18 and 20 have been formed in the non-conductive substrate 12 to expose the copper conductive traces 14a, 14b, 14c, and 14d.

[0036] Now see Figure 1E , which shows a schematic cross-sectional view of the laminate structure after forming solder bumps 22 in small holes 18 and larger solder bumps 24 in larger holes 20. Solder bumps 22 are used to connect to a chip scale package (CSP) die pad and are also used for small SMT components, such as 01005 (approximately 10 mils by 5 mils), 0201 (approximately 20 mils by 10 mils), or 008004 (approximately 8 mils by 4 mils) size resistors or capacitors. Figure 1F 1 is a schematic cross-sectional view of a laminate structure showing a bond pad integrated circuit die 26 bonded to a previously formed solder bump 22 in a hole 18 and an SMT component 30, one lead 32 of which is shown bonded to a larger solder bump 24 previously formed in a hole 20. According to one aspect of the present invention, the hole 18 can be filled with a conductive ink. Placing and connecting the bond pad integrated circuit die 26 and the SMT component 30 on the laminate structure using fiducials using existing pick and place equipment is known in the art.

[0037] Prior art lamination processes for producing PCBs use sheets or panels of FR4 or similar material that are typically 24" x 18" (approximately 600mm x 450mm). Registration of pre-etched layers for lamination onto existing pre-etched panels is extremely difficult at this scale, and the registration problem is exacerbated by the fact that the materials involved will stretch differently, especially when they are not the same type. Even if two pre-etched layers can be aligned within the target tolerance, any differences in the coefficients of thermal expansion of these materials will cause a host of problems across the 600 x 450mm panel. Mechanical registration of the different layers using drilled tool holes at these opposing scales is simply not an option. This has led to PCB manufacturing practices where a PCB manufacturing machine will build onto an existing core, etching the new layer after registering it to the existing underlying pattern using, among other things, computerized adjustments for stretching.

[0038] The present invention contemplates the use of relatively small patches 10 compared to the prior art. The patch circuit area is relatively small and can be placed in a step-and-repeat pattern across the FR4 panel. A non-limiting example of such a patch according to the present invention is a 9mm x 9mm patch "component" formed on a 50μm thick flexible polyimide substrate using a 50μm wide track (having a thickness of approximately 9μm) formed from 1 / 4 ounce copper. It is currently contemplated that a 15μm track having a thickness of approximately 7.5μm is possible using the etching concepts of the present invention. Such small patch components can be machine placed very accurately on a localized portion of the PCB using reference points using existing pick and place equipment as is known in the art. Generally speaking, the area of ​​a patch according to the present invention is no greater than approximately 500mm 2 About 1,000mm 2 When the area of ​​the patch increases above this value, registration and stretching problems start to become unsustainable, leading to assembly problems.

[0039] Interlayer vias are also important in printed circuit board assemblies, and efforts have been made to make them as small as possible given the thickness of the layers forming them. The technology of the present invention includes another way to form interlayer vias using via filling materials (Sn / Cu paste sintered in the laminate). Since the patches can be accurately placed using SMT equipment, the vias on different layers and the pads for printing solder bumps can be accurately matched. Figure 1G and Figure 1H This aspect of the invention is shown.

[0040] Figure 1G is a cross-sectional view of an exemplary laminated PCB assembly according to another aspect of the present invention. Figure 1GThe exemplary laminated PCB assembly depicted in FIG shows solder pads 28 of integrated circuit die 26 connected to conductive traces 36 on the second wiring side of PCB substrate 16 via solder bumps 22, conductive traces 14d of patch 10, through-holes 40 formed in prepreg layer 18, conductive traces 38 on the first wiring side of PCB substrate 16, and through-holes 34 formed through PCB substrate 16. As one of ordinary skill in the art will appreciate, Figure 1G The specific circuit connections shown are entirely arbitrary and are shown simply to illustrate how multi-layer vias may be incorporated into a laminate printed circuit board assembly according to the present invention.

[0041] Figure 1H is a cross-sectional view of an exemplary laminated PCB assembly according to another aspect of the present invention.

[0042] The PCB substrate 16 is shown with conductive traces 36 and PCB traces 36 on the second wiring side of the PCB substrate 16.

[0043] Through holes 34 are formed between conductive traces 38 on the first wiring side of the PCB substrate 16. A prepreg layer 18 is formed above the first wiring side of the PCB substrate 16, and as previously described, the patch 10 including the non-conductive substrate 12 having the conductive wiring traces on its surface is laminated face down into the prepreg layer 18. Via openings are laser cut in the prepreg layer 18 through the non-conductive substrate 12 of the patch 10. The prepreg layer 18 acts as an insulating layer, and through holes to the conductive traces on the patch 10 and / or on the underlying PCB substrate 16 are formed by printing Sn / Cu paste into the prepreg openings that were previously laser processed. Through holes 42 connected to the wiring traces 44 on the patch 10 are sintered during the lamination process. Through holes 42 are formed by through-hole filling before the patch 10 is laminated to the prepreg layer 18. Through holes 42 establish an electrical connection with the wiring traces 44 on the patch 10. A second sintered through-hole 46 is shown which establishes an electrical connection between the wiring trace 38 on the first wiring side of the PCB 16 and the wiring trace 48 on the non-conductive substrate 12 of the patch 10. One skilled in the art will observe that the specific connections established by through-holes 42 and 46 are merely illustrative and merely show connections that may be established with the patch 10 or with the underlying PCB substrate 16, and that these connections may be established with Sn / Cu alloy through-holes such as Figure 1G The through hole 40 shown is formed in the same process.

[0044] Figure 1H The exemplary circuit depicted in FIG shows that the leads 32 of the SMT component 30 are connected to the through holes 42 and 46 using the solder paste area 50 during the assembly process. It will be understood by those skilled in the art that Figure 1H The specific circuit connections shown are entirely arbitrary and are shown simply to illustrate how multi-layer vias may be incorporated into a laminate printed circuit board assembly according to the present invention.

[0045] Now see Figure 1I , a cross-sectional view shows an exemplary laminated printed circuit board assembly according to another aspect of the present invention. PCB substrate 16 is shown having through-holes 34 formed between conductive traces 36 on the bottom surface of PCB substrate 16 and conductive traces 38 on the first wiring side of PCB substrate 16.

[0046] exist Figure 1I In the exemplary embodiment shown, solder bumps 52 have been formed on conductive trace 38 on the first wiring side of PCB substrate 16. Solder bumps 54 have also been formed on conductive trace 14d of patch 10. A piece of z-axis tape 56 is placed in alignment with solder bumps 52 and 54 in a gap formed in prepreg layer 18 before patch 10 is placed over prepreg layer 18. Z-axis tape 56 will form an electrical connection between conductive trace 14d and conductive trace 38 through solder bumps 52 and 54 during the lamination process.

[0047] After the lamination process, small holes are formed in the non-conductive substrate 12 and filled with solder bumps 22, as previously described. An integrated circuit die 58 having solder bump connections (one of the solder bump connections is identified by reference numeral 60) can be bonded to the solder bumps 22 using a z-axis tape layer 62 in the gaps formed in the prepreg layers 64 and 66. A second PCB substrate 68 can then be laminated to the underlying structure. For illustrative purposes, the second PCB substrate 68 is shown as including through-holes 70 formed between conductive traces 72 on the bottom surface of the PCB substrate 68 and conductive traces 74 formed on the first wiring surface of the PCB substrate 68. One or more additional prepreg layers 76 are placed over the die 58 and prepreg layers 64 and 66 to maintain electrical and mechanical integrity with the die 58 laminated thereto by being embedded therein. Figure 1H As will be appreciated by those skilled in the art, Figure 1I The particular circuit connections shown are entirely arbitrary and are shown simply to illustrate how multiple unique and continuous stack-ups of laminate circuit substrate structures can be formed to meet the needs of a wide variety of designs, including embedding very fine pitch CSP dies into multi-layer laminate printed circuit board assemblies according to the present invention.

[0048] Now see Figure 2 , a top view of an exemplary patch 10 illustrates another aspect of the present invention. The thin, flexible material, non-conductive substrate 12 on which the patch is formed will be very easily bent, so copper areas 90 are included in all gaps between the conductive traces to facilitate pick and place of the patch 10, thereby forming the desired flat surface after lamination.

[0049] The patch 10 includes a plurality of connection pads 82. The connection pads 82 are electrically connected to I / O pins (one of which is shown as reference numeral 84) of an integrated circuit die 86 by copper traces (one of which is shown as reference numeral 88) formed on the thin flexible material non-conductive substrate 12. A solid copper area 90, which is not etched, is shown as remaining in the area of ​​the thin flexible material non-conductive substrate 12 between the I / O pads 82, the area occupied by the integrated circuit die 86, and the conductive traces 88 to provide dimensional stability to the patch 10.

[0050] Figures 3A to 3D are top and cross-sectional views of an exemplary embodiment of the present invention in which a patch can be folded to provide a bottom-to-top connection of a laminate structure.

[0051] Now see Figure 3A , a cross-sectional schematic diagram shows a folded patch 90 comprising a flexible non-conductive substrate 92 having a conductive trace 94 formed on one of its surfaces. An integrated circuit die 96 has been bonded by one of its I / O pads 98 to a bond pad 100 in communication with the conductive trace 94. Figure 3A The illustrative example of FIG shows a patch 90 laminated to a PCB substrate 102 using a prepreg layer 104. As noted in the previously disclosed embodiments, conductive traces 106 on the bottom surface of the PCB substrate 102 are electrically connected to conductive traces 108 on the first routing surface of the PCB substrate 102 through vias 110. As previously disclosed, routing traces 94 on the patch 90 are shown as being electrically connected to the conductive traces 108 on the first routing side of the PCB substrate 102 using a piece of z-axis tape, indicated at 112, placed in a void in the prepreg layer 104.

[0052] exist Figure 3AIn the illustrated embodiment, the patch 90 has been folded over the solder pad integrated circuit die 96. An upper PCB substrate 114 is laminated to the top surface of the folded patch 90 via a prepreg layer 116 and includes conductive traces 118 on its bottom surface (second wiring side) that are electrically connected to conductive traces 120 on its top surface (first wiring side) through preformed vias 122 in the PCB substrate 114. Vias 124 from conductor 118 to conductive traces 94 are formed by filling holes in the laser-formed prepreg layer 116 with Sn / Cu paste, which is sintered during lamination to form a Sn / Cu alloy, as previously discussed. An SMT component 126 is shown bonded to the upper PCB substrate 114 by its solder bump I / O connections (one of which is shown at 128). The folded patch 90 is shown placed in a void generally formed by apertures in one or more other prepreg layers shown in phantom at 130 to the right of the folded patch 90 so as to maintain a sufficiently flat surface upon which to laminate the upper PCB substrate 114 .

[0053] Figure 3A An advantageous feature of the folded patch is that connections to the SMT component 126 can be established by the I / O pads of the solder pad integrated circuit die 96 without requiring vias to be laterally disposed outside the perimeter of the solder pad die 96, thereby increasing the footprint of that portion of the circuit. This feature of the invention is illustrated by the connections through the conductive traces 94 of the folded patch. One of ordinary skill in the art will appreciate that Figure 3A is a cross section of the structure and the additional conductive traces of the folded patch can be used to route connections from the solder pads integrated circuit die 96 to other I / O pads on the top PCB substrate 114 and / or from the Figure 3A The lower PCB substrate 102 routing connections are at locations outside the plane of the cross-section shown.

[0054] Now see Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E , showing the method for forming a Figure 3A Portions 90a and 90b are a method of folding the patch. Figure 3B 、 Figure 3C and Figure 3D It shows Figure 3A A cross-sectional view of the formation of the folded patch 90. Figure 3B 、 Figure 3C and Figure 3D The cross section depicted in Figure 3E The line AA is intercepted, Figure 3E is a top view illustrating the simultaneous formation of multiple folded patches according to the present invention.

[0055] Now see Figure 3B , a cross-sectional view shows a substrate ready to receive the patch (including portions 90a and 90b) to be folded. A fixture 132 includes positioning pins, one of which is shown at 134. The substrate on which the folded patch 90 is to be formed is shown at 136. The substrate 136 includes a cavity 138 in which the patch (including portions 90a and 90b) will be placed before being folded. At this point, the patch (including portions 90a and 90b) is substantially flat.

[0056] A metal slide 140 is positioned above the substrate 136 and includes slots 142 that align with the locating pins 134. An aperture 144 ( Figure 3E ) is positioned above cavity 138.

[0057] Now see Figure 3C , the patch (including portions 90a and 90b) is placed in cavity 138 and secured by a thin layer of adhesive z-axis tape ( Figure 3C The portion of patch 90 on which integrated circuit die 96 is placed is shown at 90a and lies flat within cavity 138, and the edge of cavity 138 and / or the edge of aperture 144 in sliding metal plate 140 forces the portion of patch 90 to the right of cavity 138, shown at 90b, upward at an angle. Substrate 136 includes groove 148 ( Figure 3B As shown, a drop of adhesive is placed ( Figure 3C and Figure 3D 150 in the figure).

[0058] The metal slide 140 is then moved laterally towards the portion 90b of the patch so that Figure 3D The patch is folded as shown in FIG, which depicts the position of the metal slide after it has been engaged by the ends of the slots 142 to prevent lateral movement. The bead of adhesive 150, when cured, holds the distal edge of portion 90b of the patch in its folded position, thereby allowing further processing of the resulting laminate.

[0059] It should be noted that more than one folded patch 90a and 90b may be formed simultaneously. Figure 3E The top view of FIG. 1 shows a pair of exemplary folded patches 90 , but one of ordinary skill in the art will appreciate that any number of such folded patches 90 may be formed simultaneously, depending on the configuration of the laminate circuit board assembly being processed.

[0060] Now see Figures 4A to 4F , a cross-sectional schematic diagram illustrating the formation of a patch according to another exemplary embodiment of the present invention. Figures 4A to 4E An advantage of the embodiment depicted in is that an ultra-fine tracking layer of approximately 5 μm width can be formed using a continuous process.

[0061] Now see Figure 4A , a carrier layer 160 (such as a polyester sheet) having a conductive plating seed layer 162 (such as graphite) deposited on one of its surfaces is preferably formed into a roll (indicated at the rolled end 164). The use of a roll is not necessary to practice the present invention, but it allows a somewhat continuous roll-to-roll process to be used in accordance with one aspect of the present invention.

[0062] like Figure 4B As shown, the carrier layer 160 having the conductive plating seed layer 162 is cut into panels. A photoresist layer 166 is then formed on the surface of the metal layer on each panel and cured.

[0063] like Figure 4C As shown, after forming a photoresist layer 166 on the surface of the metal layer and curing the photoresist layer, the photoresist layer is masked, exposed (indicated by arrows 168), and etched to remove the photoresist in the desired areas as is well known in the art of photolithography, thereby exposing portions of the underlying conductive plating seed layer 162 in the wiring channels 170. The geometry of the wiring channels 170 defines the conductive traces that will be formed on the finished patch.

[0064] Now see Figure 4D , metal is electroplated into the wiring channel 170 using the graphite conductive seed layer 162 as a cathode. Figure 4D Two metal layers are shown, namely a first metal layer 172 and a second metal layer 174. In one particular embodiment, the first metal layer 172 may be an Au layer (which may have a thickness of, for example, approximately 0.03 μm) and the second metal layer 174 may be a Ni layer (which may have a thickness of, for example, approximately 5 μm). One of ordinary skill in the art will appreciate that in other embodiments, different metals may be employed or a single metal layer (e.g., Cu) may be employed. Conductive traces having a minimum dimension of approximately 1 μm in width and 1 μm in thickness are also contemplated in this additive electroplating process.

[0065] Now see Figure 4E , die attach substrate 176 (which, as previously noted, may be a layer of material such as polyester or polyimide with an adhesive backing) is adhered to the top of photoresist layer 166 and the top surface of exposed second metal layer 174. Die attach substrate 176 may include an adhesive backing layer 178 as a transfer adhesive and may conveniently, but not necessarily, be in the form of a roll as indicated by the curled edge at reference numeral 180.

[0066] Now see Figure 4F, the carrier layer 160 and its conductive plating seed layer 162 have been stripped away by peeling it from the assembly layer to expose the top surface of the second metal layer 174 and the panel is cut into final size patches 182.

[0067] Now see Figure 4G , shows another embodiment after the carrier layer 160 and its conductive plating seed layer 162 have been stripped off by peeling them from the assembly layer and the patch is cut into final size panels. In this embodiment, only a single plated metal layer 184 (formed of, for example, Cu) is used. The manufacturing process is similar to Figures 4A to 4F The embodiment shown is the same except that Figures 4D to 4F The two plated metal layers 172 and 174 shown have been replaced with a single plated metal layer 184 .

[0068] Various embodiments of the present invention provide small, thin, and flexible patch components with ultra-fine conductive tracks that can be very accurately machine-placed locally using fiducials. When flipped over for lamination to a PCB substrate, the conductive tracks are embedded in the prepreg layer and a central CSP pad opening can be laser-ablated through the non-conductive substrate layer 12. The thin, flexible material non-conductive substrate 12 bends easily, so copper areas are included to fill the gaps between the conductive tracks to enable pick and place of the patch, thereby creating the desired flat surface after lamination.

[0069] Laser ablation of openings is cost-effective for small CSP and 01005 component pads. Components of approximately 0201 size and above can utilize a different strategy, simultaneously "print-filling" the through-holes with a through-hole filling material that "sinters" into a Sn / Cu alloy during lamination. For these larger component pads, patches according to embodiments of the present invention can have laser-cut openings (faster and cheaper than ablation), with Sn / Cu paste printed underneath these openings, which sinters during lamination to form component pads for ordinary SMT solder attachment. Various embodiments of the present invention enable the formation of small interlayer vias. Since patches according to the present invention can be accurately placed using SMT equipment, small pads (for through-holes) for different layers and solder bumps can be accurately paired.

[0070] Ultra-fine, precision tracks are laminated down into the prepreg layer of the underlying structure comprising the PCB substrate, where they are fully secured, eliminating the low peel strength of the fine conductive tracks. The non-conductive substrate 12 becomes the "solder mask" layer for the component assembly. This eliminates the entire set of processes that would otherwise require adding an etch resist layer, as the conductive tracks come with the included etch resist.

[0071] Due to the small size of the patches, the patches can be machine-placed with extreme accuracy to register to the PCB substrate, eliminating alignment and stretching issues across the entire assembly panel. The use of small patches also minimizes any thermal mismatch or material delamination issues within the laminate substrate.

[0072] The present invention is particularly applicable to printed through-hole connections in PCB substrates, as these connections are also "sintered" under temperature and pressure during the lamination process.

[0073] While the embodiments and applications of the present invention have been shown and described, it will be apparent to those skilled in the art that many more modifications than those described above may be made without departing from the inventive concepts herein. Therefore, the present invention is not to be restricted except in the spirit of the appended claims.

Claims

1. A laminated circuit board structure comprising: a first printed circuit board substrate (102) and a second printed circuit board substrate (114) comprising conductive traces on at least a first wiring side thereof; a first prepreg layer formed over the first wiring surface of the first printed circuit board substrate and a second prepreg layer formed over the first wiring surface of the second printed circuit board substrate; as well as A folding patch (90), comprising: A flexible non-conductive substrate (92), the flexible non-conductive substrate having a wiring surface; as well as forming conductive traces (94) on the wiring side of the flexible non-conductive substrate, wherein the folded patch (90) is folded so that the wiring surfaces form the top and bottom surfaces of the folded patch, the bottom surface of the folded patch being laminated to the first prepreg layer of the first printed circuit board substrate, wherein the bottom surface of the folded patch is in contact with and pressed into the first prepreg layer, wherein portions of the first prepreg layer fill gaps between conductive traces on the bottom surface of the folded patch, The top surface of the folded patch is laminated to the second prepreg layer of the second printed circuit board substrate, wherein the top surface of the folded patch contacts and is pressed into the second prepreg layer, and portions of the second prepreg layer fill gaps between the conductive traces on the top surface of the folded patch.

2. The laminated circuit board structure according to claim 1, wherein: The conductive traces on the bottom surface of the folded patch are electrically connected to the conductive traces on the first routing side of the first printed circuit board substrate using a piece of z-axis tape placed in the voids in the first prepreg layer.

3. The laminated circuit board structure according to claim 1, wherein: The conductive traces on the top surface of the folded patch are electrically connected to the conductive traces on the first wiring side of the second printed circuit board substrate through the Sn / Cu alloy formed in the holes in the second prepreg layer.

4. The laminated circuit board structure according to claim 3, wherein: The holes in the second prepreg layer are formed by laser, and the Sn / Cu alloy is formed by filling the holes with Sn / Cu paste.

5. The laminated circuit board structure according to claim 1, wherein: Also included is a bond pad integrated circuit die (96), wherein the folded patch is folded over the bond pad integrated circuit die (96), the bond pad integrated circuit die (96) being bonded by one of its I / O pads (98) to a bond pad (100) in communication with the conductive trace (94).

6. The laminated circuit board structure according to claim 1, wherein: The folded patch is placed in the void formed by the apertures in one or more other prepreg layers (130).

7. A method for forming a folded patch, comprising: placing a substrate (136) on a fixture (132); positioning a metal slide (140) over the substrate (136), wherein an aperture (144) in the metal slide is positioned over the cavity of the substrate (136), and wherein the aperture slot (142) in the metal slide aligns with a locating pin (134) on the fixture; placing the patch in the cavity (138), wherein a first portion of the patch with the integrated circuit die (96) placed thereon lies flat in the cavity and an edge of the cavity and / or an edge of the aperture in the metal slide forces a second portion of the patch extending beyond the cavity upward at an angle; The patch is folded by moving the metal slide laterally toward the second portion of the patch until the metal slide has been engaged by the ends of the slots to prevent its lateral movement, thereby obtaining the folded patch.

8. The method according to claim 7, characterized in that The substrate includes a recess (148) in which an adhesive is positioned, and wherein the distal edge of the patch second portion contacts the adhesive such that upon curing the distal edge of the patch second portion remains in its folded position.

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