A silicon carbide trench mosfet device with three-sided trench structure and a method of fabrication

Abstract

This invention provides a silicon carbide trench MOSFET device with a three-sided trench structure and its fabrication method, comprising: growing silicon carbide epitaxy on a silicon carbide substrate and implanting to form a P-well region; forming a first barrier layer on the P-well region and implanting to form a P+ region; removing the first barrier layer to form a second barrier layer and implanting to form an N+ region; removing the second barrier layer and simultaneously performing rapid thermal annealing on the P-well, P+, and N+ regions; forming a third barrier layer and etching to form a gate trench region; removing the third barrier layer and performing dry oxygen thermal oxidation to form a gate oxide layer; forming polysilicon using chemical vapor deposition; doping the polysilicon and then etching to form a gate; depositing metal to form the drain and source, and performing rapid thermal annealing on the drain and source to form ohmic contacts. By setting the three-sided trench structure, the channel area is increased, and the on-resistance is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and more specifically to a silicon carbide trench MOSFET device with a three-sided trench structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) is a typical wide-bandgap semiconductor material. Due to its advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity, it has become an ideal choice for high-voltage, high-temperature, and high-frequency high-power power electronic devices. Compared to traditional silicon-based power devices, SiC power devices have lower conduction losses and faster switching speeds, making them widely applicable in fields such as new energy vehicles, photovoltaic inverters, 5G communication base stations, and rail transportation.

[0003] Currently, power devices based on 4H-SiC have been commercially applied, but they still suffer from low channel electron mobility; the channel mobility of 4H-SiC MOSFETs is typically 20~40 cm⁻¹. 2 / V·s, which means that its excellent material properties cannot be fully utilized.

[0004] In the commercialization of silicon carbide power MOSFETs, the horizontal-channel DTMOS (Double-Trench MOSFET) has secured a place in low-to-medium voltage (typically several hundred volts to 1.2 kV) applications due to its unique structural design and performance advantages. However, its horizontal channel structure limits the lateral silicon carbide extension to chip area, resulting in commercially available products with voltage ratings mostly below 1.2 kV, making it difficult to cover high-voltage industrial applications. Although the horizontal DTMOS (Double-Trench MOSFET) belongs to the trench structure category, it is essentially a planar device with lateral channel current, resulting in relatively high on-resistance.

[0005] The core value of silicon carbide trench gate MOSFETs lies in maximizing the high critical electric field and high electron mobility of silicon carbide material through the design of embedding the gate in a trench. Unlike planar gate MOSFETs where the channels are only distributed on the chip surface, trench gates form channels through the sides of vertical trenches. The channel current is vertical, significantly increasing the total channel length per unit area, thereby directly reducing channel resistance. Although it already significantly reduces channel resistance compared to horizontal channel MOSFETs, its vertical channels are only arranged on both sides of the gate. Further optimization of the gate trench structure, and thus the channel structure, can further reduce on-resistance.

[0006] Therefore, how to optimize the channel structure is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of this, the present invention provides a silicon carbide trench MOSFET device with a three-sided trench structure and a method for fabricating it. By using the three-sided trench structure to fabricate the silicon carbide trench gate MOSFET, an additional conductive channel is formed, which increases the channel area and reduces the on-resistance of the silicon carbide trench gate MOSFET device.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] A method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure, comprising:

[0010] Step S1: Epitaxial growth of silicon carbide on a silicon carbide substrate, and multiple aluminum ion implantations or co-implantation of aluminum ions and boron ions to form a P-well region.

[0011] Step S2: A first barrier layer is formed on the P-well region, and multiple aluminum ion implantations or aluminum ion and boron ion co-implantations are performed to form the P+ region.

[0012] Step S3: Remove the first barrier layer to form the second barrier layer, and perform multiple nitrogen ion implantations to form the N+ region;

[0013] Step S4: Remove the second barrier layer and simultaneously perform rapid thermal annealing on the P-well region, P+ region, and N+ region;

[0014] Step S5: Form a third barrier layer and perform etching to form a gate trench region;

[0015] Step S6: Remove the third barrier layer, perform RCA cleaning, and then perform dry oxygen thermal oxidation in the furnace tube to remove the oxide layer above the P+ and N+ regions, forming a gate oxide layer in the gate trench region.

[0016] Step S7: The gate oxide layer is deposited in multiple steps using chemical vapor deposition to form polysilicon; after doping the polysilicon, etching is performed to form the gate.

[0017] In step S8, metal is deposited on the back side of the silicon carbide substrate to form a drain, and metal is deposited on the P+ region and part of the N+ region to form a source. The drain and source are then subjected to rapid thermal annealing to form ohmic contacts, thus fabricating a silicon carbide trench MOSFET device with a three-sided trench structure.

[0018] Furthermore, in step S1, the doping concentration of the silicon carbide substrate is 1e. 18 cm -3 ~1e 20 cm -3 The thickness ranges from 200µm to 1000µm; the doping concentration of the silicon carbide epitaxial layer is 1e. 15 cm -3~5e 16 cm -3 The thickness ranges from 6µm to 40µm; the P-well region is formed at 500℃-800℃, with a net acceptor concentration of 5e. 16 cm -3 ~5e 17 cm -3 .

[0019] Furthermore, in step S2, the P+ region is formed at 500℃–700℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The thickness is 0.2µm~0.5µm.

[0020] Furthermore, in step S3, the N+ region is formed at 400℃–600℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The injection angle is 7°–10°, and the thickness is 0.2µm~0.5µm.

[0021] Furthermore, in step S4, the rapid thermal annealing temperature is between 1600℃ and 1800℃, using an inert atmosphere or protective atmosphere, and the time is between 1 and 10 minutes.

[0022] Furthermore, in step S5, the thickness of the gate trench region is 0.5µm~1.2µm, which is larger than the thickness of the P-well region (103) by 0.05µm~0.5µm.

[0023] Furthermore, in step S6, the temperature of dry oxygen thermal oxidation is between 1000℃ and 1300℃; the sidewall thickness of the gate oxide layer is 0.01µm to 0.5µm, and the bottom thickness is 0.02µm to 0.7µm.

[0024] Furthermore, in step S7, the chemical vapor deposition temperature is between 550°C and 700°C; the polysilicon doping concentration is 1e. 18 ~1e 20 cm -3 .

[0025] Furthermore, in step S8, part of the N+ region is the center of the N+ region; the temperature of rapid thermal annealing is between 900℃ and 1100℃, and the time is between 30 seconds and 2 minutes.

[0026] The prepared silicon carbide trench MOSFET device with a three-sided trench structure includes a silicon carbide substrate, a silicon carbide epitaxial layer, a P-well region, a P+ region, an N+ region, a gate oxide layer, a gate, a drain, and a source. The drain is located on the back side of the silicon carbide substrate, the silicon carbide epitaxial layer is located on the front side of the silicon carbide substrate, the P-well region is formed on the silicon carbide epitaxial layer, the P+ region and the N+ region are formed on the P-well region, the gate oxide layer is located at the center of the P-well region and the N+ region, the gate (108) is located on the gate oxide layer, and the source is located on the P+ region of the entire region and the N+ region of a part of the region.

[0027] As can be seen from the above technical solution, compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] 1. The silicon carbide trench MOSFET device prepared by the method of the present invention forms multiple additional conductive channels by using a three-sided trench structure to prepare the silicon carbide trench MOSFET, thereby increasing the channel area and reducing the on-resistance of the silicon carbide trench MOSFET device.

[0029] 2. The silicon carbide trench MOSFET device prepared by the method of the present invention can adjust the channel resistance by controlling the width of the three-sided trench structure. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a schematic flowchart of the method of the present invention;

[0032] Figures 2a-2i for Figure 1 A schematic diagram of the fabrication steps of a silicon carbide trench MOSFET device with a three-sided trench structure is shown.

[0033] In the figure, 101 is the silicon carbide substrate; 102 is the silicon carbide epitaxial layer; 103 is the P-well region; 104 is the P+ region; 105 is the N+ region; 106 is the gate trench region; 107 is the gate oxide layer; 108 is the gate; 109 is the drain; 110 is the source; 21 is the first barrier layer; 22 is the second barrier layer; and 23 is the third barrier layer. Detailed Implementation

[0034] To further understand the content, features, and effects of this invention, the following embodiments are provided and described in detail with reference to the accompanying drawings. It should be noted that these embodiments are descriptive, not limiting, and should not be construed as limiting the scope of protection of this invention.

[0035] like Figure 1 As shown, a silicon carbide trench MOSFET device with a three-sided trench structure and its fabrication method are disclosed, including the following steps:

[0036] Step S1: The silicon carbide substrate 101 is set to N-type, and is either 4H-SiC or 6H-SiC, with a doping concentration of 1e. 18 cm -3 ~1e 20 cm -3 The thickness ranges from 200µm to 1000µm. Epitaxial growth with a doping concentration of 1e is performed on a silicon carbide substrate 101. 15 cm -3 ~5e 16 cm -3 A silicon carbide epitaxial layer 102, with a thickness of 6µm to 40µm, is designated as the drift region. The silicon carbide epitaxial layer 102 is configured as N-type. Multiple aluminum ion implantations or co-implantations of aluminum and boron ions are performed on the silicon carbide epitaxial layer 102 to form a P-well region 103; [e.g., ...] Figure 2a As shown.

[0037] Step S2: A first barrier layer 21 is formed on the P-well region 103. Multiple aluminum ion implantations or co-implantation of aluminum and boron ions are performed on the unbarriered areas of the P-well region 103 to form a P+ region 104. The P+ region 104 is formed by multiple aluminum ion implantations or co-implantation of aluminum and boron ions at 500℃–700℃, with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The thickness is 0.2µm~0.5µm, such as Figure 2b As shown.

[0038] The P+ region 104 of the silicon carbide MOSFET device is the core of the body contact region, used to achieve a low-resistance connection between the P-well region 103 and the source 110, prevent parasitic BJT conduction, and improve device robustness.

[0039] Step S3: Remove the first barrier layer 21 to form the second barrier layer 22, and perform multiple nitrogen ion implantations on the unbarrier region of the P-well region 103 to form the N+ region 105; the N+ region 105 is formed at 400℃–600℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3An injection angle of 7°–10° is used to avoid channeling effects, with a thickness of 0.2µm~0.5µm. Figure 2c As shown.

[0040] Step S4: Remove the second barrier layer 22 and simultaneously perform rapid thermal annealing on P-well regions 103, P+ regions 104, and N+ regions 105. The rapid thermal annealing temperature is between 1600℃ and 1800℃, using an inert or protective atmosphere, for 1 to 10 minutes to ensure doping activation and lattice repair while minimizing surface damage. P-well regions 103, P+ regions 104, and N+ regions 105 must be activated in the same annealing step to avoid repeated high-temperature damage.

[0041] Step S5: A third barrier layer 23 is formed. Unbarriered areas on the P-well region 103, P+ region 104, and N+ region 105 are etched to form a gate trench region 106. The gate trench region 106 has a thickness of 0.5µm to 1.2µm, and is 0.05µm to 0.5µm thicker than the P-well region 103. Figures 2d-2f The figures shown are a top view, a front view, and a cross-sectional view along the middle. The etching process uses either inductively coupled plasma (ICP) etching or inductively coupled plasma combined with reactive ion etching (ICP-RIE).

[0042] Step S6: Remove the third barrier layer 23, perform RCA cleaning, and then perform dry oxygen thermal oxidation in the furnace tube to remove the oxide layer above the P+ region 104 and N+ region 105, forming a gate oxide layer 107 in the gate trench region 106; the dry oxygen thermal oxidation temperature is between 1000℃ and 1300℃; the sidewall thickness of the gate oxide layer 107 is 0.01µm to 0.5µm, and the bottom thickness is 0.02µm to 0.7µm.

[0043] Step S7: The gate oxide layer 107 is deposited in multiple steps using chemical vapor deposition to form polysilicon; after doping the polysilicon, etching is performed to form the gate 108; the chemical vapor deposition temperature is between 550℃ and 700℃; the polysilicon doping concentration is 1e. 18 ~1e 20 cm -3 .like Figure 2g-Figure 2h The images shown are the front view and the top view, respectively.

[0044] Step S8: Metal is deposited on the back side of the silicon carbide substrate 101 to form a drain 109, and metal is deposited over the P+ region 104 and part of the N+ region 105 to form a source 110. The drain 109 and source 110 are then subjected to rapid thermal annealing to form an ohmic contact, completing the fabrication of a silicon carbide trench gate MOSFET device with a low on-resistance three-sided trench structure. Part of the N+ region 105 is the center of the N+ region 105; the rapid thermal annealing temperature is between 900℃ and 1100℃, and the time is between 30 seconds and 2 minutes. Metal silicide is formed through interface reaction, reducing contact resistance and forming an ohmic contact. Figure 2i As shown.

[0045] Furthermore, metal deposition is achieved using physical vapor deposition (PVD), which involves bombarding a target material, such as Ti, Al, and Ni, with high-energy ions via magnetron sputtering to form a metal deposit.

[0046] like Figure 2i The silicon carbide trench MOSFET device with a three-sided trench structure shown includes a silicon carbide substrate 101, a silicon carbide epitaxial layer 102, a P-well region 103, a P+ region 104, an N+ region 105, a gate oxide layer 107, a gate 108, a drain 109, and a source 110. The drain 109 is located on the back side of the silicon carbide substrate 101, the silicon carbide epitaxial layer 102 is located on the front side of the silicon carbide substrate 101, the P-well region 103 is formed on the silicon carbide epitaxial layer 102, the P+ region 104 and the N+ region 105 are formed on the P-well region 103, the gate oxide layer 107 is located at the center of the P-well region 103 and the N+ region 105, the gate 108 is located on the gate oxide layer 107, and the source 110 is located on the entire P+ region 104 and a portion of the N+ region 105. Specific Implementation Example 1

[0048] Step S1: Both the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are N-type doped. The doping concentration of the silicon carbide substrate 101 is 2e⁻. 18 cm -3 The thickness is 350µm; the silicon carbide epitaxial layer 102 is doped with 5e-. 15 cm -3 The thickness is 12µm. At 600℃, the silicon carbide epitaxial layer 102 is subjected to multiple aluminum ion implantations or co-implantation of aluminum and boron ions to form a 0.7µm P-well region 103; the net acceptor concentration of the P-well region 103 is 1e⁻¹. 17 cm -3 .

[0049] Step S2: A first barrier layer 21 is formed above the P-well region 103. Multiple aluminum ion implantations or co-implantation of aluminum and boron ions are performed at 600°C to form the P+ region 104, with a doping concentration of 1e⁻¹. 19 cm -3 The thickness is 0.2µm.

[0050] Step S3: Remove the first barrier layer 21 to form the second barrier layer 22. Then, perform multiple nitrogen ion implantations at 600℃ to form the N+ region 105 with a doping concentration of 1e. 19 cm -3 The thickness is 0.2µm, and it is injected at an angle of 7°–10°.

[0051] Step S4: Remove the second barrier layer 22 and perform rapid thermal annealing on P-well region 103, P+ region 104 and N+ region 105 simultaneously for 5 minutes at 1700°C in an inert / protective atmosphere.

[0052] Step S5: Form a third barrier layer 23 and etch to form a gate trench region 106. The gate trench region 106 has a thickness of 0.8µm, which is 0.1µm thicker than the P-well region 103. The protruding portion of the third barrier layer 23 has a vertical width of 2µm and a horizontal width of 0.5µm, while the recessed portion has a vertical width of 0.5µm.

[0053] Step S6: Remove the third barrier layer 23 and perform RCA standard cleaning. Then, perform dry oxygen thermal oxidation at 1200°C in a furnace tube to remove the oxide layers above the P+ region 104 and N+ region 105, forming the gate oxide layer 107. The sidewall thickness of the gate oxide layer 107 is 0.03µm, and the bottom thickness is 0.05µm. Multi-step deposition is performed at 600°C using LPCVD, followed by doping of the polysilicon to a doping concentration of 1e. 19 cm -3 Finally, the polysilicon is etched to form the gate 108.

[0054] Step S7: Using physical vapor deposition, high-energy ions, such as Ti, Al, or Ni, are bombarded onto the target material by magnetron sputtering to deposit atoms onto the back side of the silicon carbide substrate 101 to form the drain 109, and sputtered onto the central portion of the P+ and N+ source regions to form the source 110. Subsequently, rapid thermal annealing at 1000°C for 1 minute is performed to form metal silicides through interfacial reactions, reducing contact resistance and forming an ohmic contact between the drain 109 and the source 110.

[0055] Compared with the traditional trench structure, the MOSFET device prepared by the above steps has a 37.5% larger vertical channel conduction area and a 27% smaller channel resistance. Specific Implementation Example 2

[0057] Step S1: Both the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are N-type doped. The doping concentration of the silicon carbide substrate 101 is 2e⁻. 18 cm -3 The thickness is 350µm; the silicon carbide epitaxial layer 102 is doped with 5e-. 15 cm -3 The thickness is 12µm. At 600℃, the silicon carbide epitaxial layer 102 is subjected to multiple aluminum ion implantations or co-implantation of aluminum and boron ions to form a 0.7µm P-well region 103; the net acceptor concentration of the P-well region 103 is 1e⁻¹. 17 cm -3 .

[0058] Step S2: A first barrier layer 21 is formed above the P-well region 103. Multiple aluminum ion implantations or co-implantation of aluminum and boron ions are performed at 600°C to form the P+ region 104, with a doping concentration of 1e⁻¹. 19 cm -3 The thickness is 0.2µm.

[0059] Step S3: Remove the first barrier layer 21 to form the second barrier layer 22. Then, perform multiple nitrogen ion implantations at 600℃ to form the N+ region 105 with a doping concentration of 1e. 19 cm -3 The thickness is 0.2µm, and it is injected at an angle of 7°–10°.

[0060] Step S4: Remove the second barrier layer 22 and perform rapid thermal annealing on P-well region 103, P+ region 104 and N+ region 105 simultaneously for 5 minutes at 1700°C in an inert / protective atmosphere.

[0061] Step S5: Form a third barrier layer 23 and etch to form a gate trench region 106. The gate trench region 106 has a thickness of 0.8µm, which is 0.1µm thicker than the P-well region 103. The protruding portion of the third barrier layer 23 has a vertical width of 2µm and a horizontal width of 0.8µm, while the recessed portion has a vertical width of 0.5µm.

[0062] Step S6: Remove the third barrier layer 23 and perform RCA standard cleaning. Then, perform dry oxygen thermal oxidation at 1200°C in a furnace tube to remove the oxide layers above the P+ region 104 and N+ region 105, forming the gate oxide layer 107. The sidewall thickness of the gate oxide layer 107 is 0.03µm, and the bottom thickness is 0.05µm. Multi-step deposition is performed at 600°C using chemical vapor deposition, followed by doping of the polysilicon to a doping concentration of 1e. 19 cm -3Finally, the polysilicon is etched to form the gate 108.

[0063] Step S7: Using physical vapor deposition, high-energy ions, such as Ti, Al, or Ni, are bombarded onto the target material by magnetron sputtering to deposit atoms onto the back side of the silicon carbide substrate 101 to form the drain 109, and sputtered onto the central portion of the P+ and N+ source regions to form the source 110. Subsequently, rapid thermal annealing at 1000°C for 1 minute is performed to form metal silicides through interfacial reactions, reducing contact resistance and forming an ohmic contact between the drain 109 and the source 110.

[0064] Compared with the traditional trench structure, the MOSFET device prepared by the above steps has a 60% larger vertical channel conduction area and a 37% smaller channel resistance.

[0065] As can be seen from the above two embodiments, the method of the present invention can increase the channel area and reduce the conduction resistance, while adjusting the channel resistance by controlling the width of the three-sided trench structure.

[0066] It should be noted that the above description of the embodiments is only for the purpose of helping to understand the method and core idea of ​​this application. For those skilled in the art, several improvements and modifications can be made to this application without departing from the principle of this application, and these improvements and modifications are also within the protection scope of the claims of this application.

Claims

1. A method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure, characterized in that, include: Step S1: A silicon carbide epitaxial layer (102) is epitaxially grown on a silicon carbide substrate (101), and the silicon carbide epitaxial layer (102) is subjected to multiple aluminum ion implantations or aluminum ion and boron ion co-implantation to form a P-well region (103). Step S2: A first barrier layer (21) is formed on the P-well region (103), and multiple aluminum ion implantations or aluminum ion and boron ion co-implantation are performed to form a P+ region (104). Step S3: Remove the first barrier layer (21) to form a second barrier layer (22), and perform multiple nitrogen ion implantations to form an N+ region (105). Step S4: Remove the second barrier layer (22) and simultaneously perform rapid thermal annealing on the P-well region (103), the P+ region (104) and the N+ region (105); Step S5: Form a third barrier layer (23) and perform etching to form a gate trench region (106). Step S6: Remove the third barrier layer (23), perform RCA cleaning, and then perform dry oxygen thermal oxidation in the furnace tube to remove the oxide layer above the P+ region (104) and the N+ region (105) and form a gate oxide layer (107) in the gate trench region (106). Step S7: The gate oxide layer (107) is deposited in multiple steps using chemical vapor deposition to form polysilicon; after doping the polysilicon, it is etched to form the gate (108). In step S8, a drain electrode (109) is formed by depositing metal on the back side of the silicon carbide substrate (101), and a source electrode (110) is formed by depositing metal on the P+ region (104) and part of the N+ region (105). The drain electrode (109) and the source electrode (110) are then subjected to rapid thermal annealing to form ohmic contacts, thereby preparing a silicon carbide trench MOSFET device with a three-sided trench structure.

2. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S1, the doping concentration of the silicon carbide substrate (101) is 1e. 18 cm -3 ~1e 20 cm -3 The thickness is 200µm~1000µm; the doping concentration of the silicon carbide epitaxial layer (102) is 1e. 15 cm -3 ~5e 16 cm -3 The thickness is 6µm~40µm; the P-well region (103) is formed at 500℃-800℃ with a net acceptor concentration of 5e. 16 cm -3 ~5e 17 cm -3 .

3. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S2, the P+ region (104) is formed at 500℃–700℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The thickness is 0.2µm~0.5µm.

4. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S3, the N+ region (105) is formed at 400℃–600℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The injection angle is 7°–10°, and the thickness is 0.2µm~0.5µm.

5. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S4, the rapid thermal annealing temperature is between 1600℃ and 1800℃, using an inert atmosphere or a protective atmosphere, and the time is between 1 and 10 minutes.

6. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S5, the thickness of the gate trench region (106) is 0.5µm to 1.2µm, and is 0.05µm to 0.5µm thicker than the thickness of the P-well region (103).

7. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S6, the temperature of dry oxygen thermal oxidation is between 1000℃ and 1300℃; the sidewall thickness of the gate oxide layer (107) is 0.01µm to 0.5µm, and the bottom thickness is 0.02µm to 0.7µm.

8. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S7, the temperature of chemical vapor deposition is between 550°C and 700°C; the polycrystalline silicon doping concentration is 1e. 18 ~1e 20 cm -3 .

9. The method for fabricating a silicon carbide trench MOSFET device with a three-sided trench structure according to claim 1, characterized in that, In step S8, part of the N+ region (105) is the center of the N+ region (105); the temperature of rapid thermal annealing is between 900℃ and 1100℃, and the time is between 30 seconds and 2 minutes.

10. A silicon carbide trench MOSFET device with a three-sided trench structure prepared by the method according to any one of claims 1-9, characterized in that, The structure includes a silicon carbide substrate (101), a silicon carbide epitaxial layer (102), a P-well region (103), a P+ region (104), an N+ region (105), a gate oxide layer (107), a gate (108), a drain (109), and a source (110). The drain (109) is located on the back side of the silicon carbide substrate (101), the silicon carbide epitaxial layer (102) is located on the front side of the silicon carbide substrate (101), and the P-well region (103) is formed on the back side of the substrate. On the silicon carbide epitaxial layer (102), the P+ region (104) and the N+ region (105) are formed on the P-well region (103), the gate oxide layer (107) is disposed at the center of the P-well region (103) and the N+ region (105), the gate (108) is disposed on the gate oxide layer (107), and the source (110) is disposed on the P+ region (104) in all regions and the N+ region (105) in part of the regions.

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