Chip, preparation method and electronic equipment

Abstract

The invention discloses a chip, a preparation method and electronic equipment, the chip comprises a substrate, a first electrode layer, a plurality of vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer and a second insulating dielectric layer, a plurality of VTFETs can be formed in the chip, and the stacking density is improved. In addition, by arranging the first gas gap, stray capacitance between the gate conductive layer and the first electrode layer can be effectively reduced, and dynamic power consumption and RC delay time of the VTFET are reduced. And the dielectric material is arranged in at least part of the region between the first gas gap and the vertical channel and between the first gas gap and the gate structure, so that at least part of the dielectric material exists between the first gas gap and the vertical channel and between the first gas gap and the gate structure, and the mechanical stability and reliability of the VTFET device structure can be improved; and the requirements of the chip on performance, power consumption, area, cost and reliability are met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip, a preparation method and an electronic device. Background Art

[0002] Continuously reducing device size and increasing integration to achieve better performance are the goals and driving forces of integrated circuit technology. The most basic unit in an integrated circuit is the field-effect transistor (FET). Traditional FETs are usually planar structures, with the current path from the drain through the channel to the source running in the horizontal direction. However, with the continued advancement of Moore's Law, the continuous shrinking of the critical dimensions (CD) of traditional planar FETs (such as gate length, contact metal spacing, etc.) has reached its physical limit, resulting in a contradiction between power consumption, performance, and cost in chips. To this end, vertical transport field-effect transistors (VTFETs) have emerged, in which the current path from the drain through the channel to the source runs in the vertical direction, rather than the horizontal direction. In this way, further shrinking of the FET area no longer depends on the compression of the FET's own characteristic dimensions. However, parasitic capacitance exists between the gate and the source and drain in the VTFET, respectively, which affects the performance of the VTFET. Summary of the Invention

[0003] The present application provides a chip, a preparation method, and an electronic device for reducing the parasitic capacitance of a VTFET and improving the performance of the VTFET.

[0004] In a first aspect, embodiments of the present application provide a chip comprising: a substrate, a first electrode layer, multiple vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer, and a second insulating dielectric layer. The first electrode layer is disposed on the substrate, and multiple vertical channels are spaced apart on a side of the first electrode layer facing away from the substrate. The vertical channels include a first region, a second region disposed on a side of the first region facing the substrate, and a third region disposed on a side of the first region facing away from the substrate, with the second region electrically connected to the first electrode layer. The first insulating dielectric layer is disposed on a side of the first electrode layer facing away from the substrate and covers the sidewalls of the second region of each vertical channel. The gate structure is disposed on a side of the first insulating dielectric layer facing away from the substrate and covers at least a portion of the sidewalls of the first region of each vertical channel. The second electrode layer is disposed on a side of each vertical channel facing away from the substrate and is electrically connected to the third region of each vertical channel. The second insulating dielectric layer is disposed on a side of the gate structure facing away from the substrate and covers the gate structure, the second electrode layer, and the sidewalls of the third region of each vertical channel. This configuration allows for the formation of multiple VTFETs within a chip, thereby increasing stacking density. Furthermore, the first insulating dielectric layer has a first gas gap. Providing the first gas gap effectively reduces parasitic capacitance between the gate conductive layer and the first electrode layer, thereby reducing the dynamic power consumption and RC delay time of the VTFET. Furthermore, by providing a dielectric material in at least a portion of the region between the first gas gap and the vertical channel and gate structure, at least a portion of the dielectric material exists between the first gas gap and the vertical channel and gate structure, respectively. This improves the mechanical stability and reliability of the VTFET device structure, thereby meeting the chip's performance, power, area, cost (PPAC), and reliability requirements.

[0005] In some embodiments, a dielectric material is disposed in the entire region between the first gas gap and the vertical channel and gate structure. The first gas gap can be enclosed in a first insulating dielectric layer, so that the first gas gap does not directly contact the vertical channel and gate structure, further improving the mechanical stability and reliability of the VTFET device structure. Of course, a dielectric material can also be disposed in a portion of the region between the first gas gap and the vertical channel and gate structure, so that the first gas gap contacts a portion of the vertical channel and gate structure.

[0006] In addition, when preparing the chip in the embodiment of the present application, a first gas gap with good shape uniformity and high mechanical stability can be formed based on process steps with a high degree of freedom, so that the shape and position of the first gas gap can be accurately controlled using process means, which can improve process integration and facilitate cost control, so that it can be widely used in logic, storage, power and other integrated circuits.

[0007] Exemplarily, the gas in the first gas gap may be air, so that the first gas gap is set as an air gap. Alternatively, the gas in the first gas gap may also be an inert gas, so that the first gas gap is set as an inert gas gap.

[0008] In some embodiments, the gate structure includes a gate conductive layer and a gate dielectric layer disposed between the gate conductive layer and the sidewalls of the first region. Furthermore, the orthographic projection of the first gas gap on the substrate and the orthographic projection of the gate conductive layer on the substrate have no or only partial overlap. This arrangement vertically reduces the volume of the gas gap disposed below the gate conductive layer, further improving the mechanical stability and reliability of the VTFET device structure.

[0009] In some embodiments, adjacent vertical channels share a same first gas gap, and an orthographic projection of the first gas gap on the substrate falls between orthographic projections of the gate conductive layers corresponding to the first regions of the adjacent vertical channels on the substrate.

[0010] In some embodiments, the gate conductive layer is disposed on both sides of the vertical channel, and the first gas gap is disposed on both sides of the vertical channel.

[0011] In some embodiments, the gate conductive layer surrounds the vertical channel, and the first gas gap surrounds the vertical channel.

[0012] In some embodiments, if the gate conductive layer surrounds the vertical channel, the VTFET may be a vertical gate-all-around (VGAA) FET.

[0013] In some embodiments, the first insulating dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, wherein the first dielectric layer has a first groove, with dielectric material disposed between the first groove and the vertical channel. Furthermore, the second dielectric layer covers the surface of the first dielectric layer facing away from the substrate and seals the open end of the first groove, thereby forming a first gas gap within the first groove. This arrangement allows the second dielectric layer and the first dielectric layer to be combined to form the first gas gap, thereby improving the mechanical stability and reliability of the VTFET device structure.

[0014] In some embodiments, the first dielectric layer and the second dielectric layer are further in contact with sidewalls of the second region of the vertical channel, respectively.

[0015] In some embodiments, the first dielectric layer and the second dielectric layer respectively surround sidewalls of the second region of the vertical channel.

[0016] In some embodiments, the second dielectric layer further covers the bottom wall and sidewalls of the first recess, thereby forming a first gas gap within the first recess. This arrangement allows the first gas gap to be enclosed by the second dielectric layer, further improving the mechanical stability and reliability of the VTFET device structure.

[0017] In some embodiments, the second insulating dielectric layer includes a second gas gap, which is disposed between the layer containing the gate structure and the layer containing the second electrode layer, and a dielectric material is disposed between the second gas gap and the vertical channel and gate structure. This configuration effectively reduces the parasitic capacitance between the gate conductive layer and the second electrode layer, thereby reducing the dynamic power consumption and RC delay time of the VTFET. Furthermore, by disposing a dielectric material in at least a portion of the region between the second gas gap and the vertical channel and gate structure, at least a portion of the dielectric material is disposed between the second gas gap and the vertical channel and gate structure, respectively. This improves the mechanical stability and reliability of the chip structure, thereby meeting the chip's requirements for PPAC and reliability.

[0018] In addition, when preparing the chip in the embodiment of the present application, a second gas gap with good shape uniformity and high mechanical stability can be formed based on process steps with a high degree of freedom, so that the shape and position of the second gas gap can be accurately controlled using process means, which can improve process integration and facilitate cost control, so that it can be widely used in logic, storage, power and other integrated circuits.

[0019] In some embodiments, a dielectric material is disposed in the entire region between the second gas gap and the vertical channel and gate structure. The second gas gap can be enclosed in a second insulating dielectric layer, so that the second gas gap does not directly contact the vertical channel and gate structure, further improving the mechanical stability and reliability of the VTFET device structure. Of course, a dielectric material can also be disposed in a portion of the region between the second gas gap and the vertical channel and gate structure, so that the second gas gap contacts a portion of the vertical channel and gate structure.

[0020] In addition, when preparing the chip in the embodiment of the present application, a second gas gap with good shape uniformity and high mechanical stability can be formed based on process steps with a high degree of freedom, which can improve process integration and facilitate cost control, so that it can be widely used in logic, storage, power and other integrated circuits.

[0021] In some embodiments, the gas in the second gas gap may be air, so that the second gas gap is configured as an air gap. Alternatively, the gas in the second gas gap may be an inert gas, so that the second gas gap is configured as an inert gas gap.

[0022] In some embodiments, the gas in the first gas gap and the gas in the second gas gap are the same or different.

[0023] In some embodiments, the gate structure includes a gate conductive layer and a gate dielectric layer disposed between the gate conductive layer and the sidewalls of the first region, and an orthographic projection of the second gas gap on the substrate overlaps with an orthographic projection of the gate conductive layer on the substrate. Thus, vertically disposing the second gas gap above the gate conductive layer can further reduce parasitic capacitance between the gate conductive layer and the second electrode layer.

[0024] In some embodiments, the orthographic projection of the second gas gap on the substrate is located within the orthographic projection of the gate conductive layer on the substrate, or a portion of the orthographic projection of the second gas gap on the substrate is located within the orthographic projection of the gate conductive layer on the substrate.

[0025] In some embodiments, the second gas gap further extends along the vertical direction, so that the second gas gap is also arranged in a strip shape in the vertical direction.

[0026] In some embodiments, the gate conductive layer is disposed on both sides of the vertical channel, and the second gas gap is disposed on both sides of the vertical channel.

[0027] In some embodiments, the gate conductive layer surrounds the vertical channel, and the second gas gap surrounds the vertical channel.

[0028] In some embodiments, the second insulating dielectric layer includes a third dielectric layer and a fourth dielectric layer, with the third dielectric layer disposed between the fourth dielectric layer and the substrate. The third dielectric layer covers the gate structure and the sidewalls of the third region of each vertical channel. The third dielectric layer has a second recess, with dielectric material disposed between the second recess and the vertical channel. Furthermore, the fourth dielectric layer covers the second electrode layer and the third dielectric layer, and the fourth dielectric layer seals the open end of the second recess to form a second gas gap within the second recess. This arrangement allows the third and fourth dielectric layers to be combined to form the second gas gap, thereby improving the mechanical stability and reliability of the VTFET device structure.

[0029] In some embodiments, the third dielectric layer includes an upper dielectric layer and multiple lower dielectric layers arranged in a stacked manner, the multiple lower dielectric layers covering the gate structure and the sidewalls of the third region of each vertical channel, and the upper dielectric layer covering the multiple lower dielectric layers. Furthermore, the multiple lower dielectric layers include a first lower dielectric layer and at least one second lower dielectric layer, wherein the first lower dielectric layer is disposed between the at least one second lower dielectric layer and the gate structure, and the first lower dielectric layer contacts the sidewalls of the third region, and the upper surface of the first lower dielectric layer facing away from the substrate is aligned with the upper surface of the third region facing away from the substrate. The upper surface of at least one of the at least one second lower dielectric layers facing away from the substrate is disposed between the upper surface of the third region facing away from the substrate and the upper surface of the gate conductive layer facing away from the substrate, thereby forming a second recess.

[0030] In some embodiments, the materials of the multiple lower dielectric layers are different, so that some lower dielectric layers can be etched by utilizing the etching selectivity ratio to avoid damaging the remaining lower dielectric layers.

[0031] In some embodiments, the upper dielectric layer and the plurality of lower dielectric layers are made of different materials, so that some lower dielectric layers can be etched by utilizing an etching selectivity ratio to avoid damaging the remaining lower dielectric layers.

[0032] In a second aspect, an embodiment of the present application further provides a chip, comprising: a substrate, a first electrode layer, a plurality of vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer, and a second insulating dielectric layer, wherein the first electrode layer is disposed on the substrate, and the plurality of vertical channels are spaced apart on the side of the first electrode layer facing away from the substrate, and the vertical channels include a first region, a second region disposed on the side of the first region facing the substrate, and a third region disposed on the side of the first region facing away from the substrate, the second region being electrically connected to the first electrode layer. The first insulating dielectric layer is disposed on the side of the first electrode layer facing away from the substrate and covers the sidewalls of the second region of each vertical channel. The gate structure is disposed on the side of the first insulating dielectric layer facing away from the substrate and covers at least a portion of the sidewalls of the first region of each vertical channel. The second electrode layer is disposed on the side of each vertical channel facing away from the substrate and is electrically connected to the third region of each vertical channel. The second insulating dielectric layer is disposed on the side of the gate structure facing away from the substrate and covers the gate structure, the second electrode layer, and the sidewalls of the third region of each vertical channel. The second insulating dielectric layer includes a second gas gap, which is disposed between the layer containing the gate structure and the layer containing the second electrode layer. The second gas gap comprises a dielectric material in at least a portion of the region between the second gas gap and each vertical channel and the gate structure. This configuration effectively reduces the parasitic capacitance between the gate conductive layer and the second electrode layer, thereby reducing the dynamic power consumption and RC delay time of the VTFET. Furthermore, by disposing a dielectric material in at least a portion of the region between the second gas gap and the vertical channel and the gate structure, at least a portion of the dielectric material exists between the second gas gap and the vertical channel and the gate structure, thereby improving the mechanical stability and reliability of the VTFET device structure and meeting the chip's requirements for PPAC and reliability.

[0033] Furthermore, the implementation of the second gas gap can refer to the above description and will not be described in detail here.

[0034] In a third aspect, an embodiment of the present application further provides an electronic device, the electronic device comprising a circuit board and a chip, wherein the chip is disposed on the circuit board. The chip is the chip in the first aspect or any embodiment of the first aspect, or the chip is the chip in the second aspect or any embodiment of the second aspect. Furthermore, the electronic device includes, for example, but is not limited to, terminal devices, communication devices, and the like. Terminal devices include, but are not limited to, mobile phones, computers, televisions, TV set-top boxes, watches, personal computers (PCs), wearable devices, workstations, and other devices. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, and the like. Electronic devices include, but are not limited to, device modules, storage circuits, logic circuits, power devices, and the like.

[0035] In a fourth aspect, an embodiment of the present application also provides a method for preparing a chip, the method comprising: forming a first electrode layer, multiple vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer and a second insulating dielectric layer on a substrate; wherein, the multiple vertical channels are spaced apart on the side of the first electrode layer facing away from the substrate, the vertical channels include a first region, a second region arranged on the side of the first region facing the substrate, and a third region arranged on the side of the first region facing away from the substrate, and the second region is electrically connected to the first electrode layer; the first insulating dielectric layer is arranged on the side of the first electrode layer facing away from the substrate, and covers the sidewalls of the second region of each vertical structure; the gate structure is arranged on the side of the first insulating dielectric layer facing away from the substrate, and covers at least a portion of the sidewalls of the first region of each vertical structure; the second electrode layer is arranged on the side of the vertical channel facing away from the substrate, and is electrically connected to the third region of each vertical structure; the second insulating dielectric layer is arranged on the side of the gate structure facing away from the substrate, and covers the gate structure, the second electrode layer and the sidewalls of the third region covering each vertical structure; wherein the first insulating dielectric layer has a first gas gap, and at least a portion of the area between the first gas gap and the vertical channel and the gate structure has a dielectric material. With this arrangement, a first gas gap can be formed in the chip.

[0036] In some embodiments, the method further includes forming a second gas gap in the second insulating dielectric layer, the second gas gap being disposed between the layer where the gate structure resides and the layer where the second electrode layer resides, and at least a portion of the area between the second gas gap and the vertical channel and the gate structure being provided with a dielectric material. Thus, a second gas gap can be formed in the chip.

[0037] In a fifth aspect, an embodiment of the present application further provides a method for preparing a chip, the method comprising: forming a first electrode layer, a plurality of vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer, and a second insulating dielectric layer on a substrate; wherein the plurality of vertical channels are spaced apart on the side of the first electrode layer facing away from the substrate, the vertical channels comprising a first region, a second region arranged on the side of the first region facing the substrate, and a third region arranged on the side of the first region facing away from the substrate, the second region being electrically connected to the first electrode layer; the first insulating dielectric layer being arranged on the side of the first electrode layer facing away from the substrate, and covering the sidewalls of the second region of each vertical structure; the gate structure A first insulating dielectric layer is disposed on the side of the first insulating dielectric layer facing away from the substrate and covers at least a portion of the sidewalls of the first region of each vertical structure. A second electrode layer is disposed on the side of the vertical channel facing away from the substrate and is electrically connected to the third region of each vertical structure. A second insulating dielectric layer is disposed on the side of the gate structure facing away from the substrate and covers the gate structure, the second electrode layer, and the sidewalls of the third region of each vertical structure. The second insulating dielectric layer has a second gas gap disposed between the layer containing the gate structure and the layer containing the second electrode layer, and at least a portion of the area between the second gas gap and the vertical channel and the gate structure is provided with dielectric material. This configuration forms a second gas gap in the chip.

[0038] In addition, the technical effects of the corresponding schemes in the second to fifth aspects can refer to the technical effects that can be obtained by the corresponding schemes in the first or second aspect, and the repeated parts will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of a chip in an embodiment of the present application;

[0041] Figure 3a and Figure 3b Schematic diagrams of a top view of the vertical channel, the gate conductive layer, the first gas gap, and the second gas gap in the embodiments of the present application;

[0042] Figure 4 Schematic diagram of another top view of the vertical channel, the gate conductive layer, the first gas gap, and the second gas gap in the embodiment of the present application;

[0043] Figure 5 This is another structural diagram of the chip in the embodiment of the present application;

[0044] Figure 6 This is another structural diagram of the chip in the embodiment of the present application;

[0045] Figures 7a to 7q They are respectively a structural schematic diagram of the chip in the embodiment of the present application during the preparation process;

[0046] Figure 8 This is another structural diagram of the chip in the embodiment of the present application;

[0047] Figures 9a to 9d They are respectively another structural schematic diagram of the chip in the embodiment of the present application during the preparation process;

[0048] Figure 10 This is another structural diagram of the chip in the embodiment of the present application.

[0049] Reference numerals

[0050] 100 - housing; 200 - circuit board; 300 - chip; 310 - substrate; 320 - first electrode layer; 321 - first metal layer; 322 - first ohmic contact layer; 330 - first insulating dielectric layer; 331 - first dielectric layer; 332 - second dielectric layer; 340 - gate structure; 341 - gate conductive layer; 342 - gate dielectric layer; 350 - second insulating dielectric layer; 351 - third dielectric layer; 3511a - first lower dielectric layer; 3511b - second lower dielectric layer; 3512 - upper dielectric layer; 352 - fourth dielectric layer; 36 0-second electrode layer; 361-second ohmic contact layer; 362-second metal layer; 371-first gas gap; 372-second gas gap; 380-vertical channel; 410-hard mask; 420-first interlayer dielectric layer; 430-second interlayer dielectric layer; 440-dielectric mask; A1-first region; A2-second region; A3-third region; a1-channel region; a2-first heavily doped region; a3-second heavily doped region; AX1-first groove; AX2-second groove; F0-vertical direction; F1-first direction; F2-second direction. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0052] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0053] The chip provided in the embodiment of the present application can be various electronic devices or integrated circuit devices for realizing one or more functions, and the chip can be widely used in various electronic devices. Electronic devices include, but are not limited to, terminal devices, communication devices, etc. Terminal devices include, but are not limited to, mobile phones, computers, televisions, TV set-top boxes, watches, personal computers (PCs), wearable devices, workstations and other devices. Communication equipment includes, but is not limited to, wireless network equipment, fixed network equipment, servers, smart broadband equipment, etc. Electronic devices or integrated circuit devices include, but are not limited to, device modules, storage circuits, logic circuits, power devices, etc., which are not listed here one by one. It is understandable that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited here.

[0054] Figure 1 This is a structural diagram of an electronic device in an embodiment of the present application. Figure 1 The electronic device includes a housing 100, a circuit board 200 disposed within the housing 100, and a chip 300 fixed to the circuit board 200. The chip 300 and the circuit board 200 may be electrically connected by bonding, riveting, or other connection methods, thereby enabling signal transmission between the chip 300 and the circuit board 200. For example, the circuit board 200 includes, but is not limited to, a printed circuit board (PCB).

[0055] Figure 2 A schematic diagram of the structure of the chip in the embodiment of the present application, referring to Figure 2 The chip 300 provided in the embodiment of the present application may include a substrate 310. For example, the material of the substrate 310 includes, but is not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), a III-V compound semiconductor, or a II-VI compound semiconductor. In some examples, the substrate 310 may be entirely composed of silicon.

[0056] A first electrode layer 320 is disposed on the substrate 310, through which signals are transmitted. For example, the first electrode layer 320 can be a single-layer structure, and the first electrode layer 320 is configured as a metal layer. Alternatively, the first electrode layer 320 can be a multi-layer structure, for example, the first electrode layer 320 includes a first metal layer 321 and a first ohmic contact layer 322, and the first metal layer 321 is disposed between the first ohmic contact layer 322 and the substrate 310, thereby achieving ohmic contact.

[0057] A plurality of vertical channels 380 are provided on the side of the first electrode layer 320 facing away from the substrate 310. These vertical channels 380 are spaced apart from one another. Each vertical channel 380 extends in a vertical direction F0 perpendicular to the plane of the substrate 310, forming a vertical channel 380 extending perpendicular to the plane of the substrate 310. Furthermore, each vertical channel 380 includes a first region A1, a second region A2 disposed on the side of the first region A1 facing the substrate 310, and a third region A3 disposed on the side of the first region A1 facing away from the substrate 310. Specifically, the second region A2, the first region A1, and the third region A3 are arranged sequentially along the vertical direction F0. For example, each vertical channel 380 includes a first heavily doped region a2, a channel region a1, and a second heavily doped region a3 sequentially arranged along the vertical direction F0. The first region A1 may be a portion of the channel region a1, the second region A2 may include the first heavily doped region a2 and a portion a11 of the channel region a1, and the third region A3 may include the second heavily doped region a3 and a portion a12 of the channel region a1. Alternatively, the first region A1 may be the channel region a1, the second region A2 may be the first heavily doped region a2, and the third region A3 may be the second heavily doped region a3.

[0058] Furthermore, the second region A2 of each vertical channel 380 is electrically connected to the first electrode layer 320. For example, the second region A2 of the vertical channel 380 is electrically connected to the first electrode layer 320 on the side facing the substrate 310, so as to transmit signals to the vertical channel 380 through the first electrode layer 320. It is understandable that the first electrode layer 320 may include a plurality of first electrodes spaced apart from each other, so that some vertical channels 380 are connected to the same first electrode, for example, vertical channels 380 arranged along the first direction F1 are connected to the same first electrode. Alternatively, different vertical channels 380 are connected to different first electrodes. In addition, in a specific implementation, the vertical channel 380 can be configured as a columnar shape, and the shape of the orthographic projection of the vertical channel 380 on the substrate 310 can be rectangular, circular, elliptical, etc. Alternatively, the vertical channel 380 can also be configured as a fin-type vertical channel.

[0059] A first insulating dielectric layer 330 is disposed on the side of the first electrode layer 320 facing away from the substrate 310. The first insulating dielectric layer 330 may cover the sidewalls of the second region A2 of each vertical channel 380. For example, the first insulating dielectric layer 330 may surround the sidewalls of the second region A2 of each vertical channel 380. Furthermore, the first insulating dielectric layer 330 directly contacts each vertical channel 380. Furthermore, a first gas gap 371 is defined within the first insulating dielectric layer 330. At least a portion of the region between the first gas gap 371, the vertical channel 380, and the gate structure 340 comprises a dielectric material. For example, the gas within the first gas gap 371 may be air, such that the first gas gap 371 is configured as an air gap. Alternatively, the gas within the first gas gap 371 may be an inert gas, such that the first gas gap 371 is configured as an inert gas gap. It is understood that the gas within the first gas gap 371 may also be other chemically inactive gases, which are not limited herein.

[0060] A gate structure 340 is provided on the side of the first insulating dielectric layer 330 facing away from the substrate 310. The gate structure 340 may cover at least a portion of the sidewall of the first region A1 of each vertical channel 380. For example, the gate structure 340 includes a gate conductive layer 341 and a gate dielectric layer 342 provided between the gate conductive layer 341 and the sidewall of the first region A1, wherein the gate conductive layer 341 may be a metal material or a polysilicon material. Alternatively, the gate structure 340 may also be a high-k (dielectric constant) metal gate (HKMG), in which case the gate structure may include a gate dielectric layer, a high-k dielectric layer, and a gate conductive layer, wherein the material of the gate conductive layer is a metal material. Of course, one or more of a work function layer and a liner layer may also be provided between the high-k dielectric layer and the gate conductive layer. Furthermore, in a specific implementation, the gate conductive layer 341 can be disposed on both sides of the vertical channel 380. For example, when the orthographic projection of the vertical channel 380 on the substrate 310 is a rectangle, the orthographic projection of the gate conductive layer 341 on the substrate 310 is disposed on two opposite sides of the orthographic projection of the vertical channel 380 on the substrate 310. Alternatively, the gate conductive layer 341 can be disposed around the vertical channel 380, and the gate structures 340 surrounding the vertical channels 380 with different functions are spaced apart from each other.

[0061] A second electrode layer 360 is provided on the side of the vertical channel 380 facing away from the substrate 310. The second electrode layer 360 can be connected to the third area A3 of each vertical channel 380, and signals are transmitted through the second electrode layer 360. For example, the second electrode layer 360 can contact the surface of the third area A3 of each vertical channel 380 facing away from the substrate 310. In a specific implementation, the second electrode layer 360 can have a single-layer structure, and the second electrode layer 360 is provided as a metal layer. Alternatively, the second electrode layer 360 can have a multi-layer structure. For example, the second electrode layer 360 includes a second metal layer 362 and a second ohmic contact layer 361, and the second ohmic contact layer 361 is provided between the second metal layer 362 and the vertical channel 380, thereby achieving ohmic contact. It is understood that the second electrode layer 360 can include a plurality of second electrodes spaced apart from each other, so that some vertical channels 380 can be connected to the same second electrode. For example, vertical channels 380 arranged along the second direction F2 can be connected to the same second electrode. Alternatively, different vertical channels 380 are connected to different second electrodes. The first direction F1 and the second direction F2 are perpendicular to each other, and both the first direction F1 and the second direction F2 are perpendicular to the vertical direction F0.

[0062] A second insulating dielectric layer 350 is also disposed on the side of the gate structure 340 facing away from the substrate 310. The second insulating dielectric layer 350 covers the gate structure 340, the second electrode layer 360, and the sidewalls of the third region A3 of each vertical channel 380. For example, the second insulating dielectric layer 350 may cover a portion of the sidewalls of the third region A3 of each vertical channel 380. For example, when the gate conductive layer 341 is disposed on both sides of the vertical channel 380, the second insulating dielectric layer 350 covers the sidewalls of the third region A3 of each vertical channel 380 located above the gate conductive layer 341. Alternatively, the second insulating dielectric layer 350 may surround the sidewalls of the second region A2 of each vertical channel 380. The second insulating dielectric layer 350 includes a second gas gap 372 disposed between the layer containing the gate structure 340 and the layer containing the second electrode layer 360. Dielectric material is disposed in at least a portion of the area between the second gas gap 372 and the vertical channel 380 and the gate structure 340. Exemplarily, the gas in the second gas gap 372 can be air, so that the second gas gap 372 is set as an air gap. Alternatively, the gas in the second gas gap 372 can also be an inert gas, so that the second gas gap 372 is set as an inert gas gap. It is understandable that the gas in the second gas gap 372 can also be set to other chemically inactive gases, which is not limited here. Furthermore, the gas in the first gas gap 371 and the gas in the second gas gap 372 can be the same or different.

[0063] In an embodiment of the present application, multiple VTFETs can be formed in a chip to increase stacking density. If the gate conductive layer 341 surrounds the vertical channel 380, the VTFET can be a vertical gate-all-around (VGAA) FET. Furthermore, the parasitic capacitance between the gate conductive layer 341 and the first electrode layer 320 can be effectively reduced by the first gas gap 371, and the parasitic capacitance between the gate conductive layer 341 and the second electrode layer 360 can be effectively reduced by the second gas gap 372, thereby reducing the dynamic power consumption and RC delay time of the VTFET. Furthermore, by setting a dielectric material in at least a portion of the area between the first gas gap 371 and the vertical channel 380 and the gate structure 340, at least a portion of the dielectric material exists between the first gas gap 371 and the vertical channel 380 and the gate structure 340, and by setting a dielectric material in at least a portion of the area between the second gas gap 372 and the vertical channel 380 and the gate structure 340, at least a portion of the dielectric material exists between the second gas gap 372 and the vertical channel 380 and the gate structure 340, thereby improving the mechanical stability and reliability of the VTFET device structure and meeting the chip's requirements for performance, power consumption, area and cost (PPAC) and reliability.

[0064] In addition, when preparing the chip in the embodiment of the present application, a first gas gap 371 and a second gas gap 372 with good shape uniformity and high mechanical stability can be formed based on process steps with a high degree of freedom, so that process means can be used to accurately control the shape and position of the first gas gap 371 and the second gas gap 372, thereby improving process integration and facilitating cost control, so that it can be widely used in logic, storage, power and other integrated circuits.

[0065] Reference Figure 2 In some embodiments, a dielectric material may be disposed throughout the entire region between the first gas gap 371 and the vertical channel 380 and the gate structure 340, thereby enclosing the first gas gap 371 within the first insulating dielectric layer 330. This prevents the first gas gap 371 from directly contacting the vertical channel 380 and the gate structure 340, and allows the first gas gap 371 to be a closed space enclosed by the first insulating dielectric layer 330. This further improves the mechanical stability and reliability of the VTFET device structure. Alternatively, a dielectric material may be disposed in a portion of the region between the first gas gap 371 and the vertical channel 380 and the gate structure 340, such that the first gas gap 371 contacts a portion of the vertical channel 380 and the gate structure 340.

[0066] Reference Figure 2, the orthographic projection of the first gas gap 371 on the substrate 310 and the orthographic projection of the gate conductive layer 341 on the substrate 310 do not overlap. Alternatively, the orthographic projection of the first gas gap 371 on the substrate 310 and the orthographic projection of the gate conductive layer 341 on the substrate 310 may only partially overlap. This arrangement can vertically reduce the volume of the gas gap provided below the gate conductive layer 341, further improving the mechanical stability and reliability of the VTFET device structure.

[0067] Furthermore, adjacent vertical channels 380 may share the same first gas gap 371 , and the orthographic projection of the first gas gap 371 on the substrate 310 falls between the orthographic projections of the gate conductive layer 341 corresponding to the first area A1 of the adjacent vertical channels 380 on the substrate 310 .

[0068] Reference Figure 2 , the orthographic projection of the first gas gap 371 on the substrate 310 and the orthographic projection of the first electrode layer 320 on the substrate 310 may have an overlapping area. Exemplarily, the orthographic projection of the first gas gap 371 on the substrate 310 and the orthographic projection of the first electrode layer 320 on the substrate 310 may have a partially overlapping area.

[0069] In some examples, reference Figure 3a and Figure 3b , Figure 3a and Figure 3b Schematic diagrams of a top view of the vertical channel, gate conductive layer, first gas gap, and second gas gap in the embodiment of the present application, wherein the gate conductive layer 341 is disposed on both sides of the vertical channel 380, and the first gas gap 371 can also be disposed on both sides of the vertical channel 380. Further, when the gate conductive layers 341 of the vertical channels 380 arranged along the second direction F2 are connected to each other and extend along the second direction F2, if adjacent vertical channels 380 share the same first gas gap 371, refer to Figure 3a , the first gas gap 371 can be formed into a strip structure extending along the second direction F2, or, referring to Figure 3b Alternatively, the first gas gaps 371 corresponding to the vertical channels 380 arranged along the second direction F2 may be spaced apart from each other.

[0070] In some other examples, reference Figure 4 , Figure 4 This is another schematic top view of the vertical channel, gate conductive layer, first gas gap, and second gas gap in an embodiment of the present application. The gate conductive layer 341 is disposed around the vertical channel 380, and the first gas gap 371 can be disposed around the vertical channel 380. Furthermore, if adjacent vertical channels 380 share the same first gas gap 371, the first gas gap 371 can form a grid-like structure.

[0071] Continue to refer to Figure 2 In some embodiments, a dielectric material is disposed in the entire region between the second gas gap 372 and the vertical channel 380 and the gate structure 340. The second gas gap 372 can be enclosed in the second insulating dielectric layer 350, thereby preventing the second gas gap 372 from directly contacting the vertical channel 380 and the gate structure 340. This can further improve the mechanical stability and reliability of the VTFET device structure. Alternatively, a dielectric material can be disposed in a portion of the region between the second gas gap 372 and the vertical channel 380 and the gate structure 340, thereby ensuring that the second gas gap 372 is in contact with a portion of the vertical channel 380 and the gate structure 340.

[0072] Reference Figure 2 , the orthographic projection of the second gas gap 372 on the substrate 310 and the orthographic projection of the gate conductive layer 341 on the substrate 310 can have an overlapping area. With this arrangement, in the vertical direction, the second gas gap 372 is arranged above the gate conductive layer 341, which can further reduce the parasitic capacitance between the gate conductive layer 341 and the second electrode layer 360. Furthermore, the orthographic projection of the second gas gap 372 on the substrate 310 can be located within the orthographic projection of the gate conductive layer 341 on the substrate 310, or a part of the orthographic projection of the second gas gap 372 on the substrate 310 can be located within the orthographic projection of the gate conductive layer 341 on the substrate 310. In addition, the second gas gap 372 can also extend in the vertical direction, so that the second gas gap 372 is also arranged in a strip shape in the vertical direction.

[0073] In some examples, reference Figure 3a and Figure 3b When the gate conductive layer 341 is disposed on both sides of the vertical channel 380, the second gas gaps 372 may also be disposed on both sides of the vertical channel 380. Furthermore, when the gate conductive layers 341 of the vertical channels 380 arranged along the second direction are connected to each other and extend along the second direction, the first gas gaps 371 may also form a strip-shaped structure extending along the second direction. Alternatively, the second gas gaps 372 corresponding to the vertical channels 380 arranged along the second direction may be spaced apart from each other.

[0074] In some other examples, reference Figure 4 When the gate conductive layer 341 is disposed around the vertical channel 380 , the second gas gap 372 may also be disposed around the vertical channel 380 .

[0075] In the embodiment of the present application, the gas gap can be formed by providing multiple dielectric layers, etching part of the dielectric layers to form grooves, and then using other dielectric layers to close the openings of the grooves.

[0076] Figure 5 This is another structural diagram of the chip in the embodiment of the present application, referring to Figure 5 The first insulating dielectric layer 330 may include a first dielectric layer 331 and a second dielectric layer 332, each stacked together. The first dielectric layer 331 is disposed between the second dielectric layer 332 and the substrate 310. Furthermore, the first dielectric layer 331 has a first groove AX1, with dielectric material interposed between the first groove AX1 and the vertical channel 380. Furthermore, the second dielectric layer 332 covers the surface of the first dielectric layer 331 facing away from the substrate 310 and seals the open end of the first groove AX1, thereby forming a first gas gap 371 within the first groove AX1. This arrangement allows the second dielectric layer 332 and the first dielectric layer 331 to be combined to form the first gas gap 371, thereby improving the mechanical stability and reliability of the chip. Furthermore, the first dielectric layer 331 and the second dielectric layer 332 each contact the sidewalls of the second region A2 of the vertical channel 380. Furthermore, the first dielectric layer 331 and the second dielectric layer 332 each surround the sidewalls of the second region A2 of the vertical channel 380.

[0077] Further, refer to Figure 5 The second dielectric layer 332 may also cover the bottom wall and sidewalls of the first groove AX1, thereby forming a first gas gap 371 in the first groove AX1 through the second dielectric layer 332. This configuration allows the first gas gap 371 to be enclosed by the second dielectric layer 332, further improving the mechanical stability and reliability of the chip.

[0078] Continue to refer to Figure 5The second insulating dielectric layer 350 may include a third dielectric layer 351 and a fourth dielectric layer 352, with the third dielectric layer 351 disposed between the fourth dielectric layer 352 and the substrate 310. Furthermore, the third dielectric layer 351 covers the gate structure 340 and the sidewalls of the third region A3 of each vertical channel 380. The third dielectric layer 351 defines a second recess AX2, with dielectric material interposed between the second recess AX2 and the vertical channel 380. Furthermore, the fourth dielectric layer 352 covers the second electrode layer 360 and the third dielectric layer 351, and the fourth dielectric layer 352 seals the open end of the second recess AX2, thereby forming a second gas gap 372 within the second recess AX2. With this configuration, the second gas gap 372 can be formed by combining the third dielectric layer 351 and the fourth dielectric layer 352, thereby improving the mechanical stability and reliability of the chip. Furthermore, when the gate conductive layer 341 is disposed on both sides of the vertical trench, the third dielectric layer 351 covers the sidewalls of the third region A3 above the gate conductive layer 341, thereby allowing the second gas gap 372 to be disposed on both sides of the vertical channel 380. When the gate conductive layer 341 surrounds the vertical trench, the third dielectric layer 351 surrounds the sidewalls of the third region A3, thereby allowing the second gas to be disposed around the vertical channel 380 as well.

[0079] In a specific implementation, the third dielectric layer 351 may be a multi-layer structure, and the second groove AX2 is formed by etching one or more layers of the multi-layer structure. Alternatively, the third dielectric layer 351 may be a single-layer structure, and the second groove AX2 is formed by etching the third dielectric layer 351.

[0080] For example, when the third dielectric layer 351 is a multi-layer structure, refer to Figure 6 , Figure 6This is another structural diagram of a chip in an embodiment of the present application. The third dielectric layer 351 may include an upper dielectric layer 3512 and multiple lower dielectric layers (e.g., 3511a, 3511b) stacked together. The multiple lower dielectric layers (e.g., 3511a, 3511b) are disposed between the upper dielectric layer 3512 and the gate structure 340. Furthermore, the multiple lower dielectric layers (e.g., 3511a, 3511b) cover the sidewalls of the gate structure 340 and the third region A3 of each vertical channel 380, and the upper dielectric layer 3512 covers the multiple lower dielectric layers (e.g., 3511a, 3511b). The multiple lower dielectric layers include a first lower dielectric layer 3511a and a second lower dielectric layer 3511b. The first lower dielectric layer 3511a is disposed between the second lower dielectric layer 3511b and the gate structure 340. The first lower dielectric layer 3511a contacts the sidewalls of the third area A3. The upper surface of the first lower dielectric layer 3511a facing away from the substrate 310 is aligned with the upper surface of the third area A3 facing away from the substrate 310. Furthermore, the upper surface of the second lower dielectric layer 3511b facing away from the substrate 310 is disposed between the upper surface of the third area A3 facing away from the substrate 310 and the upper surface of the gate conductive layer 341 facing away from the substrate 310, thereby forming a second recess AX2. For example, for the second groove AX2 provided in the same vertical channel 380, the sidewall of the second groove AX2 facing the vertical channel 380 can be formed by the first lower dielectric layer 3511a, the bottom wall of the second groove AX2 can also be formed by the first lower dielectric layer 3511a, and the sidewall of the second groove AX2 facing the vertical channel 380 can be formed by both the second lower dielectric layer 3511b and the upper dielectric layer 3512. It is understood that the number of second lower dielectric layers 3511b can also be two, three, four, or more, and this is not limited here.

[0081] In a specific implementation, the materials of the multiple lower dielectric layers can be made different, so that the etching selectivity can be used to etch certain lower dielectric layers while avoiding damage to the remaining lower dielectric layers. For example, the first lower dielectric layer 3511a and the second lower dielectric layer 3511b can be made of different materials, so that the etching selectivity can be used to etch the second lower dielectric layer 3511b while avoiding damage to the first lower dielectric layer 3511a. Furthermore, the upper dielectric layer 3512 can be made of different materials from the multiple lower dielectric layers, so that the etching selectivity can be used to etch certain lower dielectric layers while avoiding damage to the upper dielectric layer 3512 and the remaining lower dielectric layers. For example, the first lower dielectric layer 3511a, the second lower dielectric layer 3511b, and the upper dielectric layer 3512 can be made of different materials, so that the etching selectivity can be used to etch the second lower dielectric layer 3511b while avoiding damage to the first lower dielectric layer 3511a and the upper dielectric layer 3512.

[0082] It is understood that the shape of the first gas gap 371 and the shape of the second gas gap 372 can be different. Furthermore, the height and width of the first gas gap 371 can be determined according to the needs of the actual application. The height and width of the second gas gap 372 can also be determined according to the needs of the actual application.

[0083] To prepare Figure 6 Taking the structure of the chip shown as an example, the chip manufacturing method provided in the embodiment of the present application may include the following contents:

[0084] (1)Reference Figure 7a , Figure 7a This is a schematic diagram of the structure of the chip during the preparation process in an embodiment of the present application. For example, a substrate 310 is provided, and a first ohmic contact layer 322 and a first metal layer 321 are sequentially formed on the substrate 310. The first ohmic contact layer 322 and the first metal layer 321 are then etched to form a first electrode in the first electrode layer 320. A channel layer is then epitaxially grown on the side of the first electrode layer 320 facing away from the substrate 310. A hard mask 410 is then formed on the channel layer. The areas of the channel layer not covered by the hard mask 410 are then etched away to form a plurality of vertical channels 380 spaced apart from each other. The first heavily doped region a2 and the second heavily doped region a3 of each vertical channel 380 are each heavily doped, and the channel region a1 is lightly doped or undoped.

[0085] (2)Reference Figure 7b , Figure 7b This is another schematic diagram of the structure of a chip during fabrication in an embodiment of the present application. For example, a first dielectric layer 331 is deposited on the side of the first electrode layer 320 facing away from the substrate 310, with the surface of the first dielectric layer 331 facing away from the substrate 310 being no lower than the interface between the first heavily doped region a2 and the channel region a1. Furthermore, the first dielectric layer 331 contacts the corresponding region on the sidewalls of each vertical channel 380.

[0086] (3)Reference Figure 7c , Figure 7c FIG2 is another schematic diagram of the structure of a chip during fabrication according to an embodiment of the present application. For example, a first interlayer dielectric layer 420 is formed on the side of the first dielectric layer 331 facing away from the substrate 310, and the first interlayer dielectric layer 420 covers the surface of the first dielectric layer 331 facing away from the substrate 310, as well as the areas of each vertical channel 380 not covered by the first dielectric layer 331 and the hard mask 410.

[0087] (4)Reference Figure 7d , Figure 7dFIG4 is another schematic diagram of the structure of a chip during fabrication according to an embodiment of the present application. For example, the first interlayer dielectric layer 420 is etched to expose a portion of the surface of the first dielectric layer 331 facing away from the substrate 310. This portion is where the first groove AX1 is formed. The remaining portion of the surface of the first dielectric layer 331 facing away from the substrate 310 is covered by the first interlayer dielectric layer 420.

[0088] (5)Reference Figure 7e , Figure 7e Schematic diagram of another structure of the chip during the manufacturing process in an embodiment of the present application. Exemplarily, the first dielectric layer 331 exposed by the first interlayer dielectric layer 420 is etched to form a first groove AX1.

[0089] (6)Reference Figure 7f , Figure 7f FIG2 is another structural diagram of a chip during fabrication in an embodiment of the present application. Exemplarily, an amorphous deposition process is employed to form a second interlayer dielectric layer 430 on the side of the first interlayer dielectric layer 420 facing away from the substrate 310. The second interlayer dielectric layer 430 covers the surface of the first interlayer dielectric layer 420 facing away from the substrate 310, covers the bottom and sidewalls of the first groove AX1, and seals the open end of the first groove AX1. Thus, the second interlayer dielectric layer 430 forms a first gas gap 371 in the first groove AX1.

[0090] (7)Reference Figure 7g , Figure 7g FIG4 is another structural diagram of a chip during fabrication in an embodiment of the present application. For example, a dielectric mask 440 is deposited using a dielectric material, and then etched back using an etch-back process to minimize the thickness of the dielectric mask 440. This allows the surface of the dielectric mask 440 facing away from the substrate 310 to be close to the second interlayer dielectric layer 430, exposing the first interlayer dielectric layer 420 and the second interlayer dielectric layer 430 on the surface of the vertical channel 380 facing away from the substrate 310, as well as exposing the first interlayer dielectric layer 420 and the second interlayer dielectric layer 430 on a portion of the sidewall of the vertical channel 380.

[0091] (8)Reference Figure 7h , Figure 7h FIG4 is another structural diagram of a chip during fabrication according to an embodiment of the present application. For example, the first interlayer dielectric layer 420 and the second interlayer dielectric layer 430 exposed by the dielectric mask 440 are removed by etching, and the first interlayer dielectric layer 420 and the second interlayer dielectric layer 430 between the dielectric mask 440 and the vertical channel 380 are removed by etching.

[0092] (9)Reference Figure 7i , Figure 7iSchematic diagram of another structure of the chip during the preparation process in an embodiment of the present application. Exemplarily, the dielectric mask 440 is removed, completing the preparation process of the first gas gap 371. It is understandable that the second dielectric layer 332 may include a first interlayer dielectric layer 420 and a second interlayer dielectric layer 430. The first interlayer dielectric layer 420 is located between the second interlayer dielectric layer 430 and the first dielectric layer 331. The first interlayer dielectric layer 420 covers the surface of the first dielectric layer 331 on the side facing away from the substrate 310 except for the first groove AX1 area. The second interlayer dielectric layer 430 covers the surface of the first interlayer dielectric layer 420 on the side facing away from the substrate 310, covers the bottom wall and sidewalls of the first groove AX1, and seals the open end of the first groove AX1, thereby enclosing the first gas gap 371 in the first groove AX1 through the second interlayer dielectric layer 430.

[0093] (10)Reference Figure 7j , Figure 7j This is another structural diagram of a chip during the manufacturing process in an embodiment of the present application. Exemplarily, a gate dielectric layer 342 and a gate conductive layer 341 are formed on the second dielectric layer 332 to form a gate structure 340 covering the first area A1.

[0094] (11)Reference Figure 7k , Figure 7k This is another schematic diagram of the structure of a chip during fabrication in an embodiment of the present application. For example, a dielectric material is used to deposit a first lower dielectric layer 3511a, covering the gate dielectric layer 342, the gate conductive layer 341, and the second region A2 of each vertical channel 380.

[0095] (12)Reference Figure 7l , Figure 7l Schematic diagram of another structure of the chip during the manufacturing process in the embodiment of the present application. Exemplarily, a dielectric material is used to deposit a second lower dielectric layer 3511b, and the second lower dielectric layer 3511b covers the first lower dielectric layer 3511a.

[0096] (13)Reference Figure 7m , Figure 7m This is another schematic diagram of the structure of a chip during fabrication in an embodiment of the present application. By way of example, a dielectric material is used to deposit an upper dielectric layer 3512 for filling and covering the second lower dielectric layer 3511b. The materials of the first lower dielectric layer 3511a, the second lower dielectric layer 3511b, and the upper dielectric layer 3512 can all be different. Furthermore, the materials of the first lower dielectric layer 3511a, the second lower dielectric layer 3511b, and the upper dielectric layer 3512 can be selected to have a relatively large etching area.

[0097] (14)Reference Figure 7n , Figure 7n This is another structural diagram of a chip during fabrication in an embodiment of the present application. For example, a chemical mechanical polishing (CMP) process is used to planarize the upper dielectric layer 3512 and the hard mask 410 to expose the vertical channels 380 .

[0098] (15)Reference Figure 7o , Figure 7o This is another structural diagram of a chip during fabrication in an embodiment of the present application. For example, an ohmic contact layer and a metal layer are sequentially formed on the side of each vertical channel 380 facing away from the substrate 310 to form the second electrode in the second electrode layer 360 .

[0099] (16)Reference Figure 7p , Figure 7p FIG. 3 is another structural diagram of a chip in an embodiment of the present application during fabrication. For example, a portion of the second lower dielectric layer 3511b facing away from the substrate 310 is etched to form a second groove AX2.

[0100] (17)Reference Figure 7q , Figure 7q This is another schematic diagram of the structure of a chip during fabrication in an embodiment of the present application. For example, a fourth dielectric layer 352 is deposited using a dielectric material. The fourth dielectric layer 352 covers the second electrode layer 360, the surface of the second lower dielectric layer 3511b facing away from the substrate 310, and the surface of the upper dielectric layer 3512 facing away from the substrate 310. The fourth dielectric layer 352 also seals the open ends of the second grooves AX2, forming second gas gaps 372.

[0101] Based on this, the chip in the embodiment of the present application can achieve a uniform and mechanically stable first gas gap 371 and second gas gap 372 based on process steps with high degrees of freedom, thereby improving the process integration and reliability of the first gas gap 371 and second gas gap 372.

[0102] Figure 8 This is another structural diagram of the chip in the embodiment of the present application, referring to Figure 8 The chip in this embodiment is a modification of the chip in the above embodiment. The similarities are not described here. The difference lies in that a first gas gap 371 is provided only in the first insulating dielectric layer 330. This first gas gap 371 effectively reduces the parasitic capacitance between the gate conductive layer 341 and the first electrode layer 320. The remaining implementations of the first gas gap 371 can refer to the above embodiment and are not described here in detail.

[0103] Continue to refer to Figure 8 The second insulating dielectric layer 350 includes a third dielectric layer 351 and a fourth dielectric layer 352. The third dielectric layer 351 is disposed between the fourth dielectric layer 352 and the substrate 310. The third dielectric layer 351 covers the gate structure 340 and the sidewalls of the third region A3 of each vertical channel 380. The fourth dielectric layer 352 covers the second electrode layer 360 and the third dielectric layer 351.

[0104] in addition, Figure 8 The method for preparing the structure of the chip shown can be a modification of the method in the above embodiment, the difference being that after step (10), the following process is performed:

[0105] (21)Reference Figure 9a , Figure 9a Schematic diagram of another structure of a chip during fabrication in an embodiment of the present application. Exemplarily, a dielectric material is used to deposit a third dielectric layer 351 to fill and cover the gate structure 340 , each vertical channel 380 , and the hard mask 410 .

[0106] (22)Reference Figure 9b , Figure 9b Schematic diagram of another structure of the chip during the manufacturing process in the embodiment of the present application. Exemplarily, the third dielectric layer 351 and the hard mask 410 are planarized using a CMP process to expose the vertical channels 380.

[0107] (23)Reference Figure 9c , Figure 9c This is another structural diagram of a chip during fabrication in an embodiment of the present application. For example, an ohmic contact layer and a metal layer are sequentially formed on the side of each vertical channel 380 facing away from the substrate 310 to form the second electrode in the second electrode layer 360 .

[0108] (24)Reference Figure 9d , Figure 9d 3. This is another structural diagram of a chip in an embodiment of the present application during fabrication. Exemplarily, a fourth dielectric layer 352 is deposited using a dielectric material, and the fourth dielectric layer 352 covers the second electrode layer 360 and the third dielectric layer 351.

[0109] Figure 10 This is another structural diagram of the chip in the embodiment of the present application, referring to Figure 10The chip in this embodiment is a modification of the chip in the above embodiment. The similarities are not described here. The difference is that a second gas gap 372 is only provided in the second insulating dielectric layer 350. The second gas gap 372 can effectively reduce the parasitic capacitance between the gate conductive layer 341 and the second electrode layer 360. In addition, the remaining implementations of the second gas gap 372 can refer to the above embodiment and are not described in detail here. In addition, the first insulating dielectric layer 330 can be a single-layer structure (i.e., only including the first dielectric layer 331) or a multi-layer structure (i.e., including multiple first dielectric layers 331 stacked), which is not limited here.

[0110] in addition, Figure 10 The method for preparing the structure of the chip shown can be a variation of the method in the above embodiment, the difference being that after executing step (2), steps (10) to (17) are executed.

[0111] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. A chip, characterized in that: include: substrate; A first electrode layer is provided on the substrate; a plurality of vertical channels spaced apart on a side of the first electrode layer facing away from the substrate, the vertical channels comprising a first region, a second region disposed on a side of the first region facing the substrate, and a third region disposed on a side of the first region facing away from the substrate, the second region being electrically connected to the first electrode layer; a first insulating dielectric layer, disposed on a side of the first electrode layer facing away from the substrate and covering sidewalls of the second region of each of the vertical channels; a gate structure, disposed on a side of the first insulating dielectric layer facing away from the substrate and covering at least a portion of a sidewall of the first region of each of the vertical channels; a second electrode layer, disposed on a side of each vertical channel facing away from the substrate and electrically connected to the third region of each vertical channel; a second insulating dielectric layer, disposed on a side of the gate structure facing away from the substrate and covering the gate structure, the second electrode layer, and sidewalls of the third region of each vertical channel; The first insulating dielectric layer has a first gas gap, and at least a portion of the area between the first gas gap and each of the vertical channels and the gate structure has a dielectric material.

2. The chip according to claim 1, wherein: The gate structure includes a gate conductive layer and a gate dielectric layer arranged between the gate conductive layer and the sidewall of the first region, and the orthographic projection of the first gas gap on the substrate has no or partial overlapping area with the orthographic projection of the gate conductive layer on the substrate.

3. The chip according to claim 2, wherein: Adjacent vertical channels share the same first gas gap, and an orthographic projection of the first gas gap on the substrate falls between orthographic projections of the gate conductive layers corresponding to the first regions of the adjacent vertical channels on the substrate.

4. The chip according to claim 2 or 3, characterized in that The gate conductive layer is provided on both sides of the vertical channel, and the first gas gap is provided on both sides of the vertical channel; Alternatively, the gate conductive layer surrounds the vertical channel, and the first gas gap surrounds the vertical channel.

5. The chip according to any one of claims 1 to 4, characterized in that: The first insulating dielectric layer includes a first dielectric layer and a second dielectric layer stacked together; The first dielectric layer has a first groove, and dielectric material is provided between the first groove and the vertical channel; The second dielectric layer covers the surface of the first dielectric layer facing away from the substrate and closes the open end of the first groove to form the first gas gap in the first groove.

6. The chip according to claim 5, wherein: The second dielectric layer further covers the bottom wall and side walls of the first groove, so that the first gas gap is enclosed in the first groove by the second dielectric layer.

7. The chip according to any one of claims 1 to 6, wherein: The second insulating dielectric layer has a second gas gap, which is arranged between the layer where the gate structure is located and the layer where the second electrode layer is located, and a dielectric material is present between the second gas gap and the vertical channel and the gate structure.

8. A chip, characterized in that: include: substrate; A first electrode layer is provided on the substrate; a plurality of vertical channels spaced apart on a side of the first electrode layer facing away from the substrate, the vertical channels comprising a first region, a second region disposed on a side of the first region facing the substrate, and a third region disposed on a side of the first region facing away from the substrate, the second region being electrically connected to the first electrode layer; a first insulating dielectric layer, disposed on a side of the first electrode layer facing away from the substrate and covering sidewalls of the second region of each of the vertical channels; a gate structure disposed on a side of the first insulating dielectric layer facing away from the substrate and covering at least a portion of the sidewalls of the first region of each of the vertical channels; wherein the gate structure comprises a gate conductive layer and a gate dielectric layer disposed between the gate conductive layer and the sidewalls of the first region; a second electrode layer, disposed on a side of each vertical channel facing away from the substrate and electrically connected to the third region of each vertical channel; a second insulating dielectric layer, disposed on a side of the gate structure facing away from the substrate, and covering the gate structure, the second electrode layer, and a sidewall of the third region; The second insulating dielectric layer has a second gas gap, which is arranged between the layer where the gate structure is located and the layer where the second electrode layer is located, and at least part of the area between the second gas gap and each of the vertical channels and the gate structure has a dielectric material.

9. The chip according to claim 7 or 8, characterized in that The gate structure includes a gate conductive layer and a gate dielectric layer disposed between the gate conductive layer and the sidewall of the first region. The orthographic projection of the second gas gap on the substrate overlaps with the orthographic projection of the gate conductive layer on the substrate.

10. The chip according to claim 9, wherein: The gate conductive layer is provided on both sides of the vertical channel, and the second gas gap is provided on both sides of the vertical channel; Alternatively, the gate conductive layer surrounds the vertical channel, and the second gas gap surrounds the vertical channel.

11. The chip according to any one of claims 7 to 10, characterized in that: The second insulating dielectric layer includes: a third dielectric layer and a fourth dielectric layer, wherein the third dielectric layer is arranged between the fourth dielectric layer and the substrate; The third dielectric layer covers the gate structure and the sidewalls of the third region of each vertical channel, the third dielectric layer has a second groove, and a dielectric material is disposed between the second groove and the vertical channel; The fourth dielectric layer covers the second electrode layer and the third dielectric layer, and the fourth dielectric layer seals the open end of the second groove to form the second gas gap in the second groove.

12. The chip according to claim 11, wherein: The third dielectric layer includes: an upper dielectric layer and a plurality of lower dielectric layers stacked in layers, wherein the plurality of lower dielectric layers cover the gate structure and the sidewalls of the third region of each vertical channel, and the upper dielectric layer covers the plurality of lower dielectric layers; The plurality of lower dielectric layers include: a first lower dielectric layer and at least one second lower dielectric layer; The first lower dielectric layer is disposed between the at least one second lower dielectric layer and the gate structure, and the first lower dielectric layer contacts a sidewall of the third region, and an upper surface of the first lower dielectric layer facing away from the substrate is aligned with an upper surface of the third region facing away from the substrate; An upper surface of at least one of the at least one second lower dielectric layers facing away from the substrate is arranged between an upper surface of the third region facing away from the substrate and an upper surface of the gate conductive layer facing away from the substrate to form the second groove.

13. The chip according to claim 12, wherein: The multiple lower dielectric layers are made of different materials.

14. The chip according to claim 12 or 13, characterized in that: The upper dielectric layer and the plurality of lower dielectric layers are made of different materials.

15. An electronic device, characterized in that: include: A circuit board and a chip as described in any one of claims 1 to 14, wherein the chip is arranged on the circuit board.

16. A method for preparing a chip, characterized in that: include: A first electrode layer, a plurality of vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer, and a second insulating dielectric layer are formed on a substrate; wherein the plurality of vertical channels are spaced apart on a side of the first electrode layer facing away from the substrate, the vertical channels include a first region, a second region provided on a side of the first region facing the substrate, and a third region provided on a side of the first region facing away from the substrate, the second region being electrically connected to the first electrode layer; the first insulating dielectric layer is provided on a side of the first electrode layer facing away from the substrate and covers the sidewalls of the second region of each of the vertical structures; the gate structure is provided on a side of the first insulating dielectric layer facing away from the substrate and covers at least a portion of the sidewalls of the first region of each of the vertical structures; the second electrode layer is provided on a side of the vertical channels facing away from the substrate and is electrically connected to the third region of each of the vertical structures; the second insulating dielectric layer is provided on a side of the gate structure facing away from the substrate and covers the gate structure, the second electrode layer, and the sidewalls of the third region of each of the vertical structures; wherein the first insulating dielectric layer has a first gas gap, and the first gas gap and at least a portion of the area between the vertical channels and the gate structure comprise a dielectric material.

17. The preparation method according to claim 16, wherein Also includes: A second gas gap is formed in the second insulating dielectric layer, the second gas gap is arranged between the layer where the gate structure is located and the layer where the second electrode layer is located, and at least a portion of the area between the second gas gap and the vertical channel and the gate structure has a dielectric material.

18. A method for preparing a chip, characterized in that: include: A first electrode layer, a plurality of vertical channels, a first insulating dielectric layer, a gate structure, a second electrode layer and a second insulating dielectric layer are formed on a substrate; wherein the plurality of vertical channels are spaced apart on the side of the first electrode layer facing away from the substrate, the vertical channels include a first region, a second region arranged on the side of the first region facing the substrate, and a third region arranged on the side of the first region facing away from the substrate, the second region is electrically connected to the first electrode layer; the first insulating dielectric layer is arranged on the side of the first electrode layer facing away from the substrate and covers the sidewalls of the second region of each of the vertical structures; the gate structure is arranged on the side of the first insulating dielectric layer facing away from the substrate , and covers at least a portion of the side walls of the first region of each of the vertical structures; a second electrode layer is arranged on the side of the vertical channel facing away from the substrate and is electrically connected to the third region of each of the vertical structures; a second insulating dielectric layer is arranged on the side of the gate structure facing away from the substrate, and covers the gate structure, the second electrode layer and the side walls of the third region of each of the vertical structures; wherein the second insulating dielectric layer has a second gas gap, the second gas gap is arranged between the layer where the gate structure is located and the layer where the second electrode layer is located, and at least a portion of the area between the second gas gap and the vertical channel and the gate structure has a dielectric material.

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