Semiconductor terminal structure, manufacturing method thereof and power device with semiconductor terminal structure

Abstract

The invention relates to a semiconductor terminal structure, a manufacturing method thereof and a power device with the semiconductor terminal structure. A semiconductor termination structure includes: a substrate of a first conductivity type; the epitaxial layer and the substrate are sequentially arranged in a first direction, at least one first doped region and at least one second doped region are arranged in the epitaxial layer, the second doped region and the first doped region are sequentially arranged in the first direction, and an interface is arranged between the first doped region and the second doped region; each of the first doped region and the second doped region comprises a plurality of injection regions of a second conduction type which are separated from one another, and the projection of the injection regions in the first doped region on the interface intersects with the projection of the plurality of injection regions in the second doped region on the interface. According to the semiconductor terminal structure provided by the invention, more sufficient exhaustion is realized, charge balance is easier to realize, and the withstand voltage is higher and more stable.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor terminal structure, a manufacturing method thereof, and a power device having the same. Background Art

[0002] Semiconductor devices, particularly those with superjunction structures, offer high withstand voltage capabilities and low specific on-resistance. To ensure consistent process flow across the entire semiconductor device, the terminal structure of these devices employs an alternating PN column arrangement similar to a cellular structure. However, this alternating PN column arrangement results in low device tolerances and makes the PN columns susceptible to breakdown at low voltages due to charge imbalance. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor terminal structure that achieves more sufficient depletion, can more easily achieve charge balance, and has a higher and more stable withstand voltage.

[0004] Another object of the present invention is to provide a power device comprising the semiconductor terminal structure.

[0005] Another object of the present invention is to provide a method for manufacturing the semiconductor terminal structure.

[0006] According to an embodiment of the first aspect of the present invention, a semiconductor terminal structure includes: a substrate, which is of a first conductive type; and an epitaxial layer, wherein the epitaxial layer and the substrate are arranged in sequence in a first direction, at least one first doping region and at least one second doping region are provided in the epitaxial layer, the second doping region and the first doping region are arranged in sequence along the first direction, an interface is provided between the first doping region and the second doping region, the first doping region and the second doping region both include a plurality of injection regions of the second conductive type spaced apart from each other, and the projections of the plurality of injection regions in the first doping region on the interface intersect with the projections of the plurality of injection regions in the second doping region on the interface.

[0007] According to the semiconductor terminal structure of an embodiment of the present invention, at least one first doping region and at least one second doping region are provided in the epitaxial layer, the second doping region and the first doping region are arranged in sequence along the first direction, an interface is provided between the first doping region and the second doping region, the first doping region and the second doping region both include a plurality of injection regions of the second conductive type spaced apart from each other, the projections of the plurality of injection regions in the first doping region on the interface intersect with the projections of the plurality of injection regions in the second doping region on the interface, and the entire semiconductor terminal structure can realize that the doping ions in the second column can be diffused in at least two directions and the doping ions in the first column can be diffused in at least two directions, thereby realizing depletion in at least two different directions, making the depletion more sufficient, and easily realizing charge balance in the semiconductor terminal structure, especially in the first column and the second column, a flatter electric field distribution curve, and achieving higher voltage resistance and more stable voltage resistance.

[0008] According to some embodiments of the present invention, at least one of the implanted regions in the first doping region contacts at least one of the implanted regions in the second doping region at the interface.

[0009] According to some embodiments of the present invention, each of the implanted regions in the first doping region and each of the implanted regions in the second doping region do not contact each other at the interface.

[0010] According to some embodiments of the present invention, adjacent injection regions in the plurality of injection regions in the first doping region are spaced apart by the same distance; and / or adjacent injection regions in the plurality of injection regions in the second doping region are spaced apart by the same distance.

[0011] According to some embodiments of the present invention, adjacent injection regions in the plurality of injection regions in the first doping region are spaced apart by different distances; and / or adjacent injection regions in the plurality of injection regions in the second doping region are spaced apart by different distances.

[0012] According to some embodiments of the present invention, adjacent injection regions among the multiple injection regions in the first doping region are spaced apart by the same distance; and / or adjacent injection regions among the multiple injection regions in the second doping region are spaced apart by different distances, wherein, in the direction from the circumferential inner edge of the semiconductor terminal structure toward the circumferential outer edge of the semiconductor terminal structure, the distance between adjacent injection regions among the multiple injection regions in the second doping region first gradually decreases and then gradually increases.

[0013] According to some embodiments of the present invention, the multiple injection regions in the first doping region are spaced apart from each other along a second direction perpendicular to the first direction, and the multiple injection regions in the first doping region have different widths in the second direction; and / or the multiple injection regions in the second doping region are spaced apart from each other along a third direction perpendicular to the first direction, and the multiple injection regions in the second doping region have different widths in the third direction, and the third direction is different from the second direction.

[0014] According to some embodiments of the present invention, the multiple injection regions in the first doping region are spaced apart from each other along a second direction perpendicular to the first direction, and the multiple injection regions in the first doping region have the same width in the second direction; and / or the multiple injection regions in the second doping region are spaced apart from each other along a third direction perpendicular to the first direction, and the multiple injection regions in the second doping region have the same width in the third direction, which is different from the second direction.

[0015] According to some embodiments of the present invention, the epitaxial layer is provided with only one first doping region and one second doping region, and the second doping region extends from a surface of the epitaxial layer away from the substrate in the first direction to an interior of the epitaxial layer.

[0016] According to some embodiments of the present invention, a plurality of first doping regions and a plurality of second doping regions are provided in the epitaxial layer, the plurality of second doping regions and the plurality of first doping regions are alternately arranged in the first direction, and the interface is provided between adjacent first doping regions and second doping regions.

[0017] According to some embodiments of the present invention, a plurality of the first doping regions and a plurality of the second doping regions are provided in the epitaxial layer, and at least one first doping region is adjacent to at least one second doping region in the first direction.

[0018] According to some embodiments of the present invention, at least two first doping regions are adjacently arranged in the first direction.

[0019] According to some embodiments of the present invention, at least two of the second doping regions are adjacently arranged in the first direction.

[0020] According to some embodiments of the present invention, the multiple injection regions in each first doping region are spaced apart from each other along a second direction, wherein the second direction is perpendicular to the first direction, and the projections of the injection regions in at least two first doping regions on the interface at least partially overlap.

[0021] According to some embodiments of the present invention, the multiple injection regions in each of the second doping regions are spaced apart from each other along a third direction, wherein the third direction is perpendicular to the first direction and different from the second direction, and the projections of the injection regions in at least two second doping regions on the interface at least partially overlap.

[0022] According to some embodiments of the present invention, the multiple injection regions in each first doping region are spaced apart from each other along a second direction, wherein the second direction is perpendicular to the first direction, and projections of the injection regions in at least two first doping regions on the interface do not overlap.

[0023] According to some embodiments of the present invention, the multiple injection regions in each of the second doping regions are spaced apart from each other along a third direction, wherein the third direction is perpendicular to the first direction and different from the second direction, and the projections of the injection regions in at least two second doping regions on the interface do not overlap.

[0024] According to some embodiments of the present invention, the multiple injection regions in the first doping region are spaced apart from each other along a second direction perpendicular to the first direction, the multiple injection regions in the first doping region have the same depth in the first direction, and the multiple injection regions in the first doping region have the same width in the second direction; and / or the multiple injection regions in the second doping region are spaced apart from each other along a third direction perpendicular to the first direction, the multiple injection regions in the second doping region have the same depth in the first direction, and the multiple injection regions in the second doping region have the same width in the third direction, and the third direction is different from the second direction.

[0025] According to some embodiments of the present invention, the doping concentration of the injection region is different among the multiple first doping regions; and / or the doping concentration of the injection region is different among the multiple second doping regions; and / or the doping concentration of the injection region is different between the first doping region and the second doping region.

[0026] According to some embodiments of the present invention, the doping concentration of the injection region is the same among the multiple first doping regions; and / or the doping concentration of the injection region is the same among the multiple second doping regions; and / or the doping concentration of the injection region is the same between the first doping region and the second doping region.

[0027] According to some embodiments of the present invention, one of the plurality of second doped regions extends from a surface of the epitaxial layer away from the substrate in the first direction to an interior of the epitaxial layer.

[0028] According to some embodiments of the present invention, the first doping region includes a plurality of first sub-regions of a first doping type, and each adjacent two of the plurality of injection regions in the first doping region are separated by one of the first sub-regions; and / or the second doping region includes a plurality of second sub-regions of a first doping type, and each adjacent two of the plurality of injection regions in the second doping region are separated by one of the second sub-regions. An interface between each of the injection regions in each of the first doping regions and each of the first sub-regions adjacent thereto forms a curved surface convex toward the adjacent first sub-region; and / or an interface between each of the injection regions in each of the second doping regions and each of the second sub-regions adjacent thereto forms a curved surface convex toward the adjacent second sub-region.

[0029] According to some embodiments of the present invention, the semiconductor terminal structure includes multiple straight sections and at least one curved section, each of the curved sections is connected between two of the straight sections, and the at least one first doped region and the at least one second doped region are located in at least one of the curved sections.

[0030] According to some embodiments of the present invention, in the curved section, the implantation region in the second doping region extends along a path consistent with a curved path of the curved section.

[0031] According to some embodiments of the present invention, the at least one first doping region and the at least one second doping region are located in the one curved segment and at least one straight segment connected to the one curved segment.

[0032] According to some embodiments of the present invention, the multiple straight sections include two first straight sections opposite to each other and arranged parallel to a second direction and two second straight sections opposite to each other and arranged parallel to a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the number of the curved sections is four, and the four curved sections are respectively connected between adjacent first straight sections and second straight sections.

[0033] According to some embodiments of the present invention, the at least one first doped region and the at least one second doped region are located in at least one of the curved sections and one of the first straight sections, and the first straight section is connected to the one curved section. In the one curved section and the one first straight section, the implanted regions of the first doped regions extend in the epitaxial layer in a direction parallel to the third direction and are spaced apart along the second direction; in the one curved section, the implanted regions of the second doped regions extend along a curved path of the curved section; and in the one first straight section, the implanted regions of the second doped regions extend in a direction parallel to the second direction.

[0034] According to some embodiments of the present invention, the at least one first doping region and the at least one second doping region are also located in a second straight section connected to the one curved section, the multiple injection regions in the first doping region extend in a direction parallel to the second direction in the second straight section, and the multiple injection regions in the second doping region extend in a direction parallel to the third direction in the second straight section.

[0035] According to some embodiments of the present invention, the at least one second doped region is also located in a second straight section connected to the one curved section, and in the one curved section of the semiconductor terminal structure, the first straight section connected to the one curved section, and the second straight section, the surface of the epitaxial layer in the first direction away from the substrate is continuously doped with ions of the second conductive type in a region extending from the circumferential inner edge of the semiconductor terminal structure to the inner side of the circumferential outer edge of the semiconductor terminal structure.

[0036] According to some embodiments of the present invention, the range of the region is adjustable.

[0037] According to some embodiments of the present invention, the region is continuous on the surface of the epitaxial layer.

[0038] According to some embodiments of the present invention, the region comprises a plurality of spaced-apart sub-regions, and at least two of the plurality of sub-regions have different areas on the surface of the epitaxial layer.

[0039] According to some embodiments of the present invention, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0040] According to an embodiment of the second aspect of the present invention, a power device includes: a cellular structure; and a semiconductor terminal structure according to any embodiment of the first aspect of the present invention, wherein the semiconductor terminal structure is located at the circumferential periphery of the cellular structure.

[0041] According to some embodiments of the present invention, the power device is a MOSFET.

[0042] According to an embodiment of the third aspect of the present invention, a method for manufacturing a semiconductor terminal structure according to any embodiment of the first aspect of the present invention includes the following steps: S1, forming a first epitaxial layer of a first conductive type on a substrate of a first conductive type, the epitaxial layer having a first doped region; S2, forming the multiple injection regions of the second conductive type in the first doped region in the first epitaxial layer; S3, forming a second epitaxial layer of the first conductive type on the first epitaxial layer, the second epitaxial layer having a second doped region; S4, forming multiple injection regions of the second conductive type in the second doped region in the second epitaxial layer, wherein the epitaxial layer includes the first epitaxial layer and the second epitaxial layer; and S5, processing the formed structure so that there is an interface between the first doped region and the second doped region, and the projections of the multiple injection regions in the first doped region on the interface intersect with the projections of the multiple injection regions in the second doped region on the interface.

[0043] According to some embodiments of the present invention, the processing the formed structure includes: performing a heat drive-in process on the formed structure.

[0044] According to some embodiments of the present invention, after step S4 and before step S5, the method further comprises: repeating steps S1 to S4 at least once.

[0045] According to some embodiments of the present invention, step S1 includes: providing a substrate of the first conductivity type; and growing a first epitaxial layer on the substrate and implanting ions of the first conductivity type into the first epitaxial layer to form the first doped region.

[0046] According to some embodiments of the present invention, step S2 includes: determining the positions and shapes of multiple second conductivity type injection regions in the first epitaxial layer, and injecting second conductivity type ions at the positions to form the multiple second conductivity type injection regions in the first doped region.

[0047] According to some embodiments of the present invention, step S3 includes: growing a second epitaxial layer on the first epitaxial layer and implanting ions of the first conductivity type into the second epitaxial layer to form the second doped region.

[0048] According to some embodiments of the present invention, step S4 includes: determining the positions and shapes of multiple second conductivity type injection regions in the second epitaxial layer, and injecting second conductivity type ions at the positions to form the multiple second conductivity type injection regions in the second doped region.

[0049] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0051] Figure 1 FIG. 1 is a partial schematic diagram of a power device according to an embodiment of the present invention, showing a portion of a semiconductor terminal structure and a portion of a cell structure.

[0052] Figure 2 yes Figure 1 FIG. 1 is a schematic partial cross-sectional view of a semiconductor terminal structure according to an embodiment of the present invention, taken along the X-section line and the Y-section line.

[0053] Figure 3 It is along Figure 2 Schematic diagram of the cross section taken along the XY plane.

[0054] Figure 4 yes Figure 1 FIG. 1 is a schematic partial cross-sectional view of a semiconductor terminal structure according to another embodiment of the present invention taken along the X-section line and the Y-section line.

[0055] Figure 5 1 is a partial cross-sectional schematic diagram of a power device according to an embodiment of the present invention, which shows a partial schematic cross-sectional structure of a semiconductor terminal structure and a partial schematic cross-sectional structure of a cell structure.

[0056] Figure 6 is a partial cross-sectional schematic diagram of a power device according to yet another embodiment of the present invention, showing a partial schematic cross-sectional structure of a semiconductor terminal structure and a partial schematic cross-sectional structure of a cell structure.

[0057] Figure 7 FIG. 1 is a partial schematic diagram of a power device according to another embodiment of the present invention, showing a portion of a semiconductor terminal structure and a portion of a cell structure.

[0058] Figure 8 FIG. 1 is a partial schematic diagram of a power device according to yet another embodiment of the present invention, showing a portion of a semiconductor terminal structure and a portion of a cell structure.

[0059] Figure 9 FIG. 4 is a partial schematic diagram of a power device according to yet another embodiment of the present invention, showing a portion of a semiconductor terminal structure and a portion of a cell structure.

[0060] Figure 10 is a schematic flow chart of a method for manufacturing a semiconductor terminal structure according to an embodiment of the present invention.

[0061] Reference numerals:

[0062] Substrate 10; epitaxial layer 20; first doped region 30; second doped region 40; interface S;

[0063] an implantation region 2 of a second conductivity type, a second pillar 2, 2-1, 2-2;

[0064] A first column 1; a surface 6 away from the substrate;

[0065] Straight section 7; first straight section 71; second straight section 72;

[0066] curved section 8; circumferential inner edge 9; circumferential outer edge 12; cellular structure 11; power device 1000;

[0067] Field oxide layer 4; conductive polysilicon 5; well region 6; source region 13; interlayer dielectric 14; front metal 15; back metal 16. DETAILED DESCRIPTION

[0068] Embodiments of the present invention will be described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary.

[0069] The following combination Figures 1 to 10 A semiconductor terminal structure, a power device 1000 including the semiconductor terminal structure, and a method for manufacturing the semiconductor terminal structure according to embodiments of the present invention are described.

[0070] refer to Figures 1-9 According to a first aspect of the present invention, a semiconductor terminal structure is provided. For example, the semiconductor terminal structure is a superjunction terminal structure. The semiconductor terminal structure includes a substrate 10 and an epitaxial layer 20. The substrate 10 is of a first conductivity type.

[0071] like Figure 2-Figure 6 As shown, the epitaxial layer 20 and the substrate 10 are sequentially arranged in the first direction. At least one first doping region 30 and at least one second doping region 40 are provided in the epitaxial layer 20. It is understood that the number of the at least one first doping region 30 and the number of the at least one second doping region 40 can be the same or different. Figure 2-Figure 6 As shown, the second doping region 40 and the first doping region 30 are sequentially arranged along the first direction, and an interface S is formed between the first doping region 30 and the second doping region 40. In other words, the first doping region 30 and the second doping region 40 are continuous in the first direction.

[0072] Each of the first doping region 30 and the second doping region 40 includes a plurality of implanted regions 2 of the second conductivity type spaced apart from one another, and the projections of the plurality of implanted regions 2 in the first doping region 30 on the interface S intersect with the projections of the plurality of implanted regions 2 in the second doping region 40 on the interface S. The term "intersection" herein refers to a region where the projections of the implanted regions 2 in the first doping region 30 on the interface S and the projections of the implanted regions 2 in the second doping region 40 on the interface S only partially overlap. It should be understood that the term "intersection" herein does not include a situation where the projections of the plurality of implanted regions 2 in the first doping region 30 on the interface S and the projections of the plurality of implanted regions 2 in the second doping region 40 on the interface S completely overlap. For example, the implanted regions 2 of the second conductivity type in the first doping region 30 extend along a first extension path parallel to the interface S, and the implanted regions 2 of the second doping region 40 extend along a second extension path parallel to the interface, wherein the first extension path intersects the second extension path, for example, but not limited to, perpendicularly. That is, the first doping region 30 and the second doping region 40 each include a plurality of second conductivity type injection regions 2 spaced apart from each other, and the extension path of each second conductivity type injection region 2 in the second doping region 40 is different from the extension path of each second conductivity type injection region 2 in the first doping region 30. The direction in which the plurality of second conductivity type injection regions 2 in the first doping region 30 are spaced apart is referred to herein as a first spacing direction, and the direction in which the plurality of second conductivity type injection regions 2 in the second doping region 40 are spaced apart is referred to as a second spacing direction. Since the extension path of the second conductivity type injection regions 2 in the first doping region 30 intersects (i.e., is different from) the extension path of the second conductivity type injection regions 2 in the second doping region 40, the first spacing direction and the second spacing direction are necessarily different from each other and are both different from the first direction.

[0073] It should be noted that the number of second conductivity type injection regions 2 in the first doping region 30 and the number of second conductivity type injection regions 2 in the second doping region 40 can be different or the same; the first conductivity type and the second conductivity type are different. Because the multiple second conductivity type injection regions 2 in each of the first doping region 30 and the second doping region 40 are spaced apart from each other, the region between two adjacent second conductivity type injection regions 2 in each of the first doping region 30 and the second doping region 40 is the first conductivity type region of the epitaxial layer 20. For the sake of distinction, the region between two adjacent second conductivity type injection regions 2 in each of the first doping region 30 and the second doping region 40 of the epitaxial layer 20 is referred to as a first pillar, and the second conductivity type injection region 2 is referred to as a second pillar.

[0074] Through the above structure, the dopant ions in the second column in the first doping region 30 can diffuse at least in the first spacing direction toward the first column adjacent to the second column in the first doping region 30, and can diffuse in the first direction toward the region adjacent to the second column in the epitaxial layer 20 that is not doped with the second conductive type ions. Similarly, the dopant ions in the second column in the second doping region 40 can diffuse in the second spacing direction toward the first column adjacent to the second column in the second doping region 40, and can diffuse in the first direction toward the region adjacent to the second column in the epitaxial layer 20 that is not doped with the second conductive type ions. Therefore, the dopant ions in the second column can be diffused in at least two different directions in the entire semiconductor terminal structure, thereby achieving depletion in at least two different directions, making the depletion more sufficient, facilitating charge balance in the semiconductor terminal structure, and achieving higher voltage resistance and more stable voltage resistance. It can be understood that the diffusion of dopant ions in the first column to the second column is also a similar process.

[0075] According to the semiconductor terminal structure of an embodiment of the present invention, at least one first doping region 30 and at least one second doping region 40 are provided in the epitaxial layer 20, the second doping region 40 and the first doping region 30 are arranged in sequence along the first direction, and an interface S is provided between the first doping region 30 and the second doping region 40, and the first doping region 30 and the second doping region 40 both include a plurality of injection regions 2 of the second conductive type spaced apart from each other, and the projections of the plurality of injection regions 2 in the first doping region 30 on the interface S intersect with the projections of the plurality of injection regions 2 in the second doping region 40 on the interface S, and the entire semiconductor terminal structure can realize that the doping ions in the second column can be diffused in at least two directions and the doping ions in the first column can be diffused in at least two directions, thereby realizing depletion in at least two different directions, making the depletion more sufficient, and easily realizing charge balance in the semiconductor terminal structure, especially in the first column and the second column, a flatter electric field distribution curve, and achieving higher voltage resistance and more stable voltage resistance.

[0076] According to some specific embodiments of the present invention, each second conductivity type injection region 2 in the second doping region 40 does not contact each second conductivity type injection region 2 in the first doping region 30 at the interface S (not shown in the figure). In other words, each second pillar in the second doping region 40 does not contact each second pillar in the first doping region 30. For example, the depth of each second pillar in the second doping region 40 in the first direction is not sufficient to make the second pillar contact with each second pillar in the first doping region 30. At this time, the dopant ions in the second pillar in the first doping region 30 can diffuse toward the first pillar adjacent to the second pillar in the first doping region 30 in the first spacing direction, and can diffuse toward the portion of the epitaxial layer adjacent to the second pillar in the second doping region 40 in the first direction; the dopant ions in the second pillar in the second doping region 40 can diffuse toward the first pillar adjacent to the second pillar in the second doping region 40 in the second spacing direction, and can diffuse toward the portion of the epitaxial layer of the first conductivity type adjacent to the second pillar in the second doping region 40 in the first direction. Therefore, the dopant ions in the second column can diffuse in two different directions throughout the entire semiconductor terminal structure, thereby achieving depletion in two different directions. This makes depletion more complete, facilitates charge balance within the semiconductor terminal structure, and achieves a higher and more stable withstand voltage. It is understood that the diffusion of dopant ions from the first column to the second column is a similar process and will not be further described here.

[0077] According to other specific embodiments of the present invention, Figure 2 and Figure 4 As shown, at least one second conductivity type implantation region 2 in the second doping region 40 contacts at least one second conductivity type implantation region 2 in the first doping region 30 at an interface S. In other words, at least one second conductivity type implantation region 2 in the second doping region 40 contacts at least one second conductivity type implantation region 2 in the first doping region 30. For example, each second conductivity type implantation region 2 in the second doping region 40 contacts each second conductivity type implantation region 2 in the first doping region 30 at an interface S.

[0078] For example, reference Figure 3 , which is along Figure 2 , A represents the first pillar portion, 2-1 represents the second pillar in the first doping region 30, 2-2 represents the second pillar in the second doping region 40, and the arrow direction represents the doping ion diffusion direction occurring at the interface S. Specifically, the following diffusion may occur at and near the interface S: at least one of the above-mentioned (e.g. Figure 3The dopant ions in each of the second columns (shown in FIG. 1 ) can diffuse toward the first column adjacent to the second column in the first spacing direction, can diffuse toward the first column adjacent to the second column in the second spacing direction, and can also diffuse toward the first column adjacent to the second column in the second doping region 40 in the first direction; similarly, at and near the interface S, the at least one (e.g. Figure 3 The dopant ions in each of the second columns shown in FIG. 3 may diffuse toward the first column adjacent to the second column in the second spacing direction, may diffuse toward the first column adjacent to the second column in the first spacing direction, and may diffuse toward the first column adjacent to the second column in the first doping region 30 in the first direction. Figure 2 and Figure 4 , and refer to Figure 3At the interface S between the first doping region 30 and the second doping region 40, a checkerboard pattern is formed in which the second pillars and the first pillars intersect vertically, wherein the portion of the first pillar surrounded by the adjacent second pillar is shown as A. The following example is used to illustrate that the multiple second pillars in the first doping region 30 are spaced apart along the X direction, the multiple second pillars in the second doping region 40 are spaced apart along the Y direction, the first direction is the Z direction, and the X direction (i.e., the first spacing direction), the Y direction (i.e., the second spacing direction), and the Z direction are perpendicular to each other. At and near the interface S, taking location A and the second pillar surrounding location A as an example, the dopant ions in the second pillar in the first doping region 30 can diffuse in the X direction toward the portion of the first pillar adjacent to the second pillar (e.g., location A), in the Y direction toward the portion of the first pillar adjacent to the second pillar (e.g., location A), and in the z direction toward the first pillar adjacent to the second pillar in the second doping region 40. Similarly, the dopant ions in the second pillar in the second doping region 40 can diffuse in the Y direction toward the portion of the first pillar adjacent to the second pillar (e.g., location A), in the X direction toward the portion of the first pillar adjacent to the second pillar (e.g., location A), and in the z direction toward the first pillar adjacent to the second pillar in the first doping region 30. Therefore, in the entire semiconductor terminal structure, the dopant ions in at least one (e.g., each) second pillar can diffuse toward the first pillar in at least three different directions, thereby achieving depletion in at least three different directions. This makes the depletion more complete, facilitates charge balance in the semiconductor terminal structure, and achieves higher and more stable withstand voltage. It is understandable that the diffusion of dopant ions in the first column to the second column is a similar process and will not be described in detail here. In addition, it should be noted that the diffusion of ions in the first column or the second column in the first direction, the first spacing direction (e.g., the X direction), and the second spacing direction (e.g., the Y direction) discussed herein is not limited to the diffusion direction of the ions in the first column or the second column being strictly the same as the first direction, the first spacing direction (e.g., the X direction), and the second spacing direction (e.g., the Y direction), but rather refers to the diffusion direction of the ions in the first column or the second column having a component in the first direction, the first spacing direction (e.g., the X direction), and the second spacing direction (e.g., the Y direction).

[0079] Optionally, adjacent implantation regions 2 in the plurality of implantation regions 2 in the first doping region 30 are spaced at the same distance from each other; and / or adjacent implantation regions 2 in the plurality of implantation regions 2 in the second doping region 40 are spaced at the same distance from each other. In this way, the first pillars and the second pillars of the entire semiconductor terminal structure are regularly arranged, so that the depletion process occurring in the entire semiconductor terminal structure is relatively uniform.

[0080] Of course, the present application is not limited thereto. For example, the distances between adjacent implantation regions 2 in the first doping region 30 may be different; and / or the distances between adjacent implantation regions 2 in the second doping region 40 may be different.

[0081] For another example, adjacent injection regions 2 in the multiple injection regions 2 in the first doping region 30 are spaced apart by the same distance; and / or adjacent injection regions 2 in the multiple injection regions 2 in the second doping region 30 are spaced apart by different distances, wherein, in the direction from the circumferential inner edge of the semiconductor terminal structure toward the circumferential outer edge of the semiconductor terminal structure, the distance between adjacent injection regions in the multiple injection regions in the second doping region first gradually decreases and then gradually increases.

[0082] For another example, the distances between adjacent injection regions 2 in the plurality of injection regions 2 in the first doping region 30 are different; and / or the distances between adjacent injection regions 2 in the plurality of injection regions 2 in the second doping region 40 are the same.

[0083] Optionally, the multiple injection regions 2 in the first doping region 30 are spaced apart from each other along a second direction perpendicular to the first direction, and the multiple injection regions 2 in the first doping region 30 have different widths in the second direction; and / or the multiple injection regions 2 in the second doping region 40 are spaced apart from each other along a third direction perpendicular to the first direction, and the multiple injection regions 2 in the second doping region 40 have different widths in the third direction, which is different from the second direction.

[0084] Or optionally, the multiple injection regions 2 in the first doping region 30 are spaced apart from each other along a second direction perpendicular to the first direction, and the multiple injection regions 2 in the first doping region 30 have the same width in the second direction; and / or the multiple injection regions 2 in the second doping region 40 are spaced apart from each other along a third direction perpendicular to the first direction, and the multiple injection regions 2 in the second doping region 40 have the same width in the third direction, which is different from the second direction.

[0085] According to some optional embodiments of the present invention, reference Figures 1-6 , there is only one first doping region 30 and one second doping region 40 in the epitaxial layer 20, and the second doping region 40 extends from the surface of the epitaxial layer 20 away from the substrate 10 in the first direction to the interior of the epitaxial layer 20. Specifically, the number of the first doping region 30 in the epitaxial layer 20 is 1, and the number of the second doping region 40 in the epitaxial layer 20 is 1, and the second doping region 40 is farther away from the substrate 10 than the first doping region 30. The second doping region 40 extends from the surface of the epitaxial layer 20 away from the substrate 10 (the upper surface of the substrate 10 as seen in the figure) to the interior of the epitaxial layer 20. Specifically, combined with Figure 2 , Figure 3Schematic diagram of the interface between the first doping region 30 and the second doping region 40 of the semiconductor terminal structure. As described above, A represents the first pillar, 2-1 represents the second pillar in the first doping region 30, and 2-2 represents the second pillar in the second doping region 40. The direction of the arrow indicates the direction of dopant ion diffusion between the second pillar in the first doping region 30 and the second pillar in the second doping region 40 at the interface S, which can achieve depletion in the X and Y directions. Figure 2 The second doping region 40 is located at the top layer of the epitaxial layer 20, and the first doping region 30 is located below the second doping region 40. Therefore, at and near the interface S, the dopant ions in the second column in the first doping region 30 can diffuse in the X direction toward the first column portion adjacent to the second column (for example, A), can diffuse in the Y direction toward the first column portion adjacent to the second column (for example, A), and can diffuse in the z direction toward the first column adjacent to the second column in the second doping region 40; similarly, the dopant ions in the second column in the second doping region 40 can diffuse in the Y direction toward the first column portion adjacent to the second column (for example, A), can diffuse in the X direction toward the first column portion adjacent to the second column (for example, A), and can diffuse in the z direction toward the first column adjacent to the second column in the first doping region 30. It can be understood that the diffusion of dopant ions in the first column to the second column is also a similar process, which will not be described in detail here. With this arrangement, the impurity concentration distribution in the surface area of ​​the epitaxial layer 20, that is, the surface area of ​​the semiconductor terminal structure, is relatively uniform, which can further avoid the problem of easy breakdown of the surface of the semiconductor terminal structure.

[0086] According to some other optional embodiments of the present invention (not shown in the figures), a plurality of first doping regions 30 and a plurality of second doping regions 40 are provided in the epitaxial layer 20, and at least one first doping region 30 and at least one second doping region 40 are adjacently arranged in the first direction (i.e., having an interface S). It can be seen that the at least one first doping region 30 and the at least one second doping region 40 achieve their projections on the interface S intersecting with each other.

[0087] Optionally, at least two first doping regions 30 are adjacently arranged in the first direction.

[0088] Optionally, at least two second doping regions 40 are adjacently arranged in the first direction.

[0089] For example, in the layout structure of multiple first doping regions 30 and multiple second doping regions 40, there are both first doping regions 30 and second doping regions 40 adjacent to each other in the first direction, and there are also two first doping regions 30 adjacent to each other in the first direction and / or two second doping regions 40 adjacent to each other in the first direction.

[0090] According to some further optional embodiments of the present invention, Figure 4 Combined with Figure 1 , a plurality of first doping regions 30 and a plurality of second doping regions 40 are provided in the epitaxial layer 20, the plurality of first doping regions 30 and the plurality of second doping regions 40 are alternately arranged in the first direction, and an interface S is formed between adjacent first doping regions 30 and second doping regions 40. Figure 4 Shown and referenced Figure 5 and Figure 6 Along the stacking direction from the epitaxial layer 20 to the substrate 10, the epitaxial layer 20 may sequentially include a second doping region 40, a first doping region 30, a second doping region 40, a first doping region 30, and so on. With this arrangement, the implanted regions 2 in adjacent first doping regions 30 and second doping regions 40 contact at the interface S, meaning that the implanted regions 2 in adjacent first doping regions 30 and second doping regions 40 form a continuous and cross-arranged structure. This arrangement allows for more complete depletion of the semiconductor terminal structure throughout the body region, resulting in more stable withstand voltage performance.

[0091] Alternatively, as Figure 4 As shown, the multiple injection regions 2 in each first doping region 30 are spaced apart from each other along the second direction, wherein the second direction is perpendicular to the first direction, and the projections of the injection regions 2 in at least two first doping regions 30 on the interface S at least partially overlap (i.e., partially overlap or completely overlap).

[0092] Alternatively, as Figure 4 As shown, the multiple injection regions 2 in each second doping region 40 are spaced apart from each other along a third direction, wherein the third direction is perpendicular to the first direction and different from the second direction, and the projections of the injection regions in at least two second doping regions 40 on the interface S overlap (i.e., partially overlap or completely overlap).

[0093] Optionally, not shown in the figure, the multiple injection regions 2 in each first doping region 30 are spaced apart from each other along the second direction, wherein the second direction is perpendicular to the first direction, and the projections of the injection regions in at least two first doping regions 30 on the interface S do not overlap.

[0094] Optionally, not shown in the figure, the multiple injection regions 2 in each second doping region 40 are spaced apart from each other along a third direction, the third direction is perpendicular to the first direction and different from the second direction, and the projections of the injection regions in at least two second doping regions 40 on the interface S do not overlap.

[0095] Alternatively, as Figure 4 As shown, the structures of the plurality of first doping regions 30 are identical to each other, and the structures of the plurality of second doping regions 40 are identical to each other. This arrangement can improve the doping uniformity of the entire semiconductor terminal structure.

[0096] Alternatively, as Figure 4As shown, the multiple implantation regions 2 in the first doping region 30 are spaced apart from each other along a second direction perpendicular to the first direction, the multiple implantation regions 2 in the first doping region 30 have the same depth in the first direction, and the multiple implantation regions 2 in the first doping region 30 have the same width in the second direction; and / or the multiple implantation regions 2 in the second doping region 40 are spaced apart from each other along a third direction perpendicular to the first direction, the multiple implantation regions 2 in the second doping region 40 have the same depth in the first direction, and the multiple implantation regions 2 in the second doping region 40 have the same width in a third direction that is different from the second direction. For example, the third direction is perpendicular to the second direction.

[0097] Optionally, the doping concentration of the implanted region 2 is different among the plurality of first doping regions 30; and / or the doping concentration of the implanted region 2 is different among the plurality of second doping regions 40; and / or the doping concentration of the implanted region 2 is different between the first doping region 30 and the second doping region 40. In other words, in the first direction, the doping concentration of the implanted region 2 is different in the first doping regions 30 of different layers, and / or the doping concentration of the implanted region 2 is different in the second doping regions 40 of different layers, and / or the doping concentration of the implanted region 2 is different in the first doping region 30 and the second doping region 40.

[0098] Of course, the present application is not limited thereto. The doping concentration of the implanted region 2 in each first doping region 30 and each second doping region 40 may also be the same. For example, the doping concentration of the implanted region 2 may be the same across multiple first doping regions 30; and / or the doping concentration of the implanted region 2 may be the same across multiple second doping regions 40; and / or the doping concentration of the implanted region 2 may be the same across the first doping region 30 and the second doping region 40.

[0099] Alternatively, as Figure 4 As shown, one of the plurality of second doped regions 40 extends from a surface 6 of the epitaxial layer 20, distal from the substrate 10, in the first direction, into the interior of the epitaxial layer 20. Specifically, along the first direction and from the surface 6 of the semiconductor terminal structure, distal from the substrate 10, the semiconductor terminal structure includes, in sequence, the second doped region 40, the first doped region 30, the second doped region 40, the first doped region 30, and so on. This arrangement results in a relatively uniform impurity concentration distribution in the surface region of the semiconductor terminal structure, further preventing the problem of easy breakdown of the surface of the semiconductor terminal structure and improving the breakdown voltage of the near-surface region of the semiconductor terminal structure.

[0100] refer to Figure 2-Figure 4 The interface between the first pillar and the second pillar in the first doping region 30 may be a plane, and the interface between the first pillar and the second pillar in the second doping region 40 may be a plane.

[0101] However, the present application is not limited thereto. For example, the first doping region 30 includes a plurality of first sub-regions of the first doping type, and each adjacent two injection regions 2 of the plurality of injection regions 2 in the first doping region are separated by a first sub-region; and / or the second doping region 40 includes a plurality of second sub-regions of the first doping type, and each adjacent two injection regions 2 of the plurality of injection regions 2 in the second doping region are separated by a second sub-region. Obviously, the first sub-region and the second sub-region are respectively the first pillar in the first doping region 30 and the second pillar in the second doping region 40 mentioned above. The interface between each injection region 2 in each first doping region 30 and each first sub-region adjacent thereto forms a curved surface convex toward the direction of the adjacent first sub-region (not shown in the figure); and / or the interface between each injection region in each second doping region 40 and each second sub-region adjacent thereto forms a curved surface convex toward the direction of the adjacent second sub-region (not shown in the figure).

[0102] According to some optional embodiments of the present invention, reference Figures 1-9 , the semiconductor terminal structure includes a plurality of straight sections 7 and at least one curved section 8. Specifically, the circumferential outer surface of the straight section 7 of the semiconductor terminal structure is a flat surface, and the circumferential outer surface of the curved section 8 of the semiconductor terminal structure is a curved surface. For example, the circumferential outer surface of the curved section 8 is a smooth surface, but is not limited to this. Furthermore, the circumferential outer surface of the curved section 8 is an arc-shaped surface. The curved section 8 can be called a corner section of the semiconductor terminal structure. Each curved section 8 is connected between two straight sections 7, and at least one first doping region 30 and at least one second doping region 40 are located in at least one curved section 8. It can be seen that the above-mentioned first doping region 30 and second doping region 40 are present in at least one curved section 8. In the prior art, due to the curvature of the corner section, the impurity concentration distribution of the first conductive type ions and the second conductive type ions in the corner section is extremely uneven. By setting intersecting first columns and intersecting second columns in the corner section, the impurity distribution uniformity of the corner section of the semiconductor terminal structure can be improved, thereby further improving the voltage resistance and voltage resistance stability of the entire semiconductor terminal structure, and further avoiding the problem of breakdown of the semiconductor terminal structure at a lower voltage.

[0103] Optionally, at least one first doping region 30 and at least one second doping region 40 may be located in at least two curved sections 8 of the semiconductor terminal structure. Furthermore, at least one first doping region 30 and at least one second doping region 40 may be located in all curved sections 8 of the semiconductor terminal structure. The present invention is not specifically limited to this.

[0104] Optionally, in the curved section 8, the implanted region 2 in the second doped region 40 extends along a path consistent with the curved path of the curved section 8. Specifically, the "curved path" here refers to the curved path of the circumferential outer surface of the curved section 8 of the semiconductor terminal structure. Figure 1 and Figure 7-Figure 9 In the illustrated embodiment, the circumferential outer surface of the curved section 8 is a smooth surface, more specifically, an arc-shaped surface, and each implantation region of the second doping region 40 extends along an arc-shaped path. This arrangement allows each implantation region in each second doping region 40 to have a relatively uniform extension path, which can standardize the formation of each implantation region in the second doping region 40 during the manufacturing process and better control the uniformity of the impurity distribution throughout the curved section 8.

[0105] Of course, in the curved section 8, the implantation region 2 in the second doping region 40 can also be designed as needed to extend along a path that is inconsistent with the curved path of the curved section 8. The specific extension path is not particularly limited here.

[0106] According to some embodiments of the present invention, Figure 1 and Figure 7-Figure 9 As shown, at least one first doping region 30 and at least one second doping region 40 are located in a curved segment 8 and at least one straight segment 7 connected to the curved segment 8. For example, the at least one first doping region 30 and the at least one second doping region 40 can be located in the curved segment 8 and a portion of at least one straight segment 7 adjacent to the curved segment 8, or can be located in the entire curved segment 8 and at least one straight segment 7 adjacent to the curved segment 8. Such an arrangement can not only improve the impurity uniformity of the semiconductor terminal structure in the curved segment 8, but also improve the impurity uniformity of the semiconductor terminal structure in the straight segment 7, so that both the curved segment 8 and the straight segment 7 are fully depleted, thereby ultimately improving the voltage resistance and voltage stability of the entire semiconductor terminal structure.

[0107] According to some optional embodiments of the present invention, the plurality of straight sections 7 include two first straight sections 71 arranged opposite each other and parallel along a second direction, and two second straight sections 72 arranged opposite each other and parallel along a third direction. The first direction, the second direction, and the third direction are mutually perpendicular. There are four curved sections 8, each connected between adjacent first straight sections 71 and second straight sections 72. In this case, the semiconductor terminal structure includes four straight sections 7 and four curved sections 8 located between adjacent straight sections 7. Furthermore, the circumferential surface of the curved sections 8 is a smooth surface, such as an arc-shaped surface. For example, the first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction.

[0108] Of course, the semiconductor terminal structure may be composed of other numbers of straight sections 7 and other numbers of curved sections 8 , depending on the required shape of the semiconductor terminal structure, which is not limited in the present invention.

[0109] According to some specific embodiments of the present invention, Figure 1 Shown and referenced Figure 2-Figure 6 , at least one first doping region 30 and at least one second doping region 40 are located in at least one curved section 8 and one first straight section 71, and the one first straight section 71 is connected to the one curved section 8. In the one curved section 8 and the one first straight section 71, the implantation region 2 of the first doping region 30 extends in the epitaxial layer 20 along a direction parallel to the third direction and is spaced apart along the second direction. In the one curved section 8, the implantation region 2 of the second doping region 40 extends along the curved path of the curved section 8 and extends in the one first straight section 71 along a direction parallel to the second direction. At this time, the implantation region 2 in the second doping region 40 extends in a direction consistent with the circumferential direction of the semiconductor terminal structure, and the first doping region 30 and the second doping region 40 are located in a corner area of ​​the semiconductor terminal structure and a straight section 7 connected to the corner area.

[0110] According to a further embodiment of the present invention, Figure 8 Shown and referenced Figure 2-Figure 6 The at least one first doping region 30 and the at least one second doping region 40 are also located in a second straight section 72 connected to the one curved section 8. The multiple implanted regions in the first doping region 30 extend in a direction parallel to the second direction in the second straight section 72, and the multiple implanted regions in the second doping region 40 extend in a direction parallel to the third direction in the second straight section 72. Specifically, the at least one first doping region 30 and the at least one second doping region 40 are simultaneously located in at least one curved section 8, a first straight section 71 connected to the one curved section 8, and a second straight section 72 connected to the one curved section 8. The implanted regions 2 in the second doping region 40 extend in a direction consistent with the circumferential direction of the semiconductor terminal structure. The implanted regions 2 in the first doping region 30 extend in a direction parallel to the third direction in the first straight section 71 and the curved section 8 and are spaced apart along the second direction. The implanted regions in the first doping region 30 extend in a direction parallel to the second direction in the second straight section 72. With this configuration, the withstand voltage stability and tolerance of the semiconductor terminal structure are improved.

[0111] According to some further embodiments of the present invention, Figure 2-Figure 6 Combined with Figure 9At least one second doped region 40 is also located in a second straight section 72 connected to a curved section 8. In the curved section 8 of the semiconductor terminal structure, the first straight section 71 connected to the curved section 8, and the second straight section 72, the surface of the epitaxial layer 20 that is away from the substrate 10 in the first direction is continuously doped with ions of the second conductivity type in a region B extending from the circumferential inner edge 9 of the semiconductor terminal structure to the inner side of the circumferential outer edge of the semiconductor terminal structure. Thus, in addition to the above-mentioned implanted region 2, the curved section 8 (i.e., the corner section) of the terminal structure, as well as the first straight section 71 and the second straight section 72 connected to the curved section 8, are also continuously doped with ions of the second conductivity type. This helps compensate for the problem of a relatively low number of doped ions of the second conductivity type in the region near the inner side of the curved section of the semiconductor terminal structure due to the curvature, thereby improving the withstand voltage tolerance of the semiconductor terminal structure.

[0112] According to some embodiments of the present invention, the range of the region B is adjustable. In other words, the range of the region B continuously doped with ions of the second conductivity type can be adjusted according to needs.

[0113] Optionally, the region B is continuous on the surface of the epitaxial layer 20 away from the substrate in the first direction.

[0114] Optionally, the region B includes a plurality of spaced-apart subregions, and areas of at least two of the plurality of subregions on the surface of the epitaxial layer away from the substrate 10 in the first direction are different.

[0115] According to some embodiments of the present invention, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type. It is understood that the first conductivity type and the second conductivity type can be set as required. It is understood that when the first conductivity type is P-type and the second conductivity type is N-type, the first pillar is P-type and the second pillar is N-type; when the first conductivity type is N-type and the second conductivity type is P-type, the first pillar is N-type and the second pillar is P-type.

[0116] In addition, it is understood that the shapes of the P-type pillars and N-type pillars shown in the drawings are schematic. In fact, the P-type pillars and N-type pillars can be of other shapes, which are not specifically limited in this application.

[0117] According to the power device of the second embodiment of the present invention, Figures 1-9 , comprising a cellular structure 11 and the semiconductor terminal structure according to any embodiment of the first aspect of the present invention, wherein the semiconductor terminal structure is located at the circumferential periphery of the cellular structure 11.

[0118] According to the power device of the embodiment of the present invention, by including the semiconductor terminal structure described in any embodiment of the first aspect of the present invention, the doped ions in the first column can diffuse toward the second column in at least two different directions, thereby achieving depletion in at least two different directions, making the depletion more sufficient, facilitating the charge balance in the semiconductor terminal structure, and achieving higher voltage resistance and more stable voltage resistance.

[0119] Optionally, the power device is a MOSFET, but is not limited thereto.

[0120] According to an embodiment of the third aspect of the present invention, there is provided a method for manufacturing the semiconductor terminal structure according to any embodiment of the first aspect of the present invention. Figure 10 The method includes the following steps S1, S2, S3, S4 and S5.

[0121] In step S1 , a first epitaxial layer of a first conductivity type is formed on a substrate of a first conductivity type, wherein the epitaxial layer has a first doped region.

[0122] For example, step S1 specifically includes: providing a substrate of a first conductive type. Optionally, the first conductive type is N-type. For example, the resistivity of the substrate 10 is less than 30 mΩ·cm. Or optionally, the first conductive type is P-type. Step S1 also includes: growing a first epitaxial layer on the substrate and implanting ions of the first conductive type into the first epitaxial layer to form a first doped region. Optionally, when the first conductive type is N-type, a first epitaxial layer with a thickness of 5 to 10 microns is grown on the substrate 10. For example, when the first conductive type is N-type, the N-type ions may be, for example, phosphorus ions, arsenic ions, etc., but are not limited thereto; when the first conductive type is P-type, the P-type ions may be, for example, boron ions, but are not limited thereto.

[0123] At step S2, a plurality of implantation regions of the second conductivity type are formed in the first doped region in the first epitaxial layer. For example, step S2 includes: determining the positions and shapes of the plurality of implantation regions 2 of the second conductivity type in the first epitaxial layer, and implanting ions of the second conductivity type at the positions to form the plurality of implantation regions 2 of the second conductivity type in the first doped region 30.

[0124] Optionally, in the first epitaxial layer, the position and shape of the second conductivity type implantation region 2 are determined by a photolithography process, and ions of the second conductivity type are implanted at the position to form a plurality of second conductivity type implantation regions 2 in the first doped region 30 .

[0125] At step S3, a second epitaxial layer of the first conductivity type is formed on the first epitaxial layer, the second epitaxial layer having a second doped region. For example, step S3 includes: growing the second epitaxial layer on the first epitaxial layer and implanting ions of the first conductivity type into the second epitaxial layer to form the second doped region.

[0126] Optionally, a second epitaxial layer with a thickness of, for example, 5 micrometers to 10 micrometers is grown on the first epitaxial layer, and ions of the first conductivity type are implanted into the second epitaxial layer.

[0127] At step S4, a plurality of implantation regions of the second conductivity type are formed in a second doped region in the second epitaxial layer, wherein the epitaxial layer includes a first epitaxial layer and the second epitaxial layer. For example, step S4 includes: determining positions and shapes of the plurality of implantation regions of the second conductivity type in the second epitaxial layer, and implanting ions of the second conductivity type at the positions to form the plurality of implantation regions of the second conductivity type in the second doped region.

[0128] Optionally, the position and shape of the second conductive type implantation region 2 are determined on the surface of the second epitaxial layer by a photolithography process, and ions of the second conductive type are implanted at the position.

[0129] In step S5 , the formed structure is processed so that an interface S is formed between the first doping region and the second doping region, and projections of multiple injection regions in the first doping region on the interface intersect with projections of multiple injection regions in the second doping region on the interface.

[0130] Specifically, the structure formed in step S4 is processed to form a first doping region 30 and a second doping region 40 having an interface S, and the injection region in the first doping region 30 and the injection region in the second doping region 40 extend in mutually intersecting directions and are continuous or discontinuous at the interface S.

[0131] The semiconductor terminal structure manufactured by the above method realizes that the doped ions in the first column and the second column can diffuse toward the second column and the first column respectively in at least two different directions, thereby achieving depletion in at least two different directions, making the depletion more sufficient, facilitating the charge balance in the semiconductor terminal structure, and achieving higher voltage resistance and more stable voltage resistance.

[0132] Optionally, the processing the formed structure includes: performing a heat drive-in process on the formed structure.

[0133] Specifically, a thermal drive-in process is performed on the structure formed in step S4, so that the first conductivity type impurities and the second conductivity type impurities injected in the above step begin to diffuse into each other, forming a stable first conductivity type-second conductivity type structure.

[0134] According to some embodiments of the present invention, after step S4 and before step S5, the method may further include: repeatedly performing steps S1 to S4 at least once.

[0135] Specifically, after step S4, a third epitaxial layer can be grown on the second epitaxial layer and ions of the first conductive type can be injected into the third epitaxial layer; and in the third epitaxial layer, the positions and shapes of multiple second conductive type injection regions are determined, and ions of the second conductive type are injected at the positions to form multiple second conductive type injection regions in the first doped region; a fourth epitaxial layer is grown on the third epitaxial layer and ions of the first conductive type are injected into the fourth epitaxial layer; in the fourth epitaxial layer, the positions and shapes of multiple second conductive type injection regions are determined, and ions of the second conductive type are injected at the positions to form multiple second conductive type injection regions in the second doped region.

[0136] Optionally, in the process of manufacturing a semiconductor terminal structure in which only one first doping region 30 and one second doping region 40 are provided in the epitaxial layer 20, steps S2 and S3 can be repeated multiple times, and then steps S4 and S5 can be performed once, wherein the same mask pattern is used in the multiple executions of step S3, and another different mask pattern is used in step S5.

[0137] According to some embodiments of the present invention, in the process of manufacturing a semiconductor terminal structure having a plurality of first doping regions 30 and a plurality of second doping regions 40 in an epitaxial layer 20, the same mask pattern is used in multiple executions of step S2, the same mask image is used in multiple executions of step S4, and the mask pattern used in step S4 is different from the mask pattern used in step S2.

[0138] In addition, it should be noted that the description of the specific structure and specific details of the semiconductor terminal structure according to the embodiment of the first aspect of the present invention is applicable to the semiconductor terminal structure formed by the manufacturing method according to the embodiment of the second aspect of the present invention and the power device according to the embodiment of the third aspect of the present invention. For the sake of brevity, the description will not be repeated. Moreover, the description of the specific details of the manufacturing method of the semiconductor terminal structure according to the embodiment of the second aspect of the present invention is applicable to the power device according to the embodiment of the third aspect of the present invention. For the sake of brevity, the description will not be repeated. Furthermore, other structures of the semiconductor power device according to the embodiment of the third aspect of the present invention (such as Figure 5 and Figure 6 The field oxide layer 4, conductive polysilicon 5, well region 6, source region 13, interlayer dielectric 14, front metal 15, back metal 16, etc. are conventional structures in this field, and the specific formation steps of these structures are also conventional. For the purpose of brevity, they will not be repeated in this article.

[0139] It is understandable that the above preparation steps may have different orders due to the use of different preparation methods, and other auxiliary steps may be added between the steps during the specific preparation. There are no specific restrictions here, so other variations should also fall within the scope of protection of the method of the present invention.

[0140] When used in the present invention, although the terms "first," "second," etc. may be used to describe various elements in the present invention, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be called a second element, and similarly, a second element can be called a first element, without changing the meaning of the description, as long as all occurrences of "first element" are consistently renamed and all occurrences of "second element" are consistently renamed. The first element and the second element are both elements, but they do not have to be the same element.

[0141] The terms used in the present invention are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include the plural forms. Similarly, the term "and / or" as used in the present invention refers to any and all possible combinations of one or more associated listed items. In addition, when used in the present invention, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups of these.

[0142] The above technical description may refer to the accompanying drawings, which form a part of the present invention and illustrate implementation methods in accordance with the described embodiments in the accompanying drawings. Although these embodiments are described in sufficient detail to enable those skilled in the art to implement these embodiments, these embodiments are non-limiting; other embodiments can be used and changes can be made without departing from the scope of the described embodiments. For example, the order of operations described in the flowchart is non-limiting, so the order of two or more operations illustrated in the flowchart and described according to the flowchart can be changed according to several embodiments. As another example, in several embodiments, one or more operations illustrated in the flowchart and described according to the flowchart are optional or deletable. In addition, certain steps or functions can be added to the disclosed embodiments, or the order of two or more steps can be replaced. All these changes are considered to be included in the disclosed embodiments and the claims.

[0143] In addition, terms are used in the above technical description to provide a thorough understanding of the described embodiments. However, overly detailed details are not required to implement the described embodiments. Therefore, the above description of the embodiments is presented for the purpose of illustration and description. The embodiments presented in the above description and the examples disclosed based on these embodiments are provided separately to add context and assist in understanding the described embodiments. The above description is not intended to be exhaustive or to limit the described embodiments to the precise form of the invention. Based on the above teachings, several modifications, selective applications and variations are feasible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

1. A semiconductor terminal structure, characterized in that: include: a substrate of a first conductivity type; and An epitaxial layer, wherein the epitaxial layer and the substrate are arranged in sequence in a first direction, at least one first doping region and at least one second doping region are provided in the epitaxial layer, the second doping region and the first doping region are arranged in sequence along the first direction, an interface is provided between the first doping region and the second doping region, the first doping region and the second doping region each include a plurality of injection regions of the second conductivity type spaced apart from each other, and projections of the plurality of injection regions in the first doping region on the interface intersect with projections of the plurality of injection regions in the second doping region on the interface.

2. The semiconductor terminal structure according to claim 1, wherein: At least one of the implanted regions in the first doping region contacts at least one of the implanted regions in the second doping region at the interface.

3. The semiconductor terminal structure according to claim 1, wherein: Each of the implanted regions in the first doping region and each of the implanted regions in the second doping region do not contact each other at the interface.

4. The semiconductor terminal structure according to claim 1, wherein: Adjacent implantation regions in the plurality of implantation regions in the first doping region are spaced at the same distance from each other; and / or Adjacent implantation regions in the plurality of implantation regions in the second doping region are spaced apart by the same distance.

5. The semiconductor terminal structure according to claim 1, wherein: Adjacent implantation regions in the plurality of implantation regions in the first doping region are spaced at different distances from each other; and / or Adjacent implantation regions in the plurality of implantation regions in the second doping region are spaced apart by different distances.

6. The semiconductor terminal structure according to claim 1, wherein: Adjacent implantation regions in the plurality of implantation regions in the first doping region are spaced at the same distance from each other; and / or Adjacent injection regions in the multiple injection regions in the second doping region are spaced at different distances, wherein, in the direction from the circumferential inner edge of the semiconductor terminal structure toward the circumferential outer edge of the semiconductor terminal structure, the distance between adjacent injection regions in the multiple injection regions in the second doping region first gradually decreases and then gradually increases.

7. The semiconductor terminal structure according to claim 1, wherein: The plurality of implantation regions in the first doping region are spaced apart from each other along a second direction perpendicular to the first direction, and the plurality of implantation regions in the first doping region have different widths in the second direction; and / or The plurality of implantation regions in the second doping region are spaced apart from each other along a third direction perpendicular to the first direction. The plurality of implantation regions in the second doping region have different widths in the third direction, which is different from the second direction.

8. The semiconductor terminal structure according to claim 1, wherein: The plurality of implantation regions in the first doping region are spaced apart from each other along a second direction perpendicular to the first direction, and the plurality of implantation regions in the first doping region have the same width in the second direction; and / or The plurality of implantation regions in the second doping region are spaced apart from each other along a third direction perpendicular to the first direction. The plurality of implantation regions in the second doping region have the same width in the third direction, which is different from the second direction.

9. The semiconductor terminal structure according to claim 1, wherein: The epitaxial layer is provided with only one first doping region and one second doping region, and the second doping region extends from a surface of the epitaxial layer away from the substrate in the first direction to an interior of the epitaxial layer.

10. The semiconductor terminal structure according to claim 1, wherein: The epitaxial layer is provided with a plurality of the first doping regions and a plurality of the second doping regions, the plurality of the second doping regions and the plurality of the first doping regions are alternately arranged in the first direction, and the interface is provided between adjacent first doping regions and second doping regions.

11. The semiconductor terminal structure according to claim 1, wherein: A plurality of first doping regions and a plurality of second doping regions are provided in the epitaxial layer, and at least one first doping region is adjacent to at least one second doping region in a first direction.

12. The semiconductor terminal structure according to claim 11, wherein: At least two of the first doping regions are adjacently arranged in the first direction.

13. The semiconductor terminal structure according to claim 11, wherein: At least two of the second doping regions are adjacently arranged in the first direction.

14. The semiconductor terminal structure according to claim 10, wherein: The multiple implantation regions in each first doping region are spaced apart from each other along a second direction, wherein the second direction is perpendicular to the first direction, and projections of the implantation regions in at least two first doping regions on the interface at least partially overlap.

15. The semiconductor terminal structure according to claim 10, wherein: The multiple injection regions in each second doping region are spaced apart from each other along a third direction, wherein the third direction is perpendicular to the first direction and different from the second direction, and the projections of the injection regions in at least two second doping regions on the interface at least partially overlap.

16. The semiconductor terminal structure according to claim 10, wherein: The multiple implantation regions in each first doping region are spaced apart from each other along a second direction, wherein the second direction is perpendicular to the first direction, and projections of the implantation regions in at least two first doping regions on the interface do not overlap.

17. The semiconductor terminal structure according to claim 10, wherein: The multiple injection regions in each second doping region are spaced apart from each other along a third direction, wherein the third direction is perpendicular to the first direction and different from the second direction, and projections of the injection regions in at least two second doping regions on the interface do not overlap.

18. The semiconductor terminal structure according to claim 10, wherein: The plurality of implanted regions in the first doping region are spaced apart from each other along a second direction perpendicular to the first direction, the plurality of implanted regions in the first doping region have the same depth in the first direction, and the plurality of implanted regions in the first doping region have the same width in the second direction; and / or The multiple injection regions in the second doping region are spaced apart from each other along a third direction perpendicular to the first direction, the multiple injection regions in the second doping region have the same depth in the first direction, and the multiple injection regions in the second doping region have the same width in the third direction, which is different from the second direction.

19. The semiconductor terminal structure according to claim 10, wherein: The doping concentration of the implanted region is different among the plurality of first doping regions; and / or The doping concentration of the implanted region is different among the plurality of second doping regions; and / or The doping concentration of the implanted region is different between the first doping region and the second doping region.

20. The semiconductor terminal structure according to claim 10, wherein: The doping concentration of the implanted region is the same among the plurality of first doping regions; and / or The doping concentration of the implanted region is the same among the plurality of second doping regions; and / or The doping concentration of the implanted region is the same between the first doping region and the second doping region.

21. The semiconductor terminal structure according to claim 10, wherein: One of the plurality of second doped regions 40 extends from a surface of the epitaxial layer away from the substrate in the first direction to an interior of the epitaxial layer.

22. The semiconductor terminal structure according to claim 10, wherein: The first doping region includes a plurality of first sub-regions of a first doping type, and each two adjacent implant regions of the plurality of implant regions in the first doping region are separated by one of the first sub-regions; and / or the second doping region includes a plurality of second sub-regions of the first doping type, and each two adjacent implantation regions of the plurality of implantation regions in the second doping region are separated by one second sub-region, Wherein, an interface between each of the implanted regions in each of the first doped regions and each of the adjacent first sub-regions forms a curved surface convex toward the adjacent first sub-region; and / or An interface between each of the implanted regions in each of the second doped regions and each of the adjacent second sub-regions forms a curved surface that convexly faces the adjacent second sub-region.

23. The semiconductor terminal structure according to claim 1, wherein: The semiconductor terminal structure includes a plurality of straight sections and at least one curved section, each of the curved sections is connected between two straight sections, and the at least one first doping region and the at least one second doping region are located in at least one of the curved sections.

24. The semiconductor terminal structure according to claim 23, wherein: In the curved section, the implanted region in the second doped region extends along a path consistent with the curved path of the curved section.

25. The semiconductor terminal structure according to claim 23, wherein: The at least one first doping region and the at least one second doping region are located in the one curved section and at least one straight section connected to the one curved section.

26. The semiconductor terminal structure according to claim 23, wherein: The multiple straight sections include two first straight sections opposite to each other and arranged parallel to the second direction, and two second straight sections opposite to each other and arranged parallel to the third direction. The first direction, the second direction and the third direction are perpendicular to each other. There are four curved sections, and the four curved sections are respectively connected between adjacent first straight sections and second straight sections.

27. The semiconductor terminal structure according to claim 26, wherein: The at least one first doping region and the at least one second doping region are located in at least one of the curved sections and one of the first straight sections, and the first straight section is connected to the curved section. In the one curved section and the one first straight section, the implanted regions of the first doped region extend in the epitaxial layer along a direction parallel to the third direction and are spaced apart along the second direction. In the one curved section, the implantation region of the second doping region extends along a curved path of the curved section, and In the one first straight section, the implantation region of the second doping region extends along a direction parallel to the second direction.

28. The semiconductor terminal structure according to claim 27, wherein: The at least one first doping region and the at least one second doping region are also located in a second straight section connected to the one curved section, the multiple injection regions in the first doping region extend in a direction parallel to the second direction in the second straight section, and the multiple injection regions in the second doping region extend in a direction parallel to the third direction in the second straight section.

29. The semiconductor terminal structure according to claim 27, wherein: The at least one second doped region is also located in a second straight section connected to the one curved section, and in the one curved section of the semiconductor terminal structure, the first straight section connected to the one curved section, and the second straight section, the surface of the epitaxial layer in the first direction away from the substrate is continuously doped with ions of the second conductive type in a region extending from the circumferential inner edge of the semiconductor terminal structure to the inner side of the circumferential outer edge of the semiconductor terminal structure.

30. The semiconductor terminal structure according to claim 29, wherein: The extent of the area is adjustable.

31. The semiconductor terminal structure according to claim 30, wherein: The region is continuous on the surface of the epitaxial layer.

32. The semiconductor terminal structure according to claim 30, wherein: The region includes a plurality of spaced-apart sub-regions, at least two of the plurality of sub-regions having different areas on the surface of the epitaxial layer.

33. The semiconductor terminal structure according to any one of claims 1 to 32, characterized in that: The first conductivity type is N type, the second conductivity type is P type, or The first conductivity type is P type, and the second conductivity type is N type.

34. A power device, characterized in that: include: cellular structure; and The semiconductor terminal structure according to any one of claims 1 to 33, wherein the semiconductor terminal structure is located at the circumferential periphery of the cellular structure.

35. The power device according to claim 34, characterized in that The power device is a MOSFET.

36. A method for manufacturing a semiconductor terminal structure according to any one of claims 1 to 33, characterized in that: The following steps are involved: S1. Forming a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type, wherein the epitaxial layer has a first doped region; S2. Forming the plurality of implantation regions of the second conductivity type in the first doping region in the first epitaxial layer; S3. Forming a second epitaxial layer of the first conductivity type on the first epitaxial layer, wherein the second epitaxial layer has a second doped region; S4. Forming a plurality of implantation regions of the second conductivity type in the second doped region of the second epitaxial layer, wherein the epitaxial layer includes the first epitaxial layer and the second epitaxial layer; and S5. Process the formed structure so that an interface is present between the first doping region and the second doping region, and projections of the multiple injection regions in the first doping region on the interface intersect with projections of the multiple injection regions in the second doping region on the interface.

37. The method according to claim 36, wherein The processing of the formed structure comprises: The formed structure is subjected to a heat drive-in process.

38. The method according to claim 36, wherein After step S4 and before step S5, the method further includes: Repeat steps S1 to S4 at least once.

39. The method according to any one of claims 36 to 38, wherein: The step S1 comprises: providing a substrate of the first conductivity type; and A first epitaxial layer is grown on the substrate and ions of a first conductive type are implanted into the first epitaxial layer to form the first doped region.

40. The method according to any one of claims 36 to 39, wherein: The step S2 comprises: In the first epitaxial layer, positions and shapes of a plurality of second conductivity type implantation regions are determined, and ions of the second conductivity type are implanted at the positions to form the plurality of second conductivity type implantation regions in the first doping region.

41. The method according to any one of claims 36 to 40, wherein: The step S3 comprises: A second epitaxial layer is grown on the first epitaxial layer and ions of the first conductivity type are implanted into the second epitaxial layer to form the second doped region.

42. The method according to any one of claims 36 to 41, wherein: The step S4 comprises: In the second epitaxial layer, positions and shapes of a plurality of second conductivity type implantation regions are determined, and ions of the second conductivity type are implanted at the positions to form the plurality of second conductivity type implantation regions in the second doping region.

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