Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, the array substrate is provided with a pixel area and a peripheral area surrounding the pixel area, the peripheral area is provided with a first fan-out line, and the array substrate comprises a substrate body, a first fan-out line, a second fan-out line and a second fan-out line; the gate layer is positioned on one side of the substrate; the first fan-out line and the gate layer are arranged on the same layer; the protective layer is positioned on one side, far away from the substrate, of the gate layer; the protective layer is not overlapped with the first fan-out line, or the protective layer covers the first fan-out line, and the width of the protective layer covering the first fan-out line is smaller than that of the first fan-out line; the first insulating layer is positioned on one side, far away from the substrate, of the protective layer; and the source and drain electrode layer is positioned on one side, far away from the substrate, of the first insulating layer.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Oxide technology thin film transistor (TFT) has become a mainstream thin film transistor preparation technology due to its good uniformity and high mobility, and is generally suitable for high-resolution and high refresh rate products.

[0003] However, such products also have some disadvantages. The incidence of short circuit between gate lines and data lines (called DGS failure) is high. Moreover, as the resolution and refresh rate of display products increase, the incidence of DGS failure is much higher than that of ordinary products.

[0004] Currently, to address poor DGS, the gate layer pattern is typically completely encapsulated with an inert metal. However, this solution increases the single-side trace width of the gate layer by 0.5um-2um, resulting in dense fan-out lines in the fan-out area and severely compressing the gaps between them. This is detrimental to high-resolution, narrow-frame designs and reduces UV transmittance, hindering UV curing.

[0005] In view of this, how to improve the DGS defect without increasing the density of fan-out lines has become a technical problem that needs to be solved urgently. Summary of the Invention

[0006] Embodiments of the present invention provide an array substrate and a display panel to solve the technical problem in the prior art of reducing fan-out line density when improving DGS defects.

[0007] In a first aspect, to solve the above technical problems, an embodiment of the present invention provides an array substrate, wherein the array substrate has a pixel area and a peripheral area surrounding the pixel area, wherein the peripheral area is provided with a first fan-out line, including:

[0008] substrate;

[0009] A gate layer is located on one side of the base substrate; the first fan-out line is provided on the same layer as the gate layer;

[0010] a protective layer located on a side of the gate layer away from the base substrate; the protective layer does not overlap with the first fan-out line, or the protective layer covers the first fan-out line, and a width of the protective layer covering the first fan-out line is smaller than a width of the first fan-out line;

[0011] a first insulating layer, located on a side of the protective layer away from the substrate;

[0012] The source and drain electrode layer is located on a side of the first insulating layer away from the base substrate.

[0013] In one possible implementation, the peripheral region is further provided with a binding pin and a transfer terminal, the binding pin and the transfer terminal are both provided in the same layer as the gate layer; the transfer terminal is electrically connected to the first fan-out line and a data line, respectively, and the data line is located in the pixel region and provided in the same layer as the source and drain layer;

[0014] The protective layer covers the outer surface of the binding pin and the outer surface of the transfer end; wherein the outer surface includes the top surface and side surfaces of the covered object away from the base substrate.

[0015] In one possible implementation, the first fan-out line includes a first line segment, a bent line segment, and a second line segment connected in sequence; an end of the first line segment away from the bent line segment is connected to the transfer end, and an end of the second line segment away from the bent line segment is connected to the binding pin;

[0016] The protective layer also completely covers the outer surface of the second line segment.

[0017] In one possible embodiment, the array substrate includes a plurality of rows of binding pins arranged along a first direction and extending in a second direction, and second fan-out lines; the binding pins arranged along the first direction and the second direction are alternately connected to the first fan-out lines and the second fan-out lines; wherein one end of the second fan-out line away from the binding pins is connected to a corresponding data line, the second fan-out line is arranged on the same layer as the data line, and the extension direction of the second line segment is the same as the second direction;

[0018] In the second direction, the rear binding pin of some two adjacent binding pins is connected to a second line segment. The second line segment is located in a gap between the two adjacent binding pins and is connected to the rear binding pin in the gap.

[0019] In a possible implementation manner, the array substrate further includes:

[0020] a transistor located in the pixel area; the transistor including a gate and a source and drain, the gate being provided in the same layer as the gate layer, and the source and drain being provided in the same layer as the source and drain layer;

[0021] The protection layer at least completely covers the outer surface of the portion where the gate electrode overlaps with the source and drain electrode; wherein the outer surface includes the top surface and side surfaces of the covered object away from the substrate.

[0022] In a possible implementation manner, the pixel area further comprises a gate line, and the gate line is provided in the same layer as the gate layer;

[0023] The gate protrudes from the gate line, and the protection layer completely covers the outer surface of the gate.

[0024] In a possible implementation manner, the protective layer also completely covers the outer surface of the gate line.

[0025] In a possible implementation manner, the array substrate further includes:

[0026] The second insulating layer is located between the protection layer and the gate layer.

[0027] In one possible implementation manner, the gate layer includes:

[0028] A first metal layer is located on one side of the substrate;

[0029] The second metal layer is located on a side of the first metal layer away from the substrate; the activity of the protective layer and the second metal layer is lower than that of the first metal.

[0030] In a possible implementation manner, the material used for the protective layer is an inert metal.

[0031] In a second aspect, an embodiment of the present invention provides a display panel, comprising the array substrate as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0033] Figure 2 The embodiment of the present invention provides Figure 1 Cross-section along the AA' direction;

[0034] Figure 3 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of a connection of a first fan-out line provided by an embodiment of the present invention;

[0036] Figure 5 The embodiment of the present invention provides Figure 4 Cross-section along the middle BB' direction;

[0037] Figure 6 The embodiment of the present invention provides Figure 4 A cross-sectional view in CC' direction;

[0038] Figure 7 The embodiment of the present invention provides Figure 4 Another cross-sectional view in CC' direction;

[0039] Figure 8 A schematic diagram of another connection of a first fan-out line provided by an embodiment of the present invention;

[0040] Figure 9 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0041] Figure 10 A top view of a transistor in an array substrate provided by an embodiment of the present invention;

[0042] Figure 11 A top view of a transistor in another array substrate provided by an embodiment of the present invention;

[0043] Figure 12 A top view of a transistor in another array substrate provided by an embodiment of the present invention;

[0044] Figure 13 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0045] Figure 14 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0046] Figure 15 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0047] Figure 16 A schematic structural diagram of a gate layer provided in an embodiment of the present invention;

[0048] Figure 17 A schematic structural diagram of another gate layer provided by an embodiment of the present invention;

[0049] Figure 18 A flowchart of manufacturing an array substrate provided by an embodiment of the present invention;

[0050] Figure 19 A schematic diagram of forming a gate layer and a protective layer provided by an embodiment of the present invention.

[0051] Reference numerals:

[0052] Pixel area AA, peripheral area BB, base substrate 1, gate layer 2, protective layer 3, first insulating layer 4, source and drain layer 5, first fan-out line 21, second fan-out line 52, binding pin 22, transfer end 23, data line 51, first line segment 211, bending line segment 212, second line segment 213, gate line 24, body 31, tail 32, transistor 6, gate 61, source and drain 62, second insulating layer 7, first metal layer 2a, second metal layer 2b, third metal layer 2c, first direction X, second direction Y. DETAILED DESCRIPTION

[0053] Embodiments of the present invention provide an array substrate and a display panel for improving DGS defects without increasing the density of fan-out lines.

[0054] It should be understood that the specific structural and functional details disclosed in the embodiments of the present invention are merely representative and are for the purpose of describing exemplary embodiments of the present application. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0055] In the description of the present application, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof are intended to cover non-exclusive inclusions.

[0056] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0057] The terms used in this application are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural. It should also be understood that the terms "comprise" and / or "include" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not exclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0058] In the embodiments of the present invention, the term "and / or" simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0059] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained with reference to the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportion.

[0060] It should be noted that specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined as defined by the appended claims.

[0061] An array substrate and a display panel provided by embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0062] See Figure 1 and Figure 2 , Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention is shown. Figure 2 The embodiment of the present invention provides Figure 1 In the cross-sectional view along the AA' direction, the array substrate has a pixel area AA and a peripheral area BB surrounding the pixel area AA. The peripheral area BB is provided with a first fan-out line 21. The array substrate includes:

[0063] Base substrate 1;

[0064] The gate layer 2 is located on one side of the base substrate 1; the first fan-out line 21 is provided on the same layer as the gate layer 2;

[0065] The protective layer 3 is located on a side of the gate layer 2 away from the base substrate 1; the protective layer 3 does not overlap with the first fan-out line 21, or the protective layer 3 covers the first fan-out line 21, and the width W1 of the protective layer 3 covering the first fan-out line 21 is smaller than the width W2 of the first fan-out line 21;

[0066] A first insulating layer 4 is located on a side of the protective layer 3 away from the substrate 1;

[0067] The source and drain layer 5 is located on a side of the first insulating layer 4 away from the base substrate 1 .

[0068] The protective layer 3 can protect the gate layer 2 to prevent the gate layer 2 in the pixel area AA from piercing the first insulating layer 4 and short-circuiting with the source and drain layer 5. The material used for the protective layer 3 can be an inert metal or an alloy of inert metals, such as molybdenum (Mo), titanium (Ti), nickel (Ni), etc.

[0069] like Figure 1 and Figure 2 As shown, when the first fan-out line 21 is covered with the protective layer 3, the width W1 of the protective layer 3 is smaller than the width W2 of the first fan-out line 21. In this way, the width of the first fan-out line 21 will not be increased due to the presence of the protective layer 3, and the density of the first fan-out line 21 will not be increased. At the same time, the first fan-out line 21 can be protected from being damaged due to over-engraving, thereby improving the stability of the first fan-out line 21.

[0070] like Figure 3 The figure shows a structural schematic diagram of another array substrate provided by an embodiment of the present invention. The protective layer 3 may not cover the first fan-out line 21, that is, the protective layer 3 and the first fan-out line 21 do not overlap. In this way, the width of the first fan-out line 21 will not be increased due to the presence of the protective layer 3, and the density of the first fan-out line 21 will not be increased.

[0071] In the embodiment provided by the present invention, by providing a protective layer 3 between the first insulating layer 4 and the gate layer 2, the protective layer 3 can be used to protect the gate layer 2 in the pixel area AA from short-circuiting with the source / drain layer 5 located on the first insulating layer 4 away from the gate layer 2. In the peripheral area BB, the protective layer 3 is prevented from overlapping with the first fan-out line 21, or the width of the protective layer 3 covering the first fan-out line 21 is smaller than the width of the first fan-out line 21. This can prevent the width of the first fan-out line 21 from being increased, thereby achieving the goal of improving the DGS defect while not increasing the density of the first fan-out line 21.

[0072] See Figure 4-Figure 6 , Figure 4 A connection diagram of a first fan-out line provided by an embodiment of the present invention, Figure 5 The embodiment of the present invention provides Figure 4 Cross-section view in the BB' direction, Figure 6The embodiment of the present invention provides Figure 4 A cross-sectional view in the CC' direction.

[0073] A binding pin 22 and a transfer terminal 23 are also provided in the peripheral area BB, and the binding pin 22 and the transfer terminal 23 are both provided in the same layer as the gate layer 2; the transfer terminal 23 is electrically connected to the first fan-out line 21 and the data line 51 (not shown), respectively, and the data line 51 is located in the pixel area AA and is provided in the same layer as the source and drain layer 5; the first insulating layer 4 has a through hole H at the position where the transfer terminal 23 is located, and the data line 51 extends from the pixel area AA to the corresponding through hole H in the peripheral area BB and is electrically connected to the transfer terminal 23, and the protective layer 3 is composed of an inert metal or an inert metal alloy.

[0074] The protective layer 3 covers the outer surface of the binding pin 22 and the outer surface of the transfer terminal 23 ; wherein the outer surface includes the top surface and side surfaces of the covered object away from the base substrate 1 .

[0075] like Figure 5 As shown, when the covered object is the binding pin 22, the protective layer 3 covers the top surface 22a and the side surface 22b of the binding pin 22, and the top surface 11a of the binding pin 22 is located on the side of the binding pin 22 away from the base substrate 1; Figure 6 As shown, when the covered object is the transfer end 23 , the protective layer 3 covers the top surface 23 a and the side surface 22 b of the transfer end 23 , and the top surface 23 a of the transfer end 23 is located on the side of the transfer end 23 away from the base substrate 1 .

[0076] In some embodiments, the through hole H also penetrates the protective layer 3. For example, when etching the through hole H in the first insulating layer 4, there may be over-etching, resulting in the protective layer 3 being etched through. However, the protective layer 3 as a whole still covers the outer surface of the transfer terminal 23. Therefore, the through hole H also penetrates the protective layer 3 and is also considered as the protective layer 3 covering the outer surface of the transfer terminal 23. In an ideal state, the through hole H does not penetrate the protective layer 3, just as Figure 5 The protective layer 3 is etched to the side away from the transfer end 23 as in the embodiment, so that the protective layer 3 completely covers the transfer end 23.

[0077] Similarly, the way in which the protective layer 3 covers the binding pins 22 can refer to the way in which the protective layer 3 covers the transfer terminal 23, and will not be repeated here.

[0078] In some embodiments, the first insulating layer 4 may have a plurality of through holes H at the location of the transfer terminal 23, and the transfer terminal 23 may be covered with a conductive structure (including covering the plurality of through holes H), thereby improving the conductivity between the source and drain electrode layer 5 and the transfer terminal 23. The conductive structure may be provided in the same layer as the source and drain electrode layer 5, or in the same layer as the pixel electrode and the common electrode, without limitation herein.

[0079] In the embodiment provided by the present invention, by allowing the protective layer 3 to completely cover the outer surface of the binding pin 22 and the outer surface of the transfer end 23, the protective layer 3 can be used to protect the binding pin 22 and the transfer end 23 to prevent damage to the binding pin 22 and the transfer end 23 due to over-engraving.

[0080] See Figure 7 The embodiment of the present invention provides Figure 4 In another cross-sectional view taken along the CC' direction, the protective layer 3 covering the binding pin 22 includes a main body 31 and a tail portion 32 extending from the main body 31. The orthographic projection of the binding pin 22 on the base substrate 1 is located within the orthographic projection of the main body 31 on the base substrate 1, and the tail portion 32 does not overlap with the binding pin 22. Similarly, Figure 4 The protective layer 3 covering the transfer end 23 can also have a body 31 and a tail 32. For specific covering methods, please refer to Figure 7 The covering method of covering the binding pin 22 is not repeated here.

[0081] By setting the protective layer 3 to include a main body 31 and a tail 32, the orthographic projection of the covered object on the base substrate 1 is located within the orthographic projection of the main body 31 on the base substrate 1, and the tail 32 does not overlap with the covered object, thereby ensuring the integrity of the covered object wrapped by the protective layer 3, and further preventing the protected object from being damaged due to over-engraving.

[0082] Please continue to see Figure 7 The width of the tail portion 32 ranges from 0.1um to 3um.

[0083] See Figure 8 A schematic diagram illustrating another connection of a first fan-out line according to an embodiment of the present invention is shown. The first fan-out line 21 includes a first line segment 211, a bending line segment 212, and a second line segment 213 connected in sequence. An end of the first line segment 211 away from the bending line segment 212 is connected to the adapter end 23, and an end of the second line segment 213 away from the bending line segment 212 is connected to the binding pin 22.

[0084] The protective layer 3 also completely covers the outer surface of the second line segment 213. The covering manner of the protective layer 3 completely covering the outer surface of the second line segment 213 can refer to the covering manner of the protective layer 3 completely covering the binding pin 22, which will not be repeated here.

[0085] Figure 8The first line segment 211 and the meandering line segment 212 are not covered by the protective layer 3. In other embodiments, the first line segment 211 and the meandering line segment 212 may also be covered by the protective layer 3, and the width of the protective layer 3 covering the first line segment 211 and the meandering line segment 212 is smaller than the width of the first line segment 211 and the meandering line segment 212. By providing the meandering line segment 212 in the first fan-out line 21, impedance matching can be achieved for signal lines corresponding to different first fan-out lines 21; wherein the signal line may include the first fan-out line 21 and the data line 51 electrically connected to the first fan-out line 21.

[0086] It is important to understand that Figure 8 Only a portion of the data line 51 is shown in FIG. The number of bends in the bend line segment 212 is not limited to Figure 8 The quantity shown.

[0087] In the embodiment provided by the present invention, by providing a bending line segment 212 at one end of the first fan-out line 21 close to the binding pin 22 and a second line segment 213 connected between the bending line segment 212 and the binding pin 22, the bending line segment 212 can be used to achieve impedance matching of the corresponding signal line, and the protective layer 3 can also completely cover the second line segment 213, which can prevent the second line segment 213 from being damaged due to over-engraving, thereby improving the stability of the first fan-out line 21.

[0088] See Figure 9 A schematic structural diagram of another array substrate provided in an embodiment of the present invention, wherein the array substrate includes a plurality of rows of binding pins 22 arranged along a first direction X and extending in a second direction Y, and a second fan-out line 52; the binding pins 22 arranged along the first direction X and the second direction Y are alternately connected to the first fan-out line 21 and the second fan-out line 52; wherein one end of the second fan-out line 52 away from the binding pin 22 is connected to the corresponding data line 51, the second fan-out line 52 is arranged in the same layer as the data line 51, and the extension direction of the second line segment 213 is the same as the second direction Y; the binding pin 22 connected to the second fan-out line 52 is connected to the second fan-out line 52 through a connection hole ( Figure 9 (not shown) electrical connection.

[0089] In the second direction Y, the latter binding pin 22 of some two adjacent binding pins 22 is connected to the second line segment 213 . The second line segment 213 is located in the gap between the two adjacent binding pins 22 and is connected to the latter binding pin 22 in the gap.

[0090] like Figure 9As shown, in the first direction X, the first binding pin 22 in the first row of binding pins 22 is connected to the second fan-out line 52, and the second binding pin 22 is connected to the first fan-out line; in the second direction Y, the first binding pin 22 is connected to the second fan-out line 52, the second binding pin 22 is connected to the first fan-out line 21, and the third binding pin 22 is connected to the second fan-out line 52; Figure 9 In the second direction Y, the binding pin 22 in the first row and first column is adjacent to the binding pin 22 in the second row and second column, the binding pin 22 in the second row and second column is connected to the second line segment 213 corresponding to the first fan-out line 21, and the part of the second line segment 213 close to the binding pin 22 in the second row and second column is located in the gap between the binding pin 22 in the first row and first column and the binding pin 22 in the second row and second column.

[0091] It is important to understand that Figure 9 For the sake of convenience, only some of the binding pins 22 are shown. In actual applications, the binding pins 22 included in the array substrate are not limited to Figure 9 The quantity shown.

[0092] See Figure 10 A top view of a transistor in an array substrate provided in an embodiment of the present invention. The array substrate further includes:

[0093] Transistor 6 is located in pixel area AA; transistor 6 includes a gate 61 and a source-drain 62, the gate 61 is provided in the same layer as the gate layer 2, and the source-drain 62 is provided in the same layer as the source-drain layer 5;

[0094] The protective layer 3 at least completely covers the outer surface of the portion where the gate 61 and the source and drain electrodes 62 overlap; wherein the outer surface includes the top surface and side surfaces of the covered object away from the substrate 1. The covering method of the protective layer 3 completely covering the portion where the gate 61 and the source and drain electrodes 62 overlap can refer to the covering method of the protective layer 3 completely covering the binding pins 22 (such as Figure 6 and Figure 7 shown), which will not be described here.

[0095] In the embodiment provided by the present invention, by allowing the protection layer 3 to completely cover at least the outer surface of the overlapping portion of the gate 61 and the source / drain 62 , at least the gate 61 and the source / drain 62 can be prevented from short-circuiting, thereby improving DGS poor performance.

[0096] See Figure 11 This is a top view of another transistor in an array substrate provided by an embodiment of the present invention. The pixel area AA further has a gate line 24 , which is provided in the same layer as the gate layer 2 .

[0097] The gate 61 protrudes from the gate line 24, and the protective layer 3 completely covers the outer surface of the gate 61. The way in which the protective layer 3 completely covers the outer surface of the gate 61 can refer to the way in which the protective layer 3 completely covers the binding pin 22 (such as Figure 6 and Figure 7 shown), which will not be described here.

[0098] In the embodiment provided by the present invention, by allowing the protection layer 3 to completely cover the gate 61 , short circuit between the gate 61 and the source / drain 62 can be prevented, and the flatness of the region where the transistor 6 is located can be improved.

[0099] See Figure 12 A top view of another transistor in an array substrate provided by an embodiment of the present invention. The protective layer 3 also completely covers the outer surface of the gate line 24. The covering method of the protective layer 3 completely covering the outer surface of the gate line 24 can refer to the method in which the protective layer 3 completely covers the binding pin 22 (such as Figure 6 and Figure 7 shown), which will not be described here.

[0100] In the embodiment provided by the present invention, by allowing the protection layer 3 to completely cover the outer surface of the gate 61, it is also possible to prevent the gate line 24 from being short-circuited with the source and drain layers, thereby further improving DGS failure.

[0101] See Figure 13 This is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. The array substrate further includes:

[0102] The second insulating layer 7 is located between the protection layer 3 and the gate layer 2 .

[0103] By providing the second insulating layer 7 between the protective layer 3 and the gate layer 2 , the protective layer 3 can be easily etched, and the protective layer 3 can be prevented from remaining on the gate layer 2 at the location where the protective layer 3 needs to be etched away.

[0104] See Figure 14 This is a structural diagram of another array substrate provided by an embodiment of the present invention. When the protective layer 3 completely covers the transfer terminal 23, the film layer between the source and drain layer 5 and the gate layer 2 has a through hole H' that penetrates the film layer between the source and drain layer 5 and the gate layer 2.

[0105] See Figure 15 This is a structural diagram of another array substrate provided by an embodiment of the present invention. When the covered object is the binding pin 22, the second insulating layer 7 and the first insulating layer 4 covering the binding pin 22 can be removed.

[0106] It is important to understand that Figure 13 The example of the covered object being the gate 61 is given. The covered object can also be other objects, such as the gate line 24. Figure 13 The coverage form.

[0107] See Figure 16 A schematic structural diagram of a gate layer provided in an embodiment of the present invention.

[0108] Gate layer 2, including:

[0109] The first metal layer 2a is located on one side of the base substrate 1;

[0110] The second metal layer 2b is located on the side of the first metal layer 2a away from the substrate 1; the activity of the protective layer 3 and the second metal layer 2b is lower than that of the first metal.

[0111] The material used for the first metal layer 2a can be a metal material or alloy with high conductivity, such as copper (Cu), aluminum (Al), and silver (Ag). The material used for the second metal layer 2b can be a material with lower activity than the material used for the first metal layer 2a, such as an inert metal or an alloy of inert metals. The inert metal can be molybdenum (Mo), titanium (Ti), and nickel (Ni).

[0112] By setting a second metal layer 2b on the side of the first metal layer 2a away from the base substrate 1, and making the activity of the second metal layer 2b lower than that of the first metal layer 2a, the second metal layer 2b can be used to protect the first metal layer 2a to prevent the material from affecting the surface properties of the first metal layer 2a itself during the etching process of the protective layer 3, thereby preventing problems such as corrosion and oxidation.

[0113] See Figure 17 This is a schematic structural diagram of another gate layer provided by an embodiment of the present invention. The gate layer 2 further includes a third metal layer 2c located between the first metal layer 2a and the base substrate 1.

[0114] The material used for the third metal layer 2c can be a material with lower activity than that used for the first metal layer 2a, such as an inert metal or an alloy of inert metals. The inert metal can be molybdenum (Mo), titanium (Ti), or nickel (Ni).

[0115] By providing the third metal layer 2 c between the first metal layer 2 a and the base substrate 1 , the first metal layer 2 a can be further protected by the third metal layer 2 c.

[0116] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing an array substrate, see Figure 18 A flowchart of manufacturing an array substrate provided in an embodiment of the present invention includes:

[0117] S11: providing a substrate;

[0118] S12: forming a gate layer on one side of the substrate;

[0119] S13: forming a protective layer on one side of the gate layer;

[0120] S14: forming a first insulating layer on one side of the protective layer;

[0121] S15: forming a source-drain layer on one side of the first insulating layer.

[0122] In some embodiments, before forming the protection layer on one side of the gate layer, a second insulating layer may be formed on one side of the gate layer.

[0123] See Figure 19 A schematic diagram of forming a gate layer and a protective layer is provided in an embodiment of the present invention. For example, a substrate includes a gate layer and a protective layer located on one side of the gate layer, and the protective layer does not cover the wiring in the peripheral area.

[0124] S21: depositing a gate layer;

[0125] The structure of the gate layer is the same as that of the aforementioned gate layer.

[0126] S22: Setting a mask for the gate layer;

[0127] S23: etching the gate layer;

[0128] S24: depositing a protective layer;

[0129] S25: Setting a mask for a protective layer;

[0130] After setting the mask of the protection layer, the pixel area that needs to be covered by the protection layer is covered with photoresist, and the wiring in the peripheral area (such as the first fan-out line) that does not need to be covered by the protection layer is not covered with photoresist.

[0131] S26: etching the protective layer.

[0132] When etching the protective layer, the display area and other areas that need to be covered by the protective layer are protected by photoresist, forming a structure in which the protective layer covers the gate pattern. The areas in the peripheral area where the wiring does not need to be covered by the protective layer are not protected by photoresist, so the protective layer is etched away and the corresponding wiring is not covered by the protective layer.

[0133] If a second insulating layer is provided between the gate layer and the protection layer, it is necessary to deposit the second insulating layer, set a mask for the second insulating layer, etch the second insulating layer, and then perform 214 before S24 .

[0134] Based on the same inventive concept, an embodiment of the present invention provides a display panel, which includes the array substrate as described above.

[0135] The display panel can be a liquid crystal display panel or an electroluminescent display panel. The liquid crystal display panel can be used to form a liquid crystal display screen, a liquid crystal television and other display devices. The electroluminescent display panel can be used to form an electroluminescent display screen, an electroluminescent television, etc.; it can also be used to form mobile devices such as mobile phones, tablet computers, and notebooks.

[0136] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0137] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, comprising a pixel region and a peripheral region surrounding the pixel region, wherein the peripheral region is provided with a first fan-out line, characterized in that: include: substrate; A gate layer is located on one side of the base substrate; the first fan-out line is provided on the same layer as the gate layer; a protective layer located on a side of the gate layer away from the base substrate; the protective layer does not overlap with the first fan-out line, or the protective layer covers the first fan-out line, and a width of the protective layer covering the first fan-out line is smaller than a width of the first fan-out line; a first insulating layer, located on a side of the protective layer away from the substrate; The source and drain electrode layer is located on a side of the first insulating layer away from the base substrate.

2. The array substrate according to claim 1, wherein: The peripheral area is further provided with a binding pin and a transfer terminal, and the binding pin and the transfer terminal are both provided in the same layer as the gate layer; the transfer terminal is electrically connected to the first fan-out line and the data line respectively, and the data line is located in the pixel area and provided in the same layer as the source and drain layer; The protective layer covers the outer surface of the binding pin and the outer surface of the transfer end; wherein the outer surface includes the top surface and side surfaces of the covered object away from the base substrate.

3. The array substrate according to claim 2, wherein: The first fan-out line includes a first line segment, a bending line segment, and a second line segment connected in sequence; an end of the first line segment away from the bending line segment is connected to the transfer end, and an end of the second line segment away from the bending line segment is connected to the binding pin; The protective layer also completely covers the outer surface of the second line segment.

4. The array substrate according to claim 3, wherein: The array substrate includes a plurality of rows of binding pins arranged in a first direction and extending in a second direction, and second fan-out lines; the binding pins arranged in the first direction and the second direction are alternately connected to the first fan-out lines and the second fan-out lines; wherein one end of the second fan-out line away from the binding pins is connected to the corresponding data line, the second fan-out line and the data line are arranged in the same layer, and the extension direction of the second line segment is the same as the second direction; In the second direction, the rear binding pin of some two adjacent binding pins is connected to a second line segment. The second line segment is located in a gap between the two adjacent binding pins and is connected to the rear binding pin in the gap.

5. The array substrate according to claim 1, wherein: The array substrate further includes: a transistor located in the pixel area; the transistor including a gate and a source and drain, the gate being provided in the same layer as the gate layer, and the source and drain being provided in the same layer as the source and drain layer; The protection layer at least completely covers the outer surface of the portion where the gate electrode overlaps with the source and drain electrode; wherein the outer surface includes the top surface and side surfaces of the covered object away from the substrate.

6. The array substrate according to claim 5, wherein: The pixel area further comprises a gate line, and the gate line is arranged in the same layer as the gate layer; The gate protrudes from the gate line, and the protection layer completely covers the outer surface of the gate.

7. The array substrate according to claim 6, wherein: The protection layer also completely covers the outer surface of the gate line.

8. The array substrate according to any one of claims 1 to 7, wherein: The array substrate further includes: The second insulating layer is located between the protection layer and the gate layer.

9. The array substrate according to any one of claims 1 to 7, wherein: The gate layer includes: A first metal layer is located on one side of the substrate; The second metal layer is located on a side of the first metal layer away from the substrate; the activity of the protective layer and the second metal layer is lower than that of the first metal.

10. The array substrate according to any one of claims 1 to 7, wherein: The material used for the protective layer is inert metal.

11. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 10.

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