Method for producing magnetic sensor

Abstract

The invention relates to a method for producing a magnetic sensor, in which at least one depth portion is produced or formed in the surface of the front side of a substrate, in which a magnetic material is grown on the bottom of the at least one depth portion in a galvanization process frame, at least one element that at least partially affects the magnetic field, i.e. A magnetic current-conducting element, is formed as a final result of the galvanization process, at least one magnetic induction element connected to the substrate being formed such that the magnetic current-conducting element is separated from the substrate in relation to the front side of the substrate. The magnetic induction element is arranged higher than at least one magnetic flow guiding element made of a galvanically grown magnetic material. The invention also relates to a magnetic sensor.

Description

Technical Field

[0001] The present invention relates to a method for producing a magnetic sensor and a magnetic sensor. Background Art

[0002] In the manufacture of magnetic sensors, devices are often required to generate, direct, concentrate, or shield the external magnetic field to be measured in order to achieve a specific sensing range, sensitivity, or sensing direction. Such magnetic flow guiding elements can, for example, be composed of a layer of soft magnetic material several microns thick.

[0003] The induction element can be manufactured on a silicon chip (wafer) in a semiconductor compatible process, for example. The guiding, shielding or concentrating effect of the magnetic flow guiding element on the magnetic flow at the induction element becomes stronger as the vertical distance between the induction element and the shielding element becomes smaller. Here, the induction element can be arranged laterally inside and / or outside the area of ​​the magnetic flow guiding element. In order to minimize the vertical distance, the magnetic flow guiding element can be manufactured directly on the wafer as part of the wafer process before the actual induction element is manufactured. For example, such a magnetic flow guiding element can be grown on the wafer within the framework of a selective electrogalvanizing process (selective electroplating). Here, the surface of the material that should not be grown must be protected by a non-conductive material. If such a material is composed of photoresist, for example, then for reasons of thermal stability, the photoresist must be removed after the shielding element is produced. In this case, a surface morphology step several microns high is usually formed between the magnetic flow guiding element and the area outside the magnetic flow guiding element, which can seriously hinder subsequent processing in a typical semiconductor process.

[0004] Alternatively, if a dielectric material is used to cover an area where a soft magnetic material should not be grown, the deposition of this non-conductive material and its etching are both huge challenges because this material easily generates stress on the wafer after application. In particular, when a non-conductive material is applied to one side of the wafer with a thickness of several microns, this stress can cause the wafer to warp, which makes subsequent processing impossible or even causes the wafer to break. This is particularly important in the processing of 300mm wafers. Although the process used when applying the non-conductive material will affect the resulting wafer curvature to a certain extent, it is very difficult or even impossible for a dielectric layer (non-conductive layer) several microns thick.

[0005] Another problem arises during the subsequent processing of these wafers, since subsequent temperature steps again change the layer stresses of the layer system and can lead to new problems such as wafer bowing, delamination or stress cracks in non-conductive materials and / or their upper and lower layer systems.

[0006] Even if the wafer contains at least one protection diode or other electronic circuit before processing, another problem arises if this circuit must be electrically connected later in the manufacturing process. For example, this electrical connection must pass through the dielectric layer and through the conductive seed layer without shorting it out. Particularly due to the thickness of the dielectric layer, manufacturing the electrical connection for this protection diode is very complex and requires a large amount of chip area. Summary of the Invention

[0007] The object of the present invention is to provide a solution which overcomes the above-mentioned disadvantages.

[0008] This object is achieved by means of the respective subject matter of the independent claims. Advantageous embodiments of the invention are the subject matter of the respective dependent claims.

[0009] According to a first aspect, there is provided a method for manufacturing a magnetic sensor, comprising the following steps:

[0010] producing at least one recess in the surface of the front side of the substrate,

[0011] depositing an electrically conductive seed material on the surface of the substrate and on the surface including the bottom of the at least one recess, to form a conductive seed layer extending continuously from the edge region of the substrate into the recess, said conductive seed layer being electrically contactable in the edge region of the substrate,

[0012] Depositing an electrically insulating material, in particular a dielectric material, on the conductive seed layer, in particular directly depositing it, to form an electrically insulating layer, in particular a dielectric layer, on the conductive seed layer, in particular directly forming it,

[0013] removing the electrically insulating layer in the respective bottom of the at least one recess and in the edge region of the substrate, so that the electrically conductive seed layer is not covered by the electrically insulating layer at the respective bottom of the at least one recess and in the edge region of the substrate,

[0014] performing a zinc plating process to grow a magnetic material on a surface of the conductive seed layer facing away from a corresponding bottom of the at least one deep portion to form at least one magnetic flow guiding element,

[0015] At least one magnetic induction element connected to the substrate is formed such that, relative to the front side of the substrate, the magnetic induction element is arranged higher than at least one magnetic flow guiding element composed of a zinc-grown magnetic material.

[0016] According to a second aspect, there is provided a magnetic sensor comprising:

[0017] substrate,

[0018] wherein at least one recess is formed in the surface of the front side of the substrate,

[0019] wherein a conductive seed layer is formed on the surface of the substrate and on the surface including the bottom of the at least one recessed portion, the conductive seed layer extending continuously from the edge region of the substrate into the recessed portion;

[0020] wherein an electrically insulating layer, in particular a dielectric layer, is formed, in particular directly on the surface of the electrically conductive seed layer, wherein the electrically conductive seed layer is not covered by the electrically insulating layer at the respective bottom of the at least one recess and in the edge region of the substrate,

[0021] wherein at least one magnetic flow guiding element composed of a zinc-grown magnetic material is formed on the conductive seed layer at the corresponding bottom of at least one of the deep portions;

[0022] Therein, at least one magnetic induction element connected to the substrate is formed such that it is arranged higher than at least one magnetic flow guiding element composed of a zinc-grown magnetic material relative to the front side of the substrate.

[0023] The present invention is based on and encompasses the recognition that the aforementioned object is achieved by creating or forming at least one recess in the surface of the front side of a substrate. A magnetic material is grown on the bottom of the at least one recess during a galvanizing process, so that as a result of the galvanizing process, at least one element that at least partially influences the magnetic field, namely a magnetic flow guiding element, is formed. This element is therefore located within the at least one recess, and not directly on the front side of the substrate, as in the prior art. As a result, the aforementioned disadvantages can be effectively avoided.

[0024] The conductive seed layer covers the surface including the bottom of the corresponding at least one recessed portion and continuously extends from the recessed portion to an edge region of the substrate.

[0025] For example, a galvanizing process is performed as follows: a conductive seed layer is electrically contacted in the edge region of the substrate. Also within the edge region of the substrate, but within the electrically contacted edge region (the contact zone), there is a region completely covered by a non-conductive material (the sealing zone). Furthermore, the galvanizing process particularly includes the use of a galvanizing bath that contacts the substrate surface but is separated from the contact region of the substrate at the outer substrate edge by the sealing zone.

[0026] The contact area, i.e., the conductive seed layer at the edge of the substrate, forms an electrode, while the zinc plating bath and / or another electrode in the zinc plating bath forms a counter electrode. A current path, i.e., an electrical connection, exists from the contact area at the edge of the substrate through the conductive seed layer on the substrate surface and at the sides and bottom of the recess to the zinc plating bath, and optionally to the other electrode.

[0027] When a voltage is applied to the electrode and the counter electrode, current flows between the electrode and the counter electrode, causing the magnetic material to grow by zinc plating on the conductive seed layer at the bottom of the deep portion.

[0028] By arranging a conductive seed layer and its electrically insulating covering in appropriate areas of the wafer, a particular technical advantage is that, within the framework of the galvanizing process, the magnetic material grows only on the bottom of the corresponding at least one deep portion, and not on the surface of the corresponding at least one deep portion and / or the surface of the substrate.

[0029] For example, the edge region (contact zone) extends from the edge of the substrate to a minimum of 1.5 mm and a maximum of 3.0 mm. In this edge region, the electrically insulating layer is at least partially removed. Because this region is separated from the galvanizing bath by a sealing zone and, therefore, is not in mechanical contact with the galvanizing bath, no magnetic material can grow there.

[0030] For example, this brings the technical advantage that the edge region can be effectively utilized to electrically connect or contact the conductive seed layer in the region of the bottom of the at least one recessed portion.

[0031] During the galvanizing process, the conductive seed layer in the area of ​​the bottom of at least one recess, which is electrically contacted via the edge region, forms one electrode, while the galvanizing bath and / or another electrode in the galvanizing bath forms a counterelectrode. Deposition occurs only on surfaces where current can flow between the electrode and the counterelectrode and where the surface is in mechanical contact with the galvanizing bath. During the galvanizing process, the edge region of the substrate is mechanically and electrically isolated from the galvanizing bath by the seal.

[0032] In one embodiment of the method, it is provided that removing the electrically insulating layer comprises performing a photolithographic process, according to which the electrically insulating layer to be removed, in particular the dielectric layer, is at least partially removed from the electrically conductive seed layer by means of an etching process.

[0033] For example, this provides the technical advantage that the removal can be performed efficiently.

[0034] The etching process includes, for example, isotropic and / or anisotropic etching or etching behavior.

[0035] A photolithography process, for example, involves applying a photoresist, such as a negative or positive photoresist, to the surface of a substrate, wherein the applied photoresist is removed by exposure and development in the areas where the electrically insulating layer (especially the dielectric layer) is to be removed. This means that the areas where the electrically insulating layer (especially the dielectric layer) is to be removed are not covered by the photoresist, i.e., are free of such photoresist.

[0036] To reinforce the electrically insulating material at the sidewalls of the at least one recess, for example, according to one embodiment of the method, a spacer process can be performed before depositing the electrically insulating material. For example, the electrically insulating material, in particular a dielectric material, can be deposited on the surface including the sidewalls of the at least one recess in an isotropic (conformal) deposition process and anisotropically etched back in a subsequent step. As a result, the electrically insulating material remains particularly on the sidewalls of the at least one recess, effectively protecting them during the galvanizing process.

[0037] In one embodiment of the method, after the galvanizing process has been carried out, a chemical mechanical polishing process is carried out on the surface of the substrate to form a smooth, flat surface. For example, this can be carried out directly after the galvanizing process or, for example, after applying an additional electrically insulating layer, in particular a dielectric layer. The goal of the chemical mechanical polishing process is in particular to produce a surface that is as smooth and flat as possible. For example, the polishing process can be stopped within the uppermost electrically insulating layer, in particular a dielectric layer, after removing the conductive seed layer from the surface of the substrate (except for at least one deep cut), after removing the uppermost magnetic layer of the magnetic flow guiding element, or at any other height that retains at least a portion of the at least one deep cut in which the galvanized grown magnetic material is located.

[0038] For example, this brings the technical advantage of effectively forming a flat, smooth surface on the substrate. Advantageously, this allows for efficient subsequent manufacturing processes of the magnetic sensing element and allows for a small lateral distance between the magnetic flow guiding element and the sensing element. Generally, this brings the technical advantage of enabling efficient subsequent processing or handling of the substrate. In particular, low surface topography and low surface roughness are beneficial for the manufacture of at least one magnetic sensing element.

[0039] In one embodiment of the method, it is provided that the seed material comprises one or more of the following materials: Ta, TaN, Cu, CuN, Ti, TiN, Cr and NiFe.

[0040] This offers the technical advantage, for example, that particularly suitable seed materials can be used.

[0041] In one embodiment of the method, it is provided that the conductive seed material is deposited such that the layer thickness of the conductive seed layer on the bottom of the recess is within an open, semi-open or closed range of 20 nm to 300 nm or more.

[0042] For example, this provides the technical advantage that a particularly suitable layer thickness can be set, which has a sufficiently low electrical resistance so that the electrogalvanic zinc deposition process, ie the galvanizing process, can be carried out or executed with good homogeneity.

[0043] In one embodiment of the method, the dielectric material may include one or more of the following materials: SiO2, SiO X , Si 3 N 4 , SiON and Al 2 O 3 and can optionally consist of a plurality of successively applied layers and / or layer sequences.

[0044] This results in the technical advantage that particularly suitable dielectric materials can be used, for example.

[0045] The seed layer may also be referred to as a "seed layer" in English.

[0046] Galvanizing processes include, for example, electroplating.

[0047] The recessed portion has a depth within an open range, a semi-open range, or a closed range of, for example, 0.1 μm to 20 μm.

[0048] The magnetic sensing element is particularly sensitive to in-plane or out-of-plane magnetic sensing elements. The in-plane magnetic sensing element refers to a magnetic sensing element that is sensitive to a magnetic field parallel to the substrate surface. The out-of-plane magnetic sensing element refers to a magnetic sensing element that is sensitive to a magnetic field perpendicular to the substrate surface.

[0049] The substrate is, for example, a wafer, such as a Si wafer (ie, silicon wafer), a SiO 2 wafer (ie, silicon dioxide wafer), or a SiO wafer (ie, silicon-on-insulator wafer). The substrate is, for example, a semiconductor substrate.

[0050] The photoresist material includes, for example, photoresist, in particular, negative-tone photoresist or positive-tone photoresist.

[0051] The term "resist" can also be used for "photoresist".

[0052] The descriptions of the method also apply to the magnetic sensor, and vice versa, which means that the technical functions and technical features of the magnetic sensor according to the second aspect are analogously derived from the corresponding technical functions and technical features of the method according to the first aspect, and vice versa.

[0053] For example, the magnetic sensor according to the second aspect is manufactured by means of the method according to the first aspect.

[0054] In the described sense, arranging comprises depositing, or for example depositing, in particular conformal deposition or non-conformal deposition. The expression "depositing" in particular comprises conformal deposition or non-conformal deposition.

[0055] The magnetic induction element is based on, for example, the AMR effect (anisotroper magnetoresistiver effect) and / or the GMR effect (giant magnetoresistance effect or Reisenmagnetowiderstand effect) and / or the TMR effect (tunnel magnetoresistance effect or magnetischer Tunnelwiderstand effect) or the Hall effect.

[0056] The expression "at least one" means "one or more".

[0057] When the singular form of the magnetic induction element is used, the plural form should always be understood, and vice versa. This also applies to the magnetic flow guiding element. For example, multiple such elements can be formed. This also applies to the recess. For example, multiple such recesses can be formed. Any description of a single recess also applies to multiple recesses, and vice versa.

[0058] For example, a plurality of depressions have a common, coherent seed layer in the described sense.

[0059] The magnetic material is or includes, for example, nickel-iron alloy (81:19).

[0060] Influencing in the described sense includes, for example, a (deflection) guidance and the resulting strengthening or weakening of the magnetic field at the induction element, or a change in the directional component of the magnetic field at the induction element.

[0061] The magnetic flow guiding element is configured in particular to influence the magnetic field, ie in particular to (deflect) guide and / or intensify or weaken the magnetic field reaching the inductive element.

[0062] In the sense of the description, the recess is limited or defined by the bottom and, for example, a single, optionally also curved, side wall or a plurality of adjacent, for example curved side walls. It should be noted that the term "side wall" can also be used as the term "inner wall" in general.

[0063] The side walls of the recess can, for example, extend perpendicularly to the bottom. The side walls of the recess can, for example, extend at an angle. The recess can, for example, have inclined side walls or inner walls. In cross section, this results in a funnel shape. For example, the recess has a funnel shape. In other words, the recess is, for example, a funnel-shaped recess. The base of the funnel can have various geometric shapes, such as, but not limited to, a rectangle, a plate that is larger than the sensing element, a rectangle with long and short sides (i.e., more like a strip), an n-gon (n>2), any pattern consisting of curved lines, or any combination of these, depending on the desired deflection effect. For example, directly adjacent side walls can be arranged at any angle to one another.

[0064] For example, the deep section can be configured with (slightly) inclined sidewalls. For example, the angle between the bottom and one or all of the sidewalls of the deep section can be between 90° and 110°, such that the bottom surface of the deep section is smaller than the opening of the deep section at the substrate surface (i.e., for example, the wafer surface), and the bottom of the deep section lies within the region of the opening at the substrate surface. This has the advantage that, despite alignment inaccuracies, the edge of the photoresist region can be preferably formed on the inclined sidewalls of the deep section, rather than within the bottom surface or outside the deep section. Consequently, despite alignment inaccuracies, at least a portion of the sidewalls (particularly the upper portion) is protected in any case, and, on the other hand, no bottom residue of dielectric material is formed at the bottom of the deep section, as will be described further below. For example, this can also be combined with a spacer process, e.g., as described above, by depositing and structuring additional dielectric material in addition to (before or after) the steps described, wherein a combination of conformal deposition of the additional dielectric material and anisotropic etching can, in particular, produce a layer of additional dielectric material on the sidewalls of the deep section. This has the advantage of a self-aligned process, thereby reducing residue at the bottom of the deep portion, combined with sufficient dielectric material on the sidewalls.

[0065] The side length of the base surface of the recessed portion can be, for example, several micrometers to several hundred micrometers.

[0066] In one embodiment of the method, the electrically conductive seed layer is structured such that at least one electrically conductive structure, in particular a conductor track-like structure, formed from the seed material is formed from an edge region of the substrate to the region of the at least one recess.

[0067] Therefore, the conductive seed material can also be optionally structured. Therefore, the electrical connection of the conductive seed material in the area of ​​the deepening can advantageously be achieved by means of such a conductive structure made of the conductive seed material. In addition, by means of structuring, the current flow to at least one deepening can advantageously be effectively influenced by means of the structure width and / or structure thickness. The structure comprises or is, for example, one or more conductor tracks. Therefore, the structure width is, for example, or comprises, a conductor track width. Therefore, the structure thickness comprises, for example, a conductor track thickness. The structure width and / or structure thickness of one or more conductor tracks can vary along their course or be implemented differently.

[0068] The diameter of the substrate is, for example, 150 mm, 200 mm or 300 mm. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The present invention will be described in more detail below with reference to the preferred embodiments.

[0070] Figure 1 Flowchart of a method for manufacturing a magnetic sensor,

[0071] Figures 2 to 13 a corresponding wafer in cross-sectional views at different points in time in a method for manufacturing a magnetic sensor,

[0072] Figure 14 Magnetic sensor in cross-sectional view,

[0073] Figure 15 In a method for manufacturing a magnetic sensor, a wafer in a cross-sectional view at a point in time,

[0074] and

[0075] Figure 16 Wafer in top view.

[0076] In the following, the same features may be given the same reference numerals. DETAILED DESCRIPTION

[0077] Figure 1 A flow chart showing a method for manufacturing a magnetic sensor, comprising the following steps:

[0078] producing 101 at least one recess in the surface of the front side of the substrate,

[0079] an electrically conductive seed material is deposited 103 on the surface of the substrate and on the surface including the side walls and the bottom of the at least one recess, in order to form a conductive seed layer which extends continuously from an edge region of the substrate into the recess, the conductive seed layer being electrically contactable in the edge region of the substrate (and the conductive seed layer can optionally be structured such that at least one electrically conductive structure, in particular a conductor track-like structure, formed from the seed material extends from an edge region of the substrate into the region of the at least one recess, wherein the structuring of the conductive layer is optionally provided while still ensuring continuous electrical contact),

[0080] depositing 105 an electrically insulating material (especially a dielectric material) directly onto the conductive seed layer to form an electrically insulating layer, especially a dielectric layer, directly on the conductive seed layer,

[0081] removing 107 the electrically insulating layer on the respective bottom of the at least one deep portion and in the edge region of the substrate, so that the electrically conductive seed layer is not covered by the electrically insulating layer at the respective bottom of the at least one deep portion and in the edge region of the substrate,

[0082] performing 109 a galvanizing process to grow a magnetic material on a surface of the conductive seed layer facing away from a corresponding bottom of the at least one deep portion to form at least one magnetic flow guiding element,

[0083] At least one magnetic induction element connected to the substrate is formed 111 such that the magnetic induction element is arranged higher than at least one magnetic flow guiding element composed of a zinc-grown magnetic material relative to the front side of the substrate.

[0084] The magnetic induction element is arranged higher relative to the front side of the substrate than the at least one magnetic flow guidance element consisting of zinc-grown magnetic material, which means in particular that the magnetic induction element is arranged inside and / or outside the region of the magnetic flow guidance element as viewed laterally.

[0085] Figure 2 A wafer 201 is shown in a cross-sectional view as an example of a substrate in the descriptive sense.

[0086] A dielectric layer 205 has been applied to the surface 203 of the front side 204 of the wafer 201. This can also be a dielectric layer system, for example a combination of SiO and SiO2. The wafer 201 has a back side 206 opposite the front side 204 of the wafer 201. In addition, the wafer 201 includes a first protection diode 207 and a second protection diode 209, which are located below the surface 203 of the wafer 201. It should be noted that the two protection diodes 207 and 209 are optional. In an embodiment not shown, other electronic circuits are provided instead of or in addition to the protection diodes 207 and 209. In an embodiment not shown, no such protection diodes 207 and 209 are provided, or a different number of such protection diodes are provided, or other electronic circuits are provided.

[0087] Figure 3 Wafer 201 is shown, onto which photoresist 301 has been applied. Photoresist 301 is an example of a photoresist material in the described sense. The photoresist has been structured by means of an exposure and development process, resulting in areas on surface 203 of wafer 201 where photoresist 301 is absent. This area is designated by reference numeral 303. As shown and described below, a recess will be etched into surface 203 of wafer 201 in this area 303.

[0088] The photoresist 301 is exposed and developed so as to be transparent in the subsequent etching process (such as Figure 4 ), the dielectric material 205 in the area not covered by the photoresist is first etched (removed), and then a deep portion 401 is etched into the surface 203 of the wafer 201. Figure 4 Wafer 201 is shown with photoresist 301 removed.

[0089] The recessed portion 401 is bounded or defined by a bottom 403 and a single, optionally curved, side wall or multiple adjacent side walls. It should be noted that the term "side wall" may also be used interchangeably with "inner wall." In the cross-sectional view, two reference numerals are used for the two side walls: a first side wall 405 and a second side wall 407. It should be noted that the first and second side walls 405, 407 may also be corresponding sections of a single curved side wall.

[0090] The edge length of the deepened portion 401 may be, for example, several micrometers to several hundred micrometers.

[0091] The diameter of the wafer 201 may be, for example, 150 mm, 200 mm, or 300 mm.

[0092] A desired recess 401 is etched into the wafer 201 using a photolithography process and, for example, an etching process (e.g., plasma etching). After a seed layer and an insulating layer are applied and structured in the etched recess, material is grown by an electroplating process (i.e., a deposition process) using zinc electroplating. This will be described further below.

[0093] Figure 5 The conformal deposition of a conductive seed layer is shown, which consists, for example, of a 20 nm to 300 nm thick metal (e.g., a layer sequence of Ta, TaN, Cu, Ti, TiN, NiFe, Cr or other conductive materials or combinations of these). The seed layer is provided with reference numeral 501. The seed layer 501 completely covers the front side of the wafer 204, in particular the side walls 405, 407 and the bottom 403. Thus, a coherently extending seed layer is formed in the described sense.

[0094] according to Figure 6 , a dielectric material is deposited. This dielectric material is, for example, SiO2, Si3N4, Al2O3, or a similar material, or a layer combination of these materials. In this arrangement, the dielectric material covers the entire front side of the wafer 204, so that the seed layer 501 is completely covered by the correspondingly formed dielectric layer (indicated by reference numeral 601).

[0095] Figure 7 The wafer 201 is shown during a photolithography process, according to which a photoresist 701 is applied to the wafer 201 and removed again in various areas by means of exposure and development (photolithography). Accordingly, the photoresist 701 has been removed from the bottom 403 and the edge region 705 of the wafer 201. The edge region 705 extends from the edge 703 to a predetermined distance from the edge 703. The edge 703 here refers to the outer wafer edge.

[0096] Therefore, in particular, a photolithography process is performed so that the bottom 403 of the deep portion 401 is free of photoresist 701, and the side walls 405 and 407 are covered with photoresist, and the other surfaces 203 of the substrate 201 (i.e., the unetched surface 203 (the surface outside the deep portion)) are covered with photoresist 701, and the edge area 705 is free of photoresist 701.

[0097] In order to overcome the high surface topography, for example, a spray-resist process (ie, Spray-Resist process) can be used. However, other methods can also be used to apply the photoresist.

[0098] according to Figure 8The dielectric material (i.e., dielectric layer 601) not covered by photoresist 701 is etched. Thus, the dielectric material is etched. The etching stops in the photoresist-free or photoresist-free area at the bottom 403 of the deep portion 401 and in the edge area 705 on the seed layer 501. Figure 8 Shown is an anisotropic etching process, i.e. directional etching, with high selectivity (etching rate ratio between dielectric layer and photoresist). That is to say, the etching process is in the direction (anisotropy) towards the bottom of the deep portion, and the etching rate of dielectric material is higher than the etching rate of photoresist and seed layer. This causes the edge of the deep portion to still be covered by dielectric material. After the etching process, the photoresist is removed. Anisotropy (lateral to vertical etching rate ratio), the selectivity of the etching process (the etching rate ratio of dielectric material and photoresist) and the thickness of the photoresist layer on the sidewall must be coordinated with each other so that after etching, the sidewall is still at least partially covered by dielectric material.

[0099] exist Figure 8 In the illustration shown, the resist or photoresist 701 has been removed.

[0100] The result is a structure that meets the requirements of the subsequent galvanizing process:

[0101] The bottom 403 of the deep portion 401 is provided with a conductive layer (seed layer 501 ), which has a coherent electrical contact with the wafer edge region 705 and / or the wafer edge 703 , so that electrical contact of the seed layer 501 can be made in the wafer edge region 705 .

[0102] All areas where magnetic material should not grow, ie, sidewalls 405 , 407 and the unetched surface 203 of wafer 201 , have an electrically insulating layer (dielectric layer 601 ) on the surface.

[0103] The edge region 705 of the wafer 201 is free of electrically insulating material and can therefore be used as an electrical connection for the zinc plating process.

[0104] By anisotropic etching, in the region of the transition between the sidewalls 405, 407 and the bottom 403, parts of the dielectric layer 601 may remain on the seed layer 501 in the region of the recessed bottom 403. Reference numerals 801 and 803 denote these regions.

[0105] according to Figure 9 Now, within the framework of this galvanizing process, magnetic material is grown on the seed layer 501 covering the bottom 403 of the excavation 401 to form an element 901 at least partially influencing the magnetic field (ie a magnetic flow guiding element).

[0106] The magnetic material is, for example, or includes NiFe.

[0107] Influencing in the described sense includes, for example, a (deflection) guidance and the resulting strengthening or weakening of the magnetic field at the induction element, or a change in the directional component of the magnetic field at the induction element.

[0108] Figure 10 The surface 203 of the wafer 201 is shown after a chemical mechanical polishing process is performed on the surface 203 of the wafer 201. Figure 9 In the wafer 201 shown, according to the polishing process, a portion of the dielectric layer 601 , the seed layer 501 and the SiO 2 layer 205 are removed to obtain a flat surface.

[0109] As a result, a magnetic element having a thickness of one to several micrometers is formed in the recessed portion 401 of the wafer 201. This magnetic element can, for example, serve as a shielding element, a deflecting element, a weakening element, or an enhancing element for the external magnetic field, without subjecting the wafer 201 to any or no significant increase in stress. Furthermore, such a wafer has a flat surface that is particularly suitable for subsequent processing using standard semiconductor processes.

[0110] In the described sense, a flat surface can be a surface with low topography, i.e., a surface with few protrusions or recesses in the Z direction (a perpendicular direction relative to the front side of the wafer (usually the substrate)). In the described sense, a planarized surface can be a surface that originally had topography but no longer has it after the planarization process, and is therefore also a flat surface.

[0111] Figures 11 to 13 Similar to Figures 8 to 10 The corresponding steps are shown, wherein the difference is that, in combination Figure 7 and Figure 8 Description of the etching frame, according to Figure 11 An isotropic and / or low-selectivity etch is performed. Isotropic here means having similar etching rates in all directions (i.e. also in the direction towards the sidewalls). In this case, low selectivity means similar etching rates for the dielectric material and the photoresist. This reduces the residues 801 and 803 described in the first variant.

[0112] Figure 14 Shows the use of Figure 10 Magnetic sensor 1400 is fabricated on wafer 201 shown in FIG. In this case, the function of the magnetic flow guiding element is to partially deflect the magnetic field in the planar direction (i.e., parallel to the wafer surface) toward the magnetic flow guiding element, thereby causing the magnetic field on the sensing element to be reduced and / or changed in direction, thereby weakening the sensor function and extending the sensing range.

[0113] Two magnetic sensing elements, namely, a first magnetic sensing element 1401 and a second magnetic sensing element 1403, are formed above element 901. Both magnetic sensing elements 1401 and 1403 can be electrically contacted from above via a common conductive contact structure 1405. From below, each of the two magnetic sensing elements 1401 and 1403 has its own conductive contact structure 1407 and 1409 for electrically contacting the respective magnetic sensing elements 1401 and 1403. Conductive contact structure 1407 contacts first magnetic sensing element 1401 from below and connects it to first protection diode 207. Conductive contact structure 1409 contacts second magnetic sensing element 1403 from below and connects it to second protection diode 209. However, any number of sensing elements can be connected differently from the one shown here, using the illustrated upper and lower contact structures or other contact structures (not shown) to form a suitable combination of series and parallel connections and / or Wheatstone bridge circuits.

[0114] The electrically conductive contact structures 1405 , 1407 , 1409 and the two magnetic sensing elements 1401 , 1403 are located within an electrically insulating layer 1411 or an electrically insulating layer sequence.

[0115] Figure 15 The wafer is shown at a point in time in the method for producing a magnetic sensor, which corresponds to Figure 9 or Figure 12 time point. Figure 15 The wafer 201 shown in FIG is substantially similar to Figure 12 2 . Here, too, an isotropic etching is performed, reducing residues 801 and 803 until they no longer exist. In this example, a dielectric layer 1501 is also applied between surface 203 and dielectric layer 205, which together with dielectric layer 205 forms a dielectric layer system. For example, further dielectric layer 1501 is a SiN layer, and dielectric layer 205 is, for example, a SiO2 layer.

[0116] Figure 15 The wafer 201 shown in FIG. Figure 12 Another difference between wafer 201 shown in FIG and FIG is that sidewalls 405 and 407 do not extend perpendicularly to bottom 403, but rather extend at an angle. Thus, deep portion 401 has inclined sidewalls or inner walls. In cross section, this forms a funnel shape. Therefore, deep portion 401 has a funnel shape. In other words, deep portion 401 is a funnel-shaped deep portion.

[0117] Therefore, the excavation 401 is constructed so that it has (slightly) inclined sidewalls. For example, the angle between the bottom 403 and one of the sidewalls 405, 407 of the excavation 401 can be between 90° and 110°, so that the bottom surface of the excavation 401 is smaller than the opening of the excavation 401 at the substrate surface 203 (in this case, the wafer surface), and the bottom 403 of the excavation 401 is laterally located within the region of the opening at the substrate surface 203. This has the advantage that, despite alignment inaccuracies, the edge of the photoresist region can be reliably formed on the inclined sidewalls 405, 407 of the excavation 401, rather than within the bottom surface or outside the excavation. Therefore, despite alignment inaccuracies, at least a portion (particularly the upper portion) of the sidewalls 405, 407 is protected in any case, and, on the other hand, the residues 801, 803 of dielectric material, as described above, do not occur. For example, this can also be combined with a spacer process, wherein, in addition to the described steps (before or after), additional dielectric material is deposited and structured, wherein, by a combination of conformal deposition of the additional dielectric material and anisotropic etching, an additional layer of dielectric material can be generated, especially on the sidewalls of the recessed section. This has the advantage of a self-aligned process, so that, combined with sufficient dielectric material on the sidewalls, residues at the bottom of the recessed section are reduced.

[0118] Figure 16 The wafer 201 is shown in a top view onto the front side 204. The wafer 201 is similar to Figure 14 , but is different in that it has a plurality of magnetic sensors 1400, which can be similar to those according to Figure 14 The magnetic sensor 1400 may be formed, or may be different from the magnetic sensor 1400 according to Figure 14 Magnetic sensor 1400. Therefore, according to Figure 16 The plurality of magnetic sensors 1400 partition a common wafer.

[0119] The figure also shows two edge regions: the outer edge region 705 corresponds to the contact region, where the conductive layer is not covered by the dielectric material. The inner edge region 1601 corresponds to the sealing region. The sealing region is completely covered by the dielectric material and can be used to seal (mechanically and electrically) between the zinc plating solution and the contacted wafer edge.

[0120] For example, in a general embodiment, it may be provided that after forming at least one magnetic induction element, one or more further magnetic flow guiding elements are formed such that these magnetic flow guiding elements are arranged higher than the at least one magnetic induction element relative to the front side of the substrate.

[0121] In other words, after forming the at least one magnetic induction element, the additional magnetic flow deflector and / or additional magnetic shielding element can be formed so that these elements are arranged higher than the at least one magnetic induction element relative to the front side of the substrate. Since these additional elements are applied after the induction element is fabricated, surface planarization is not necessary, which can save the corresponding planarization process. Furthermore, these additional elements can advantageously be manufactured using conventional semiconductor processes, making the overall method efficient.

[0122] In summary, the concept described here is based, inter alia, on the fact that, for example, a recess of several micrometers is first etched into the surface of a substrate (e.g., a silicon wafer or SiO2 wafer), wherein, after applying a seed layer and applying and structuring a dielectric layer in the etched silicon structure, the magnetic material is grown by an electrogalvanizing process. For example, one or more of the following steps are provided:

[0123] A structured photoresist mask and / or a structured hard mask is generated and the desired structure (deep section) is plasma-etched into a silicon wafer (i.e., silicon material), in particular to a depth of several micrometers. For example, known methods (e.g., plasma or wet etching methods) can be used to etch deep silicon structures. The method can also be applied to SiO2 wafers; in this case, the deep section is etched into the SiO2.

[0124] For example, a dielectrically conductive seed layer is deposited, in particular conformally deposited, for example a 20 nm to 300 nm thick metal (eg Ta, TaN, Cu, Ti, TiN, NiFe or other conductive materials or layer combinations of these materials).

[0125] For example, a dielectric material is deposited, especially conformally deposited, such as SiO2 or SiO X Either Si3N4 or SiON or Al2O3 or similar materials, or layer combinations of these materials.

[0126] For example, a photolithography process is performed, which in particular ensures that the bottom of the recess is free of photolithography material, in particular free of photoresist.

[0127] The photolithography process is performed at least in such a way that the sidewalls of the recessed portion are at least partially covered by a photolithography material (in particular a photoresist).

[0128] For example, the photolithography process is performed in such a manner that the unetched surface of the substrate (ie, the surface outside the recessed portion except for the edge region) is covered with a photolithography material (especially photoresist).

[0129] The photolithography process is performed, for example, in such a way that the wafer edge and in particular the corresponding edge region are free of photolithographic material (in particular photoresist).

[0130] To overcome high surface topography during photoresist coating, for example, a spray photoresist process may (but is not required to) be performed.

[0131] For example, etching of the dielectric material is performed, wherein the dielectric material is removed in the photoresist-free areas at the bottom of the recess and in the edge region, and the etching stops on the conductive material (ie, on the seed layer).

[0132] For example, removing photoresist materials, especially photoresist.

[0133] The result is, for example, a structure that meets the requirements of the subsequent galvanizing process:

[0134] The bottom of the recess is provided with a conductive layer which has a continuous electrical contact to the edge of the wafer.

[0135] With the exception of the edge region 705 , all regions in which material should not grow, ie the sidewalls and the surface of the wafer outside the at least one recess, have an electrically insulating layer.

[0136] The wafer edge is at least partially free of electrically insulating material and can serve as an electrical connection terminal during the galvanizing process.

[0137] For example, a galvanizing process can now be carried out using such a structure, wherein, during the galvanizing process, magnetic material (eg NiFe) is gradually grown starting from the open area at the bottom of the excavation.

[0138] After the growth of the magnetic material, ie after the magnetic flow guiding elements are formed, another dielectric layer can be deposited.

[0139] Subsequently, for example, a chemical mechanical polishing process may be performed to remove a portion of the dielectric at the surface of the silicon wafer to planarize the surface, ie, reduce the surface topography of the surface.

[0140] For example, the chemical mechanical polishing process can be further performed, after completely removing the upper dielectric layer in at least some areas, and then additionally removing parts of other dielectric layers, seed layers, carrier materials and magnetic materials to further flatten the surface and, in particular, to reduce the distance between the magnetic flow guiding element and the substrate surface, thereby shortening the distance to the inductive element to be subsequently installed.

[0141] The result is, in particular, an element made of soft magnetic material and having a thickness of up to several microns, which is capable of at least partially influencing an external magnetic field, in particular deflecting it, thereby increasing, decreasing, and / or changing the direction of the magnetic field on the inductive element—in other words, a magnetic flux guiding element. This element is formed within the recessed portion. For example, the method described here has the advantage that the wafer is not subjected to significantly increased stresses and does not experience excessive bending. Furthermore, the method proposed here has the technical advantage that, after the element is manufactured from magnetic material, a flat surface of the substrate (in particular, a silicon wafer or SiO2 wafer) is achieved, which is advantageously suitable for subsequent processing using standard semiconductor processes and, in particular, for the arrangement of magnetic inductive elements.

[0142] As previously mentioned Figure 8 and Figure 11 As described, the dielectric layer can be etched isotropically or anisotropically. If the anisotropic etching ratio is high in the etching, and the selectivity between the photoresist (especially the photoresist), the dielectric material and the seed layer is high, then at the bottom of the deep portion, a residual structure of the dielectric material will be formed along the sidewall (which may also be referred to as the wall portion). If the isotropic etching ratio is higher in the etching, and / or the etching rate selectivity to the photoresist is low, then this residual structure composed of the dielectric material will be less constructed in the bottom area, or may even be avoided completely. Alternatively, the deep portion can also be constructed so that the deep portion has slightly inclined sidewalls. For example, the angle between the bottom of the deep portion and the sidewall can be between 90° and 110°, so that the bottom surface of the deep portion is smaller than the opening of the deep portion at the substrate surface, and the bottom of the deep portion is located within the range of the opening area at the substrate surface. This has the following advantages, even if there is alignment inaccuracy, the edge of the photoresist area can be reliably formed on the inclined sidewall, and will not appear inside the bottom surface or outside the deep portion. Therefore, even in the presence of alignment inaccuracies, at least a portion of the sidewalls (particularly the upper portion) can be protected in this case, and no bottom residue of dielectric material, as described above, is generated. This can also be combined with a spacer process, whereby, in addition to the above steps (before or after), additional dielectric material is deposited and structured. The additional layer of dielectric material is generated, particularly on the sidewalls of the deep cut, by a combination of conformal deposition of the additional dielectric material and anisotropic etching. This has the following advantages: a self-aligned process, thereby reducing residue at the bottom of the deep cut, while maintaining sufficient dielectric material on the sidewalls.

[0143] Therefore, based on the solution proposed here, the problem of surface morphology and wafer stress generated by electroplating in a coated and structured photoresist or dielectric layer can be advantageously solved by manufacturing the structure in the semiconductor substrate (especially a silicon wafer or SiO2 wafer) itself, that is, by making one or more recessed portions in the wafer, wherein a conductive layer (i.e., a seed layer) is deposited on these surface morphologies and the areas where material should not grow are covered with a dielectric material.

[0144] With the solution proposed here, it is advantageously possible to deposit magnetic materials with a thickness of up to several micrometers by means of selective electroplating.

[0145] Furthermore, at the end of the zinc plating process, the wafer surface can advantageously have little or no surface topography, so that it is suitable for efficient subsequent processing using standard semiconductor processes.

[0146] Compared to the known prior art described above, the method proposed here produces no or only minimal additional wafer bowing, because instead of applying a thick material with a different expansion coefficient than silicon to the wafer surface, a very thin layer (e.g., 20–300 nm) is applied in a recess in the substrate (silicon or SiO2). Specifically, multiple or a single recess is provided in the wafer, within which the magnetic material is to be grown. This effectively solves the problem of wafer bowing and all its attendant consequences, or at least significantly mitigates it.

[0147] If the method is designed to use protection diodes, so-called EMC diodes (EMC stands for electromagnetic compatibility), or other electrical or electronic circuits that may need to be electrically connected to one or more magnetic sensing elements, then, when using silicon wafers, these can advantageously be produced in advance in the wafer itself. This, unlike the prior art described above, does not present any problems, as they can be arranged on the wafer surface next to the etched or plated structures. Since, in the proposed solution, no thick dielectric layers are required through which the electrical contact structures must be produced, contacting is significantly simpler and more space-saving.

[0148] Therefore, in particular, an electroplated element made of magnetic material is proposed, which, unlike the prior art described above, is surrounded by a substrate material, is separated from the substrate material at least at the side walls of the recess by at least one layer of dielectric material, and is separated from the substrate material at the bottom and side walls of the recess by a seed layer.

Claims

1. A method for manufacturing a magnetic sensor (1400), comprising the following steps: producing (101) at least one recess (401) in the surface (203) of the front side (204) of the substrate (201), Depositing (103) a conductive seed material on the surface (203) of the substrate (201) and on the surface including the bottom (403) of the at least one deep portion (401) to form a conductive seed layer (501) extending continuously from an edge region (705) of the substrate (201) into the deep portion (401), the conductive seed layer being electrically contactable in the edge region (705) of the substrate (201), depositing (105) an electrically insulating material, in particular a dielectric material, onto the conductive seed layer (501) to form an electrically insulating layer (601), in particular a dielectric layer, on the conductive seed layer (501), removing (107) the electrically insulating layer (601) at the respective bottom (403) of the at least one deepening (401) and, in particular, at least partially in the edge region (705) of the substrate (201), so that the electrically conductive seed layer (501) is not covered by the electrically insulating layer (601) at the respective bottom (403) of the at least one deepening (401) and in the edge region (705) of the substrate (201), performing (109) a zinc plating process to grow magnetic material on a surface of the conductive seed layer (501) facing away from the corresponding bottom (403) of the at least one deep portion (401), thereby forming at least one magnetic flow guiding element (901), At least one magnetic induction element (1405, 1407, 1409) connected to the substrate (201) is formed (111) so that the magnetic induction element is arranged higher than the at least one magnetic flow guiding element (901) composed of a zinc-grown magnetic material relative to the front side (204) of the substrate (201).

2. The method according to claim 1, wherein Removing the electrically insulating layer comprises performing a photolithographic process according to which the electrically insulating layer to be removed, in particular the dielectric layer, is at least partially removed from the electrically conductive seed layer (501) by means of an etching process.

3. The method according to claim 1 or 2, wherein After performing the zinc plating process, and in particular after depositing another dielectric layer, a chemical mechanical polishing process is performed on the surface (203) of the substrate (201) to form a flat surface.

4. A method according to any one of the preceding claims, wherein The seed crystal material includes one or more of the following materials: Ta, TaN, Cu, Ti, TiN, Cr and NiFe.

5. A method according to any one of the preceding claims, wherein The conductive seed crystal material is deposited on the bottom (403) of the deep portion (401) so that the layer thickness of the conductive seed crystal layer (501) on the bottom (403) of the deep portion (401) is within an open interval, a semi-open interval or a closed interval of 20nm to 300nm.

6. A method according to any one of the preceding claims, wherein The conductive seed layer (501) is structured so that at least one conductive structure, in particular a conductor track-like structure, formed from the seed material is constructed in the region from the edge region (705) of the substrate (201) to the at least one recess (401).

7. A method according to any one of the preceding claims, wherein The dielectric material includes one or more of the following materials: SiO2, SiON, SiO X , Si3N4 and Al2O3.

8. A method according to any one of the preceding claims, wherein In order to reinforce the electrically insulating material at one or more sidewalls (405, 407) of the at least one deepening (401), a spacer process is performed before depositing the electrically insulating material.

9. A magnetic sensor (1400), comprising: a substrate (201), wherein at least one deep portion (401) is formed in the surface (203) of the front side (204) of the substrate (201), A conductive seed crystal layer (501) is formed on the surface (203) of the substrate (201) and on the surface including the bottom (403) of the at least one deep portion (401), extending continuously from the edge region (705) of the substrate (201) into the deep portion (401). wherein an electrically insulating layer (601), in particular a dielectric layer, is formed on the surface of the electrically conductive seed layer (501), wherein the electrically conductive seed layer (501) is not covered by the electrically insulating layer (601), in particular at least partially, at the respective bottom (403) of the at least one deepening (401) and in the edge region (705) of the substrate (201), wherein at least one magnetic flow guiding element (901) composed of a zinc-grown magnetic material is formed on the conductive seed crystal layer (501) at the corresponding bottom (403) of the at least one deep portion (401); At least one magnetic induction element (1405, 1407, 1409) connected to the substrate (201) is formed so that, relative to the front side (204) of the substrate (201), the magnetic induction element is arranged higher than the at least one magnetic flow guiding element (901) composed of a zinc-grown magnetic material.

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