Rapid short circuit detection circuit for switching device

Abstract

The invention discloses a rapid short-circuit detection circuit for a switching device, and relates to the technical field of switching devices. The input end of the voltage judgment module is used for being connected with a grid resistor, the output end of the voltage judgment module is connected with the processing unit, and when the grid voltage is larger than the reference voltage, a first trigger signal is sent to the processing unit; the input end of the charge judgment module is used for being connected with a grid resistor, the output end of the charge judgment module is connected with the processing unit, and when the grid charge quantity is larger than the reference charge quantity, a second trigger signal is sent to the processing unit; wherein the ratio of the reference voltage to the gate voltage when the reference voltage is completely switched on is larger than or equal to 0.9 and smaller than 1, and the value range of the reference charge quantity is larger than the gate charge quantity when the hard switch fails and smaller than the gate charge quantity when the soft switch is switched on. According to the invention, the value ranges of the reference voltage and the reference charge quantity are designed to distinguish short circuit and soft and hard switch working conditions, and rapid short circuit detection of the switch device is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching devices, and in particular relates to a fast short-circuit detection circuit for switching devices. Background Art

[0002] Short-circuit failures in power devices can be categorized as either Type I or Type II. Type I short circuits occur when the upper and lower transistors of the same bridge arm are simultaneously turned on, creating a short-circuit loop between the bridge arm and the power supply. This occurs primarily when a device in either the upper or lower arm fails to shut down properly, causing the other device to short-circuit at the moment of turn-on. This type of short circuit is also known as a hard switch fault (HSF). During a hard switch fault, the parasitic inductance of the short-circuit loop is very small. Therefore, at the moment of turn-on, the drain-source voltage of the power device drops slightly before quickly recovering. The current flowing through the device quickly reaches its peak short-circuit current. Subsequently, due to rising temperature, the electron mobility within the device's inversion layer decreases, increasing the device impedance and causing the current to decrease. During this short period of time, the device experiences a significant amount of short-circuit energy, which can easily lead to device failure. Type II short circuits occur between bridge arms. This occurs when the load is suddenly short-circuited during normal circuit operation, often referred to as a fault under load (FUL). In the case of a load fault, due to the large parasitic inductance in the short-circuit loop, the current passing through the device and the voltage across the two ends rise slowly, making it more difficult to detect than a Class I short circuit. More energy is stored in the short circuit, and a larger spike is often generated during the shutdown protection process.

[0003] Short-circuit detection options currently include desaturation detection, gate charge detection, current detection, voltage detection, parasitic inductance voltage detection, and PCB Rogowski coil detection. Gate charge detection offers advantages such as high detection speed, high bandwidth, and the absence of a Kelvin source device. However, it lacks the ability to detect Class II short-circuits.

[0004] Desaturation detection requires a blanking time to prevent false turn-on, so even the fastest desaturation detection methods currently available require a detection time of approximately 1μs. While current SiC MOSFETs are continuously improving their short-circuit withstand time through structural optimization, these improvements are limited, and continuing to use desaturation detection may not meet the needs of future hybrid devices.

[0005] Therefore, there is an urgent need to develop a fast short circuit detection circuit for switching devices to solve the problems in the existing technology. Summary of the Invention

[0006] The application aims to provide a switching device fast short circuit detection circuit, which distinguishes short circuit and soft and hard switching conditions by designing the value range of reference voltage and reference charge amount, and realizes fast short circuit detection of the switching device, so as to solve the technical problem that the gate charge detection in the background technology cannot detect the second type short circuit condition.

[0007] To solve the above technical problems, the specific technical solutions of the application are as follows:

[0008] A switching device fast short circuit detection circuit, characterized in that it comprises:

[0009] a processing unit;

[0010] a voltage determination module, an input end of the voltage determination module being used for connection with a driving resistor, and an output end of the voltage determination module being connected with the processing unit, the voltage determination module being used for comparing a gate voltage with a reference voltage, and sending a first trigger signal to the processing unit when the gate voltage is greater than the reference voltage;

[0011] a charge determination module, an input end of the charge determination module being used for connection with the driving resistor, and an output end of the charge determination module being connected with the processing unit, the charge determination module being used for comparing a gate charge amount with a reference charge amount, and sending a second trigger signal to the processing unit when the gate charge amount is greater than the reference charge amount;

[0012] wherein the ratio of the reference voltage to the gate voltage when the switch is fully opened is greater than or equal to 0.9 and less than 1, and the value range of the reference charge amount is greater than the gate charge amount when the switch is in hard switching failure and less than the gate charge amount when the switch is in soft opening.

[0013] Further, the charge determination module comprises:

[0014] an instrument amplification module, which is used for sampling and amplifying the gate current;

[0015] an integration module, an input end of the integration module being connected with an output end of the instrument amplification module, and the integration module being used for continuously integrating the gate current;

[0016] a comparison module, an input end of the comparison module being connected with an output end of the integration module, an output end of the comparison module being connected with the processing unit, and the comparison module being used for comparing the integration module output voltage with the charge amount voltage, and sending the second trigger signal to the processing unit when the integration module output voltage is greater than the charge amount voltage; wherein the value range of the charge amount voltage is greater than the integration module output voltage when the switch is in hard switching failure and less than the integration module output voltage when the switch is in soft opening.

[0017] Further, the instrument amplification module comprises a first amplifier, a second amplifier and a third amplifier.

[0018] The non-inverting input terminal of the first amplifier and the non-inverting input terminal of the second amplifier are respectively used to connect to the two ends of the driving resistor; the inverting input terminal of the first amplifier is connected to the inverting input terminal of the second amplifier through a fifth resistor;

[0019] The output end of the first amplifier is connected to the non-inverting input end of the third amplifier through an eighth resistor; the output end of the second amplifier is connected to the inverting input end of the third amplifier through a ninth resistor; and the non-inverting input end of the third amplifier is also grounded through a tenth resistor;

[0020] The inverting input terminal and the output terminal of the first amplifier are further connected via a sixth resistor; the inverting input terminal and the output terminal of the second amplifier are further connected via a seventh resistor; and the inverting input terminal and the output terminal of the third amplifier are further connected via an eleventh resistor.

[0021] Furthermore, the integration module includes a fourth amplifier, the inverting input terminal of the fourth amplifier is connected to the output terminal of the instrument amplifier module through a resistor; the non-inverting input terminal of the fourth amplifier is grounded through a resistor, and a parallel capacitor, resistor and analog switch are also connected between the inverting input terminal and the output terminal of the fourth amplifier, and the control terminal of the analog switch is connected to the processing unit, and the processing unit controls the on and off of the analog switch.

[0022] Furthermore, the comparison module includes a second comparator, the non-inverting input terminal of the second comparator is connected to the fifteenth resistor, the inverting input terminal of the second comparator is connected to the charge voltage, and the output terminal of the second comparator is connected to the processing unit through the sixteenth resistor.

[0023] Furthermore, it also includes a voltage divider module, the input end of the voltage divider module is used to connect to the driving resistor, and the output end is connected to the voltage determination module and the charge determination module. The voltage divider module is used to divide the voltage drop on the driving resistor and connect the voltage determination module and the charge determination module to the driving resistor.

[0024] Furthermore, the voltage divider module includes a first voltage divider unit and a second voltage divider unit, the first voltage divider unit includes a first resistor, one end of the first resistor is connected to the first end of the driving resistor, and the other end is grounded through the second resistor and serves as the first output end of the voltage divider module;

[0025] The second voltage dividing unit includes a third resistor, one end of the third resistor is connected to the second end of the driving resistor, and the other end is connected to the second resistor through a fourth resistor and grounded and serves as the second output end of the voltage dividing module.

[0026] Furthermore, the voltage determination module includes a first comparator, the non-inverting input terminal of the first comparator is connected to the second end of the driving resistor through the voltage divider module, the inverting input terminal is connected to the reference voltage, and the output terminal is connected to the processing module through the resistor.

[0027] Furthermore, the processing unit includes an FPGA, which is connected to the output ends of the voltage determination module and the charge determination module through a digital channel isolator to receive a first trigger signal and a second trigger signal; the FPGA is connected to the control end of the analog switch through the digital channel isolator to control the on and off of the analog switch.

[0028] Furthermore, an auxiliary detection module is included, and the auxiliary detection module includes:

[0029] A comparator, wherein the non-inverting input terminal of the comparator is connected to the voltage through a resistor, the inverting input terminal is connected to the auxiliary detection voltage, and the output terminal is connected to the FPGA through a resistor and a digital channel isolator;

[0030] A diode, wherein the anode of the diode is connected to the non-inverting input terminal of the comparator, and the cathode of the diode is used to be connected to the drain of the switching device to be tested.

[0031] The present invention has the following advantages:

[0032] (1) This application designs the range of reference voltage and reference charge to distinguish between short circuit and soft and hard switching conditions, thereby realizing blind-zone detection of hard switching faults. While ensuring detection accuracy, it can greatly accelerate the short circuit detection speed of the hybrid device, provide faster protection for the device, and improve the reliability of the hybrid device.

[0033] (2) This application fully utilizes the advantages of the gate charge detection circuit in rapid detection under hard switching faults by designing an instrument amplifier module, and the detection time remains stable under different working conditions. At the same time, the designed instrument amplifier module makes the sampling bandwidth wider and the distortion of the signal waveform smaller, and can restore the switching signal to the maximum extent, thereby greatly reducing the short-circuit energy suffered by the device. When the switching device is MOSFET, compared with the traditional desaturation detection method, only 1 / 18 of the detection response time is required, and the short-circuit energy suffered is only 1 / 3.

[0034] (3) This application introduces an auxiliary detection module to correct desaturation detection errors, which is beneficial to improving the accuracy of detection and enhancing the reliability of the device.

[0035] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1This is a circuit diagram of the overall structure of embodiment 1 of the present invention;

[0037] Figure 2 This is a schematic diagram of the overall structure of the second embodiment of the present invention;

[0038] Figure 3 This is a logic block diagram of hard switch fault detection according to the second embodiment of the present invention;

[0039] Figure 4 The output signal waveforms of the present invention under hard switch fault and normal soft switching are shown respectively;

[0040] Figure 5 A comparison chart of hard switch fault detection time under different working conditions between the present invention and the existing desaturation detection technology;

[0041] Figure 6 This is a comparison diagram of the hard switch fault short-circuit energy borne by the hybrid device under different working conditions between the present invention and the existing desaturation detection technology. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. In this application, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0043] When in use, the switching device generally includes a switching device and a driver connected to the control terminal of the switching device through a driving resistor, wherein, Figure 1 As shown, when the switching device is a SiC MOSFET, it includes a SiC driver, a gate resistor, and a SiC MOSFET. The first end of the gate resistor is connected to the SiC driver, and the second end is connected to the gate of the SiC MOSFET.

[0044] Example 1

[0045] This embodiment provides a fast short circuit detection circuit for a switching device, which is applicable to switching devices with Miller platform phenomenon, such as Figure 1 Shown, including:

[0046] processing unit;

[0047] a voltage determination module, wherein the input end of the voltage determination module is used to be connected to the gate resistor, the output end of the voltage determination module is connected to the processing unit, and when the gate voltage is greater than the reference voltage, the first trigger signal is sent to the processing unit;

[0048] a charge determination module, wherein the input end of the charge determination module is connected to the gate resistor, the output end of the charge determination module is connected to the processing unit, and when the gate charge amount is greater than the reference charge amount, the second trigger signal is sent to the processing unit;

[0049] Among them, the ratio of the reference voltage to the gate voltage when fully turned on is greater than or equal to 0.9 and less than 1, preferably greater than or equal to 0.9 and less than or equal to 0.95, and the reference charge value range is greater than the gate charge during hard switching failure and less than the gate charge during soft turning on.

[0050] Among them, the switching devices that have the Miller platform phenomenon include power devices such as SiC MOSFET and IGBT.

[0051] The reference voltage V in the voltage detection module REF1 The value is set to a voltage close to the fully turned-on voltage to avoid I DS The effect of rapid rise on the voltage drop across the source parasitic inductance is REF1 A detection point trigger signal is issued when the gate charge under normal turn-on and hard switching fault is significantly different.

[0052] The value of the reference charge in the charge determination module is selected between the gate charge of soft turn-on and the gate charge of hard switch fault, so as to distinguish between normal turn-on and hard switch fault.

[0053] Setting the detection point above the Miller platform and before the nearly fully turned-on state during the switching process can improve the reliability of detection under different operating conditions. The gate charge required during soft turn-on is used as a reference. Even if there is no Miller platform during soft turn-on, the drain-source voltage during soft turn-on is close to 0V, while the drain-source voltage during hard switching faults is close to the bus voltage. Therefore, the parasitic capacitance during hard switching faults is smaller than that during soft turn-on, and the gate charge flowing during soft turn-on will be correspondingly greater than that during hard switching faults.

[0054] In the event of a hard switching fault, the V DS It hardly decreases, so V GS The Miller platform in the rising process disappears, and the gate charge, which is the area enclosed by the gate current over time, is also smaller than that in hard turn-on. Therefore, the abnormal decrease in gate charge during the turn-on process can be detected to determine the occurrence of hard switching faults.

[0055] It also includes a voltage divider module, the input end of the voltage divider module is used to connect to the gate resistor, and the output end is connected to the voltage determination module and the charge determination module. The voltage divider module is used to divide the voltage drop on the gate resistor and connect the voltage determination module and the charge determination module to the gate resistor.

[0056] The voltage divider module includes a first voltage divider unit and a second voltage divider unit, the input end of the first voltage divider is connected to the first end of the gate resistor, and the input end of the second voltage divider unit is connected to the second end of the gate resistor, wherein the first end of the gate resistor is an end close to the driving module, and the second end is an end close to the switching device to be tested.

[0057] The first voltage dividing unit includes a first resistor R1, one end of the first resistor R1 is connected to the gate resistor R Gmos The first end of the voltage divider module is connected to the first end of the voltage divider module, and the other end is grounded through the second resistor R2 and serves as the first output end of the voltage divider module.

[0058] The second voltage dividing unit includes a third resistor R3, one end of the third resistor R3 is connected to the gate resistor R Gmos The other end is connected to the second resistor R2 through the fourth resistor R4 and is grounded and serves as the second output end of the voltage divider module.

[0059] Preferably, in this embodiment, the first voltage divider unit and the second voltage divider unit both have a voltage divider ratio of 9:1, which effectively improves the stability and reliability of the circuit. This application sets the above-mentioned voltage divider module to avoid generating large common-mode interference.

[0060] Due to the SiC MOSFET's rapid turn-on speed, the gate voltage rise rate of the SiC MOSFET exceeds 2000V / μs during a short circuit at a 600V bus voltage, with a frequency component exceeding 100MHz on the rising edge. The current feedback op amp in this design has a maximum output slew rate of up to 8000V / μs, capable of withstanding a high supply voltage of up to 28V. Even when outputting a 10V peak signal into a 100Ω load, it still maintains a bandwidth of 320MHz and an output capacity of 400mA, meeting sampling requirements. Considering both sampling accuracy and the need to limit the power consumption of the detection circuit, the instrumentation amplifier's power supply is set to ±8V. At this supply voltage, the selected current feedback op amp has an undistorted output range of approximately ±6V. In this embodiment, R1 and R3 in the voltage divider circuit are 9.09kΩ resistors, and R2 and R4 are 1kΩ resistors, providing a 9:1 voltage divider on the input signal. Excessively large voltage divider ratios can lead to significant circuit interference, and the subsequent amplifier gain must be increased, which can easily introduce distortion, zero drift, and other issues, making sampling accuracy difficult to guarantee. If the voltage divider ratio is too small, power consumption will increase and the temperature drift problem will be aggravated. Therefore, the appropriate voltage divider ratio range should be at least between 6:1 and 18:1.

[0061] The voltage determination module includes a first comparator CMP1, the non-inverting input terminal of the first comparator CMP1 is connected to the gate resistor R through a voltage divider module. Gmos The second end of the inverting input terminal is connected to the reference voltage, and the output terminal is connected to the processing module through a resistor.

[0062] In this embodiment, the reference voltage is set at 1.7V, which is 17V before 9:1 voltage division. It is a value higher than the Miller platform and is basically in a fully conductive state. It is not easy to cause false triggering of short circuit detection, thereby improving the reliability of detection.

[0063] The charge determination module includes:

[0064] An instrument amplifier module, wherein the input end of the instrument amplifier module is connected to both ends of the gate resistor through a voltage divider module, and is used for sampling and amplifying the gate current;

[0065] an integration module, wherein an input end of the integration module is connected to an output end of the instrument amplifier module and is used to realize continuous integration of the gate current;

[0066] A comparison module, wherein the input end of the comparison module is connected to the output end of the integration module, and the output end of the comparison module is connected to the processing unit, for comparing the output voltage of the integration module with the charge voltage V REF2 When the output voltage of the comparison integration module is greater than the charge voltage, a second trigger signal is sent to the processing unit; wherein the value range of the charge voltage is greater than the output voltage of the integration module during hard switching failure and less than the output voltage of the integration module during soft switching.

[0067] Hard turn-on and soft turn-on cause more gate charge to flow than in short-circuit conditions. The gate charge is directly proportional to the integral value output by the integral module. Therefore, the output value of the integral module is selected within the range between soft turn-on and short-circuit turn-on.

[0068] According to the experimental results, when the SiC MOSFET is hard-on and soft-on, the integral values ​​output by the integration module are 6.2V and 5.6V respectively. In the case of a short circuit, the output voltage of the integration module is less than 3.3V. Therefore, 5V is selected as the charge voltage V of the comparison module. REF2 More suitable.

[0069] The instrument amplifier module includes a first amplifier AMP1, a second amplifier AMP2 and a third amplifier AMP3.

[0070] The non-inverting input terminal of the first amplifier AMP1 is connected to the second output terminal of the voltage divider module.

[0071] The non-inverting input terminal of the second amplifier AMP2 is connected to the first output terminal of the voltage divider module.

[0072] The inverting input terminal of the first amplifier AMP1 is connected to the inverting input terminal of the second amplifier AMP2 through a fifth resistor R5;

[0073] The output terminal of the first amplifier AMP1 is connected to the non-inverting input terminal of the third amplifier AMP3 through the eighth resistor R8;

[0074] The output terminal of the second amplifier AMP2 is connected to the inverting input terminal of the third amplifier AMP3 through a ninth resistor R9;

[0075] The non-inverting input terminal of the third amplifier AMP3 is also grounded via a tenth resistor R10.

[0076] The inverting input terminal and the output terminal of the first amplifier AMP1 are further connected via a sixth resistor R6;

[0077] The inverting input terminal and the output terminal of the second amplifier AMP2 are further connected via a seventh resistor R7;

[0078] The inverting input terminal and the output terminal of the third amplifier AMP3 are further connected via an eleventh resistor R11.

[0079] The instrument amplifier module includes a first input terminal, a second input terminal, and an output terminal. In this embodiment, the non-inverting input terminal of the first amplifier AMP1 serves as the first input terminal of the instrument amplifier module, the non-inverting input terminal of the second amplifier AMP2 serves as the second input terminal of the instrument amplifier module, and the output terminal of the third amplifier AMP3 serves as the output terminal of the instrument amplifier module.

[0080] The integration module includes a fourth amplifier AMP4, the inverting input terminal of the fourth amplifier AMP4 is connected to the output terminal of the instrument amplifier module through a twelfth resistor R12; the non-inverting input terminal of the fourth amplifier AMP4 is grounded through a thirteenth resistor R13, and a capacitor C1, a fourteenth resistor R14 and an analog switch S1 are further connected in parallel between the inverting input terminal and the output terminal of the fourth amplifier AMP4. The control terminal of the analog switch S1 is connected to the processing unit, and the processing unit controls the on and off of the analog switch S1.

[0081] The structure of the instrument amplifier module can resolve the conflict between input impedance and bandwidth. The instrument amplifier module includes a current feedback operational amplifier and adopts unity gain sampling. Its high slew rate and large bandwidth can meet the requirements of rapid changes in sampling end current and restore the real signal to the maximum extent.

[0082] The integration module includes an input end, an output end and a control end. The output end of the fourth amplifier AMP4 serves as the output end of the integration module, the control end of the analog switch S1 serves as the control end of the integration module, one end of the twelfth resistor R12 serves as the input end, and the other end is connected to the inverting input end of the fourth amplifier AMP4.

[0083] The comparison module includes a second comparator CMP2, a non-inverting input terminal of the second comparator CMP2 is connected to the fifteenth resistor R15, an inverting input terminal of the second comparator CMP2 is connected to the charge voltage, and an output terminal of the second comparator CMP2 is connected to the processing unit through the sixteenth resistor R16.

[0084] In this embodiment, the processing unit includes an FPGA, which is connected to the output end of the comparison module through a digital channel isolator and to the output end of the voltage determination module through a digital channel isolator, and is used to receive signals from the comparison module and the voltage determination module; and is connected to the control end of the analog switch S1 of the integration module through a digital channel isolator, and is used to control the on and off of the analog switch S1. When the drive signal PWM is at a high level, the analog switch S1 is disconnected, and when the drive signal PWM is at a low level, the analog switch S1 is closed, so that the integration module is enabled and reset.

[0085] The digital channel isolator is used to convert the first trigger signal and the second trigger signal into digital signals and provide them to the FPGA. When the FPGA receives the digital signals converted from the first trigger signal and the second trigger signal, it turns off the switching device.

[0086] When a hard switching fault occurs, the device’s V DS&CE It will not drop to a low voltage and is near the bus voltage. The Miller platform disappears during the rising process of the gate voltage, and the gate charge passing through the gate during the opening process decreases. The instrument amplifier module is used to sample and amplify the current of the gate resistor, and the gate charge is measured through the integration module. When the charge is less than the gate charge that should be at soft opening, it is considered that a hard switching fault has occurred. The comparison module outputs an analog fault signal, which is then converted into a digital signal by the digital channel isolator and sent to the FPGA digital control module.

[0087] Existing short-circuit detection technologies primarily rely on desaturation detection. In contrast, this design proposes a short-circuit detection driver circuit that leverages the significant change in SiC MOSFET gate charge during hard-switching faults to achieve fast and stable detection, significantly reducing the energy experienced by the hybrid device during a short-circuit event. In the event of a hard-switching fault, the detection response time is 1 / 18th that of desaturation detection, and the short-circuit energy experienced by the MOSFET is only 1 / 3 that of a desaturation detection circuit.

[0088] Example 2

[0089] This embodiment differs from the first embodiment in that it further includes an auxiliary detection module, which includes:

[0090] Comparator CMP5, the non-inverting input terminal of the comparator CMP5 is connected to the auxiliary voltage V through the resistor R27 C Connect the inverting input terminal to the auxiliary detection voltage V REF4 The output end is connected to the FPGA through resistor R28 and digital channel isolator;

[0091] A diode D1 , wherein the anode of the diode D1 is connected to the non-inverting input terminal of the comparator CMP5 , and the cathode of the diode D1 is connected to the drain of the switch device to be tested.

[0092] This application uses a strategy of desaturation detection assisted by gate charge detection to prevent SiCMOSFET with weak short-circuit performance from performance degradation or even damage, and to ensure extremely high detection reliability. In conjunction with the implementation of the first circuit, more accurate detection can be achieved, ensuring that the system can continue to maintain normal operation when the previous level of detection is falsely triggered.

[0093] When the device is working normally, the conduction voltage drop is low, the diode D1 is in the on state, and the anode voltage of the comparator CMP5 is the sum of the conduction voltage drops of the device and the diode, which is less than the short-circuit auxiliary detection voltage V REF4 , comparator CMP5 outputs a low level. When the device is short-circuited, V DS&CE Rising, diode D1 reverse blocking, the positive input voltage is approximately equal to the auxiliary voltage V C , higher than the reference voltage V REF4 , the comparator outputs a high level. Compared to traditional desaturation detection, this application uses FPGA-controlled sampling time, eliminating the need for blanking capacitors and pull-down clamps. The FPGA continuously samples the CMP5 output signal after the device is fully turned on or the gate charge circuit detects a short circuit in each cycle. If the sampling result remains high for multiple consecutive times, it is determined that the hybrid device has a short circuit.

[0094] like Figure 3 The figure shows a block diagram of the hybrid parallel device under hard-switching fault detection, as provided in this embodiment. By leveraging the fast gate charge detection speed, the SiC MOSFET soft shutdown operation is prioritized upon fault detection, preventing damage to the weaker SiC MOSFET. If the desaturation detection result indicates that the device is not short-circuited, the gate charge detection is considered a false alarm, the SiC MOSFET drive signal is restored, and the system continues normal operation.

[0095] like Figure 4 , is the comparison of the relevant signals of short circuit detection during hard switch fault and normal soft opening in this embodiment. In the figure, VHSF1 is the gate voltage comparator output. Because the gate charge required for hard switching fault is less than that for soft switching, the gate voltage rises faster under hard switching fault, and the time point of triggering gate charge detection is earlier. HSF2 The level flip event will also be earlier. When the hybrid device is turned on normally, the isolated V ISOHSF1 The rising edge is detected by V ISOHSF2 is high, and after a period of time V ISODesat It is still low, so the device does not operate normally. However, when a hard switching fault occurs, V ISOHSF1 The rising edge is detected by V ISOHSF2 If it is still low, it is judged that the gate charge is too small and a hard switching fault has occurred, and a fault signal V is immediately issued. MOS_FAULT After turning off the SiC MOSFET, desaturation detection confirmed the occurrence of a short circuit.

[0096] In addition, the present application provides a comparison between this embodiment and the desaturation detection circuit of Infineon's 1ED3431 driver chip. This chip is one of the driver chips that currently uses desaturation detection to detect short circuits faster. In this comparison, the chip is configured with a blanking time of 400ns and a filtering time of 225ns to ensure the fastest detection speed. The short-circuit detection time is defined as the time from the start of the rise of the SiC MOSFET short-circuit current to the reversal of the SiC MOSFET fault shutdown signal level.

[0097] like Figure 5 and Figure 6 , which is a comparison of the novel short-circuit detection drive circuit provided in the embodiment of the present application under a hard switching fault and the desaturation detection circuit of the 1ED3431 driver chip under different operating conditions. The novel short-circuit detection drive circuit of the present application maintains good consistency in detection time under various operating conditions, with an average detection time of 53.66ns, while the desaturation detection of the 1ED3431 driver chip averages 971.25ns. The novel short-circuit detection drive circuit of the present invention only requires 5.5% of the time of the desaturation detection to detect the occurrence of a hard switching fault. And in terms of short-circuit energy comparison, the short-circuit energy borne by the novel short-circuit detection drive circuit SiC MOSFET under various operating conditions of the present invention is only 1 / 3 of that of the desaturation detection circuit, which greatly reduces the energy borne by the device under hard switching.

[0098] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A fast short circuit detection circuit for a switching device, characterized in that: include: processing unit; a voltage determination module, wherein the input end of the voltage determination module is connected to the driving resistor, and the output end is connected to the processing unit, the voltage determination module is used to compare the gate voltage with the reference voltage, and when the gate voltage is greater than the reference voltage, send a first trigger signal to the processing unit; a charge determination module, wherein the input end of the charge determination module is connected to the driving resistor, and the output end is connected to the processing unit, the charge determination module is used to compare the gate charge amount with the reference charge amount, and when the gate charge amount is greater than the reference charge amount, send a second trigger signal to the processing unit; The ratio of the reference voltage to the gate voltage when fully turned on is greater than or equal to 0.9 and less than 1, and the reference charge value range is greater than the gate charge value during hard switching failure and less than the gate charge value during soft turning on.

2. The switching device fast short circuit detection circuit according to claim 1, characterized in that: The charge determination module includes: Instrument amplifier module, used for sampling and amplifying gate current; an integration module, wherein an input end of the integration module is connected to an output end of the instrument amplifier module and is used to realize continuous integration of the gate current; A comparison module, wherein the input end of the comparison module is connected to the output end of the integration module, and the output end of the comparison module is connected to the processing unit, and is used to compare the output voltage of the integration module with the charge voltage. When the output voltage of the integration module is greater than the charge voltage, a second trigger signal is sent to the processing unit; wherein the charge voltage has a value range greater than the output voltage of the integration module during a hard switch fault and less than the output voltage of the integration module during a soft switch.

3. The switching device fast short circuit detection circuit according to claim 2, characterized in that: The instrument amplification module includes a first amplifier, a second amplifier and a third amplifier; The non-inverting input terminal of the first amplifier and the non-inverting input terminal of the second amplifier are respectively used to connect to the two ends of the driving resistor; the inverting input terminal of the first amplifier is connected to the inverting input terminal of the second amplifier through a fifth resistor; The output end of the first amplifier is connected to the non-inverting input end of the third amplifier through an eighth resistor; the output end of the second amplifier is connected to the inverting input end of the third amplifier through a ninth resistor; and the non-inverting input end of the third amplifier is further grounded through a tenth resistor; The inverting input terminal and the output terminal of the first amplifier are further connected via a sixth resistor; the inverting input terminal and the output terminal of the second amplifier are further connected via a seventh resistor; and the inverting input terminal and the output terminal of the third amplifier are further connected via an eleventh resistor.

4. The switching device fast short circuit detection circuit according to claim 3, characterized in that: The integration module includes a fourth amplifier, an inverting input terminal of the fourth amplifier is connected to the output terminal of the instrument amplifier module via a resistor; a non-inverting input terminal of the fourth amplifier is grounded via a resistor, and a capacitor, a resistor, and an analog switch are connected in parallel between the inverting input terminal and the output terminal of the fourth amplifier. The control terminal of the analog switch is connected to the processing unit, and the processing unit controls the on and off of the analog switch.

5. The switching device fast short circuit detection circuit according to claim 4, characterized in that: The comparison module includes a second comparator, a non-inverting input terminal of the second comparator is connected to a fifteenth resistor, an inverting input terminal of the second comparator is connected to a charge voltage, and an output terminal of the second comparator is connected to the processing unit through a sixteenth resistor.

6. The switching device fast short circuit detection circuit according to any one of claims 1 to 5, characterized in that: It also includes a voltage divider module, the input end of the voltage divider module is used to connect to the driving resistor, and the output end is connected to the voltage determination module and the charge determination module. The voltage divider module is used to divide the voltage drop on the driving resistor and connect the voltage determination module and the charge determination module to the driving resistor.

7. The switching device fast short circuit detection circuit according to claim 6, characterized in that: The voltage divider module includes a first voltage divider unit and a second voltage divider unit. The first voltage divider unit includes a first resistor, one end of the first resistor is used to be connected to the first end of the driving resistor, and the other end is grounded through the second resistor and serves as the first output end of the voltage divider module; The second voltage dividing unit includes a third resistor, one end of the third resistor is connected to the second end of the driving resistor, and the other end is connected to the second resistor through a fourth resistor and grounded and serves as the second output end of the voltage dividing module.

8. The fast short circuit detection circuit for a switching device according to any one of claims 1 to 5 or 7, characterized in that: The voltage determination module includes a first comparator, wherein the non-inverting input terminal of the first comparator is connected to the second end of the driving resistor through a voltage divider module, the inverting input terminal is connected to a reference voltage, and the output terminal is connected to the processing module through a resistor.

9. The switching device fast short circuit detection circuit according to claim 8, characterized in that: The processing unit includes an FPGA, which is connected to the output ends of the voltage determination module and the charge determination module through a digital channel isolator to receive a first trigger signal and a second trigger signal; the FPGA is connected to the control end of the analog switch through the digital channel isolator to control the on and off of the analog switch.

10. The switching device fast short circuit detection circuit according to claim 8, characterized in that: The auxiliary detection module includes: A comparator, wherein the non-inverting input terminal of the comparator is connected to the voltage through a resistor, the inverting input terminal is connected to the auxiliary detection voltage, and the output terminal is connected to the FPGA through a resistor and a digital channel isolator; A diode, wherein the anode of the diode is connected to the non-inverting input terminal of the comparator, and the cathode of the diode is used to be connected to the drain of the switching device to be tested.

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