Test system, method and equipment based on memory extension equipment, medium and product

Abstract

The invention discloses a test system, method, device, medium and product based on a memory extension device, and relates to the technical field of computers, a processor and a memory extension interconnection component are connected through a memory extension bus, and a simulation test of the memory extension device is added. The memory expansion interconnection assembly is connected with the memory expansion device through the serial bus, so that the processor is directly connected with the memory expansion device, and the memory expansion interconnection assembly is located at the position outside the processor. Delay caused by a local memory access path is avoided, and the transmission efficiency is improved. The technical problem that the simulation processing result obtained according to the program duration under a traditional memory access path is low in accuracy can be solved, and the technical effects that the simulation test of the memory extension device is achieved, meanwhile, the function of full-system simulation is achieved, and the simulation accuracy of memory access of the mounted CXL memory extension device is improved are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a test system and method based on a memory expansion device, a device, a medium and a product. BACKGROUND

[0002] A Compute Express Link (CXL) memory expansion solution solves the limited memory capacity and bandwidth, which can alleviate the limited available memory. Compared with a traditional Peripheral Component Interconnect Express (PCIE) link, a Central Processing Unit (CPU) can have cache coherency with a load / store semantic to communicate with a peripheral device. However, a conventional simulation process determines a simulation processing result by running a program duration of a CPU, a bus and a local memory under a traditional memory access path, which overestimates the performance of the traditional memory access path and underestimates the performance improvement brought by the CXL memory expansion device, resulting in a deviation between the simulation result and the actual situation.

[0003] Therefore, how to improve the simulation accuracy of memory access of the CXL memory expansion device is an urgent problem for those skilled in the art to solve. SUMMARY

[0004] The present application provides a test system and method based on a memory expansion device, a device, a medium and a product to at least solve the problem of low accuracy of a simulation processing result obtained by a simulation process according to a program duration under a traditional memory access path in the related art.

[0005] The present application provides a test system based on a memory expansion device, comprising a processor, a memory expansion interconnection component and a memory expansion device; wherein the memory expansion interconnection component is located at a position outside the processor; The processor is connected to the memory expansion interconnection component through a memory expansion bus; The memory expansion interconnection component is connected to the memory expansion device through a serial bus.

[0006] The present application provides a test method based on a memory expansion device, applied to a test system, the test system comprising a processor, a memory expansion interconnection component and a memory expansion device; wherein the memory expansion interconnection component is located at a position outside the processor; the processor is connected to the memory expansion interconnection component through a memory expansion bus; the memory expansion interconnection component is connected to the memory expansion device through a serial bus, and the method comprises: The memory expansion interconnection component is controlled to convert the access memory request into a target request identified by the memory expansion device in response to the access memory request issued by the processor, and determine a target memory expansion device mounted according to address information of the target request; The target memory expansion device is controlled to feed corresponding target data to the processor through the memory expansion interconnection component.

[0007] The application further provides an electronic device, comprising a memory for storing a computer program and a processor for executing the computer program to implement the steps of any of the test methods based on the memory expansion device.

[0008] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the test methods based on the memory expansion device.

[0009] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the test methods based on the memory expansion device.

[0010] According to the application, on the one hand, the simulation test of the memory expansion device is added to the test system relative to the local memory access path, because the processor and the memory expansion interconnection component are connected through the memory expansion bus. The access memory request issued by the processor can be issued to the memory expansion interconnection component through the memory expansion bus, and then transmitted to the memory expansion device connected through the serial bus, so as to realize the transmission simulation of the access memory request in the memory expansion interconnection component involved in the memory expansion device. Through the serial bus connection between the memory expansion interconnection component and the memory expansion device, the processor is directly connected with the memory expansion device, and the memory expansion interconnection component is located outside the processor and is independent of the processor. Relative to the traditional local memory access path, the transmission is in the CPU, and then transmitted to the memory expansion device through the IO bus, which is limited by the memory controller in the CPU. The transmission efficiency is improved by avoiding the delay of the traditional IO bus local memory access path. Through the transmission of the serial bus of the application, a more real transmission path and flexible communication delay simulation can be provided. On the other hand, the transmission process of the entire access path of the memory expansion device of the application can simulate the comprehensive test of the entire operating system, which cannot be simulated by the program running time of the traditional local memory access path. The application realizes the full system simulation by the memory access of the processor, the memory expansion device and the supported operating system in the full system mode, improves the comprehensiveness of the simulation test of the system. At the same time, the simulation processing result is based on the performance test of the memory expansion device, so as to improve the accuracy of the simulation result, reduce the deviation between the simulation result and the actual situation, and improve the simulation accuracy.

[0011] Therefore, the technical problem of low accuracy of the simulation processing result obtained by the program running time according to the traditional memory access path can be solved, the function of simulation test of the memory expansion device and full system simulation is achieved, and the simulation accuracy of the memory access of the mounted CXL memory expansion device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1 A structure diagram of a test system based on a memory expansion device is provided for the embodiments of the application. Figure 2 A cascading connection schematic diagram between switching devices is provided for the embodiments of the application. Figure 3A multi-tree connection schematic diagram between switching devices provided by the embodiment of the present application; Figure 4 A structure diagram of another test system based on a memory expansion device provided by the embodiment of the present application; Figure 5 A flowchart of a test method based on a memory expansion device provided by the embodiment of the present application; Figure 6 A memory architecture schematic diagram of a CXL technology provided by the embodiment of the present application; Figure 7 A control mode schematic diagram of a memory expansion controller provided by the embodiment of the present application; Figure 8 A control mode schematic diagram of a memory expansion device provided by the embodiment of the present application; Figure 9 A structure schematic diagram of a test device based on a memory expansion device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0015] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0016] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0017] In combination with a specific application environment architecture or a specific hardware architecture relied on by the execution of the test method based on the memory expansion device, the specific application environment architecture or the specific hardware architecture is described herein. The test system is a simulation test based on a simulator, and in a conventional scheme, a commercial hardware such as a CPU that lacks support for CXL, and researches corresponding to CXL memory are all corresponding to a simulation system, and cannot accurately model and characterize the actual CXL memory. The conventional local memory access path is based on the CXLMemSim simulator (a pure software simulation calculation tool for performance qualification of CXL.mem), simulates the execution of an existing and unmodified program, and divides the execution of the program into multiple epochs; when an epoch is completed, CXLMemSim collects performance monitoring events, and calculates the simulated epoch execution time according to the events, and the time for the epoch to run to completion is the execution time of the entire program. Through this method, CXLMemSim only simulates the program running time in the form of epochs, and does not simulate the entire operating system, avoids the performance overhead of the full system (the entire system of the simulation server, full system simulation is a method of simulating the entire computer system including processors, memories, input / output (Input / Output, I / O) devices, etc.), and allows easy adjustment of the storage hierarchy and delay, making it possible to study the storage scheduling of complex applications.

[0018] Figure 1 A structure diagram of a test system based on a memory expansion device provided by an embodiment of the present application is shown in Figure 1 , which includes a processor 1, a memory expansion interconnection component 2, and a memory expansion device 3; wherein the memory expansion interconnection component 2 is located at a position outside the processor 1; The processor 1 is connected to the memory expansion interconnection component 2 through a memory expansion bus; The memory expansion interconnection component 2 is connected to the memory expansion device 3 through a serial bus.

[0019] Specifically, in the present application, the test of the memory expansion device is mainly aimed at, and the memory expansion interconnection component realizes the memory expansion function and the interconnection function. The memory expansion function includes memory pooling, and through multiple memory expansion devices, a memory pool can be combined, allowing multiple CPUs or computing units to share memory resources. Dynamic resource allocation is supported, and memory allocation can be dynamically adjusted according to system requirements. The protocol design of the component ensures low-latency memory access, and even when accessing across nodes, high performance can be maintained. Regarding the interconnection function, high-performance interconnection function is provided, multi-level switching is supported, and efficient communication of multiple devices is allowed.

[0020] The memory expansion interconnect component of this application is distinct and independent from the processor, located externally. In conventional technical solutions, the local access path connects the CXL memory expansion device to the IO bus, the processor to the memory bus, and the IO bus and memory bus are connected via a bridge. Access between the processor and the CXL memory expansion device is achieved via the bridge. In conventional technical solutions, the bridge is a hardware structure located inside a processor such as a CPU, and is used to connect different functional modules within the CPU.

[0021] It should be noted that the connection relationship between the processor, memory expansion interconnect assembly, and memory expansion device in this embodiment is different from the local access path corresponding to the bridge structure. This is mainly reflected in the following aspects: 1. Different Architectural Design: An internal bridge connects the CPU to system memory, graphics cards, and other devices, relying on the CPU's own memory controller and I / O controller. The I / O bus connects various input and output devices, supporting traditional memory access and I / O operations, and is suitable for handling high-frequency, small-volume data access. The architecture of this embodiment establishes an independent, high-performance bus management mechanism that supports memory expansion, cache coherence management, and memory and device pooling.

[0022] Second, different memory access methods: The local memory access path using the bridge is limited by the CPU's internal memory controller. Memory access on the I / O bus uses methods such as Direct Memory Access (DMA), which reduces access speed and efficiency. This embodiment uses a memory expansion interconnect component to allow the CPU to access external memory modules via the memory expansion bus, supporting larger memory capacity and higher bandwidth, as well as memory pooling and sharing, to achieve low-latency, high-bandwidth memory access.

[0023] 3. Performance Optimization: The local memory access path of the bridge can only support a limited number of memory modules and IO devices. This embodiment supports almost unlimited memory expansion, can build a large-scale memory network, and realize dynamic memory allocation and sharing.

[0024] Support for memory expansion allows simulation of more memory capacity without shutting down the system, thereby increasing the scalability of the simulation test system.

[0025] The memory expansion interconnection component is independent of the processor, and multiple processors can share a memory pool. A separate memory expansion interconnection component is introduced between the CPU and the memory expansion device, the memory technology is decoupled from the specific memory interface technology supported by the CPU, and multiple memory types are supported. Compared with the local memory access path of the traditional CPU internal bridge and the IO bus, the unified interface and protocol simplify the system design, reduce the design complexity, and improve the reliability and maintainability of the system.

[0026] The processor is connected with the memory expansion interconnection component through a memory expansion bus, the processor issues different types of CPU access memory requests, and the memory expansion interconnection component responds to the access memory request issued by the processor, converts the request to obtain a target request recognized by the memory expansion device. The memory expansion interconnection component is connected with the memory expansion device through a serial bus, the serial bus realizes high-bandwidth and low-delay data transmission, supports multiple device connections, and has good scalability and flexibility. The memory expansion interconnection component determines the target memory expansion device mounted according to the address information of the target request, determines the memory access of the target memory expansion device through the connection relationship between the memory expansion interconnection component and the memory expansion device, and feeds back the accessed data to the processor in the target memory expansion device.

[0027] According to the embodiments of the present application, on the one hand, the simulation test of the memory expansion device is added to the test system relative to the local memory access path, because the processor and the memory expansion interconnection component are connected through the memory expansion bus. The access memory request issued by the processor can be transmitted to the memory expansion interconnection component through the memory expansion bus and then transmitted to the memory expansion device connected through the serial bus, so as to realize the transmission simulation of the access memory request in the memory expansion interconnection component involved in the memory expansion device. Through the serial bus connection between the memory expansion interconnection component and the memory expansion device, the processor is directly connected with the memory expansion device, and the memory expansion interconnection component is located outside the processor and is independent of the processor. Relative to the traditional local memory access path, the transmission is in the CPU and then transmitted to the memory expansion device through the IO bus, which is limited by the memory controller in the CPU, avoids the delay of the traditional local memory access path of the IO bus, and improves the transmission efficiency. Through the transmission of the serial bus of the present application, a more real transmission path and flexible communication delay simulation can be provided. On the other hand, the transmission process of the entire access path of the memory expansion device of the present application can realize full-system simulation through the memory access of the processor, the memory expansion device and the supported operating system in the full-system mode, improve the comprehensiveness of the simulation test of the system, and make the simulation processing result based on the performance test of the memory expansion device, so as to improve the accuracy of the simulation result, reduce the deviation between the simulation result and the actual situation, and improve the simulation accuracy.

[0028] Therefore, the technical problem of low accuracy of the simulation processing result obtained according to the program length in the traditional memory access path can be solved, the function of simulation test of the memory expansion device and full-system simulation is achieved, and the simulation accuracy of the memory access of the mounted CXL memory expansion device is improved.

[0029] In some embodiments, as shown in Figure 1 The memory expansion interconnection component 2 includes a memory expansion controller 4 and a switching device 5. The processor 1 is connected with the memory expansion controller 4 through the memory expansion bus. The memory expansion controller 4 is connected with the switching device 5 through the serial bus. The switching device 5 is connected with at least one memory expansion device 3 through the serial bus.

[0030] Specifically, the memory expansion controller is mainly responsible for receiving memory request packets sent by the processor, packaging the request packets into the format of the memory expansion bus for downstream transmission, responding to the access memory request issued by the processor, and converting the access memory request to obtain a target request recognized by the memory expansion device. The memory expansion controller is connected with the switching device through a serial bus. The switching device is used to connect at least one memory expansion device, determine the target memory expansion device mounted on the switching device according to the address information of the target request, and realize efficient memory expansion and resource sharing. At the same time, multi-level switching is supported, which improves the scalability, resource utilization, memory pooling and dynamic resource allocation of the system.

[0031] The target memory expansion device feeds back the corresponding target data to the processor through the switching device and the memory expansion controller.

[0032] The memory expansion controller and the switching device provided by the embodiment both support memory expansion function, allowing CPU to access additional memory expansion devices, thereby increasing the memory capacity of the system. The memory expansion controller supports the Compute Express Link Cache Protocol (CXL.cache protocol), ensuring cache consistency between CPU and accelerator. This helps to improve the performance and reliability of the system, especially in application scenarios that require frequent access to shared memory. The switching device supports memory pooling and device pooling, allowing multiple devices to share memory resources. This can significantly improve resource utilization and reduce the total cost of the system. Both support high-performance computing and are suitable for application scenarios such as data centers, artificial intelligence and scientific computing. They can significantly improve the computing performance of the system through low-latency and high-bandwidth connections.

[0033] In some embodiments, the number of memory expansion devices is related to the number of ports of the switching device; one port connects one memory expansion device; When the number of memory expansion devices exceeds the number of ports of one switching device, multiple switching devices are connected with the memory expansion devices through a serial bus.

[0034] Specifically, considering that the number of memory expansion devices can be multiple, the type and number of memory expansion devices can be known before the CPU actually accesses, therefore, the final number of switching devices needs to be determined based on the number of memory expansion devices and the number of ports of the switching device. In accordance with the principle that one port of the switching device connects one memory expansion device, when the number of memory expansion devices exceeds the number of ports of one switching device, it means that there are many memory expansion devices, and one switching device is not enough, so multiple switching devices are needed to be connected with the memory expansion devices through a serial bus.

[0035] The number of memory expansion devices is set to the number of switching devices to ensure that the switching devices can mount all the memory expansion devices, improve the utilization rate of memory resources, and realize memory pooling.

[0036] In some embodiments, the memory expansion devices are connected in a cascade manner between the plurality of switching devices, a first port of a current switching device is connected to a second port of a previous switching device through a serial bus, a second port of the current switching device is connected to a first port of a next switching device through the serial bus, and a first port of a first switching device is connected to a memory expansion controller through the serial bus.

[0037] Specifically, Figure 2 A schematic diagram of the cascade connection between the switching devices according to the embodiments of the present application is shown in FIG. 1. Figure 2 As shown in FIG. 1, the cascade manner is that one port of a switching device is connected to a previous switching device, and another port of the switching device is connected to a next switching device. At the same level, only one switching device exists, and the remaining ports are connected to memory expansion devices. The cascade connection is in linear order to form a chain structure.

[0038] The cascade connection of the switching devices according to the embodiments of the present application increases the number of ports of the switching devices as much as possible to facilitate the connection and use of the memory expansion devices, optimizes the utilization rate of the memory expansion devices, and saves the hardware cost of the switching devices.

[0039] In some other embodiments, the memory expansion devices are connected in a multi-branch tree manner between the plurality of switching devices, a first switching device serves as a root node, a first port of the first switching device is connected to a memory expansion controller through a serial bus, and the remaining ports of the first switching device except the first port are connected to switching devices and / or memory expansion devices as child nodes through the serial bus.

[0040] Specifically, Figure 3 A schematic diagram of the multi-branch tree connection between the switching devices according to the embodiments of the present application is shown in FIG. 2. Figure 3As shown, the concept of the multi-fork tree is that nodes are connected in a hierarchical structure to form a tree structure. The same level of switching devices can exist multiple, or can be connected to the next level of multiple switching devices, by adding more child nodes to expand the function and capacity of the system. The first switching device is taken as the root node, the first port of the first switching device is connected with the memory expansion controller through the serial bus, and the remaining ports of the first switching device except the first port are connected through the serial bus as the switching devices and / or memory expansion devices of the child nodes. It should be noted that the switching devices of the child nodes are corresponding to different levels, which are all taken as child nodes. The first switching device is taken as the first level, and the switching devices and memory expansion devices in the second level are taken as the child nodes of the first level. The switching devices and memory expansion devices in the third level are taken as the child nodes of the second level, which are also corresponding to the child nodes of the first level. Therefore, the subsequently connected switching devices and / or memory expansion devices are all taken as the child nodes of the first level.

[0041] The multi-fork tree connection of the switching device provided by the embodiment has a tree structure, and a node can have multiple child nodes to form a branch structure, supporting complex hierarchical data organization. The multi-fork tree has low delay and can transmit in parallel in multiple branches.

[0042] In some embodiments, the test system further comprises a simulation object unit; The simulation object unit is connected with the processor and the memory expansion interconnection component through the memory expansion bus, and is configured to construct at least one memory access request.

[0043] Figure 4 Another structure diagram of the test system based on the memory expansion device provided by the embodiment of the application is shown in FIG. 6. Figure 4 As shown, the test system further comprises a simulation object unit 6 connected with the processor 1 and the memory expansion controller 4 through the memory expansion bus, and configured to construct at least one memory access request. Specifically, the simulation object unit 6 can simulate and construct a single memory access request or a plurality of continuous memory access requests, so that the process of encapsulating the Flit format (flow control unit) according to the CXL protocol and verifying the encapsulated Flit packet information can be more clearly studied. It should be noted that the number of requests encapsulated by each Flit is not fixed, and different numbers of memory access requests can be set by the Sim_object module (simulation object unit) to study the efficiency of Flit format encapsulation and the communication overhead caused thereby. Further, a fixed number of memory access requests can be issued to view the information after Flit format encapsulation, and the difference from the original request is compared. If continuous requests are issued, it is difficult to view and compare the Flit format information content.

[0044] The connection relationship of the simulation object unit provided in the embodiment can provide effective and real memory expansion device simulation and emulation, and the access speed of the memory expansion device is closer to the real level than other simulation and emulation platforms.

[0045] In some embodiments, the test system further comprises a local memory device; The local memory device is connected with the processor through the memory expansion bus.

[0046] As Figure 4 shown, the local memory device 7 is further included, and the local memory device 7 herein can follow the conventional memory access path or be improved according to the conventional memory access path, which is not limited herein.

[0047] The connection relationship of the local memory access path provided in the embodiment enables the test system to have the access function of mixed heterogeneous memory, optimizes the access performance of dynamic data migration by distributing data into different types of memory according to the access mode and performance requirement of the data, and allows the pooling of different types of memory resources in the mixed heterogeneous memory system, improves the utilization rate of memory resources, and reduces memory redundancy.

[0048] Further, the application further provides a test method based on a memory expansion device, Figure 5 A flowchart of a test method based on a memory expansion device provided in the embodiment of the application is shown in Figure 5 application to a test system, the test system comprising a processor, a memory expansion interconnection component and a memory expansion device; wherein the memory expansion interconnection component is located at a position outside the processor; the processor is connected with the memory expansion interconnection component through a memory expansion bus; the memory expansion interconnection component is connected with the memory expansion device through a serial bus, and the method comprises the following steps: S11: controlling the memory expansion interconnection component, converting and processing an access memory request in response to an access memory request issued by the processor to obtain a target request recognized by the memory expansion device; and determining a target memory expansion device to be mounted according to the address information of the target request; S12: controlling the target memory expansion device to feed corresponding target data to the processor through the memory expansion interconnection component.

[0049] Specifically, Figure 6 A memory architecture schematic diagram of the CXL technology provided in the embodiment of the application is shown in Figure 6As shown, the host processor and the memory expansion device, the processor core of the host processor, is the main computing unit of the processor, responsible for executing instructions and processing data. The host processor can access the main memory on its own device and the device memory of the memory expansion device. When the host processor needs to access the device memory of the memory expansion device, it sends a request through the CXL.mem protocol. This request is first received by the memory expansion controller (CXL Controller) in the Home Agent, and then forwarded to the CXL Controller in the Client Agent through the CXL Controller. The CXL Controller in the Client Agent forwards the request to the memory controller (Memory Controller), which accesses the device memory. The CXL.mem protocol is used for memory access, allowing the host processor to directly access the device memory on the memory expansion device.

[0050] I / O operation: When the host processor needs to perform I / O operation with the memory expansion device, it sends a request through the CXL.IO protocol. This request is also received by the CXL Controller in the Home Agent, and then forwarded to the CXL Controller in the Client Agent through the CXL Controller. The CXL Controller in the Client Agent forwards the request to the corresponding I / O device. The CXL.IO protocol is used for I / O operation, allowing the host processor to directly access the I / O resources on the memory expansion device. Among them, Figure 6 The input-output memory management unit (IOMMU) in the memory expansion device is responsible for managing the memory access of the I / O device, providing memory protection and address translation functions. Specifically, the IOMMU can prevent the I / O device from accessing memory regions that do not belong to them, thereby improving the security and stability of the system. The physical address of the I / O device can be converted to the virtual address of the system memory, or vice versa. This allows the I / O device to access the system memory without the intervention of the CPU.

[0051] Memory consistency: In order to ensure the consistency of data, the coherence / memory logic (Coherence / Memory Logic) in the Home Agent monitors memory access to ensure that all devices access the latest data.

[0052] The description of the features in the embodiments of the method can refer to the related description of the embodiments of the test system based on the memory expansion device, which will not be repeated here, and has the same beneficial effects as the test system based on the memory expansion device described above.

[0053] In some embodiments, in response to the access memory request issued by the processor, the method comprises: receiving an instruction set of a target type of processor based on the simulation platform; generating a corresponding access memory request according to the instruction set, for the memory expansion interconnection component to respond to the access memory request.

[0054] Specifically, it should be noted that the processor provides different types of simulation corresponding to different instruction sets, and the simulation platform receives an instruction set of a target type of processor based on the simulation platform, to generate a corresponding access memory request according to the instruction set, i.e. to generate different types of access memory requests, for the memory expansion interconnection component to respond to the access memory request. As for the simulation platform, it can be Gem5 or other platforms, and as for the Gem5 platform, it provides rich configuration options, which can simulate different processor architectures, memory hierarchies, device models, etc. At the same time, Gem5 also supports multiple simulation modes, including system call simulation, instruction level simulation and event driven simulation, and the appropriate simulation mode can be selected according to the demand.

[0055] The embodiment provided in the embodiment supports the sharing of memory between multiple processors, enables multiple processors to access memory expansion devices, achieves lower latency, and improves computing efficiency.

[0056] In some embodiments, the access memory request is converted to obtain a target request recognized by the memory expansion device, comprising: defining an adapter class for the target type of processor in advance; converting the address format of the access memory request to a first address format according to the address format of the adapter class; converting the data format of the access memory request to a first data format according to the data format of the adapter class; converting the operation type format of the access memory request to a first operation type format according to the operation type format of the adapter class; converting the request size of the access memory request to a first request size according to the request size of the adapter class; determining the target request according to the first address format, the first data format, the first operation type format and the first request size.

[0057] Specifically, different CPU types may generate memory access requests in different formats. For example, the formats of memory access requests for CPUs based on the x86 architecture and CPUs based on the Advanced Reduced Instruction Set Computer Machine (ARM) architecture may differ. The adapter pattern is a design pattern used to convert the interface of one class to the interface of another class. In this case, an adapter can be defined for each CPU type to convert requests in a specific format into requests in a unified format. The factory pattern is a design pattern used to create objects without specifying a specific class. In this case, a factory class can be defined to create corresponding adapter objects based on the CPU type. Factory class: Define a factory class that returns the corresponding adapter object based on the CPU type. Adapter object: Each adapter object is responsible for converting requests in a specific format into requests in a unified format.

[0058] In this embodiment, when requests of different CPU types are identified, they need to be converted into requests of a unified format, that is, from four dimensions: address conversion, data conversion, operation type conversion, and request size conversion. The target request is determined based on the first address format, first data format, first operation type format, and first request size obtained by converting the four dimensions.

[0059] The target request conversion method provided in this embodiment utilizes an adapter pattern and a factory pattern to identify and convert memory access requests from different CPU types into a unified format. This enables unified management and response to memory access requests from different CPU types. This approach improves system flexibility and scalability while simplifying the processing logic for memory access requests.

[0060] In some embodiments, a memory expansion interconnect assembly includes a memory expansion controller and a switch device; the processor is connected to the memory expansion controller via a memory expansion bus; the memory expansion controller is connected to the switch device via a serial bus; when the switch device is connected to at least one memory expansion device via the serial bus and the number of the switch device is one, determining a mounted target memory expansion device based on address information of a target request includes: Pre-establishing a first address mapping table between the requested address information and the address information of the memory expansion device in the switching device; Determine a corresponding address range according to the first address mapping table and the address information of the target request; Determines the target memory expansion device based on the address range.

[0061] Specifically, in combination with the structural connection relationship of the memory expansion interconnection assembly in the above-mentioned embodiments, when the number of switching devices is one, how to determine the target memory expansion device according to the address information of the target request, about the switching device supporting multiple topological structures, allowing efficient data transmission, managing the mounting and access of the memory expansion device through the address mapping table. The address mapping table records the mapping relationship between the memory address range and the memory expansion device. When the CPU initiates a memory access request, the switching device (CXL_xbar) will forward the request to the correct memory expansion device according to the address mapping table. Address range division: during system initialization, the switching device will divide the memory address space into different ranges according to the system configuration, and map each range to a specific memory expansion device. Request analysis: when the CPU initiates a memory access request, the switching device will analyze the address information in the request, look up the address mapping table, and determine which memory expansion device the address belongs to. Forward the request: according to the result of the address mapping table, the switching device forwards the request to the corresponding target memory expansion device.

[0062] It should be noted that the switching device supports dynamic address mapping, allowing the connection relationship of the memory expansion device to be adjusted according to system requirements at runtime, for example, when a certain memory expansion device fails or needs to be reconfigured, the switching device can dynamically update the address mapping table and remap the request to other available memory expansion devices.

[0063] The embodiment provided by the present embodiment determines the corresponding address range through the first address mapping table to determine the target memory expansion device based on one switching device, ensuring low-latency transmission of memory access requests and flexible management of memory resources during system operation.

[0064] In some embodiments, the memory expansion interconnection assembly includes a memory expansion controller and a switching device; the processor is connected with the memory expansion controller through a memory expansion bus; the memory expansion controller is connected with the switching device through a serial bus; when the number of switching devices is multiple, the multiple switching devices are connected in a cascade manner, and the connection process of the cascade manner includes: In the case where the number of memory expansion devices exceeds the number of ports of a switching device, the number of switching devices is determined according to the number of memory expansion devices and the number of reserved ports of the switching device; wherein the reserved port is a port of the switching device excluding the port connected to the next switching device and the port connected to the previous switching device, and the port for connecting the memory expansion device; Connect the memory expansion device according to the number of switching devices and the corresponding number of reserved ports.

[0065] Specifically, considering the case that the number of switching devices is multiple, and the connection is in a cascade manner, the specific connection manner is determined according to the number of memory expansion devices and the number of reserved ports of the switching device. It should be noted that the reserved ports are the ports connecting the memory expansion devices except the ports connecting the switching devices.

[0066] The memory expansion devices are connected based on the number of reserved ports of the switching device and the number of switching devices to realize the cascade manner. The cascade manner here can be random arrangement of the memory expansion devices.

[0067] The cascade manner of the multiple switching devices provided by the embodiment can expand the function or capacity of the system step by step.

[0068] In some embodiments, the target memory expansion device mounted according to the address information of the target request comprises: The address mark information of the switching device to which the multiple memory expansion devices belong is acquired in advance; The second address mapping table between the address information of the request in the first switching device, the address information of the memory expansion device, and the address mark information of the different switching devices is established in advance; The target address mark information and the target address range are determined according to the second address mapping table and the address information of the target request; The target memory expansion device is determined according to the target address mark information and the target address range.

[0069] Specifically, the address mark information of the switching device to which the multiple memory expansion devices belong is considered under the cascade of the switching device, and there is one switching device at each level, so there is one or more memory expansion devices belonging to one switching device, and the address mark information of the switching device at each level is set in advance. The second address mapping table between the address information of the request, the address information of the memory expansion address, and the address mark information of the different switching devices is determined to determine the target address mark information and the target address range of the target switching device, so as to determine the target memory expansion device.

[0070] The embodiment provided in the application determines the target memory expansion device in the multiple switching devices in the cascade manner based on the second address mapping table, and adds the address mark information of the switching device at the same level to improve the screening efficiency under the multiple switching devices.

[0071] In some embodiments, the memory expansion interconnection component comprises a memory expansion controller and a switching device; the processor is connected with the memory expansion controller through a memory expansion bus; the memory expansion controller is connected with the switching device through a serial bus; when the switching device is connected with at least one memory expansion device through the serial bus and the number of the switching devices is multiple, the multiple switching devices are connected in a multi-branch tree mode, and the connection process of the multi-branch tree mode comprises: obtaining performance parameters of the multiple memory expansion devices; performing rank sorting processing according to the multiple performance parameters to determine the memory expansion devices in respective ranks; regarding the memory expansion devices in the same rank as child nodes in the same rank; regarding the child nodes in the same rank as belonging to the same switching device; arranging the memory expansion devices in different ranks to child nodes and parent nodes in different ranks to determine a multi-branch tree rank corresponding to the multiple switching devices; determining a connection relationship between the switching devices and the memory expansion devices according to the multi-branch tree rank.

[0072] Specifically, in combination with the connection relationship between the multiple switching devices in the multi-branch tree mode in the above-mentioned embodiments, in this embodiment, considering different parent nodes and child nodes, the performance parameters of the multiple memory expansion devices are corresponded, the memory expansion devices with similar performance parameters are regarded as child nodes in the same rank and belong to the same switching device, the performance parameters are subjected to rank sorting processing to determine the memory expansion devices in respective ranks, the memory expansion devices are arranged to child nodes and parent nodes in different ranks to form a multi-branch tree rank, and finally the connection relationship between the switching devices and the memory expansion devices is determined.

[0073] The embodiment provided in the present application divides the parent nodes or child nodes in the corresponding ranks based on the performance parameters of the memory expansion devices, ensures that the memory expansion devices with similar performance parameters belong to the same switching device or the same rank of switching devices, improves the access speed, and ensures the consistency of the access path.

[0074] In some embodiments, the target memory expansion device mounted is determined according to address information of a target request, comprising: obtaining address marker information and corresponding node ranks of switching devices to which the multiple memory expansion devices belong in advance; previously establishing a third address mapping table between the address information of the request, the address information of the memory expansion device, the address marker information of the different switching devices and the node ranks in the first switching device; determining target address marker information, a target address range and a target node rank according to the third address mapping table and the address information of the target request; The target memory expansion device is determined according to the target address mark information, the target address range, and the target node level.

[0075] Specifically, based on the determination process of the target memory expansion device in the cascading mode in the above embodiment, the node level of the switching device is additionally added to construct a third address mapping table. The target address mark information, the target address range, and the target node level are determined according to the third address mapping table, and finally the target memory expansion device is determined.

[0076] The embodiment provides the determination of the target memory expansion device in the multiple switching devices in the multi-branch tree mode based on the third address mapping table, and the determination of the target memory expansion device in the multiple switching devices in the multi-branch tree mode based on the third address mapping table. The joining of the address mark information of the switching device at different node levels and in the same level improves the screening efficiency under the multi-level switching device, and ensures that the access paths of the corresponding memory expansion devices are consistent when accessing different node levels.

[0077] In some embodiments, before the access memory request is converted and processed to obtain the target request identified by the memory expansion device, the method further comprises: obtaining the first critical request quantity and the first actual request quantity stored in the request queue in the memory expansion controller; In the case where the difference between the first critical request quantity and the first actual request quantity is less than the first threshold, a first buffer request instruction is sent to the processor to slow down the delivery of the access memory request.

[0078] Specifically, Figure 7 A control mode diagram of a memory expansion controller provided by the embodiment of the application is shown in FIG. 1. Figure 7 As shown in FIG. 1, the first critical request quantity and the first actual request quantity stored in the request queue in the memory expansion controller are obtained. When the difference between the first critical request quantity and the first actual request quantity is less than the first threshold, that is, when the first actual request quantity is about to reach the first critical request quantity, it indicates that the request size in the request queue is large. If the memory request packet from the processor is continuously received and processed at the current delivery response speed, congestion or suspension may occur. The application needs to respond to the access memory request and immediately send a response to the processor to inform the suspension of delivery.

[0079] The setting of the request queue in the memory expansion controller provided by the embodiment ensures the orderliness of the delivery process, prevents system overload, and reduces network congestion, improves network transmission efficiency, and maintains system stability and reliability.

[0080] In some embodiments, the access memory request is converted and processed to obtain the target request identified by the memory expansion device, comprising: When the difference between the first critical request number and the first actual request number is greater than or equal to the first threshold, encapsulating the memory access request to obtain first encapsulated data; Comparing the data specifications of the first packaged data with the data specifications of the preset packaged data; If the data specification of the first encapsulated data reaches the data specification of the preset encapsulated data, the first encapsulated data is converted to obtain a target request, and is transmitted to the switching device.

[0081] Specifically, if Figure 7 As shown, when the difference between the first critical request number and the first actual request number is greater than or equal to the first threshold, the subsequent encapsulation processing is performed normally. The encapsulation processing work here can be based on Flit encapsulation or other encapsulation formats, which is not limited here. The first encapsulated data is encapsulated. When the data specification of the preset encapsulated data needs to be reached according to the data specification of the first encapsulated data, it is converted and processed to obtain the target request. If it is not reached, it is returned to the step of reading the memory access request to continue reading until the data specification of the preset encapsulated data is reached.

[0082] By adding a request queue, the memory access request sent by the CPU only needs to be written into the request queue of the memory expansion controller. The memory expansion controller encapsulates multiple memory access request packets into Flit format through the read request queue for subsequent transmission.

[0083] Figure 7 The steps are as follows: S21: writing the memory access request into the request queue in the memory expansion controller; S22: Determine in the request queue of the memory expansion controller whether the difference between the first critical request number and the first actual request number is less than a first threshold; if so, proceed to step S23; if not, proceed to step S24; S23: Sending a first buffer request; S24: encapsulating the memory access request to obtain first encapsulated data; S25: Determine whether the data specification of the first packaged data meets the data specification of the preset packaged data; if so, proceed to step S26; if not, return to step S22; S26: converting the first encapsulated data to obtain a target request; S27: receiving a feedback data request uploaded by the switching device; S28: Encapsulate the feedback data request and proceed to step S21.

[0084] The data encapsulation processing process in the memory expansion controller provided by the embodiment converts a traditional access memory request into an access request packet of a CXL protocol, and transmits the packet by using a packaging format of the CXL. The decoupling of the memory expansion controller is realized by using a request queue, and the pipelining and efficient access of the CXL memory expansion device are realized. A large number of parameter configurations can be provided for the controller, so that the test effect is closest to the access efficiency of the real CXL memory expansion device.

[0085] In some embodiments, the target data processing process of the target memory expansion device includes: The target request is parsed and encapsulated to obtain second encapsulation data; The second encapsulation data is sent to the memory corresponding to the memory expansion device for memory access to obtain target data; The target data is sent to a sending request queue of the target memory expansion device, and the target data is encapsulated to obtain third encapsulation data; The data specification of the third encapsulation data is compared with the data specification of the preset encapsulation data; If the data specification of the third encapsulation data reaches the data specification of the preset encapsulation data, the third encapsulation data is sent to the switching device and transmitted to the processor through the memory expansion controller.

[0086] Specifically, Figure 8 A control mode diagram of the memory expansion device provided by the embodiment of the application is shown in FIG. 1. Figure 8 The target request is parsed and encapsulated to obtain second encapsulation data. The parsing and encapsulation processing process uses the same format as the encapsulation processing process in the above embodiment. The target data is sent to a sending request queue of the target memory expansion device, and the target data is encapsulated to obtain third encapsulation data. The encapsulation processing process here can be the same as the encapsulation format of the encapsulation processing in the above embodiment, or can be different, which is not limited here. The target data is the final access data.

[0087] Similarly, if the data specification of the third encapsulation data reaches the data specification of the preset encapsulation data, the third encapsulation data is sent to the switching device and transmitted to the processor through the memory expansion controller.

[0088] The data encapsulation processing process in the memory expansion device provided by the embodiment converts a traditional access memory request into an access request packet of a CXL protocol, and transmits the packet by using a packaging format of the CXL. The decoupling of the memory expansion controller is realized by using a request queue, and the pipelining and efficient access of the CXL memory expansion device are realized.

[0089] In some embodiments, before the target data is sent to the sending request queue of the target memory expansion device, the method further includes: acquire a second critical request quantity of a sending request queue of the target memory expansion device and a second actual request quantity stored; In a case where a difference between the second critical request quantity and the second actual request quantity is less than a second threshold value, a second buffer request instruction is sent to the switching device to slow down the delivery of the target data.

[0090] Specifically, by increasing the response queue to solve the dependence on the memory module, the memory access response from the memory and the response generated by the memory expansion device only need to be written into the response queue of the memory expansion device, and the multiple memory access responses are packaged into Flit format by reading the response queue for subsequent sending. The memory expansion device is directly mounted on the memory bus through the serial bus, the CPU can directly manage the memory expansion device, directly access the memory of the memory expansion device, the serial bus simulates the behavior of the CXL bus, and provides the packaging and transmission of the CXL protocol package.

[0091] As shown in FIG. 1, the steps are as follows: Figure 8 S31: The target request is parsed and packaged to obtain second packaging data; S32: The second packaging data is sent to the memory corresponding to the memory expansion device for memory access to obtain target data; S33: The target data is sent to the sending request queue of the target memory expansion device; S34: It is judged whether a difference between the second critical request quantity and the second actual request quantity is less than a second threshold value in the sending request queue of the target memory expansion device; if yes, step S35 is entered, and if no, step S36 is entered; S35: The second buffer request instruction is sent; S36: The target data is packaged to obtain third packaging data; S37: It is judged whether the data specification of the third packaging data reaches a preset data specification of the packaging data; if yes, step S38 is entered; and if no, the step S33 is returned; S38: The third packaging data is sent to the switching device.

[0092] The request queue provided in the memory expansion device in the embodiment ensures the orderliness in the feedback sending process of the target data, improves the transmission efficiency of the network, and maintains the stability and reliability of the system.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0094] ​The embodiment of the present application also provides a testing device based on a memory expansion device, Figure 9 A schematic diagram of a test device based on a memory expansion device provided in an embodiment of the present application is shown in FIG. Figure 9 Shown, including: The first control module 11 is used to control the memory expansion interconnect component, respond to the memory access request issued by the processor, convert the memory access request to obtain a target request identified by the memory expansion device; and determine the mounted target memory expansion device according to the address information of the target request; The second control module 12 is used to control the target memory expansion device and feed back the corresponding target data to the processor through the memory expansion interconnection component.

[0095] For the description of the features in the embodiment corresponding to the device, please refer to the relevant description of the embodiment corresponding to the testing method based on the memory expansion device, which will not be repeated here.

[0096] An embodiment of the present application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned test method embodiments based on a memory expansion device.

[0097] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned memory expansion device-based test method embodiments when running.

[0098] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0099] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned test method embodiments based on a memory expansion device are implemented.

[0100] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned test method embodiments based on a memory expansion device.

[0101] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the claimed application. Accordingly, modifications and / or additions, other than those explicitly described herein, can be obvious to those skilled in the art in the light of this disclosure. The claimed application is intended to embrace all such modifications and / or additions.

[0102] The above provides a test system, method, device, medium and product based on memory expansion equipment. The principles and implementation manners of the application are described by applying specific examples. The above description of the embodiments is only used to help understand the method and core idea of the application. It should be pointed out that, for those skilled in the art, without departing from the principles of the application, some improvements and modifications can be made to the application, and these improvements and modifications also fall within the protection scope of the application.

Claims

1. A test system based on a memory expansion device, characterized in that: The invention comprises a processor, a memory expansion interconnection component and a memory expansion device; wherein the memory expansion interconnection component is located outside the processor; The processor is connected to the memory expansion interconnect component via a memory expansion bus; The memory expansion interconnection component is connected to the memory expansion device via a serial bus.

2. The memory expansion device-based test system according to claim 1, wherein: The memory expansion interconnect assembly includes a memory expansion controller and a switching device; The processor is connected to the memory expansion controller via a memory expansion bus; The memory expansion controller is connected to the switching device via a serial bus; The switching device is connected to at least one memory expansion device via a serial bus.

3. The memory expansion device-based test system according to claim 2, wherein: The number of the memory expansion devices is related to the number of ports of the switching device; one port is connected to one memory expansion device; When the number of the memory expansion devices exceeds the number of ports of a switching device, a plurality of switching devices are connected to the memory expansion device via a serial bus.

4. The memory expansion device-based test system according to claim 3, wherein: The memory expansion device is connected between multiple switching devices in a cascade manner, wherein the first port of the current switching device is connected to the second port of the previous switching device via a serial bus; the second port of the current switching device is connected to the first port of the next switching device via a serial bus; wherein the first port of the first switching device is connected to the memory expansion controller via a serial bus.

5. The memory expansion device-based test system according to claim 3, wherein: The memory expansion device is connected between multiple switching devices in a multi-tree manner, with the first switching device serving as a root node, and the first port of the first switching device being connected to the memory expansion controller via a serial bus; The remaining ports of the first switching device except the first port are connected to the switching device serving as a child node and / or the memory expansion device via a serial bus.

6. The memory expansion device-based test system according to claim 1, wherein: The test system further includes a simulation object unit; The simulation object unit is connected to the processor and the memory expansion interconnection component via a memory expansion bus, and is used to construct at least one memory access request.

7. The memory expansion device-based test system according to claim 1, wherein: The test system also includes a local memory device; The local memory device is connected to the processor via a memory expansion bus.

8. A test method based on a memory expansion device, characterized in that: The method is applied to a test system, the test system comprising a processor, a memory expansion interconnect assembly, and a memory expansion device; wherein the memory expansion interconnect assembly is located outside the processor; the processor and the memory expansion interconnect assembly are connected via a memory expansion bus; the memory expansion interconnect assembly and the memory expansion device are connected via a serial bus, and the method comprises: Controlling the memory expansion interconnect component to convert the memory access request issued by the processor to obtain a target request identified by the memory expansion device; and determining a mounted target memory expansion device based on address information of the target request; The target memory expansion device is controlled to feed corresponding target data back to the processor through the memory expansion interconnect component.

9. The memory expansion device-based testing method according to claim 8, characterized in that: Responding to a memory access request issued by the processor, including: receiving an instruction set of a processor of a target type based on the simulation platform; A corresponding memory access request is generated according to the instruction set, so that the memory expansion interconnect component can respond to the memory access request.

10. The memory expansion device-based testing method according to claim 9, wherein: Converting the memory access request to obtain a target request recognized by the memory expansion device includes: pre-defining an adapter class for a processor of the target type; Converting the address format of the memory access request according to the address format of the adapter class to obtain a first address format; Converting the data format of the memory access request according to the data format of the adapter class to obtain a first data format; Converting the operation type format of the memory access request according to the operation type format of the adapter class to obtain a first operation type format; Converting the request size of the memory access request according to the request size of the adapter class to obtain a first request size; The target request is determined according to the first address format, the first data format, the first operation type format, and the first request size.

11. The memory expansion device-based testing method according to claim 8, wherein: The memory expansion interconnection component includes a memory expansion controller and a switching device; the processor is connected to the memory expansion controller via a memory expansion bus; The memory expansion controller is connected to the switching device via a serial bus; when the switching device is connected to at least one memory expansion device via a serial bus and the number of the switching device is one, determining a mounted target memory expansion device according to the address information of the target request, including: Pre-establishing a first address mapping table between the requested address information and the address information of the memory expansion device in the switching device; Determining a corresponding address range according to the first address mapping table and the address information of the target request; The target memory expansion device is determined according to the address range.

12. The memory expansion device-based testing method according to claim 8, wherein: The memory expansion interconnection component includes a memory expansion controller and a switching device; the processor is connected to the memory expansion controller via a memory expansion bus; The memory expansion controller is connected to the switching device via a serial bus; when the switching device is connected to at least one memory expansion device via a serial bus and there are multiple switching devices, the multiple switching devices are connected in a cascade manner, and the connection process of the cascade manner includes: In the case where the number of the memory expansion devices exceeds the number of ports of a switching device, the number of the switching devices is determined according to the number of the memory expansion devices and the number of reserved ports of the switching device; wherein the reserved ports are ports of the switching device excluding ports connected to the next switching device and the previous switching device, and are used to connect to the memory expansion device; The memory expansion device is connected according to the number of the switching devices and the corresponding number of reserved ports.

13. The memory expansion device-based testing method according to claim 8, wherein: The memory expansion interconnection component includes a memory expansion controller and a switching device; the processor is connected to the memory expansion controller via a memory expansion bus; The memory expansion controller is connected to the switching device via a serial bus; when the switching device is connected to at least one memory expansion device via a serial bus and there are multiple switching devices, the multiple switching devices are connected using a multi-tree method, and the multi-tree connection process includes: Get the performance parameters of multiple memory expansion devices; Performing a ranking process based on multiple performance parameters to determine memory expansion devices within their respective ranks; Treat memory expansion devices at the same level as child nodes of the same level; Assign subnodes of the same level to the same switching device; Arrange memory expansion devices at different levels to child nodes and parent nodes at different levels to determine the multi-tree levels corresponding to multiple switching devices; The connection relationship between the switching device and the memory expansion device is determined according to the multitree level.

14. The memory expansion device-based testing method according to claim 12, wherein: Determining a mounted target memory expansion device according to the address information of the target request includes: Pre-acquire address tag information of the switching devices to which the plurality of memory expansion devices belong; Pre-establishing a second address mapping table between the requested address information, the address information of the memory expansion device, and the address tag information of different switching devices in the first switching device; Determining target address tag information and a target address range according to the second address mapping table and the address information of the target request; The target memory expansion device is determined according to the target address tag information and the target address range.

15. The memory expansion device-based testing method according to claim 13, wherein: Determining a mounted target memory expansion device according to the address information of the target request includes: Pre-acquire address tag information and corresponding node levels of the switching devices to which the plurality of memory expansion devices belong; Pre-establishing a third address mapping table between the requested address information, the address information of the memory expansion device, the address tag information of different switching devices, and the node levels in the first switching device; Determining target address tag information, target address range, and target node level according to the third address mapping table and the address information of the target request; The target memory expansion device is determined according to the target address tag information, the target address range, and the target node level.

16. The memory expansion device-based testing method according to any one of claims 11 to 13, characterized in that: Before converting the memory access request to obtain a target request recognized by the memory expansion device, the method further includes: Obtaining a first critical number of requests and a first actual number of requests stored in a request queue within the memory expansion controller; When the difference between the first critical request quantity and the first actual request quantity is smaller than a first threshold, a first buffer request instruction is sent to the processor to slow down the issuance of the memory access request.

17. The memory expansion device-based testing method according to claim 16, wherein: Converting the memory access request to obtain a target request recognized by the memory expansion device includes: When the difference between the first critical request quantity and the first actual request quantity is greater than or equal to a first threshold, encapsulating the memory access request to obtain first encapsulated data; comparing the data specification of the first packaged data with the data specification of the preset packaged data; If the data specification of the first encapsulated data reaches the data specification of the preset encapsulated data, the first encapsulated data is converted to obtain a target request, and is transmitted to the switching device.

18. The memory expansion device-based testing method according to any one of claims 11 to 13, characterized in that: The target data processing process of the target memory expansion device includes: Parsing and encapsulating the target request to obtain second encapsulated data; Sending the second encapsulated data to the memory corresponding to the memory expansion device for memory access to obtain target data; Sending the target data to a sending request queue of the target memory expansion device, and encapsulating the target data to obtain third encapsulated data; comparing the data specification of the third package data with the data specification of the preset package data; If the data specification of the third encapsulated data reaches the data specification of the preset encapsulated data, the third encapsulated data is sent to the switching device and transmitted to the processor via the memory expansion controller.

19. The memory expansion device-based testing method according to claim 18, wherein: Before sending the target data to the sending request queue of the target memory expansion device, the method further includes: Obtaining a second critical number of requests and a stored second actual number of requests of a sending request queue of the target memory expansion device; When the difference between the second critical request quantity and the second actual request quantity is smaller than a second threshold, a second buffer request instruction is sent to the switching device to slow down the sending of the target data.

20. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the memory expansion device-based testing method as claimed in any one of claims 8 to 19 when executing the computer program.

21. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the test method based on the memory expansion device according to any one of claims 8 to 19 are implemented.

22. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the memory expansion device-based testing method according to any one of claims 8 to 19 are implemented.

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