Etching process development method, etching process and semiconductor product

Abstract

The invention relates to an etching process development method, and the method comprises the steps: 1, carrying out the exposure of different regions of a same wafer through employing different photomasks, and forming different process layer patterns; 2, after photoetching is completed, photoetching key size data are collected; 3, adjusting etching parameters according to the photoetching key size data, and performing etching operation; step 4, after etching is completed, collecting etching critical dimension data; and step 5, failure analysis is carried out, a profile morphology result is confirmed, and whether the photoetching critical dimension data and the etching critical dimension data meet process specification requirements is confirmed. An independent pattern area corresponding to the same process layer of different products or different process layers of the same product is constructed on the same wafer. And the etching core parameters are dynamically regulated and controlled according to the pattern of each region, so that differential etching accurate control on different regions is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to an etching process development method, an etching process and a semiconductor product. BACKGROUND

[0002] In the current global semiconductor market competition is becoming increasingly fierce, and the technology iteration speed is accelerating, and the product life cycle is continuously shortened. Enterprises continue to pursue shorter product development cycles and faster production rhythms in order to seize the technology highland and market share. Shortening the research and development time not only can accelerate the landing and application of advanced technology nodes, but also can significantly reduce development costs and improve investment returns. This trend forces enterprises to optimize the research and development management system, strengthen multi-department cooperation, and integrate design and manufacturing links, so as to realize the rapid response to market demand, and ultimately build the core competitiveness of enterprises.

[0003] In the semiconductor manufacturing process, etching is a key link of pattern transfer, and its precision and stability directly affect the device performance and yield. Especially for critical layers such as gate, via and other fine structures, the quality of etching profile is crucial. In order to accurately evaluate the etching effect, the traditional method often relies on physical slicing combined with scanning electron microscope (SEM) to observe and measure the profile morphology. This destructive detection method means that different products in the same level or different key layers in the same product need to be independently developed and verified due to the differences in their structural characteristics and process requirements.

[0004] Under the traditional development mode, the process debugging of each layer needs to consume a whole wafer for multiple tests and final slicing verification, resulting in high material and time costs. In addition, process development involves multiple highly coupled links such as lithography and etching, and requires repeated optimization of photoresist process, adjustment of etching parameters, and profile verification, forming an iterative cycle. Usually, a single lithography-etching cycle takes 1-2 days, and completing the development of a stable process often needs to go through multiple iterations, resulting in a single layer process development cycle of 4 to 5 days. With the continuous miniaturization of technology nodes and the increasing complexity of three-dimensional structures, this inefficient mode of slicing-dependent and serial development has become a significant bottleneck restricting the development efficiency of advanced processes, and innovative methods are needed to achieve a breakthrough in improvement. SUMMARY

[0005] The present invention aims to provide an etching process development method, etching process, and semiconductor product. Adopting the concept of "wafer integrated development," two to three masks with differentiated patterns are designed under the basic conditions of consistent film material, similar transmittance, and similar PRS requirements. Through the precise coordination of the zoned exposure and development processes, independent pattern areas corresponding to the same process layer of different products or different process layers of the same product are constructed on the same wafer. Subsequently, based on the unique process requirements of the patterns in each region, the core parameters of the etching recipe (pressure, power, gas type, and ratio) are dynamically adjusted to achieve precise control of differentiated etching in different regions. Ultimately, only a single slice analysis is required to simultaneously obtain etching profile data for different product process layers or different process layers of the same product. The present invention is specifically implemented through the following technical solutions: According to a first aspect of the present application, there is provided an etching process development method, comprising: Step 1: Use different masks to expose different areas of the same wafer to form different process layer patterns; Step 2: After the lithography is completed, collect the lithography key dimension data; Step 3: adjusting etching parameters according to the photolithography critical dimension data and performing etching operation; Step 4: After etching is completed, collect etching key dimension data; Step 5: Perform failure analysis, confirm the cross-sectional morphology results, and confirm whether the photolithography critical dimension data and etching critical dimension data meet the process specification requirements.

[0006] Preferably, in step 1, the process layer patterns are process layers of different products or different process layers of the same product.

[0007] Preferably, the thin film layer materials, thicknesses and doping types of the different process layer patterns on the same wafer match each other, and the transmittance difference at the critical wavelength is within ±10%.

[0008] Preferably, the different process layer patterns are one or more of an up-and-down arrangement, a left-and-right arrangement, and a cross arrangement, and the process layer patterns are independently partitioned.

[0009] Preferably, in step 3, adjusting the etching parameters includes: adjusting the pressure of the back side helium cooling system, adjusting the etching power, and adjusting the etching gas parameters for etching.

[0010] Preferably, the etching gas parameter is to adjust a gas combination, and the gas combination includes one or more combinations of C4F8, C4F6, C5F8, CF4, CHF3, O2 and Ar.

[0011] Preferably, the photolithography critical dimension and the etching critical dimension are measured and collected by a scanning tunneling microscope.

[0012] Preferably, in step 5, the indicators for confirming the cross-sectional morphology result include sidewall angle, bottom roughness, and whether there is etching residue.

[0013] According to a second aspect of the present application, an etching process is provided, which adopts the above-mentioned etching process development method.

[0014] According to a third aspect of the present application, a semiconductor product is provided, which adopts the above etching process.

[0015] The benefits of this etching process development approach are as follows: Compared to the traditional process model of "single-layer (process layer) single wafer development, 4-5 day cycle, and multiple slicing", this solution achieves three core breakthroughs through a collaborative optimization mechanism of mask partition design and dynamic matching of etching parameters: 1. Increased efficiency: 2-3 layers of process validation can be completed within the same development cycle, increasing development efficiency by 100%-200%; 2. Sharp cost reduction: The single-wafer multi-layer integrated design reduces slicing costs by more than 60%, while also reducing wafer consumables loss; Precision assurance: By independently controlling partition parameters, the critical dimensions of each layer's etching profile are on par with the accuracy of traditional single-layer development. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the steps of an etching process development method of the present invention; Figure 2 This is a cross-sectional structural diagram of etching of the same process layer of different products in Example 1 of the present invention; Figure 3 This is an etching cross-sectional structure diagram of different process layers of the same product in Example 2 of the present invention. DETAILED DESCRIPTION

[0017] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0018] It should be noted that the above detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs.

[0019] like Figure 1As shown, the etching process development method of the present application includes the following steps: Step 1: Use different masks to expose different areas of the same wafer to form different process layer patterns; In this step, process layer patterns for the same process layer across different products are selected, with the same film and a TR (Thickness Range) difference within ±10%. Alternatively, process layer patterns for different process layers within the same product are selected, with the same film and a TR difference within ±10%. The required thin film material, thickness, and doping type for different process layer patterns on the same wafer are matched, enabling process development on the same wafer.

[0020] During the photolithography process, different process layer patterns are arranged in one or more of a vertical, horizontal, or crosswise arrangement, with each layer pattern being independently partitioned. Typically, a horizontally or vertically symmetrical layout is employed (for example, the left half is exposed using mask A, and the right half is exposed using mask B). This allows for simultaneous verification of the replication of two different graphic designs under the same process conditions.

[0021] Step 2: After the lithography is completed, collect the lithography key dimension data; In this step, after the photolithography process is complete but before etching begins, a scanning electron microscope (SEM) or other metrology equipment is used to measure and collect the critical dimension (CD) data of the developed photoresist pattern. This data serves as a baseline value before etching.

[0022] Step 3: adjusting etching parameters according to the photolithography critical dimension data and performing etching operation; In this step, adjusting the etching parameters includes adjusting the pressure of the backside helium cooling system, adjusting the etching power (high-frequency power and low-frequency power), and adjusting the etching gas parameters for etching. The etching gas parameters are adjusted gas combinations, and the gas combination includes one or more combinations of C4F8, C4F6, C5F8, CF4, CHF3, O2, and Ar.

[0023] Step 4: After etching is completed, collect etching key dimension data; In this step, after the etching process is completed and the photoresist is removed, the SEM is again used to measure and collect critical dimension (CD) data of the pattern that has been transferred to the underlying film.

[0024] Step 5: Perform failure analysis, confirm the cross-sectional morphology results, and confirm whether the photolithography critical dimension data and etching critical dimension data meet the process specification requirements.

[0025] In this step, confirmation is performed through profile analysis (FA). Typically, the sample is sectioned using a scanning electron microscope or transmission electron microscope (TEM) (e.g., using a focused ion beam (FIB)), and the profile of the pattern is then observed. Indicators to monitor include sidewall angle (perpendicularity), bottom roughness, the presence of etching residues, and the presence of overetching or undercutting.

[0026] Comprehensively evaluate critical dimension (CD) data and profile results to confirm whether they fully meet product requirement specifications (PRS). This includes CD uniformity and repeatability, as well as whether the profile meets design requirements. If so, the formulation is solidified. If not, repeat the above steps for the next round of parameter adjustment and verification based on the current experimental data.

[0027] Example 1 In a specific embodiment, for etching PRS (angle ≥ 86°) of the same layer pattern of different products, the specific steps are as follows: 1. Photolithography specific area exposure preparation like Figure 2 As shown, a wafer integrating the same layer pattern for two different products was selected to form the layer 1 pattern for product A and the layer 1 pattern for product B, with the etch PRS (Process Requirement Specification) for both being essentially identical. Preliminary photolithography and development processes ensured that the two patterns formed independent partitions on the wafer, and that the photolithography critical dimensions (CDs) were collected, as shown in the following table: The critical dimension CD of the same layer pattern lithography of different products matches the traditional single layer CD

[0028]

[0029] HC (Harmonization Confidence) analysis: The mean values ​​of the Litho partition 5-point CD and the FULL map CD are M.R_1=0.5≤1.5 and M.R_2=0.8≤1.5. Therefore, there is no significant difference between the two methods.

[0030] 2. Etching core parameter adjustment For dielectric etching, by optimizing the recipe parameters for the gas combination (C4F8 / C4F6 / C5F8 / CF4 / CHF3 / O2 / AR), pressure adjustment (5-300mT), etching power setting (HF / LF: 50-2500W), and backside helium (back He) cooling system pressure setting (5-30T), wafer etching and stripping were performed, and the etching critical dimensions (CDs) were collected, as shown in the following table: The critical dimension CD of the same layer pattern etching of different products matches the traditional single layer CD

[0031]

[0032] Harmonization Confidence (HC) analysis: The mean values ​​of the 5-point CD in the etch partition and the full map CD are M.R_1 = 0.2 ≤ 1.5 and M.R_2 = 1.2 ≤ 1.5. Therefore, there is no significant difference between the two methods.

[0033] 3. Perform FA according to the handbook to confirm whether the profile and CD meet the PRS requirements.

[0034] Example 2 In this embodiment, for etching PRS (angle ≥ 86°) of different layer patterns of the same product, the specific steps are as follows: 1. Photolithography specific area exposure preparation like Figure 3 As shown, a wafer integrating different layer patterns for the same product was selected to form the A layer 1 pattern and the A layer 2 pattern, with the etch PRS (Process Requirement Specification) for both patterns remaining essentially identical. Preliminary photolithography and development processes ensured that the two patterns formed independent partitions on the wafer, and that the photolithography critical dimensions (CDs) were collected. Specific data is shown in the table below: The critical dimension CD of different layer pattern lithography of the same product matches the traditional single layer CD

[0035]

[0036] HC (Harmonization Confidence) analysis: The mean values ​​of the Litho partition 5-point CD and the FULL map CD are M.R_1=0.4≤1.5 and M.R_2=1.3≤1.5. Therefore, there is no significant difference between the two methods.

[0037] 2. Etching core parameter adjustment For dielectric etching, wafer etching and resist stripping are performed by optimizing recipe parameters, such as the gas combination (C4F8 / C4F6 / C5F8 / CF4 / CHF3 / O2 / AR), pressure adjustment (5-300mT), etching power setting (HF / LF: 50-2500W), and back helium (back He) cooling system pressure setting (5-30T).

[0038] Poly etching is performed by optimizing the gas combination (SF6 / Cl2 / BCl3 / CF4 / CHF3 / O2 / AR / HeO / N2), pressure adjustment (5-300mT), etching power setting (HF / LF: 50-2500W), and backside helium (back He) cooling system pressure setting (5-30T). The wafer is etched, polymer is removed, and the etched critical dimensions (CDs) are collected. The specific inputs are shown in the following table: The critical dimension CD of the same layer pattern etching of different products matches the traditional single layer CD

[0039]

[0040] Harmonization Confidence (HC) analysis: The mean values ​​of the 5-point CD in the etch partition and the full map CD are M.R_1=0.3≤1.5 and M.R_2=1.35≤1.5. Therefore, there is no significant difference between the two methods.

[0041] FA Perform FA according to the handbook to confirm whether the profile and CD meet the PRS requirements.

[0042] By adopting the aforementioned etching process development approach, compared to the traditional process model of "single-layer, single-wafer development, 4-5 day cycle, and multiple slicing," this solution achieves three core breakthroughs through a collaborative optimization mechanism of mask partition design and dynamic matching of etching parameters: 1. Increased efficiency: 2-3 layers of process validation can be completed within the same development cycle, increasing development efficiency by 100%-200%; 2. Sharp cost reduction: Single wafer multi-layer integrated design reduces slicing costs by more than 60%, while also reducing wafer consumables loss 3. Accuracy assurance: Through independent control of partition parameters, the critical dimensions of each layer etching profile are on par with the accuracy of traditional single-layer development.

[0043] This integrated process of "one exposure - one etching - one slicing" breaks through the efficiency bottleneck while taking into account the rigor and economy of process verification, providing a competitive and feasible innovative path for semiconductor etching process development.

[0044] It should be noted that the terms used herein are intended only to describe specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0045] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0046] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, product, or apparatus.

[0047] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be subsequently positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0048] In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless the context dictates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

[0049] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for developing an etching process, characterized in that: The method comprises: Step 1: Use different masks to expose different areas of the same wafer to form different process layer patterns; Step 2: After the lithography is completed, collect the lithography key dimension data; Step 3: adjusting etching parameters according to the photolithography critical dimension data and performing etching operation; Step 4: After etching is completed, collect etching key dimension data; Step 5: Perform failure analysis, confirm the cross-sectional morphology results, and confirm whether the photolithography critical dimension data and etching critical dimension data meet the process specification requirements.

2. The etching process development method according to claim 1, characterized in that: In step 1, the process layer patterns are process layers of different products or different process layers of the same product.

3. The etching process development method according to claim 2, characterized in that: The thin film layer material, thickness and doping type of the different process layer patterns on the same wafer match each other, and the transmittance difference at the key wavelength is within ±10%.

4. The etching process development method according to claim 1, characterized in that: The different process layer patterns are one or more of up-and-down arrangement, left-and-right arrangement, and cross arrangement, and the process layer patterns are independent partitions.

5. The etching process development method according to claim 1, characterized in that: In step 3, adjusting the etching parameters includes: adjusting the pressure of the back side helium cooling system, adjusting the etching power, and adjusting the etching gas parameters for etching.

6. The etching process development method according to claim 5, characterized in that: The etching gas parameters are to adjust the gas combination, and the gas combination includes one or more combinations of C4F8, C4F6, C5F8, CF4, CHF3, O2 and Ar.

7. The etching process development method according to claim 1, characterized in that: The photolithography critical dimensions and the etching critical dimensions are measured and collected by a scanning tunneling microscope.

8. The etching process development method according to claim 1, characterized in that: In step 5, the indicators for confirming the cross-sectional morphology results include sidewall angle, bottom roughness, and the presence of etching residues.

9. An etching process, characterized in that: The etching process development method according to any one of claims 1 to 8 is adopted.

10. A semiconductor product, characterized in that: The etching process according to claim 9 is adopted.

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