Digital chaotic circuit system and method

Abstract

The invention provides a digital chaotic circuit system and a design method thereof, and the method comprises the steps: carrying out the quantization preprocessing of an analog chaotic signal, and generating an initial quantization chaotic signal; original signals from an external signal source are verified, sampled and preprocessed to obtain original discrete signals, and the original discrete signals serve as signal sources of an encryption scene; the initial quantized chaotic signal and the original discrete signal are superposed to obtain a digital chaotic signal, analog-to-digital conversion of the chaotic signal is realized, the original discrete signal is effectively submerged in the initial quantized chaotic signal, and high randomness and noise-like property of the digital chaotic signal are ensured; the output state of the digital chaotic signal is adjusted according to the randomness test result of the digital chaotic signal, and the analog chaotic circuit and the digital chaotic circuit are respectively used for signal processing in the early stage and the later stage of chaotic signal generation, so that the reliability of the digital chaotic signal is improved, and the signal generation cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chaotic signal generating circuits, and in particular to a digital chaotic circuit system and a design method thereof. Background Art

[0002] Chaotic signals exhibit characteristics such as initial value sensitivity, randomness, noise-like properties, and a wideband spectrum, making them widely used in scenarios such as information encryption and secure communications. Chaotic signals are primarily generated by chaotic circuit systems, which currently include analog and digital circuit systems. Analog circuit systems generate chaotic signals with good randomness, but their complex circuit structures make precise signal generation difficult. Digital circuit systems generate chaotic signals with greater precision, simpler circuit structures, and easier signal control, but they require significant hardware resources. During chaotic signal generation, the initial signal serves as the foundation, and its sensitivity and randomness directly impact the performance of the resulting chaotic signal after subsequent processing and conversion. Current chaotic signal generation methods that utilize only analog and digital circuits cannot simultaneously meet the requirements of high randomness, noise-like properties, and low hardware cost. Furthermore, they cannot correlate the chaotic signal generation process with specific external signals, reducing the compatibility and applicability of chaotic signals in various encryption scenarios. Summary of the Invention

[0003] The purpose of the present invention is to provide a digital chaotic circuit system and a design method thereof, which quantizes and preprocesses an analog chaotic signal to generate an initial quantized chaotic signal; verifies and samples the original signal from an external signal source to obtain an original discrete signal, which is used as a signal source for an encryption scenario; superimposes the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, realizes the conversion of the chaotic signal from analog to digital, effectively submerges the original discrete signal in the initial quantized chaotic signal, and ensures the high randomness and noise-like properties of the digital chaotic signal; and further adjusts the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal, processes the analog chaotic signal and the digital chaotic signal respectively in the early and late stages of chaotic signal generation, thereby improving the reliability of the digital chaotic signal and reducing the signal generation cost.

[0004] The present invention is achieved through the following technical solutions:

[0005] A digital chaotic circuit system, comprising:

[0006] A simulated chaotic signal generator, used for generating a simulated chaotic signal;

[0007] A first signal preprocessor, configured to perform quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal;

[0008] The second signal preprocessor is used to verify the original signal from the external signal source and then perform sampling preprocessing on the verified original signal to obtain an original discrete signal;

[0009] A digital chaotic converter, configured to superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal;

[0010] The signal output device is used to adjust the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal.

[0011] Optionally, the simulated chaotic signal generator includes:

[0012] An original chaotic signal source, used to generate a binary chaotic signal;

[0013] A D / A conversion circuit is used to convert the binary chaotic signal into an analog chaotic signal;

[0014] an oscilloscope verification circuit, used to obtain and analyze the chaotic attractor phase diagram of the simulated chaotic signal to determine whether the chaotic simulation signal matches the simulation result;

[0015] The filtering and amplifying circuit is used to sequentially perform low-pass filtering and amplifying processing on the simulated chaotic signal matching the simulation result.

[0016] Optionally, the first signal preprocessor is configured to perform quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal, comprising:

[0017] Performing specific bit quantization acquisition on the simulated chaotic signal to obtain a discrete signal sequence; wherein the discrete signal sequence includes a plurality of signal subsequences with specific bit numbers;

[0018] performing a shift difference operation on all signal subsequences under the discrete signal sequence, and determining the number of all valid random bits contained in the discrete signal sequence;

[0019] Generate an initial quantized chaotic signal according to all effective random bit numbers;

[0020] The second signal preprocessor is used to verify the original signal from the external signal source and then perform sampling preprocessing on the original signal that has successfully been verified to obtain an original discrete signal, including:

[0021] Authenticating the external signal source to determine whether the external signal source meets the preset identity conditions;

[0022] Performing noise reduction and compression processing on an original signal from an external signal source that meets a preset identity condition, and verifying whether the original signal meets a preset effective signal-to-noise ratio condition;

[0023] According to the preset sampling frequency, the original signal that meets the preset effective signal-to-noise ratio condition is sampled and preprocessed to obtain the original discrete signal.

[0024] Optionally, performing specific bit quantization acquisition on the simulated chaotic signal to obtain a discrete signal sequence includes:

[0025] Step S1, using the following formula (1), the simulated chaotic signal is quantized and collected with a specific number of bits.

[0026]

[0027] In the above formula (1), y[n] represents the discrete signal sequence after quantization; R[n] represents the local dynamic range, that is, the sliding window; b[n] represents the number of adaptive bits; x(n×T s ) represents the simulated chaotic signal; T s represents the sampling interval; n represents the number of sampling times; Indicates rounding down;

[0028] Step S2, using the following formula (2), according to the quantized discrete signal sequence, obtain the estimated entropy of the subsequence,

[0029]

[0030] In the above formula (2), H(S k ) represents the estimated entropy; N represents the number of preset quantization levels; p j Indicates S k The probability that the sample value falls into the jth quantization interval; S k It represents a number of signal subsequences with specific bits, that is, the k-th signal subsequence extracted from y[n];

[0031] Step S3, using the following formula (3), according to the target entropy, adjust the control of the digital chaotic circuit system on the chaotic effect,

[0032] u[k]=K P ×[H0-H(S k )](3)

[0033] In the above formula (3), u[k] represents the control output, which is an adjustable parameter applied to the digital chaotic circuit system; K P represents the proportional gain; H0 represents the target entropy;

[0034] If u[k]<0, the digital chaotic circuit system is controlled to suppress chaos; otherwise, the digital chaotic circuit system is controlled to restore chaos.

[0035] Optionally, the digital chaotic converter is configured to superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, including:

[0036] According to the time sequence difference between the initial quantized chaotic signal and the original discrete signal, a superimposition clock signal of the initial quantized chaotic signal and the original discrete signal is determined;

[0037] According to the superimposition clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal;

[0038] The signal outputter is configured to adjust an output state of the digital chaotic signal according to a randomness test result of the digital chaotic signal, including:

[0039] A plurality of sub-signal sequences are extracted from the digital chaotic signal, and randomness tests are performed on all the sub-signal sequences to determine a proportion of sub-signal sequences passing the randomness tests among all the sub-signal sequences;

[0040] The proportion is compared with a preset proportion threshold value, if the proportion is greater than or equal to the preset proportion threshold value, the digital chaotic signal is directly outputted, and if the proportion is less than the preset proportion threshold value, the digital chaotic signal is not outputted.

[0041] A design method of a digital chaotic circuit system, including:

[0042] An analog chaotic signal is generated, and the analog chaotic signal is quantized and preprocessed to generate an initial quantized chaotic signal;

[0043] An original signal from an external signal source is checked, and a successfully checked original signal is sampled and preprocessed to obtain an original discrete signal;

[0044] The initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal;

[0045] According to a randomness test result of the digital chaotic signal, an output state of the digital chaotic signal is adjusted.

[0046] Optionally, the analog chaotic signal is generated, including:

[0047] A binary chaotic signal is generated, and the binary chaotic signal is converted into an analog chaotic signal;

[0048] The analog chaotic signal is analyzed in a chaotic attractor phase diagram to determine whether the chaotic analog signal matches a simulation result;

[0049] The analog chaotic signal matching the simulation result is sequentially subjected to low-pass filtering and amplification processing.

[0050] Optionally, performing quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal includes:

[0051] Performing specific bit quantization acquisition on the simulated chaotic signal to obtain a discrete signal sequence; wherein the discrete signal sequence includes a plurality of signal subsequences with specific bit numbers;

[0052] performing a shift difference operation on all signal subsequences under the discrete signal sequence, and determining the number of all valid random bits contained in the discrete signal sequence;

[0053] Generate an initial quantized chaotic signal according to all effective random bit numbers;

[0054] After verifying the original signal from the external signal source, the successfully verified original signal is sampled and preprocessed to obtain the original discrete signal, including:

[0055] Authenticating the external signal source to determine whether the external signal source meets the preset identity conditions;

[0056] Performing noise reduction and compression processing on an original signal from an external signal source that meets a preset identity condition, and verifying whether the original signal meets a preset effective signal-to-noise ratio condition;

[0057] According to the preset sampling frequency, the original signal that meets the preset effective signal-to-noise ratio condition is sampled and preprocessed to obtain the original discrete signal.

[0058] Optionally, superimposing the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal comprises:

[0059] Determining a superimposed clock signal of the initial quantized chaotic signal and the original discrete signal according to a timing difference between the initial quantized chaotic signal and the original discrete signal;

[0060] According to the superimposed clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal;

[0061] Adjusting the output state of the digital chaotic signal according to a randomness test result of the digital chaotic signal includes:

[0062] extracting a plurality of sub-signal sequences from the digital chaotic signal, performing a randomness test on all the sub-signal sequences, and determining a proportion of the sub-signal sequences that pass the randomness test in all the sub-signal sequences;

[0063] The proportion is compared with a preset proportion threshold value, if the proportion is greater than or equal to the preset proportion threshold value, the digital chaotic signal is directly output; if the proportion is less than the preset proportion threshold value, the digital chaotic signal is not output.

[0064] Compared with the prior art, the present application has the following beneficial effects:

[0065] The digital chaotic circuit system and the design method thereof provided by the present application quantize and preprocess an analog chaotic signal to generate an initial quantized chaotic signal; check and sample a raw signal from an external signal source to obtain a raw discrete signal, which is used as a signal source of an encryption scene; superimpose the initial quantized chaotic signal and the raw discrete signal to obtain a digital chaotic signal, thereby realizing the conversion of the chaotic signal from analog to digital, effectively submerging the raw discrete signal in the initial quantized chaotic signal, and ensuring the high randomness and noise-like nature of the digital chaotic signal; and according to the randomness test result of the digital chaotic signal, the output state of the digital chaotic signal is adjusted, the analog chaotic signal and the digital chaotic signal are processed in the early and late stages of the generation of the chaotic signal, and the reliability of the digital chaotic signal is improved and the signal generation cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings. Among them:

[0067] Figure 1 The structural diagram of the digital chaotic circuit system provided by the present application.

[0068] Figure 2 The structural diagram of the analog chaotic signal generator.

[0069] Figure 3 The chaotic attractor phase diagram of the actually generated analog chaotic signal.

[0070] Figure 4 The chaotic attractor phase diagram of the analog chaotic signal generated by Matlab software simulation.

[0071] Figure 5 The flowchart of the design method of the digital chaotic circuit system provided by the present application. DETAILED DESCRIPTION

[0072] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0073] As used herein, the terms "comprise," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0074] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0075] See also Figure 1 As shown, an embodiment of the present application provides a digital chaotic circuit system. The digital chaotic circuit system includes:

[0076] A simulated chaotic signal generator, used for generating a simulated chaotic signal;

[0077] A first signal preprocessor, configured to perform quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal;

[0078] The second signal preprocessor is used to verify the original signal from the external signal source and then perform sampling preprocessing on the verified original signal to obtain an original discrete signal;

[0079] A digital chaotic converter is used to superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal;

[0080] The signal output device is used for adjusting the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal.

[0081] The beneficial effects of the above embodiments are as follows: the digital chaotic circuit system quantizes and preprocesses the analog chaotic signal to generate an initial quantized chaotic signal; verifies and samples the original signal from the external signal source to obtain the original discrete signal, which is used as the signal source for the encryption scenario; superimposes the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, realizing the conversion of the chaotic signal from analog to digital, effectively submerging the original discrete signal in the initial quantized chaotic signal, and ensuring the high randomness and noise-like properties of the digital chaotic signal; and also adjusts the output state of the digital chaotic signal according to the randomness test results of the digital chaotic signal, and processes the analog chaotic signal and the digital chaotic signal in the early and late stages of chaotic signal generation, respectively, to improve the reliability of the digital chaotic signal and reduce the signal generation cost.

[0082] In another embodiment, the simulated chaotic signal generator comprises:

[0083] An original chaotic signal source, used to generate a binary chaotic signal;

[0084] A D / A conversion circuit, used for converting a binary chaotic signal into an analog chaotic signal;

[0085] Oscilloscope verification circuit, used to obtain and analyze the chaotic attractor phase diagram of the simulated chaotic signal to determine whether the chaotic simulation signal matches the simulation result;

[0086] The filtering and amplifying circuit is used to sequentially perform low-pass filtering and amplifying processing on the simulated chaotic signal matching the simulation result.

[0087] See also Figure 2The analog chaotic signal generator utilizes a relatively simple analog circuit structure to initially generate an analog chaotic signal in the initial chaotic signal generation phase. This fully utilizes the analog chaotic signal's ability to generate highly random and accurate chaotic signals, providing a good signal foundation for subsequent digital chaotic signal generation while reducing the hardware cost of chaotic signal generation. Specifically, the analog chaotic signal generator primarily comprises an original chaotic signal source, a D / A conversion circuit (i.e., an analog-to-digital conversion circuit), an oscilloscope verification circuit, and a filtering and amplification circuit. The original chaotic signal source can be, but is not limited to, an FPGA chip EP1C6T144C8. This FPGA chip can directly generate binary chaotic signals, and the signal parameters of the binary chaotic signal can be changed by adjusting the FPGA chip's operating parameters. Considering that the binary chaotic signal is a digital signal, in order to obtain an analog chaotic signal, a D / A conversion circuit can be connected to the output of the original chaotic signal source to process and convert the binary chaotic signal into an analog chaotic signal. The D / A conversion circuit can use the D / A chip AD9707, which has a 125MSPS update rate, 8-bit resolution, differential current output and flexible power supply voltage, and can use complementary differential output to perform analog-to-digital conversion on binary chaotic signals. In the chaotic signal generation process, Matlab software is usually used to simulate the chaotic signal first to determine the generation parameters of the chaotic signal, and then the working parameters of the FPGA chip and the D / A chip are set according to the above generation parameters to generate a simulated chaotic signal. Taking into account the difference between simulation and chip signal generation and conversion, there will inevitably be differences between the simulated chaotic signal actually generated and the simulated chaotic signal simulated by software. In order to ensure that the simulated chaotic signal actually generated matches the desired signal, an oscilloscope verification circuit including an oscilloscope can be used to obtain and analyze the chaotic attractor phase diagram of the actually generated simulated chaotic signal (see Figure 3 ) and the corresponding chaotic attractor phase diagram of chaotic signal simulation using Matlab software (see Figure 4 ) to determine the difference in their phase diagrams (for example, determining the phase difference between the two phase diagrams and performing a threshold comparison on the phase difference), thereby determining whether the actually generated chaotic simulation signal matches the Matlab software simulation result. Furthermore, when it is determined that the actually generated simulated chaotic signal matches the simulation result, a filtering and amplification circuit is used to sequentially perform low-pass filtering and voltage amplification on the simulated chaotic signal to ensure that the processed simulated chaotic signal meets the requirements of subsequent quantization conversion processing. The filtering and amplification circuit can utilize commonly used low-pass filter chips and operational amplifier chips of existing technologies, which will not be described in detail here.

[0088] In another embodiment, the first signal preprocessor is used to perform quantization preprocessing on the simulated chaotic signal, and generating the initial quantized chaotic signal includes:

[0089] The simulated chaotic signal is quantized and collected with a specific number of bits to obtain a discrete signal sequence; wherein the discrete signal sequence includes a number of signal subsequences with specific number of bits;

[0090] Performing a shift difference operation on all signal subsequences under the discrete signal sequence, and determining the number of all valid random bits contained in the discrete signal sequence;

[0091] Generate an initial quantized chaotic signal according to all effective random bit numbers;

[0092] The second signal preprocessor is used to verify the original signal from the external signal source and then perform sampling preprocessing on the verified original signal to obtain the original discrete signal, including:

[0093] Authenticate the external signal source to determine whether the external signal source meets the preset identity conditions;

[0094] Performing noise reduction and compression processing on the original signal from the external signal source that meets the preset identity conditions, and verifying whether the original signal meets the preset effective signal-to-noise ratio conditions;

[0095] According to the preset sampling frequency, the original signal that meets the preset effective signal-to-noise ratio condition is sampled and preprocessed to obtain the original discrete signal.

[0096] The simulated chaotic signal generated above is a model-like chaotic signal, comprising a continuous signal sequence. To accurately and effectively superimpose it with the original signal from an external signal source, the simulated chaotic signal is first quantized and collected at a specific bit number, such as an 8-bit number, to obtain a discrete signal sequence. This discrete signal sequence then contains several 8-bit signal subsequences. This specific bit quantization can be implemented using a Cai circuit, which will not be described in detail here. A shift-differentiation operation is then performed on all 8-bit signal subsequences within the discrete signal sequence, and the number of all valid random bits contained in the discrete signal sequence is determined, thereby achieving a random transformation of all bits within the discrete signal sequence. This shift-differentiation operation can preferably be implemented using an LM317 chip. All valid random bits are then integrated to generate an initial quantized chaotic signal, ensuring that this initial quantized chaotic signal exhibits high randomness and noise-like properties.

[0097] In order to use chaotic signals to encrypt external signals, the external signal source, such as an external communication terminal, is first authenticated to obtain its identity information. If this identity information is on a preset identity whitelist, the external signal source is determined to meet the preset identity conditions; otherwise, it is determined that the external signal source does not meet the preset identity conditions. The original signal emitted by the external signal source that meets the preset identity conditions is then subjected to Kalman filtering and data compression to determine the actual signal-to-noise ratio (SNR). If the actual SNR is greater than or equal to a preset SNR threshold, the original signal is determined to meet the preset effective SNR condition; otherwise, it is determined that the original signal does not meet the preset effective SNR condition. Finally, the original signal that meets the preset effective SNR condition is sampled and preprocessed at a preset sampling frequency to obtain the original discrete signal. Through the above process, the original signal from the external signal source is digitized and denoised to ensure that the original discrete signal effectively matches the initial quantized chaotic signal.

[0098] In another embodiment, a specific number of bits is quantized and collected on the simulated chaotic signal to obtain a discrete signal sequence, including:

[0099] Step S1, using the following formula (1), the simulated chaotic signal is quantized to a specific number of bits.

[0100]

[0101] In the above formula (1), y[n] represents the discrete signal sequence after quantization; R[n] represents the local dynamic range, that is, the sliding window; b[n] represents the number of adaptive bits; x(n×T s ) represents the simulated chaotic signal; T s represents the sampling interval; n represents the number of sampling times; Indicates rounding down;

[0102] Step S2, using the following formula (2), according to the quantized discrete signal sequence, obtain the estimated entropy of the subsequence,

[0103]

[0104] In the above formula (2), H(S k ) represents the estimated entropy; N represents the number of preset quantization levels; p j Indicates S k The probability that the sample value falls into the jth quantization interval; S k It represents a number of signal subsequences with specific bits, that is, the k-th signal subsequence extracted from y[n];

[0105] Step S3, using the following formula (3), according to the target entropy, adjust the control of the digital chaotic circuit system on the chaotic effect,

[0106] u[k]=K P ×[H0-H(S k )] (3)

[0107] In the above formula (3), u[k] represents the control output, which is an adjustable parameter applied to the digital chaotic circuit system; K P represents the proportional gain; H0 represents the target entropy;

[0108] If u[k]<0, the digital chaotic circuit system is controlled to suppress chaos; otherwise, the digital chaotic circuit system is controlled to restore chaos.

[0109] Using the above formula (1), the analog chaotic signal is quantized and collected with a specific number of bits to obtain a discrete signal sequence, which can ensure that b[n] increases to capture details when the signal changes drastically; conversely, b[n] decreases to save bits; then using the above formula (2), the estimated entropy of the subsequence is obtained based on the quantized discrete signal sequence, which is convenient for subsequent control; then using the above formula (3), according to the target entropy, the control of the chaotic effect of the digital chaotic circuit system is adjusted, thereby using entropy-based control to replace complex calculations, which is more suitable for real-time systems.

[0110] In another embodiment, the digital chaotic transformer is used to superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, including:

[0111] determining a superimposed clock signal of the initial quantized chaotic signal and the original discrete signal according to a time sequence difference between the initial quantized chaotic signal and the original discrete signal;

[0112] According to the superposition clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal;

[0113] The signal output device is used to adjust the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal, including:

[0114] Extracting a number of sub-signal sequences from the digital chaotic signal, performing a randomness test on all the sub-signal sequences, and determining the proportion of the sub-signal sequences that pass the randomness test in all the sub-signal sequences;

[0115] The proportion is compared with the preset proportion threshold. If the proportion is greater than or equal to the preset proportion threshold, the digital chaotic signal is directly output; if the proportion is less than the preset proportion threshold, the digital chaotic signal is not output.

[0116] First, the signal timing difference between the initial quantized chaotic signal and the original discrete signal is obtained. A superimposed clock signal corresponding to the timing synchronization adjustment of the initial quantized chaotic signal and the original discrete signal when the initial quantized chaotic signal and the original discrete signal are superimposed is determined. That is, the initial quantized chaotic signal and the original discrete signal each adjust their timing according to the superimposed clock signal, thereby achieving timing synchronization between the initial quantized chaotic signal and the original discrete signal. Then, based on the superimposed clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed at the signal strength to obtain a digital chaotic signal, thereby ensuring that the digital chaotic signal contains information from both the initial quantized chaotic signal and the original discrete signal. To ensure that the digital chaotic signal has sufficiently high randomness, several sub-signal sequences are extracted from the digital chaotic signal. All sub-signal sequences are subjected to a randomness test using NIST SP8000-22, and the proportion of sub-signal sequences that pass the randomness test among all sub-signal sequences is determined, that is, the ratio of the number of sub-signal sequences that successfully pass NIST SP8000-22 to the total number of all sub-signal sequences is determined. The proportion is then compared with the preset proportion threshold. If the proportion is greater than or equal to the preset proportion threshold, the digital chaotic signal is directly output; if the proportion is less than the preset proportion threshold, the digital chaotic signal is not output, thereby improving the reliability of the digital chaotic signal.

[0117] See also Figure 5 As shown, an embodiment of the present application provides a design method for a digital chaotic circuit system. The design method includes:

[0118] generating a simulated chaotic signal, performing quantization preprocessing on the simulated chaotic signal, and generating an initial quantized chaotic signal;

[0119] After verifying the original signal from the external signal source, the successfully verified original signal is sampled and pre-processed to obtain the original discrete signal;

[0120] The initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal;

[0121] According to the randomness test result of the digital chaotic signal, the output state of the digital chaotic signal is adjusted.

[0122] The beneficial effects of the above embodiments are as follows: the design method of the digital chaotic circuit system quantizes and preprocesses the analog chaotic signal to generate an initial quantized chaotic signal; verifies and samples the original signal from the external signal source to obtain the original discrete signal, which is used as the signal source for the encryption scenario; superimposes the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, realizes the conversion of the chaotic signal from analog to digital, effectively submerges the original discrete signal in the initial quantized chaotic signal, and ensures the high randomness and noise-like properties of the digital chaotic signal; and also adjusts the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal, and processes the analog chaotic signal and the digital chaotic signal respectively in the early and late stages of chaotic signal generation, thereby improving the reliability of the digital chaotic signal and reducing the signal generation cost.

[0123] In another embodiment, generating a simulated chaotic signal includes:

[0124] generating a binary chaotic signal and converting the binary chaotic signal into an analog chaotic signal;

[0125] Obtain and analyze the chaotic attractor phase diagram of the simulated chaotic signal to determine whether the chaotic simulation signal matches the simulation result;

[0126] The simulated chaotic signal that matches the simulation result is processed by low-pass filtering and amplification in sequence.

[0127] In another embodiment, performing quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal includes:

[0128] The simulated chaotic signal is quantized and collected with a specific number of bits to obtain a discrete signal sequence; wherein the discrete signal sequence includes a number of signal subsequences with specific number of bits;

[0129] Performing a shift difference operation on all signal subsequences under the discrete signal sequence, and determining the number of all valid random bits contained in the discrete signal sequence;

[0130] Generate an initial quantized chaotic signal according to all effective random bit numbers;

[0131] After verifying the original signal from the external signal source, the successfully verified original signal is sampled and preprocessed to obtain the original discrete signal, including:

[0132] Authenticate the external signal source to determine whether the external signal source meets the preset identity conditions;

[0133] Performing noise reduction and compression processing on the original signal from the external signal source that meets the preset identity conditions, and verifying whether the original signal meets the preset effective signal-to-noise ratio conditions;

[0134] According to the preset sampling frequency, the original signal that meets the preset effective signal-to-noise ratio condition is sampled and preprocessed to obtain the original discrete signal.

[0135] In another embodiment, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal, including:

[0136] determining a superimposed clock signal of the initial quantized chaotic signal and the original discrete signal according to a time sequence difference between the initial quantized chaotic signal and the original discrete signal;

[0137] According to the superposition clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal;

[0138] According to the randomness test result of the digital chaotic signal, the output state of the digital chaotic signal is adjusted, including:

[0139] Extracting a number of sub-signal sequences from the digital chaotic signal, performing a randomness test on all the sub-signal sequences, and determining the proportion of the sub-signal sequences that pass the randomness test in all the sub-signal sequences;

[0140] The proportion is compared with the preset proportion threshold. If the proportion is greater than or equal to the preset proportion threshold, the digital chaotic signal is directly output; if the proportion is less than the preset proportion threshold, the digital chaotic signal is not output.

[0141] The design method of the digital chaotic circuit system of the present invention corresponds to and is consistent with the operation and effect of the above-mentioned digital chaotic circuit system, and the design method of the digital chaotic circuit system will not be repeated here.

[0142] In general, the digital chaotic circuit system and its design method quantize and preprocess the analog chaotic signal to generate an initial quantized chaotic signal; verify and sample the original signal from the external signal source to obtain the original discrete signal, which is used as the signal source for the encryption scenario; superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, realizing the conversion of the chaotic signal from analog to digital, effectively submerging the original discrete signal in the initial quantized chaotic signal, and ensuring the high randomness and noise-like properties of the digital chaotic signal; and also adjust the output state of the digital chaotic signal according to the randomness test results of the digital chaotic signal, and process the analog chaotic signal and the digital chaotic signal in the early and late stages of chaotic signal generation, respectively, to improve the reliability of the digital chaotic signal and reduce the signal generation cost.

[0143] The above is only a specific embodiment of the present invention, and any other improvements made based on the concept of the present invention are considered to be within the protection scope of the present invention.

Claims

1. A digital chaotic circuit system, characterized in that: include: A simulated chaotic signal generator, used for generating a simulated chaotic signal; A first signal preprocessor, configured to perform quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal; The second signal preprocessor is used to verify the original signal from the external signal source and then perform sampling preprocessing on the verified original signal to obtain an original discrete signal; A digital chaotic converter, configured to superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal; The signal output device is used to adjust the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal.

2. The digital chaotic circuit system according to claim 1, wherein: The simulated chaotic signal generator comprises: An original chaotic signal source, used to generate a binary chaotic signal; A D / A conversion circuit is used to convert the binary chaotic signal into an analog chaotic signal; an oscilloscope verification circuit, used to obtain and analyze the chaotic attractor phase diagram of the simulated chaotic signal to determine whether the chaotic simulation signal matches the simulation result; The filtering and amplifying circuit is used to sequentially perform low-pass filtering and amplifying processing on the simulated chaotic signal matching the simulation result.

3. The digital chaotic circuit system according to claim 1, wherein: The first signal preprocessor is used to perform quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal, which includes: Performing specific bit quantization acquisition on the simulated chaotic signal to obtain a discrete signal sequence; wherein the discrete signal sequence includes a plurality of signal subsequences with specific bit numbers; performing a shift difference operation on all signal subsequences under the discrete signal sequence, and determining the number of all valid random bits contained in the discrete signal sequence; Generate an initial quantized chaotic signal according to all effective random bit numbers; The second signal preprocessor is used to verify the original signal from the external signal source and then perform sampling preprocessing on the original signal that has successfully been verified to obtain an original discrete signal, including: Authenticating the external signal source to determine whether the external signal source meets the preset identity conditions; Performing noise reduction and compression processing on an original signal from an external signal source that meets a preset identity condition, and verifying whether the original signal meets a preset effective signal-to-noise ratio condition; According to the preset sampling frequency, the original signal that meets the preset effective signal-to-noise ratio condition is sampled and preprocessed to obtain the original discrete signal.

4. The digital chaotic circuit system according to claim 1, wherein: The simulated chaotic signal is quantized and collected with a specific number of bits to obtain a discrete signal sequence, including: Step S1, using the following formula (1), the simulated chaotic signal is quantized and collected with a specific number of bits. In the above formula (1), y[n] represents the discrete signal sequence after quantization; R[n] represents the local dynamic range, that is, the sliding window; b[n] represents the number of adaptive bits; x(n×T s ) represents the simulated chaotic signal; T s represents the sampling interval; n represents the number of sampling times; Indicates rounding down; Step S2, using the following formula (2), according to the quantized discrete signal sequence, obtain the estimated entropy of the subsequence, In the above formula (2), H(S k ) represents the estimated entropy; N represents the number of preset quantization levels; p j Indicates S k The probability that the sample value falls into the jth quantization interval; S k It represents a number of signal subsequences with specific bits, that is, the k-th signal subsequence extracted from y[n]; Step S3, using the following formula (3), according to the target entropy, adjust the control of the digital chaotic circuit system on the chaotic effect, in[k]=K P ×[H0-H(S k )](3) In the above formula (3), u[k] represents the control output, which is an adjustable parameter applied to the digital chaotic circuit system; K P represents proportional gain; H0 represents target entropy; If u[k]<0, the digital chaotic circuit system is controlled to suppress chaos; otherwise, the digital chaotic circuit system is controlled to restore chaos.

5. The digital chaotic circuit system according to claim 1, wherein: The digital chaotic converter is used to superimpose the initial quantized chaotic signal and the original discrete signal to obtain a digital chaotic signal, including: Determining a superimposed clock signal of the initial quantized chaotic signal and the original discrete signal according to a timing difference between the initial quantized chaotic signal and the original discrete signal; According to the superimposed clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal; The signal output device is used to adjust the output state of the digital chaotic signal according to the randomness test result of the digital chaotic signal, including: extracting a plurality of sub-signal sequences from the digital chaotic signal, performing a randomness test on all the sub-signal sequences, and determining a proportion of the sub-signal sequences that pass the randomness test in all the sub-signal sequences; The proportion is compared with a preset proportion threshold. If the proportion is greater than or equal to the preset proportion threshold, the digital chaotic signal is directly output; if the proportion is less than the preset proportion threshold, the digital chaotic signal is not output.

6. A design method for a digital chaotic circuit system, characterized in that: include: generating a simulated chaotic signal, and performing quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal; After verifying the original signal from the external signal source, the successfully verified original signal is sampled and pre-processed to obtain the original discrete signal; The initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal; and the output state of the digital chaotic signal is adjusted according to a randomness test result of the digital chaotic signal.

7. The design method according to claim 6, wherein: Generate simulated chaotic signals, including: generating a binary chaotic signal, and converting the binary chaotic signal into an analog chaotic signal; Obtaining and analyzing the chaotic attractor phase diagram of the simulated chaotic signal to determine whether the chaotic simulation signal matches the simulation result; The simulated chaotic signal that matches the simulation result is processed by low-pass filtering and amplification in sequence.

8. The design method according to claim 6, wherein: Performing quantization preprocessing on the simulated chaotic signal to generate an initial quantized chaotic signal includes: Performing specific bit quantization acquisition on the simulated chaotic signal to obtain a discrete signal sequence; wherein the discrete signal sequence includes a plurality of signal subsequences with specific bit numbers; performing a shift difference operation on all signal subsequences under the discrete signal sequence, and determining the number of all valid random bits contained in the discrete signal sequence; Generate an initial quantized chaotic signal according to all effective random bit numbers; After verifying the original signal from the external signal source, the successfully verified original signal is sampled and preprocessed to obtain the original discrete signal, including: Authenticating the external signal source to determine whether the external signal source meets the preset identity conditions; Performing noise reduction and compression processing on an original signal from an external signal source that meets a preset identity condition, and verifying whether the original signal meets a preset effective signal-to-noise ratio condition; According to the preset sampling frequency, the original signal that meets the preset effective signal-to-noise ratio condition is sampled and preprocessed to obtain the original discrete signal.

9. The design method according to claim 6, wherein: The initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal, comprising: Determining a superimposed clock signal of the initial quantized chaotic signal and the original discrete signal according to a timing difference between the initial quantized chaotic signal and the original discrete signal; According to the superimposed clock signal, the initial quantized chaotic signal and the original discrete signal are superimposed to obtain a digital chaotic signal; Adjusting the output state of the digital chaotic signal according to a randomness test result of the digital chaotic signal includes: extracting a plurality of sub-signal sequences from the digital chaotic signal, performing a randomness test on all the sub-signal sequences, and determining a proportion of the sub-signal sequences that pass the randomness test in all the sub-signal sequences; The proportion is compared with a preset proportion threshold. If the proportion is greater than or equal to the preset proportion threshold, the digital chaotic signal is directly output; if the proportion is less than the preset proportion threshold, the digital chaotic signal is not output.

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