Integrated circuit test method and system

Abstract

The invention relates to the technical field of integrated circuit testing, in particular to an integrated circuit testing method and system. The method comprises the following steps: carrying out power-on operation on a to-be-tested integrated circuit, carrying out probe contact standard comparison, and generating a probe contact quality evaluation code; performing probe channel distribution processing according to the probe contact quality evaluation code, performing magnetic field excitation frequency band analysis, and generating magnetic field excitation avoidance frequency band data; applying a static vector magnetic field environment to the to-be-tested integrated circuit based on the magnetic field excitation avoidance frequency band data, and performing circuit channel test processing to obtain circuit test characteristic response data; performing channel test analysis according to the circuit test characteristic response data to obtain integrated circuit test result data; and performing cross-module fault relevance detection according to the integrated circuit test result data to obtain functional module fault relevance data. Abnormal channel jump and impedance fluctuation detection of the integrated circuit is realized through multi-frequency-point probe array testing in a static magnetic field environment.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to an integrated circuit testing method and system. Background Art

[0002] In the complex environment of integrated circuits, various parasitic capacitances, inductances, and coupling effects combine with the intrinsic properties of magnetoresistive elements, resulting in a significant presence of extrinsic components in the measured signal. This situation is particularly severe during high-frequency testing, where the impact of parasitic effects on measurement results increases exponentially with increasing frequency. Furthermore, magnetoresistive elements exhibit significant anisotropy and nonlinearity, meaning their response characteristics undergo complex variations with magnetic field direction, intensity, and frequency, further complicating testing. Traditional magnetoresistive testing methods in integrated circuits primarily rely on static or low-frequency measurement techniques. While these methods perform well for measuring simple magnetoresistive structures, they have significant limitations when dealing with complex magnetoresistive elements integrated into CMOS circuits. First, they cannot provide dynamic response characteristics across a wide frequency spectrum, failing to meet the high-frequency characterization requirements of modern high-speed circuits. Second, these methods typically rely on external probing, making it difficult to precisely locate the magnetoresistive element at a specific location within the chip, severely impacting measurement accuracy. Furthermore, existing methods often confuse parasitic effects with the intrinsic properties of the magnetoresistive element during measurement, resulting in significant deviations from actual performance. Summary of the Invention

[0003] Based on this, the present invention provides an integrated circuit testing method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for testing an integrated circuit includes the following steps:

[0005] Step S1: Powering on the IC to be tested to obtain initialization test configuration data; analyzing the probe point status based on the initialization test configuration data, and performing a probe contact standard comparison to generate a probe contact quality assessment code;

[0006] Step S2: performing probe channel allocation processing according to the probe contact quality assessment code to obtain probe channel signal allocation data; performing non-magnetic field scattering parameter measurement according to the probe channel signal allocation data, and performing magnetic field excitation frequency band analysis to generate magnetic field excitation avoidance frequency band data;

[0007] Step S3: applying a static vector magnetic field environment to the integrated circuit under test based on the magnetic field excitation avoidance frequency band data, and then performing dynamic circuit channel test processing to obtain circuit test characteristic response data; wherein the circuit test characteristic response data includes electromagnetic field signal data of each channel, electrical characteristic signal data of each channel, and power supply voltage signal data;

[0008] Step S4: Identify channel jump abnormality events based on the electrical characteristic signal data of each channel; calculate impedance spectrum fluctuation rate data based on the power supply voltage signal data; perform health assessment based on the electromagnetic field signal data of each channel, channel jump abnormality events, and impedance spectrum fluctuation rate data to obtain integrated circuit test result data;

[0009] Step S5: Perform functional module mapping according to the integrated circuit test result data, and perform cross-module fault correlation detection to obtain functional module fault correlation data.

[0010] Preferably, the present invention further provides an integrated circuit testing system for executing the integrated circuit testing method described above, the integrated circuit testing system comprising:

[0011] The probe initialization module is used to power on the IC to be tested and obtain initialization test configuration data; analyze the probe point status according to the initialization test configuration data, compare the probe contact standards, and generate a probe contact quality assessment code;

[0012] The dynamic frequency band allocation module is used to perform probe channel allocation processing based on the probe contact quality assessment code to obtain probe channel signal allocation data; perform non-magnetic field scattering parameter measurement based on the probe channel signal allocation data, and perform magnetic field excitation frequency band analysis to generate magnetic field excitation avoidance frequency band data;

[0013] A magnetic field environment response module is used to apply a static vector magnetic field environment to the integrated circuit under test based on the magnetic field excitation avoidance frequency band data, and then perform dynamic circuit channel test processing to obtain circuit test characteristic response data; wherein the circuit test characteristic response data includes electromagnetic field signal data of each channel, electrical characteristic signal data of each channel, and power supply voltage signal data;

[0014] The circuit channel test module is used to identify channel jump abnormal events based on the electrical characteristic signal data of each channel; calculate the impedance spectrum fluctuation rate data based on the power supply voltage signal data; and perform health assessment based on the electromagnetic field signal data of each channel, channel jump abnormal events, and impedance spectrum fluctuation rate data to obtain integrated circuit test result data;

[0015] The fault correlation analysis module is used to map the functional modules according to the integrated circuit test result data, and perform cross-module fault correlation detection to obtain functional module fault correlation data.

[0016] The present invention establishes a reliable starting point for testing by initializing the test configuration and the probe contact quality assessment mechanism, effectively overcoming the signal distortion problem caused by poor probe contact in traditional testing, and laying the foundation for the accurate measurement of magnetoresistive element characteristics. The intelligent allocation processing of the probe channel optimizes the test resource configuration and improves the system utilization efficiency. At the same time, the combination of non-magnetic field scattering parameter measurement and magnetic field excitation frequency band analysis innovatively identifies and avoids frequency bands susceptible to interference, effectively separating parasitic effects from the intrinsic characteristics of the magnetoresistive element. The introduction of a static vector magnetic field environment in conjunction with dynamic circuit channel testing enables the comprehensive capture of the anisotropic response characteristics of the magnetoresistive element, breaking through the limitation of traditional test methods that can only measure under a single magnetic field condition. The test architecture of multi-channel parallel acquisition of multi-dimensional signals significantly improves test efficiency and provides richer parameter characterization, especially in the measurement of dynamic response characteristics in the high-frequency domain. The channel jump abnormal event identification mechanism is combined with the impedance spectrum fluctuation rate calculation to construct a health assessment system based on multi-dimensional parameters, which enables the system to more accurately reflect the true performance status of the magnetoresistive element inside the integrated circuit, effectively solving the problem of significant deviation between the measurement results of traditional methods and actual performance. The introduction of functional module mapping and cross-module fault correlation detection elevates single-point testing to system-level diagnosis, enabling the tracing of fault propagation paths and identification of associated fault points, providing new insights for comprehensive performance evaluation of complex integrated circuits. This expansion of diagnostics from point to surface significantly improves the accuracy and efficiency of fault location, reducing the time and cost of repair and design optimization. Therefore, an integrated circuit testing method of the present invention ensures high-quality transmission of test signals through probe contact quality assessment and dynamic channel allocation mechanism; adopts scattering parameter measurement and eddy current damping factor analysis in a non-magnetic field environment to accurately identify the magnetic field excitation avoidance frequency band; innovatively constructs a multi-frequency point testing system in a static vector magnetic field environment to separate electromagnetic field signals and electrical characteristic signals; establishes three-dimensional judgment criteria (rate, time, jitter) for channel jump abnormal events to achieve accurate capture of abnormal behavior; quantifies the dynamic response characteristics of integrated circuits through impedance spectrum fluctuation rate calculation; creatively maps single-channel faults to the functional module level, and uses cross-module fault correlation detection to construct a complete fault propagation network; integrates the weight calculation method of fault propagation depth and impact range to achieve accurate positioning of key fault nodes, solving the blind spot problem of traditional testing methods in complex integrated circuit fault positioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1. A schematic flow chart of the steps of the integrated circuit testing method of the present invention;

[0018] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0019] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. It is obvious that the embodiments described are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present invention.

[0020] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0021] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0022] To achieve this, please refer to Figure 1 The present invention provides an integrated circuit testing method, comprising the following steps:

[0023] Step S1: Powering on the IC to be tested to obtain initialization test configuration data; analyzing the probe point status based on the initialization test configuration data, and performing a probe contact standard comparison to generate a probe contact quality assessment code;

[0024] Step S2: performing probe channel allocation processing according to the probe contact quality assessment code to obtain probe channel signal allocation data; performing non-magnetic field scattering parameter measurement according to the probe channel signal allocation data, and performing magnetic field excitation frequency band analysis to generate magnetic field excitation avoidance frequency band data;

[0025] Step S3: applying a static vector magnetic field environment to the integrated circuit under test based on the magnetic field excitation avoidance frequency band data, and then performing dynamic circuit channel test processing to obtain circuit test characteristic response data; wherein the circuit test characteristic response data includes electromagnetic field signal data of each channel, electrical characteristic signal data of each channel, and power supply voltage signal data;

[0026] Step S4: Identify channel jump abnormality events based on the electrical characteristic signal data of each channel; calculate impedance spectrum fluctuation rate data based on the power supply voltage signal data; perform health assessment based on the electromagnetic field signal data of each channel, channel jump abnormality events, and impedance spectrum fluctuation rate data to obtain integrated circuit test result data;

[0027] Step S5: Perform functional module mapping according to the integrated circuit test result data, and perform cross-module fault correlation detection to obtain functional module fault correlation data.

[0028] In an embodiment of the present invention, the integrated circuit testing method includes the following steps:

[0029] Step S1: Powering on the IC to be tested to obtain initialization test configuration data; analyzing the probe point status based on the initialization test configuration data, and performing a probe contact standard comparison to generate a probe contact quality assessment code;

[0030] In one embodiment of the present invention, the integrated circuit under test is placed on a test fixture, and a 1.8V operating voltage is output via a DC regulated power supply. After the power supply is turned on, the voltage remains stable for 30 seconds. Subsequently, the test system reads a preset test configuration from non-volatile memory via the SPI bus at a 1MHz clock frequency. This configuration contains a probe coordinate table, a switch control sequence, a frequency test point distribution map, and judgment threshold parameters, forming an initialized test configuration data structure. Based on this configuration data, the test system writes switch status values ​​to a 128-bit control register on the integrated circuit under test via the JTAG interface, controls the probe selection switch, reads switch status feedback, and generates probe point connection status data. Subsequently, the test system uses a four-terminal method to output a constant current of 1mA to each probe, measures the voltage across the probes, calculates the contact resistance, and compares it with a 50Ω threshold. The test system activates an on-chip phase-locked loop (PLL) to generate a test frequency signal, controls a vector network analyzer (VNA) to measure the reflection coefficient, compares the measured value with a preset -20dB standard, and generates a probe contact quality assessment code based on the result.

[0031] Step S2: performing probe channel allocation processing according to the probe contact quality assessment code to obtain probe channel signal allocation data; performing non-magnetic field scattering parameter measurement according to the probe channel signal allocation data, and performing magnetic field excitation frequency band analysis to generate magnetic field excitation avoidance frequency band data;

[0032] In an embodiment of the present invention, the system parses the probe contact quality assessment code, identifies unqualified probe channels assessed as "medium" or "poor," and generates a channel calibration control instruction containing a channel ID, status code, and calibration parameters. For each unqualified probe, the test system fine-tunes the physical position by controlling the on-chip piezoelectric microactuator with an adjustment accuracy of 0.1μm until the contact resistance is less than 30Ω or the maximum number of adjustments is reached. Probes that cannot be adjusted to meet the standards are marked as permanently failed channels. The system executes a channel reallocation algorithm, prioritizes the integrity of key signal channels, and forms probe channel signal allocation data. The test system then confirms that the ambient magnetic field strength is less than 0.1μT and uses a vector network analyzer to measure the scattering parameters between all channels in a frequency range of 100MHz to 12GHz, with a step of 100MHz. The test system converts the scattering parameters into circuit equivalent parameters, analyzes the degree of suppression of resonance by substrate eddy current loss, calculates the eddy current damping factor at each frequency point, identifies frequency bands with a damping factor greater than 0.8, and forms magnetic field excitation avoidance frequency band data.

[0033] Step S3: applying a static vector magnetic field environment to the integrated circuit under test based on the magnetic field excitation avoidance frequency band data, and then performing dynamic circuit channel test processing to obtain circuit test characteristic response data; wherein the circuit test characteristic response data includes electromagnetic field signal data of each channel, electrical characteristic signal data of each channel, and power supply voltage signal data;

[0034] In this embodiment of the present invention, a magnetic field setting instruction is sent to the three-axis Helmholtz coil controller via the SPI interface of the integrated circuit under test. The command sets the X-axis to 35.36 Oe, the Y-axis to 35.36 Oe, and the Z-axis to 0 Oe, resulting in a combined magnetic field strength of 50 Oe, with the direction forming a 45-degree angle with the plane of the integrated circuit. The system collects magnetic field data in real time through a magnetic field sensor array. When the magnetic field variation within 10 consecutive sampling points is less than 0.05 Oe and the overall stability reaches ±0.1 Oe, a magnetic field stability ready signal is generated. Based on the magnetic field excitation avoidance band data, the test system controls the vector network analyzer to perform a -30 dBm low-power diagnostic scan in the high-loss frequency band and a -10 dBm standard power performance scan in the effective operating frequency band. The test system splices the two scan data in the frequency domain to form the wide-spectrum scattering parameters of each channel, extracts the parasitic signals in the low-injection-power diagnostic scan as electromagnetic field signal data, calculates the mixed response spectrum of the effective working area and subtracts the parasitic baseline to obtain the electrical characteristic signal data, and synchronously collects the power supply voltage to form the power supply voltage signal data, completing the circuit test characteristic response data acquisition.

[0035] Step S4: Identify channel jump abnormality events based on the electrical characteristic signal data of each channel; calculate impedance spectrum fluctuation rate data based on the power supply voltage signal data; perform health assessment based on the electromagnetic field signal data of each channel, channel jump abnormality events, and impedance spectrum fluctuation rate data to obtain integrated circuit test result data;

[0036] In this embodiment of the present invention, each channel's current is calibrated based on its electrical characteristic signal data, the shunt characteristics are calculated, and the current gradient curve is derived using the central difference method. The system identifies the rising edge, plateau, and falling edge intervals in the gradient curve and calculates the maximum transition rate, transition duration, and transition edge jitter. Abnormal channels are flagged by comparing the transition rate with the upper and lower thresholds of 800A / s and 80A / s, the transition duration with the upper and lower thresholds of 8ms and 0.8ms, and the time deviation between adjacent transition pulses with the 20% jitter threshold. A severe transition anomaly event is identified when a channel meets two or more abnormal conditions simultaneously or when the same anomaly occurs eight times in 15 consecutive tests. Simultaneously, the test system calculates the instantaneous impedance sequence of each channel based on the power supply voltage signal data, removes outliers, calculates the impedance mean and standard deviation, and calculates the impedance spectrum fluctuation rate. The test system performs cluster analysis on abnormal channels, performs electromagnetic field coupling analysis, and combines the fluctuation rate data with a fault type rule library to calculate the overall health index, identify the faulty module, and generate integrated circuit test result data.

[0037] Step S5: Perform functional module mapping according to the integrated circuit test result data, and perform cross-module fault correlation detection to obtain functional module fault correlation data.

[0038] In this embodiment of the present invention, the test system loads a chip functional module layout diagram and maps probe channels to 16 functional modules using a coordinate matching algorithm. It calculates the failure rate of each module and generates a module fault mapping table. The system uses conditional mutual information entropy to analyze cross-module fault correlations, constructs a 16×16 correlation strength matrix, and applies Granger causality testing to determine the direction of fault propagation and generate cross-module correlation data. The test system constructs a fault propagation network diagram, calculates the propagation depth using a depth-first search and the impact range using a breadth-first search. It then quantifies the fault impact by combining node centrality and generates fault impact weight data. The system ranks fault nodes based on impact weight, functional importance, and repair difficulty, marking the top 25% as critical fault nodes. Finally, the test system constructs an integrated fault correlation graph, applies a community detection algorithm to identify clusters of closely related faulty modules, and performs fault tree analysis to generate functional module fault correlation data, including a fault correlation graph, critical propagation paths, a fault impact heat map, and repair priority recommendations. This provides comprehensive and detailed analysis results for integrated circuit fault diagnosis.

[0039] Preferably, step S1 includes the following steps:

[0040] Step S11: Power on the integrated circuit to be tested, read the preset test configuration, and obtain the initialization test configuration data;

[0041] Step S12: activating the on-chip probe selection switch of the integrated circuit to be tested according to the initialization test configuration data, and generating probe point connection status data;

[0042] Step S13: Based on the probe point connection status data, the contact resistance of the integrated circuit to be tested is detected one by one, and when the contact resistance is greater than 50Ω, it is marked as abnormal, and the probe contact resistance evaluation data is obtained;

[0043] Step S14: Based on the probe contact resistance evaluation data, the on-chip phase-locked loop circuit in the integrated circuit to be tested is started to generate a 100 MHz-10 GHz test frequency signal to generate multi-frequency test signal data;

[0044] Step S15: injecting a test signal into an on-chip probe of the integrated circuit to be tested through a vector network analyzer based on the multi-frequency test signal data, measuring and evaluating its reflection coefficient, and generating an original reflection coefficient value of the probe;

[0045] Step S16: Compare the original reflection coefficient value of the probe with a preset contact standard of less than -20 dB, mark unqualified probes, and generate a probe contact quality assessment code.

[0046] In an embodiment of the present invention, at the beginning of the test, the output of the DC regulated power supply is set to 1.8V, and the operating voltage is provided to the integrated circuit to be tested through the power pin on the test board. After the regulated power supply is started, a 30-second stabilization period is maintained to ensure that the internal state of the circuit is fully established. The test system then reads the preset test configuration from the non-volatile memory of the test system via the SPI bus at a clock frequency of 1MHz. The read content includes the probe coordinate table, switch control sequence, frequency test point distribution map, and judgment threshold parameters. The test system loads this data into the system RAM to form an initialized test configuration data structure, which contains 64 probe point position information, a 128-bit switch control word, and 6 test frequency values.

[0047] Based on the switch control word in the initialization test configuration data, the test system writes the switch status values ​​to the 128-bit control register on the IC under test via the JTAG test interface. The write process uses 16-bit parallel transfer mode, completing the entire 128-bit data write in eight passes. Each control bit corresponds to an on-chip probe select switch. A "1" control bit closes the corresponding probe switch, while a "0" control bit opens it. After writing, the test system delays for 2μs to ensure that all switch states are stable. It then reads the on-chip 128-bit status feedback register to obtain the actual switch status. The test system compares the read switch status value with the written value to generate 128 bits of probe point connection status data, each bit of which represents the current connection state of a probe point.

[0048] The test system determines the probe points to be measured based on the probe point connection status data and uses the four-terminal method to measure contact resistance. During measurement, the test system outputs a constant test current of 1mA to each probe point through a current source, while simultaneously measuring the voltage drop across the probes with a high-precision voltmeter. The current source is implemented using an LM334 constant current source circuit, and the voltage measurement is acquired using a 24-bit ADC converter with a sampling rate set to 100kS / s. 100 samples are collected at each point and averaged to eliminate noise. The test system calculates the contact resistance by dividing the measured voltage by the current value. The calculated result is compared with a threshold of 50Ω to generate probe contact resistance evaluation data. This data includes the measured resistance value for each probe point and an abnormality flag. An abnormality flag of "1" indicates that the resistance exceeds 50Ω.

[0049] Check the contact status of the key points (power supply, ground, clock, control) in the probe contact resistance evaluation data. After confirming that there are no abnormalities, write the frequency control word to the phase-locked loop circuit on the integrated circuit to be tested through the JTAG interface. The phase-locked loop circuit adopts a fractional N structure with a reference frequency of 10MHz. The test frequency is generated by setting different frequency division coefficients N and multiplication coefficients M. The test system sets the phase-locked loop parameters in the order of 100MHz, 500MHz, 1GHz, 2.5GHz, 5GHz, and 10GHz. After each frequency point is set, wait for the lock indication signal to stabilize (the lock time does not exceed 200μs), and then measure the actual output frequency and record it. The test system records the theoretical value, actual value, lock time and phase noise of each frequency point as a multi-frequency test signal data table.

[0050] The test system controls an Agilent N5230C vector network analyzer to measure the reflection coefficient of the IC under test. The VNA first performs a standard calibration process to eliminate the effects of test cables and connectors. Then, based on the frequency values ​​in the multi-frequency test signal datasheet, the VNA generates a -10dBm test signal at six frequencies: 100MHz, 500MHz, 1GHz, 2.5GHz, 5GHz, and 10GHz. This signal is injected into the on-chip probe of the IC under test via an RF probe. The VNA measures the reflected signal at each frequency, collecting 32 data points at each frequency and averaging them. The bandwidth is set to 1kHz, and the IF filter bandwidth is 100Hz to ensure measurement accuracy. The test system records the complex reflection coefficient at each probe point at each frequency, forming a matrix of the probe's raw reflection coefficient values.

[0051] The reflection coefficient amplitude values ​​for each probe point at each test frequency are extracted from the probe's raw reflection coefficient matrix and compared to the preset -20dB contact standard. This comparison process uses a point-by-point comparison method to determine the reflection coefficient of each probe at each test frequency. The judgment rule is as follows: if the reflection coefficient at all frequencies is less than -20dB, the probe contact quality is rated "Excellent" and coded "00"; if the reflection coefficient at any frequency is between -20dB and -15dB, it is rated "Good" and coded "01"; if the reflection coefficient at any frequency is between -15dB and -10dB, it is rated "Fair" and coded "10"; and if the reflection coefficient at any frequency is greater than -10dB, it is rated "Poor" and coded "11." The test system stores each probe's evaluation result as a two-bit binary code, forming a complete probe contact quality evaluation code.

[0052] Preferably, step S2 includes the following steps:

[0053] Step S21: If there are unqualified items in the probe contact quality assessment code, a recalibration operation is triggered for the probe channel, and a channel calibration control instruction is generated;

[0054] Step S22: performing on-chip probe commissioning on the IC to be tested based on the channel calibration control instruction, determining available test channels, and performing probe channel allocation processing to obtain probe channel signal allocation data;

[0055] Step S23: performing non-magnetic field scattering parameter measurement based on the probe channel signal distribution data, and performing equivalent circuit response analysis to generate original equivalent circuit response data;

[0056] Step S24: quantifying the degree of suppression of circuit resonance by substrate eddy current loss based on the original equivalent circuit response data to obtain eddy current damping factor data;

[0057] Step S25: Generate magnetic field excitation avoidance frequency band data based on the frequency bands marked with eddy current damping factor data greater than 0.8.

[0058] In an embodiment of the present invention, the probe contact quality assessment code is parsed, and the quality assessment results of each probe channel are extracted using a binary bit operation method. During the parsing process, the test system divides the 128-bit probe contact quality assessment code into groups of 2 bits to obtain the assessment results of 64 probes. The test system then traverses all the assessment results, identifies the probe channels with assessment codes of "10" (medium) or "11" (poor), and marks these channels as unqualified items. For each unqualified probe channel, the test system generates a channel calibration control instruction containing the channel ID, current state value and calibration parameters. The instruction adopts a 32-bit structure, of which 8 bits are the channel ID, 8 bits are the current state code, and 16 bits are the calibration parameters. The calibration parameters include the probe position fine-tuning value and the test signal strength compensation value. The calibration control instructions of all unqualified channels are organized into an instruction queue and passed to the next step after being sorted by priority.

[0059] Physical position fine-tuning is performed on each failed probe in the instruction queue. This fine-tuning process is achieved by controlling an on-chip piezoelectric microactuator with a drive voltage range of 0-5V and a position adjustment accuracy of 0.1μm. After position adjustment, the test system remeasures the probe contact resistance using the previously described measurement method until the contact resistance is less than 30Ω or the maximum number of adjustments, five, is reached. Probes that cannot meet the requirements through physical adjustment are marked as permanently failed channels by the test system. The test system then executes a channel reallocation algorithm. This algorithm determines the allocation of critical signal channels based on the circuit test topology and available channels using a maximum flow algorithm from graph theory. This allocation process prioritizes the integrity of critical signal channels such as power, ground, clock, and control signals. Remaining signals are allocated in descending order of importance. This ultimately generates probe channel signal allocation data, which contains the actual allocation status of each of the 64 probes and the types of signals they carry.

[0060] The vector network analyzer (VNA) was controlled to perform a complete scattering parameter measurement. Before measurement, the system first confirmed that the test environment's magnetic field strength was less than 0.1 μT and monitored the ambient magnetic field in real time using a Hall-effect magnetic field sensor. During the measurement, the VNA set the test frequency range to 100 MHz to 12 GHz, with a frequency step of 100 MHz. At each frequency point, the VNA measured the scattering parameters across all channels, namely the input reflection coefficient, reverse transmission coefficient, forward transmission coefficient, and output reflection coefficient. Data was collected at 120 frequency points, totaling 121 frequency points. After the measurement, the test system converted the scattering parameters into circuit equivalent model parameters. The conversion process used the Gauss-Newton iteration method to fit the circuit equivalent parameters, including the inductance L, capacitance C, resistance R, and mutual inductance M. The fitting accuracy was controlled to a mean square error of less than 0.01, and the number of iterations was limited to 100. The fitting results formed the original equivalent circuit response data, which contained the circuit's equivalent parameter values ​​and frequency response characteristics across the entire frequency range.

[0061] The original equivalent circuit response data is used to analyze the inhibitory effect of substrate eddy current loss on circuit resonance. During the analysis, the system first determines the resonant frequency point of the circuit by finding the frequency point where the imaginary part of the impedance passes through zero and the real part is the smallest. For each resonant frequency point, the test system calculates the quality factor Q value, which is calculated by dividing the resonant frequency by the 3dB bandwidth. The system then establishes an ideal lossless model, which removes all resistive loss effects and calculates the ideal Q value. The eddy current damping factor is calculated by the ratio of the actual Q value to the ideal Q value. The calculation formula is α = 1-Q actual / Q ideal, where α is the eddy current damping factor, Q actual is the measured quality factor, and Q ideal is the quality factor of the ideal lossless model. The test system calculates the eddy current damping factor for each frequency point to form a frequency-damping factor comparison table, which contains the eddy current damping factor values ​​for all 120 test frequency points.

[0062] During the judgment process, the system traverses the eddy current damping factor values ​​of all frequency points and identifies frequency points with a damping factor greater than 0.8. For frequency points that continuously exceed the threshold, the system merges them into frequency bands, with the band boundaries determined by the first and last frequency points exceeding the threshold. The merging process requires that the frequency intervals do not exceed 300MHz; otherwise, they are considered to be different frequency bands. The system adds a 200MHz safety margin to each identified avoidance frequency band to form the final magnetic field excitation avoidance frequency band data. This data contains the upper and lower limits of all frequency bands to be avoided and is recorded in the format of start frequency - end frequency. For example, "2.3GHz-3.7GHz" indicates that magnetic field excitation should not be applied within this frequency band.

[0063] Preferably, in step S23, performing non-magnetic field scattering parameter measurement according to the probe channel signal distribution data and performing equivalent circuit response analysis includes:

[0064] Perform signal amplitude detection based on the probe channel signal allocation data. When the signal amplitude attenuation is greater than 3dB, gain compensation is triggered to obtain on-chip probe state mapping data.

[0065] Performing a preset stepped frequency scan start on an internal frequency synthesizer in the IC under test based on the on-chip probe state mapping data to obtain frequency scan initialization data;

[0066] Use Hall sensors to confirm that the background magnetic field in the test area is less than 0.1 Oe to create a non-magnetic test environment;

[0067] In a non-magnetic test environment, the forward transmission coefficient and reflection coefficient of the IC under test are measured at the mid-frequency point using a vector network analyzer based on the frequency sweep initialization data, generating full-band scattering parameter measurement data.

[0068] The equivalent circuit parameters are calculated based on the full-band scattering parameter measurement data, and the electrical topology path response of the integrated circuit under test is performed to generate the original equivalent circuit response data; among which, the equivalent circuit parameters include parasitic resistance value, parasitic inductance value, and parasitic capacitance value.

[0069] In an embodiment of the present invention, a high-speed signal generator is called according to the probe channel signal allocation data to inject a standard test signal with an amplitude of 0dBm and a frequency of 1GHz into each channel. The actual signal amplitude is measured by an on-chip signal detector. The detector adopts a logarithmic detector structure with a dynamic range of -30dBm to +10dBm and a measurement accuracy of ±0.1dB. The test system records the actual signal amplitude of each channel and calculates the attenuation value by comparing it with the standard injection amplitude. When it is detected that the signal attenuation exceeds the 3dB threshold, the channel gain compensation mechanism is automatically triggered. Gain compensation is achieved through an on-chip programmable gain amplifier with a compensation range of 0-12dB and a step accuracy of 0.5dB. The test system sets the corresponding gain compensation value according to the attenuation value to ensure that the signal amplitude deviation after compensation does not exceed ±0.5dB. After all channels complete gain calibration, the test system generates on-chip probe state mapping data containing the actual attenuation values ​​and compensated gain values ​​of 64 channels.

[0070] The test system configures the internal frequency synthesizer of the IC under test (ICD) via the JTAG interface according to the on-chip probe status mapping data. The configuration process first sets a base frequency of 10 MHz and a multiplication factor of 64, resulting in a phase-locked loop (PLL) output frequency of 640 MHz. The frequency control register is then configured, with the sweep start frequency set to 100 MHz, the stop frequency set to 12 GHz, and the step frequency set to 100 MHz. The sweep direction is upsampling, with a sweep rate of 10 ms per frequency point. The frequency switching threshold is also set to 0.001% to ensure frequency stability. The frequency synthesizer utilizes a fractional-N PLL architecture, with a lock time of no more than 100 μs and a phase noise rating of better than -90 dBc / Hz. After starting the frequency synthesizer, the test system monitors the lock indicator and, upon confirmation of successful lock, records the actual output frequency. This creates a frequency sweep initialization data table containing 120 frequency points, recording the theoretical value, actual value, and lock status for each frequency point.

[0071] A triaxial Hall-effect magnetic field sensor array, model TMR2001, was deployed in the test area, boasting a sensitivity of 10mV / Oe, a measurement range of ±10Oe, and a resolution of 0.001Oe. The sensor array consists of five sensors, positioned 10mm above the chip under test and 20mm in each of four directions, forming a three-dimensional monitoring network. The test system continuously reads all sensor data at a 100Hz sampling rate using a 24-bit ADC to calculate the magnetic field intensity distribution within the test area. If the magnetic field intensity exceeds 0.1Oe at any location, an alarm is automatically triggered and the test is paused. To minimize ambient magnetic field interference, the test system utilizes a three-layer magnetic shielding system: an inner layer made of high-permeability Permalloy, a middle layer of silicon steel sheeting, and an outer layer of aluminum alloy, with a shielding coefficient exceeding 60dB. The test system also disables all surrounding electromagnetic interference sources and confirms that the background magnetic field in the test area is stable below 0.05Oe before proceeding with subsequent measurements.

[0072] After confirming the establishment of a non-magnetic test environment, the test system controlled the Agilent E5071C vector network analyzer to perform a full calibration using the SOLT (Short-Open-Load-Transmission) method, using calibration kit 85052D. After calibration, the test system set the vector network analyzer's sweep parameters based on the frequency table provided in the frequency sweep initialization data. The sweep configuration included a frequency range of 100 MHz to 12 GHz, 121 frequency points, an IF bandwidth of 100 Hz, an output power of -10 dBm, and 16 averages. The test system then controlled the vector network analyzer to sequentially measure the input reflection coefficient, forward transmission coefficient, reverse transmission coefficient, and output reflection coefficient. After each frequency point measurement, the data was immediately transmitted to the test system and stored in real time. After all frequency points were measured, the test system organized the scattering parameter data into a four-dimensional data matrix containing all S-parameters at all frequency points, representing the full-band scattering parameter measurement data.

[0073] The equivalent circuit parameters of the integrated circuit under test are calculated based on full-band scattering parameter measurement data. The calculation process uses a nonlinear least squares method to iteratively solve the equivalent circuit parameters by establishing a mapping relationship between the equivalent circuit model and the measured S-parameters. First, the system converts the S-parameters to Z-parameters (impedance parameters) using standard microwave network parameter conversion formulas. Subsequently, the system establishes a π-type equivalent circuit model, which includes series resistance Rs, series inductance Ls, parallel capacitances Cp1 and Cp2, and substrate resistance Rsub. The system uses the Levenberg-Marquardt algorithm for parameter fitting, with initial values ​​set to typical process parameters. The iteration termination criteria are that the change rate of the sum of squared residuals is less than 0.001% or the number of iterations reaches 500. After fitting is complete, the system extracts the parasitic resistance values ​​(range: 0.1-10Ω), parasitic inductance values ​​(range: 0.1-10nH), and parasitic capacitance values ​​(range: 0.1-10pF). The system substitutes these parameters into the circuit simulation engine, calculates the circuit response characteristics across the full frequency band, and generates the original equivalent circuit response data.

[0074] Preferably, quantifying the degree of suppression of circuit resonance by substrate eddy current loss based on the original equivalent circuit response data in step S24 includes:

[0075] Performing a first-order derivative of the parasitic resistance value in the original equivalent circuit response data, and then extracting a curve of the parasitic resistance value varying with frequency to obtain a parasitic resistance frequency differential curve;

[0076] Identify the frequency bands with a slope greater than 0.16 ohms / GHz in the parasitic resistance frequency differential curve and generate skin effect dominant frequency band markers;

[0077] The curve of parasitic inductance value varying with frequency is extracted based on the original equivalent circuit response data, and the curve is segmented and fitted based on the skin effect dominant frequency band marker to obtain the geometric mutual inductance coefficient and dynamic eddy current additional inductance data;

[0078] The LC resonance frequency at each frequency point is calculated based on the parasitic capacitance value and geometric mutual inductance in the original equivalent circuit response data, and the inherent electromagnetic resonance spectrum is generated;

[0079] The inherent electromagnetic resonance spectrum is correlated with the dynamic eddy current additional inductance data to quantify the degree to which the resonance characteristics of the integrated circuit under test are suppressed by the substrate eddy current loss, and the eddy current damping factor data is generated.

[0080] In the embodiment of the present invention, a parasitic resistance value array is extracted from the original equivalent circuit response data. The array contains the parasitic resistance values ​​corresponding to 121 frequency points (100 MHz to 12 GHz, with a step size of 100 MHz). The test system uses the central difference method to calculate the first-order derivative. For the parasitic resistance value R(f at the frequency point fi), i), its first-order derivative is expressed by the formula dR / df=[R(f i+1 )―R(f i―1 )] / (f i+1 ―f i―1 ) calculation, where f i+1 and f i―1 The values ​​for dR / df are adjacent high-frequency and low-frequency points, respectively, and dR / df is the derivative of the resistance with respect to frequency. For boundary points f1 and f121, the test system uses forward and backward differencing instead of center differencing. After calculation, the test system generates a 121-point parasitic resistance frequency differential curve, with frequency (in GHz) plotted on the horizontal axis and the resistance frequency derivative (in Ω / GHz) on the vertical axis. To reduce the impact of measurement noise, the test system smoothes the curve using a 5-point sliding average filter.

[0081] The test system performs threshold analysis on the parasitic resistance frequency differential curve, identifying all frequency points where the slope exceeds 0.16Ω / GHz. The threshold of 0.16Ω / GHz is determined by measuring a reference sample of a standard silicon substrate (resistivity 10Ω·cm), which is calibrated before testing. The test system first calculates the slope change between adjacent points and then marks all frequency points where the slope exceeds the threshold. Consecutive frequency points that meet the criteria are merged into the same frequency band, with the starting and ending points of the band being the point before the first point meeting the criteria and the ending point after the last point meeting the criteria. Adjacent frequency bands separated by fewer than three frequency points are merged into a single band. The test system ultimately generates a table of skin-effect-dominant frequency bands, which contains the start and end frequencies, average slope values, and maximum slope values ​​within each identified frequency band. In actual measurements, the system typically identifies two to four skin-effect-dominant frequency bands, distributed between 2 GHz and 10 GHz.

[0082] An array of parasitic inductance values ​​is extracted from the original equivalent circuit response data, and a frequency-inductance curve is plotted. The inductance curve is then divided into multiple frequency bands based on a table of skin-effect-dominated frequency band markers. For non-skin-effect-dominated frequency bands, the test system uses a constant model, L(f) = L0, for fitting, where L0 is the average inductance within the band. For skin-effect-dominated frequency bands, the test system uses an exponential decay model, L(f) = L0·exp(-k·f), for fitting, where L0 is the inductance value extrapolated to zero frequency, k is the attenuation coefficient, and f is the frequency. The fitting process uses a nonlinear least squares method, with the error function defined as the sum of the squares of the difference between the measured value and the model prediction. From the fitting results, the test system extracts the geometric mutual inductance coefficient, M (equal to the L0 value in the non-skin-effect region), and the dynamic eddy current additional inductance, ΔL(f) (equal to L(f)-M). The test system generates a 121-point dynamic eddy current additional inductance data table, recording the additional inductance caused by eddy currents at each frequency point.

[0083] The test system extracts the parasitic capacitance value array from the original equivalent circuit response data, and calculates the LC resonant frequency under ideal conditions (without eddy current loss) by combining the geometric mutual inductance coefficient M obtained in the previous step. The calculation is based on the formula Where fr is the resonant frequency, M is the geometric mutual inductance, and C is the parasitic capacitance value. The test system calculates the corresponding LC resonant frequency for each of the 121 frequency points to form a resonant frequency comparison table. Subsequently, the test system identifies the actual resonant point through the S-parameter amplitude-frequency response curve. The identification method is to find the maximum point of the forward transmission coefficient parameter or the minimum point of the input reflection coefficient parameter. For multi-resonance systems, the test system uses a peak detection algorithm to identify all resonant peaks. It requires that the frequency interval between adjacent resonant peaks is not less than 500MHz, and the peak amplitude is more than 10dB higher than the background noise. The test system finally generates an inherent electromagnetic resonance spectrum table, which includes the theoretical resonant frequency, the measured resonant frequency, and the peak quality factor Q value (calculated by dividing the resonant frequency by the 3dB bandwidth).

[0084] The test system correlates the inherent electromagnetic resonance spectrum with dynamic eddy current added inductance data to quantify the degree to which eddy current losses suppress the resonant characteristics. The test system first establishes an ideal resonance model, which only considers the geometric mutual inductance M and parasitic capacitance C, and calculates the ideal resonant frequency fr_ideal and the ideal quality factor Q_ideal. It then establishes an eddy current influence model, which considers the influence of dynamic eddy current added inductance ΔL(f) and calculates the actual resonant frequency fr_actual and the actual quality factor Q_actual. The eddy current damping factor α is defined as: α = 1-(Q_actual / Q_ideal), representing the proportion of the quality factor reduction caused by substrate eddy current losses. The test system calculates the eddy current damping factor for each resonant frequency point and generates an eddy current damping factor data table. This table contains damping factor values ​​for 121 frequency points, typically ranging from 0 to 1, where 0 indicates no damping and 1 indicates complete damping (resonance is completely suppressed). The test system uses cubic spline interpolation to smooth the eddy current damping factor curve to ensure data continuity.

[0085] Preferably, step S3 includes the following steps:

[0086] Step S31: Sending a magnetic field setting instruction to an external three-axis Helmholtz coil controller via the SPI interface based on the integrated circuit under test to apply a static vector magnetic field environment and simultaneously collect magnetic field values ​​in real time to obtain real-time magnetic field strength readings; wherein the field strength of the static vector magnetic field environment is 50 Oe, and the vector direction is at a 45-degree angle with the plane of the integrated circuit under test;

[0087] Step S32: Perform stability judgment on the real-time magnetic field strength readings. When the magnetic field variation within 10 consecutive sampling points is less than 0.05 Oe and the overall magnetic field stability reaches ±0.1 Oe, the magnetic field is determined to be stable and a magnetic field stability ready signal is generated.

[0088] Step S33: Based on the magnetic field stabilization ready signal, a low injection power diagnostic scan is performed on each probe channel of the IC under test using a vector network analyzer by using the frequency band marked in the magnetic field excitation avoidance frequency band data to generate a high loss region parasitic coupling spectrum; wherein the low injection power is set to -30 dBm;

[0089] Step S34: Based on the magnetic field stabilization ready signal and the unmarked frequency bands in the magnetic field excitation avoidance frequency band data, a standard injection power performance scan is performed on each probe channel of the integrated circuit under test using a vector network analyzer to generate a mixed response spectrum in an effective working area; wherein the standard injection power is set to -10 dBm;

[0090] Step S35: splicing the parasitic coupling spectrum of the high-loss region and the mixed response spectrum of the effective working region in the frequency domain to obtain the wide-spectrum scattering parameters of each channel;

[0091] Step S36: performing magnetic field-circuit processing on the wide spectrum scattering parameters of each channel, and using the parasitic signals of the low injection power diagnostic scan as the electromagnetic field signal data of each channel;

[0092] Step S37: performing parasitic baseline processing based on the parasitic coupling spectrum of the high-loss region, and subtracting the parasitic baseline from the mixed response spectrum of the effective working region to obtain electrical characteristic signal data of each channel;

[0093] Step S38: When executing the scanning process of each probe channel, the power supply voltage pin of the integrated circuit to be tested is synchronously collected to obtain power supply voltage signal data.

[0094] In an embodiment of the present invention, a magnetic field setting instruction is sent to the three-axis Helmholtz coil controller via the SPI interface of the integrated circuit under test at a 1MHz clock frequency. The instruction contains 16 bytes of data, of which three 4-byte floating-point numbers represent the three-axis magnetic field intensity setting values, setting the X-axis to 35.36Oe, the Y-axis to 35.36Oe, and the Z-axis to 0Oe, resulting in a combined magnetic field intensity of 50Oe and a direction at a 45-degree angle with the plane of the integrated circuit. The remaining 4 bytes are the control word, which includes the start bit, calibration bit, feedback enable bit, etc. The coil controller uses a TI TMS320F28335 digital signal processor to implement PID control with a control accuracy of 0.01Oe. The Helmholtz coil is wound with 1mm diameter enameled wire, with 100 turns on the X-axis, 100 turns on the Y-axis, and 120 turns on the Z-axis. The coil radius is 120mm and is driven by a precision current source with a current resolution of 0.1mA. The test system collects the magnetic field of the test area in real time through a magnetic field sensor array with a sampling frequency of 100Hz, and transmits the data back to the test host to form a real-time magnetic field strength reading.

[0095] The stability of the real-time magnetic field strength readings is judged. The sliding window algorithm is used for judgment, and the window size is 10 sampling points, corresponding to an actual time of 100ms. The test system calculates the absolute value of the difference in magnetic field strength between each two adjacent points in the window. If all differences are less than 0.05Oe, the short-term stability is judged to meet the standard. At the same time, the test system calculates the difference between the maximum and minimum magnetic field values ​​in the window. If the difference is less than 0.2Oe (that is, the stability reaches ±0.1Oe), the overall stability is judged to meet the standard. The test system notifies other test equipment of the magnetic field status through a TTL level signal. A low level indicates that the magnetic field is being adjusted, and a high level indicates that the magnetic field is stable. The stability judgment standard must be met continuously for 3 sampling windows (a total of 300ms) before a magnetic field stability ready signal is generated to avoid misjudgment caused by instantaneous stability. The signal is transmitted to the external trigger port of the vector network analyzer through an optical coupler to eliminate ground loop interference.

[0096] After receiving the magnetic field stabilization ready signal, the system first reads data from the magnetic field excitation avoidance band. This data covers multiple frequency ranges, such as the high-loss bands of 2.3 GHz to 3.7 GHz and 7.2 GHz to 9.1 GHz. The test system controls an Agilent N5230C vector network analyzer (VNA) and sets the following test parameters: frequency range 100 MHz to 12 GHz, injection power -30 dBm, IF bandwidth 100 Hz, and averaging 32 times. The system then performs a detailed scan of the marked high-loss bands using a segmented sweep method, with a frequency resolution of 10 MHz. Before scanning, the VNA undergoes a standard SOLT calibration. The system controls the multi-channel RF switch to select each probe channel individually, performing a sweep measurement on each channel. Four scattering parameters, namely input reflection coefficient, forward transmission coefficient, reverse transmission coefficient, and output reflection coefficient, are recorded, and the corresponding magnetic field avoidance bands are marked. After all channels are scanned, the data is organized to form a parasitic coupling spectrum database for the high-loss region.

[0097] Based on the magnetic field stability-ready signal, the test system extracts the unmarked effective operating frequency band from the magnetic field excitation avoidance band data. The test system then uses a vector network analyzer to perform a second sweep, increasing the injection power to -10dBm while keeping all other parameters constant. To reduce measurement time, the sweep covers only the unmarked effective operating frequency band, avoiding areas of high loss. The test employs a segmented sweep strategy, dividing the full frequency band into multiple sub-bands for sweeping, each corresponding to an unmarked effective operating frequency band. The sub-bands are connected using logarithmic frequency interpolation to ensure data continuity. The test system also controls the multi-channel RF switch to select each probe channel individually, performing a standard injection power sweep on each channel and recording four scattering parameters. During the sweep, the test system monitors magnetic field stability. If the magnetic field stability exceeds the ±0.1Oe range, the measurement is immediately paused and the test is resumed to allow for magnetic field stabilization. After all channels are swept, the test system compiles the data to form a mixed response spectrum for the effective operating area.

[0098] The parasitic coupling spectrum of the high-loss region and the mixed response spectrum of the active region are spliced ​​in the frequency domain. The splicing process first establishes a complete 1201-point frequency grid covering the 100 MHz to 12 GHz range, with a grid spacing of 10 MHz. The test system then maps the two spectrum data onto this grid. For overlapping frequency points (at the frequency band boundaries) where data is available for both spectra, a weighted average is used to determine the final value, with the weight inversely proportional to the injection power used during the measurement. For frequencies where spectral data is missing, the test system uses cubic spline interpolation, based on data from 20 adjacent frequency points, to ensure a smooth and continuous spectral curve. The test system performs noise filtering on the spliced ​​spectrum using a Savitzky-Golay filter (with an 11-point window width and a polynomial order of 3) to remove high-frequency noise introduced during the spectrum splicing process. After splicing is complete, the test system generates a wide-spectrum scattering parameter dataset for each channel, containing input reflection coefficient, forward transmission coefficient, reverse transmission coefficient, and output reflection coefficient parameter data for the entire frequency band.

[0099] Magnetic field-circuit processing is performed on the wide-spectrum scattering parameters of each channel. This processing first identifies parasitic signal characteristics during low-injection-power diagnostic scans, including magnetic field-induced resonant peaks, nonlinear distortion, and areas of noise enhancement. This identification method utilizes a peak detection algorithm combined with baseline drift correction, with the detection threshold set at 6 dB above the background noise level. For each channel, the test system extracts the scattering parameters measured at -30 dBm injection power, calculates their frequency derivative curve, and marks frequency points in the derivative curve with a rate of change exceeding 1 dB / 10 MHz as magnetic field-sensitive points. The test system then analyzes the variation characteristics of these sensitive points before and after the application of a magnetic field, extracting the parameter offsets caused by the magnetic field. After normalizing these offset characteristics, the test system constructs a magnetic field response characteristic curve, which is labeled as the electromagnetic field signal data for each channel. This data contains the distribution of each channel's sensitivity to magnetic fields and its response characteristics across the entire frequency band.

[0100] Parasitic baseline processing is performed based on the parasitic coupling spectrum in the high-loss region. This processing method uses an adaptive baseline correction algorithm, which first applies a least-squares polynomial fit to the spectrum. The fitting order is automatically selected based on the spectrum complexity (usually 4-6 orders). The fitting curve serves as the parasitic baseline, reflecting the system response in the absence of a valid signal. The test system then subtracts this parasitic baseline from the mixed response spectrum in the effective working area to eliminate the influence of the system's inherent response. The subtraction operation is performed in the complex domain, processing the real and imaginary parts of the scattering parameters separately while retaining phase information. For abnormal peaks that appear in certain channels in specific frequency bands, the test system uses median filtering with a filter window width of 5 frequency points to suppress them. After processing, the test system recalculates the normalized scattering parameters and generates electrical characteristic signal data for each channel. This data reflects the purely electrical characteristic response of the integrated circuit under applied magnetic field conditions.

[0101] While scanning each probe channel, data from the IC's power supply voltage pins is simultaneously collected. This data is collected using an Agilent 34410A high-precision digital multimeter with a sampling rate of 100 kS / s and a resolution of 6.5 bits. The test system connects low-capacitance probes (less than 0.5 pF) to the IC's Vdd and Vss pins to measure the real-time power supply voltage. To reduce measurement interference, the probes are connected to the multimeter input via 100 Ω resistors, forming a low-pass filter. During the acquisition process, the test system records the power supply voltage value corresponding to each test frequency, marking the corresponding frequency, test channel, and test timestamp. The test system also monitors power supply voltage stability, calculating the mean, standard deviation, and maximum offset. If a power supply voltage fluctuation exceeding a set threshold (±5%) is detected, the test system marks the corresponding measurement point as an outlier. After the full scan is complete, the test system compiles the collected data and generates a power supply voltage signal data table containing the power supply status of all test points.

[0102] Preferably, identifying channel jump abnormal events according to the electrical characteristic signal data of each channel in step S4 includes:

[0103] Perform current calibration processing on each channel according to the electrical characteristic signal data of each channel to obtain calibrated current data of each channel;

[0104] Perform signal channel current aggregation analysis on the calibrated current data of each channel to obtain the shunt characteristic data of each channel;

[0105] Calculate the current change gradient of each channel based on the shunt characteristic data of each channel and generate the current change gradient curve of each channel;

[0106] Identify the transition edge interval according to the current change gradient curve of each channel to obtain the transition edge interval data of each channel; wherein the transition edge interval identification includes the rising edge, the plateau section and the falling edge;

[0107] Calculate the maximum transition rate of each channel based on the transition edge interval data of each channel;

[0108] Calculate the transition duration of each channel based on the transition edge interval data of each channel;

[0109] Extract the jitter value of each channel's transition edge based on the current change gradient curve of each channel's transition edge interval data;

[0110] Channel transition abnormalities are identified based on the maximum transition rate, transition duration, and transition edge jitter of each channel.

[0111] In an embodiment of the present invention, impedance parameters are obtained by converting S parameters to Z parameters. The conversion uses standard microwave network formulas to map the input reflection coefficient, forward transmission coefficient, reverse transmission coefficient, and output reflection coefficient parameters to Z11, Z21, Z12, and Z22 parameters. Subsequently, the test system calculates the current value of each channel based on the impedance parameters. The calculation formula is I=V / Z, where I is the channel current, V is the test excitation voltage (converted from the injected power -10dBm, corresponding to the effective value voltage 0.1V), and Z is the channel complex impedance. The current calculation takes into account the frequency dependence of the impedance and is calculated separately at 1201 frequency points. The test system then performs current calibration. The calibration process uses a pre-calibrated current calibration matrix, which is obtained by measuring the standard reference impedance. The calibration matrix eliminates the effects of parasitic capacitance, inductance, and crosstalk of the test system and improves measurement accuracy. The calibration calculation uses matrix multiplication to multiply the original current data with the calibration matrix to obtain the calibrated current data of each channel.

[0112] The test system calculates the current correlation coefficients between each of the 64 channels, forming a 64×64 correlation coefficient matrix. The calculation uses the Pearson correlation coefficient method, taking into account the current amplitude and phase information. Subsequently, the test system uses a hierarchical clustering algorithm (using the Ward distance minimization method) to classify channels with similar current characteristics into the same category, setting the clustering threshold to a correlation coefficient of 0.85. For each cluster group, the test system calculates the sum, average, variance, and maximum deviation of the current within the group. The system further analyzes the deviation of each channel current from the average current of the cluster group to which it belongs, and calculates the shunt ratio, which is defined as the single-channel current divided by the total current of the cluster group. The test system stores the shunt ratio curve of each channel in the entire frequency band as the shunt characteristic data of each channel. The data includes the channel ID, the cluster group ID to which it belongs, the frequency point, and the corresponding shunt ratio value.

[0113] The calculation adopts the central difference method. For the split ratio P(fi) at the frequency point fi, its gradient is calculated by the formula G(f i )=[P(f i+1 )―P(f i―1 )] / (f i+1 ―f i―1 ) calculation, where G(f i ) is the frequency point f iThe current change gradient at is expressed in Hz^-1. For the boundary points f1 and f1201, the test system uses a one-sided difference method to calculate the gradient. To reduce the influence of high-frequency noise, the test system applies a Savitzky-Golay filter (window width 11 points, polynomial order 3) to the raw gradient data to obtain a smooth gradient curve. The test system normalizes the calculation results by dividing the gradient value by the maximum absolute value of the gradient across the entire frequency band to obtain a normalized gradient value. The test system plots the normalized gradient curve of each channel across the entire frequency band as a current change gradient curve for each channel. The horizontal axis of the curve is frequency (unit: GHz) and the vertical axis is the normalized gradient value (dimensionless).

[0114] The identification process first sets gradient thresholds: +0.3 for rising edges, -0.3 for falling edges, and ±0.1 for plateaus. The test system scans the gradient curve for each channel. When three consecutive points with gradient values ​​greater than +0.3 are detected, they are marked as the start of a rising edge. When the rising trend ends (three consecutive points with gradient values ​​less than +0.3), they are marked as the end of a rising edge. Similarly, when three consecutive points with gradient values ​​less than -0.3 are detected, they are marked as the start of a falling edge; when the falling trend ends, they are marked as the end of a falling edge. A plateau is defined as an interval with gradient values ​​within ±0.1 for at least 10 consecutive points. The test system records the start and end frequencies, interval type (rising edge / plateau / falling edge), average gradient value, maximum gradient value, and gradient standard deviation of each transition interval to form the transition interval data for each channel. Intervals of the same type with a distance less than 50 MHz are merged into a single interval.

[0115] Extract all rising and falling edge intervals from the transition edge interval data of each channel. For each rising edge interval, the test system calculates the total change in the current shunt ratio in the interval and divides it by the frequency span to obtain the average jump rate; at the same time, the value of the maximum gradient point in the interval is recorded as the maximum jump rate. Similarly, for each falling edge interval, the test system calculates the total change in the current shunt ratio in the interval (taking the absolute value) and divides it by the frequency span to obtain the average jump rate; at the same time, the absolute value of the maximum gradient point in the interval is recorded as the maximum jump rate. The test system finds the global maximum jump rate of each channel from all transition edge intervals, and records the corresponding frequency point, interval type (rising edge / falling edge) and rate value. The maximum jump rate unit is MHz^-1, which represents the change in the shunt ratio caused by each megahertz frequency change.

[0116] The frequency span of each transition edge interval (rising edge or falling edge) is converted into a time domain parameter. The conversion is based on the typical response characteristics of the integrated circuit and adopts the frequency-time mapping relationship T = 1 / (2πΔf), where T is the transition duration and Δf is the frequency span of the transition edge interval. The test system applies this formula to all transition edge intervals of each channel to calculate the corresponding transition duration. At the same time, the test system calculates the average, standard deviation, maximum and minimum values ​​of all transition durations in the channel to form the transition duration statistical characteristics. For transition edge intervals with abnormally large spans (greater than 2GHz) or abnormally small spans (less than 10MHz), the test system marks them as potential abnormal intervals. The test system stores the transition duration data of each channel as a transition duration table, which contains the channel ID, transition edge ID, duration value and abnormal flag.

[0117] A linear fit is performed on the gradient curve of each transition edge interval to obtain an ideal gradient curve. The fitting is performed using the least squares method, calculating the linear equation G_fit(f) = af + b, where G_fit(f) is the fitted gradient value at frequency f, a is the slope, and b is the intercept. The test system then calculates the deviation between the actual gradient value and the fitted value, defined as the jitter value J(f) = |G(f) - G_fit(f)|, where J(f) is the jitter value at frequency f and G(f) is the actual measured gradient value. The test system calculates the RMS jitter value within each transition edge interval as the comprehensive jitter metric for that interval. The test system also records the maximum jitter value and its location within the interval. The test system organizes the jitter characteristics of all transition edge intervals into a per-channel transition edge jitter table, which includes the channel ID, transition edge ID, RMS jitter value, maximum jitter value, and jitter spectrum characteristics.

[0118] Channel transition anomalies are comprehensively identified based on the maximum transition rate, transition duration, and transition edge jitter of each channel. This identification uses a multi-parameter weighted judgment method to establish an anomaly scoring model: S = w1×R+w2×(1 / T)+w3×J, where S is the anomaly score, R is the normalized maximum transition rate, T is the normalized transition duration, J is the normalized transition edge jitter, and w1, w2, and w3 are weighting factors (set to 0.5, 0.3, and 0.2, respectively). The test system calculates an anomaly score for each channel and marks the channel as an abnormal channel when the score exceeds the preset threshold of 0.75. The test system also identifies specific anomaly patterns: a "fast transition anomaly" is identified when the maximum transition rate exceeds 1.5×10^-3MHz^-1 and the transition duration is less than 100ns; a "jitter anomaly" is identified when the transition edge jitter value exceeds 0.2 and the maximum transition rate fluctuation is greater than 30%; and a "multiple transition anomaly" is identified when the interval between adjacent transition edges is less than 50% of the expected value. The test system generates a channel transition anomaly event report that includes the abnormal channel ID, anomaly type, anomaly score, and key parameters.

[0119] It is particularly important to identify channel transition anomalies based on the maximum transition rate, transition duration, and transition edge jitter of each channel, including:

[0120] Based on the maximum hopping rate of each channel, it is determined whether each channel has a hopping rate abnormality event, and a rate abnormality flag of each channel is obtained. Among them, when the maximum hopping rate of the channel exceeds 800A / s or is lower than 80A / s, it is determined that the channel has a hopping rate abnormality;

[0121] Determine whether each channel has a transition time anomaly event based on the transition duration of each channel, and obtain a time anomaly flag for each channel; when the transition duration of a channel exceeds 8ms or is less than 0.8ms, it is determined that the channel has a transition time anomaly;

[0122] The jitter value of each channel's transition edge is evaluated using a preset jitter threshold to determine whether there is a transition jitter anomaly event in each channel, thereby obtaining a jitter anomaly flag for each channel. When the transition time deviation between two adjacent pulses of a channel's transition edge exceeds 20%, the channel is determined to have a transition jitter anomaly.

[0123] A comprehensive assessment of channel abnormal transition events is performed based on each channel's rate anomaly flag, each channel's time anomaly flag, and each channel's jitter anomaly flag, generating channel abnormal transition mark data. A severe abnormal transition event is determined to have occurred in a channel when two or more abnormal flag conditions are simultaneously met, or when the same type of abnormal flag appears at least eight times in 15 consecutive channel tests.

[0124] In an embodiment of the present invention, an abnormality judgment is performed based on the maximum jump rate data of each channel calculated in the above steps. The judgment process first converts the current change gradient into the current change rate. The conversion formula is R=G×V / Z×f, where R is the current change rate (unit: A / s), G is the normalized gradient value, V is the test voltage (0.1V), Z is the channel impedance (ohm), and f is the measurement frequency (Hz). The test system compares the maximum jump rate of each channel with the preset threshold value. The upper limit of the threshold is set to 800A / s and the lower limit is set to 80A / s. The threshold value is determined by measuring the typical jump response of the standard reference device (10Ω standard resistor). The normal jump rate range is 100A / s to 700A / s. When a channel's maximum transition rate exceeds 800 A / s, the test system marks the channel as "overspeed transition" (with the flag set to "10"). When the maximum transition rate is less than 80 A / s, it is marked as "slow transition" (with the flag set to "01"). When the rate is within the normal range, it is marked as "normal rate" (with the flag set to "00"). The test system generates a 64-bit status word containing rate anomaly flags for all channels.

[0125] During the judgment process, the test system compares the transition duration of each channel against preset time thresholds, with an upper threshold of 8 milliseconds and a lower threshold of 0.8 milliseconds. These thresholds were determined by statistically analyzing the transition response characteristics of 500 standard samples. Normal transition durations range from 1 millisecond to 5 milliseconds. The test system then iterates over the transition duration data for all channels and makes a judgment for each transition edge interval. If a channel's transition duration exceeds 8 milliseconds, the test system marks the channel as "long transition" (with the flag set to "10"); if the transition duration is less than 0.8 milliseconds, it is marked as "short transition" (with the flag set to "01"); and if the duration is within the normal range, it is marked as "normal" (with the flag set to "00"). For channels with multiple transition edges, the test system uses a "most severe anomaly first" principle: if any one transition edge is abnormal, the entire channel is marked as abnormal. The test system generates a 64-bit status word containing timing anomaly flags for all channels.

[0126] The test system calculates the transition time deviation between adjacent pulses within each channel. For each pair of adjacent transition edges in a channel, the test system calculates the relative deviation of their transition durations, D = |T1-T2| / [(T1+T2) / 2], where D is the relative deviation and T1 and T2 are the transition durations of the two adjacent pulses. The default jitter threshold is 20%, determined by measuring the jitter characteristics of 100 stable samples. The normal jitter range is 5%-15%. If the calculated relative deviation D exceeds 20%, the test system determines that the channel has transition jitter anomaly and sets the jitter anomaly flag to "1"; otherwise, it is set to "0". For channels with only a single transition edge, the test system determines jitter anomaly by analyzing the gradient fluctuation within the transition edge. This method calculates the ratio of the standard deviation to the mean of the gradient curve. A jitter anomaly is detected when this ratio exceeds 0.3. The test system generates a 64-bit status word containing jitter anomaly flags for all channels.

[0127] The assessment uses a two-tiered decision strategy: single-test multiple-anomaly decision and multiple-test cumulative-anomaly decision. In the single-test multiple-anomaly decision, the test system examines three types of anomaly flags for each channel. If two or more of these flags are present simultaneously (i.e., rate anomaly and timing anomaly, rate anomaly and jitter anomaly, timing anomaly and jitter anomaly, or all three), the channel is immediately flagged as a "severe transition anomaly" (with the flag bit set to "11"). In the multiple-test cumulative-anomaly decision, the test system maintains a sliding window table that records the anomaly flags for each channel over the last 15 tests. If a channel exhibits eight or more of the same type of anomaly flag within a 15-test window, the channel is also flagged as a "severe transition anomaly." The test system aggregates the anomaly assessment results for all channels into per-channel transition anomaly flag data, which includes the channel ID, anomaly type code (00: normal, 01: minor anomaly, 10: moderate anomaly, 11: severe anomaly), anomaly description, and statistical information.

[0128] Preferably, calculating the impedance spectrum fluctuation rate data according to the power supply voltage signal data in step S4 includes:

[0129] Calculate the total circuit current based on the shunt characteristic data of each channel;

[0130] Calculate the equivalent total impedance data through the power supply voltage signal data and the integrated circuit to be tested;

[0131] Based on the equivalent total impedance data and the shunt characteristic data of each channel, the channel instantaneous impedance distribution calculation is performed to obtain the instantaneous impedance sequence of each channel;

[0132] Calculate the impedance mean of each channel based on the instantaneous impedance sequence of each channel;

[0133] Calculate the impedance standard deviation of each channel based on the instantaneous impedance sequence and impedance mean of each channel;

[0134] The impedance spectrum fluctuation rate of each channel in the integrated circuit to be tested is calculated based on the impedance mean value and the standard deviation of the impedance of each channel to generate impedance spectrum fluctuation rate data.

[0135] In this embodiment of the present invention, a full-frequency analysis is performed on the current shunt characteristic data of each channel, extracting channel current data at 1201 frequency points (from 100 MHz to 12 GHz). The calculation process uses a vector summation method, taking into account both the current amplitude and phase information. For each frequency point fi, the test system performs a complex vector summation of the currents of 64 channels, using the formula I_total(fi) = ∑I_k(fi), where I_total(fi) is the total circuit current at frequency point fi, and I_k(fi) is the current of the kth channel at frequency point fi. The summation process considers phase relationships, using complex arithmetic to ensure that currents with the same phase are constructive and currents with opposite phases are destructive. The test system uses floating-point precision to ensure at least 6 significant digits. The calculation results form the total circuit current spectrum data, which includes current amplitude (unit: mA) and phase angle (unit: degrees) data for all 1201 frequency points. Frequency points with abnormally low current (below 1 μA) are marked as "low signal-to-noise ratio regions" by the test system.

[0136] The equivalent total impedance is calculated using the power supply voltage signal data and the previously calculated total circuit current spectrum data. The calculation uses Ohm's law: Z_total(fi) = V(fi) / I_total(fi), where Z_total(fi) is the equivalent total impedance at frequency point fi, V(fi) is the power supply voltage measured at that frequency point, and I_total(fi) is the total circuit current at that point. Because the power supply voltage measurement sampling rate (100kS / s) does not completely correspond to the network analyzer frequency points, the test system first performs time-frequency mapping on the power supply voltage data, associating the voltage data with the corresponding frequency points using the test timestamp. For missing data points during the mapping process, the test system uses cubic spline interpolation to fill in the gaps. Impedance calculations are performed in the complex domain, preserving the real and imaginary impedance information. The test system generates equivalent total impedance data, including impedance magnitudes (in ohms) and phase angles (in degrees) for 1201 frequency points. Frequency points with abnormal voltage or current measurements are marked as invalid data.

[0137] The system calculates the instantaneous impedance distribution of each channel based on the equivalent total impedance data and the shunt characteristics of each channel. This calculation uses the impedance distribution ratio method. For the kth channel at frequency point fi, its instantaneous impedance is calculated as Z_k(fi) = Z_total(fi) / P_k(fi), where Z_k(fi) is the instantaneous impedance of the channel, Z_total(fi) is the equivalent total impedance, and P_k(fi) is the shunt ratio of that channel (defined as the ratio of the channel current to the total current). The calculation is performed frequency-by-frequency, calculating the instantaneous impedance values ​​for all 64 channels at 1201 frequency points. For frequencies where the shunt ratio is less than 0.001, the test system applies a correction factor to mitigate calculation errors caused by small denominators. This correction method sets a minimum valid shunt ratio threshold of 0.001. Calculations below this threshold are used instead of the actual value, and the result is marked as "low confidence data." The test system organizes the calculation results into a sequence of instantaneous impedance of each channel. The sequence includes the channel ID, frequency point and corresponding complex impedance value (real part and imaginary part).

[0138] Before calculation, the test system first performs outlier removal, using a modified Z-score method to identify outliers. The median and absolute median deviation of the impedance series for each channel are calculated. If a point deviates from the median by more than 3.5 times the absolute median deviation, it is marked as an outlier and excluded. The test system then calculates the mean of the impedance series after outlier removal using the formula Z_mean_k = (1 / N)·∑Z_k(fi), where Z_mean_k is the mean impedance of the kth channel, N is the number of valid frequency points, and Z_k(fi) is the instantaneous impedance of the channel at frequency point fi. The impedance mean calculation processes the real and imaginary parts of the impedance separately, then combines them into a complex form. For channels with strong frequency dependence, the test system divides the frequency range into three sub-bands: low (100 MHz-1 GHz), mid (1 GHz-5 GHz), and high (5 GHz-12 GHz). The impedance mean of each sub-band is calculated to generate multi-band impedance signature data.

[0139] The impedance standard deviation of each channel is calculated based on the instantaneous impedance sequence and impedance mean of each channel. The calculation uses the sample standard deviation formula Where σ_k is the impedance standard deviation of the kth channel, N is the number of effective frequency points, Z_k(f i ) is the channel at frequency point f i The instantaneous impedance at , Z_mean_k is the mean impedance of the channel. During the calculation process, the test system processes the real and imaginary parts of the impedance respectively, obtains the real standard deviation σ_real_k and the imaginary standard deviation σ_imag_k, and then calculates the composite standard deviation For multi-band impedance signature data, the test system calculates the standard deviation for each sub-band. The results are stored as per-channel impedance standard deviation data, including the channel ID, full-band standard deviation, sub-band standard deviation, and the frequency distribution of the standard deviation. Furthermore, the test system calculates the frequency derivative of the standard deviation to assess impedance fluctuations over frequency.

[0140] The impedance spectrum fluctuation is calculated based on the impedance mean and the standard deviation of each channel's impedance. Fluctuation is defined as the ratio of the standard deviation to the mean and is calculated using the formula FVR_k = σ_k / |Z_mean_k|, where FVR_k is the impedance spectrum fluctuation of the kth channel, σ_k is the impedance standard deviation, and |Z_mean_k| is the modulus of the impedance mean. For complex impedances, the fluctuation is calculated using the complex standard deviation σ_complex_k and the impedance modulus |Z_mean_k|. The test system performs fluctuation calculations on all 64 channels, generating a channel fluctuation distribution graph. The test system also calculates the frequency dependence of the fluctuation by calculating the local fluctuation within a sliding window (100MHz width) and generating a fluctuation-frequency curve. The test system compares the channel fluctuations with a preset threshold (0.2) and marks channels that exceed the threshold as "high fluctuation channels." Finally, the test system generates impedance spectrum fluctuation data, including the full-band fluctuation, sub-band fluctuation, a fluctuation-frequency curve, and anomaly markers for each channel.

[0141] Preferably, in step S4, health assessment is performed based on the electromagnetic field signal data of each channel, channel jump abnormality events, and impedance spectrum fluctuation rate data, and the integrated circuit test result data obtained includes:

[0142] The abnormal channels of the integrated circuit to be tested are grouped according to the abnormal channel jump events to obtain a test abnormal channel group;

[0143] Perform abnormal channel electromagnetic field coupling analysis on the abnormal channel group tested using electromagnetic field signal data of each channel to obtain channel electromagnetic coupling abnormal pattern data;

[0144] Based on the channel electromagnetic coupling abnormal mode data, impedance spectrum fluctuation rate data and channel jump abnormal events, single channel fault type rule matching is performed to generate single channel fault type data;

[0145] The health of the integrated circuit to be tested is evaluated through single-channel fault type data, and then the fault is located to obtain the integrated circuit test result data.

[0146] In the embodiment of the present invention, a 64×64 channel correlation matrix is ​​constructed, and the matrix element (i, j) represents the abnormal correlation between channel i and channel j. The calculation formula is: Where N(i∩j) is the number of times an anomaly occurs simultaneously in both channels, and N(i) and N(j) are the total number of anomalies in each channel, respectively. The test system applies a spectral clustering algorithm based on the correlation matrix to group channels. A similarity graph is constructed using the k-nearest neighbor method (k is set to 5). The number of clusters is determined through Laplace matrix eigendecomposition (eigenvalues ​​are arranged in descending order, and the first position with a difference greater than 0.5 is taken as the cluster number). After clustering, the test system groups the abnormal channels according to the clustering results, marking each abnormal channel group's central channel (the channel with the most severe anomaly within the group), coverage (the physical distribution of channels within the group), and dominant anomaly type (the most frequently occurring anomaly type within the group).

[0147] Electromagnetic field coupling analysis was performed on the test abnormal channel groups. The analysis process first extracted the electromagnetic field response characteristics of each abnormal channel group from the raw data, including magnetic field sensitivity (parameter offset caused by magnetic field changes), frequency selectivity (peak response frequency), and phase relationship (phase difference between channel responses). The test system used the mutual information entropy method to quantify the electromagnetic coupling strength between channels. The calculation formula is MI(X, Y) = ∑∑p(x, y)lg(p(x, y) / p(x)p(y)), where X and Y are the electromagnetic response sequences of the two channels, p(x, y) is the joint probability distribution, and p(x) and p(y) are the marginal probability distributions. The coupling analysis results were plotted as a coupling strength heat map, and strongly coupled subnetworks were identified using a threshold segmentation (set to 0.6). The test system matched the strongly coupled topology to a preset electromagnetic coupling anomaly pattern library containing 15 typical coupling anomaly patterns (such as star coupling, chain coupling, and ring coupling). The matching process uses a graph isomorphism algorithm to calculate the similarity of topological structures, identify the most matching abnormal pattern and record the matching degree, and generate channel electromagnetic coupling abnormal pattern data.

[0148] Single-channel fault type rule matching is performed based on channel electromagnetic coupling anomaly pattern data, impedance spectrum fluctuation data, and channel transition anomaly events. The matching process combines a decision tree with a rule base. The rule base contains 32 predefined fault modes, each associated with a specific combination of anomaly features. The test system first constructs a feature vector for each channel. The feature vector consists of 18 elements: three transition features (rate anomaly flag, time anomaly flag, and jitter anomaly flag), five impedance features (fluctuation rate, frequency dependence, real offset, imaginary offset, and phase angle anomaly), and 10 electromagnetic features (magnetic field sensitivity, frequency selectivity, and coupling type). The test system classifies the feature vector using a decision tree based on the C4.5 algorithm. The decision tree is trained on 1000 standard fault samples, and the decision threshold is determined by minimizing the classification error rate. For channels where the decision tree classification confidence level falls below 85%, the test system applies a fuzzy rule inference engine for secondary judgment. This rule engine, based on the Mamdani model, contains 64 if-then rules. Its input is the feature vector, and its output is a probability distribution of the fault type. Finally, the test system determines the fault type for each abnormal channel and generates single-channel fault type data.

[0149] The overall health of the IC under test is assessed and faults are located using single-channel fault type data. The assessment process first calculates the overall health index H = 1-(w1×N1+w2×N2+w3×N3) / N, where N is the total number of channels, N1, N2, and N3 are the number of channels with mild, moderate, and severe faults, respectively, and w1, w2, and w3 are weight coefficients (0.2, 0.5, and 0.8, respectively). The test system divides the circuit status into four levels based on the health index: excellent (H ≥ 0.9), good (0.8 ≤ H < 0.9), fair (0.6 ≤ H < 0.8), and poor (H < 0.6). Subsequently, the test system performs fault location analysis, using a fault propagation path tracing algorithm to expand from single-channel faults to functional module-level faults. The localization process, based on a pre-established circuit topology, maps channels to functional modules, identifies modules with high fault rates, and calculates the failure probability of each module: P_m = ∑wiPi / ∑wi, where Pi is the failure probability of channel i within the module and wi is the channel weight (proportional to the channel's importance). The test system ultimately generates integrated circuit test result data, including an overall health rating, a list of faulty modules (sorted by descending probability of failure), a failure mode analysis, and repair recommendations.

[0150] It is particularly important to map functional modules based on the IC test result data and perform cross-module fault correlation detection. Specifically:

[0151] Perform functional module mapping based on the integrated circuit test result data to obtain a module fault mapping table;

[0152] Perform cross-module fault correlation detection based on the module fault mapping table to obtain cross-module correlation data;

[0153] The fault impact degree is quantitatively calculated based on cross-module correlation data to obtain fault impact weight data; the weight value is calculated based on the fault propagation depth and impact range;

[0154] Sort the importance of fault nodes based on fault impact weight data to obtain key fault node data;

[0155] The module fault mapping table, cross-module correlation data, fault impact weight data and key fault node data are comprehensively analyzed to obtain the functional module fault correlation data.

[0156] In this embodiment of the present invention, a predefined chip functional module layout diagram is loaded. This layout diagram includes 16 main functional modules (such as clock generators, digital signal processing units, analog front ends, and storage controllers) and their physical coordinate ranges. The test system maps 64 probe channels to corresponding functional modules using a coordinate matching algorithm. Each channel uniquely corresponds to a functional module based on its physical location. For channels that cross module boundaries, the test system uses a weighted distribution method to allocate fault contributions based on the proportion of channel coverage area in each module. The test system then counts the number and severity of faulty channels in each module and calculates the module failure rate F_m = ∑(S_i × W_i) / N_m, where S_i is the fault severity of channel i (graded from 1 to 10), W_i is the channel importance weight, and N_m is the total number of channels contained in module m. The test system generates a module fault mapping table, which includes module ID, failure rate, fault type distribution, a list of severely faulty channels, and module function importance level.

[0157] Cross-module fault correlation detection is performed based on the module fault mapping table. This detection utilizes a multivariate time series correlation analysis method, constructing a 16×16 module correlation matrix. Correlation strength is calculated based on conditional mutual information entropy (CMI(X, Y|Z)) = H(X, Z) + H(Y, Z) - H(Z) - H(X, Y, Z), where X and Y represent the fault time series of the two modules, Z represents the control variable sequence (such as power supply fluctuations and temperature variations), and H() represents information entropy. The test system extracts module fault records for 100 test samples from a historical test database. Based on these records, conditional mutual information entropy between modules is calculated to construct a correlation strength matrix. Correlation determination utilizes a significance test with a p-value threshold of 0.01. Only statistically significant correlations are recorded. The test system further analyzes the directionality of correlations, using a Granger causality test to determine the direction of fault propagation. Directed correlations are identified when the test statistic F-value is greater than 10 and the p-value is less than 0.05. Finally, the test system generates cross-module correlation data, including correlation strength matrix, correlation direction map and abnormal correlation path markers.

[0158] A fault propagation network graph is constructed, in which nodes represent functional modules, edges represent inter-module association paths, and edge weights represent association strengths. The test system applies a network flow algorithm to calculate the influence weight of each node using the formula W_i = α × D_i + β × R_i + γ × C_i, where W_i is the influence weight of node i, D_i is the propagation depth (the longest path length from the node), R_i is the influence range (the number of downstream nodes affected by the node), C_i is the node centrality (a betweenness centrality metric), and α, β, and γ are weight coefficients (set to 0.3, 0.5, and 0.2, respectively). The propagation depth D_i is calculated using a depth-first search algorithm, starting from the faulty node and traversing along the directed edges, recording the maximum hierarchical depth. The influence range R_i is calculated using a breadth-first search algorithm, counting the number of downstream nodes reachable from node i. Node centrality C_i represents the criticality of a node in the fault propagation network and is determined by calculating the number of shortest paths passing through the node. The test system generates fault impact weight data, which contains the impact weight value of each module and its component details.

[0159] A multi-dimensional scoring mechanism is employed, comprehensively considering the fault impact weight, module functional importance, and repair difficulty. The scoring formula is S_i = W_i × F_i × (1 / D_i), where S_i is the comprehensive importance score of node i, W_i is the impact weight calculated above, F_i is the module functional importance (a predefined value ranging from 1-10, determined by the chip design documentation), and D_i is the repair difficulty index (ranging from 1-5, derived from historical maintenance records). The test system sorts all faulty modules in descending order by comprehensive score and generates a fault node importance ranking table. For nodes with similar scores (differences less than 5%), the test system further considers the cumulative time of the fault and the frequency of recurrence for further sorting. The top 25% of the nodes in the ranking are labeled "critical fault nodes"—nodes with high impact weight, high functional importance, or low repair difficulty. The test system combines the ranking results and critical node labels to form critical fault node data.

[0160] A comprehensive analysis is conducted on the module fault mapping table, cross-module correlation data, fault impact weight data, and key fault node data. The analysis process begins by constructing an integrated fault correlation graph, which combines the four aforementioned data types and is represented as a weighted directed graph. Node attributes include fault type, severity, and functional impact, while edge attributes include correlation strength, propagation probability, and timing dependency. The test system applies a community detection algorithm (using the Louvain method) to this graph to identify clusters of closely connected faulty modules and determine the main fault propagation paths and bottlenecks. The test system then performs a fault tree analysis, tracing back from leaf nodes (observed fault symptoms) to root nodes (potential fault sources), calculating the probability distribution of each fault source. For key fault nodes, the test system generates a detailed impact matrix to quantify their impact on each system function. Finally, the test system integrates all analysis results to generate functional module fault correlation data, including a fault correlation graph, fault source rankings, critical propagation paths, a fault impact heat map, and repair priority recommendations.

[0161] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0162] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing an integrated circuit, characterized in that: The following steps are involved: Step S1: Power on the integrated circuit to be tested to obtain initialization test configuration data; Analyze the probe point status according to the initialization test configuration data, compare the probe contact standards, and generate the probe contact quality assessment code; Step S2: performing probe channel allocation processing according to the probe contact quality assessment code to obtain probe channel signal allocation data; performing non-magnetic field scattering parameter measurement according to the probe channel signal allocation data, and performing magnetic field excitation frequency band analysis to generate magnetic field excitation avoidance frequency band data; Step S3: applying a static vector magnetic field environment to the integrated circuit under test based on the magnetic field excitation avoidance frequency band data, and then performing dynamic circuit channel test processing to obtain circuit test characteristic response data; wherein the circuit test characteristic response data includes electromagnetic field signal data of each channel, electrical characteristic signal data of each channel, and power supply voltage signal data; Step S4: Identify channel jump abnormality events based on the electrical characteristic signal data of each channel; calculate impedance spectrum fluctuation rate data based on the power supply voltage signal data; perform health assessment based on the electromagnetic field signal data of each channel, channel jump abnormality events, and impedance spectrum fluctuation rate data to obtain integrated circuit test result data; Step S5: Perform functional module mapping according to the integrated circuit test result data, and perform cross-module fault correlation detection to obtain functional module fault correlation data.

2. The integrated circuit testing method according to claim 1, wherein: Step S1 includes the following steps: Step S11: Power on the integrated circuit to be tested, read the preset test configuration, and obtain the initialization test configuration data; Step S12: activating the on-chip probe selection switch of the integrated circuit to be tested according to the initialization test configuration data, and generating probe point connection status data; Step S13: Based on the probe point connection status data, the contact resistance of the integrated circuit to be tested is detected one by one, and when the contact resistance is greater than 50Ω, it is marked as abnormal, and the probe contact resistance evaluation data is obtained; Step S14: Based on the probe contact resistance evaluation data, the on-chip phase-locked loop circuit in the integrated circuit to be tested is started to generate a 100 MHz-10 GHz test frequency signal to generate multi-frequency test signal data; Step S15: injecting a test signal into an on-chip probe of the integrated circuit to be tested through a vector network analyzer based on the multi-frequency test signal data, measuring and evaluating its reflection coefficient, and generating an original reflection coefficient value of the probe; Step S16: Compare the original reflection coefficient value of the probe with a preset contact standard of less than -20 dB, mark unqualified probes, and generate a probe contact quality assessment code.

3. The integrated circuit testing method according to claim 1, wherein: Step S2 includes the following steps: Step S21: If there are unqualified items in the probe contact quality assessment code, a recalibration operation is triggered for the probe channel, and a channel calibration control instruction is generated; Step S22: performing on-chip probe commissioning on the IC to be tested based on the channel calibration control instruction, determining available test channels, and performing probe channel allocation processing to obtain probe channel signal allocation data; Step S23: performing non-magnetic field scattering parameter measurement based on the probe channel signal distribution data, and performing equivalent circuit response analysis to generate original equivalent circuit response data; Step S24: quantifying the degree of suppression of circuit resonance by substrate eddy current loss based on the original equivalent circuit response data to obtain eddy current damping factor data; Step S25: Generate magnetic field excitation avoidance frequency band data based on the frequency bands marked with eddy current damping factor data greater than 0.

8.

4. The integrated circuit testing method according to claim 3, wherein: In step S23, the non-magnetic field scattering parameter measurement is performed according to the probe channel signal distribution data, and the equivalent circuit response analysis is performed, including: Perform signal amplitude detection based on the probe channel signal allocation data. When the signal amplitude attenuation is greater than 3dB, gain compensation is triggered to obtain on-chip probe state mapping data. Performing a preset stepped frequency scan start on an internal frequency synthesizer in the IC under test based on the on-chip probe state mapping data to obtain frequency scan initialization data; Use Hall sensors to confirm that the background magnetic field in the test area is less than 0.1 Oe to create a non-magnetic test environment; In a non-magnetic test environment, the forward transmission coefficient and reflection coefficient of the IC under test are measured at the mid-frequency point using a vector network analyzer based on the frequency sweep initialization data, generating full-band scattering parameter measurement data. The equivalent circuit parameters are calculated based on the full-band scattering parameter measurement data, and the electrical topology path response of the integrated circuit under test is performed to generate the original equivalent circuit response data; among which, the equivalent circuit parameters include parasitic resistance value, parasitic inductance value, and parasitic capacitance value.

5. The integrated circuit testing method according to claim 3, wherein: Quantifying the degree of suppression of circuit resonance by substrate eddy current loss based on the original equivalent circuit response data in step S24 includes: Performing a first-order derivative of the parasitic resistance value in the original equivalent circuit response data, and then extracting a curve of the parasitic resistance value varying with frequency to obtain a parasitic resistance frequency differential curve; Identify the frequency bands with a slope greater than 0.16 ohms / GHz in the parasitic resistance frequency differential curve and generate skin effect dominant frequency band markers; The curve of parasitic inductance value varying with frequency is extracted based on the original equivalent circuit response data, and the curve is segmented and fitted based on the skin effect dominant frequency band marker to obtain the geometric mutual inductance coefficient and dynamic eddy current additional inductance data; The LC resonance frequency at each frequency point is calculated based on the parasitic capacitance value and geometric mutual inductance in the original equivalent circuit response data, and the inherent electromagnetic resonance spectrum is generated; The inherent electromagnetic resonance spectrum is correlated with the dynamic eddy current additional inductance data to quantify the degree to which the resonance characteristics of the integrated circuit under test are suppressed by the substrate eddy current loss, and the eddy current damping factor data is generated.

6. The integrated circuit testing method according to claim 1, wherein: Step S3 includes the following steps: Step S31: Sending a magnetic field setting instruction to an external three-axis Helmholtz coil controller via the SPI interface based on the integrated circuit under test to apply a static vector magnetic field environment and simultaneously collect magnetic field values ​​in real time to obtain real-time magnetic field strength readings; wherein the field strength of the static vector magnetic field environment is 50 Oe, and the vector direction is at a 45-degree angle with the plane of the integrated circuit under test; Step S32: Perform stability judgment on the real-time magnetic field strength readings. When the magnetic field variation within 10 consecutive sampling points is less than 0.05 Oe and the overall magnetic field stability reaches ±0.1 Oe, the magnetic field is determined to be stable and a magnetic field stability ready signal is generated. Step S33: Based on the magnetic field stabilization ready signal, a low injection power diagnostic scan is performed on each probe channel of the IC under test using a vector network analyzer by using the frequency band marked in the magnetic field excitation avoidance frequency band data to generate a high loss region parasitic coupling spectrum; wherein the low injection power is set to -30 dBm; Step S34: Based on the magnetic field stabilization ready signal and the unmarked frequency bands in the magnetic field excitation avoidance frequency band data, a standard injection power performance scan is performed on each probe channel of the integrated circuit under test using a vector network analyzer to generate a mixed response spectrum in an effective working area; wherein the standard injection power is set to -10 dBm; Step S35: splicing the parasitic coupling spectrum of the high-loss region and the mixed response spectrum of the effective working region in the frequency domain to obtain the wide-spectrum scattering parameters of each channel; Step S36: performing magnetic field-circuit processing on the wide spectrum scattering parameters of each channel, and using the parasitic signals of the low injection power diagnostic scan as the electromagnetic field signal data of each channel; Step S37: performing parasitic baseline processing based on the parasitic coupling spectrum of the high-loss region, and subtracting the parasitic baseline from the mixed response spectrum of the effective working region to obtain electrical characteristic signal data of each channel; Step S38: When executing the scanning process of each probe channel, the power supply voltage pin of the integrated circuit to be tested is synchronously collected to obtain power supply voltage signal data.

7. The integrated circuit testing method according to claim 1, wherein: Identifying channel jump abnormal events according to the electrical characteristic signal data of each channel in step S4 includes: Perform current calibration processing on each channel according to the electrical characteristic signal data of each channel to obtain calibrated current data of each channel; Perform signal channel current aggregation analysis on the calibrated current data of each channel to obtain the shunt characteristic data of each channel; Calculate the current change gradient of each channel based on the shunt characteristic data of each channel and generate the current change gradient curve of each channel; Identify the transition edge interval according to the current change gradient curve of each channel to obtain the transition edge interval data of each channel; wherein the transition edge interval identification includes the rising edge, the plateau section and the falling edge; Calculate the maximum transition rate of each channel based on the transition edge interval data of each channel; Calculate the transition duration of each channel based on the transition edge interval data of each channel; Extract the jitter value of each channel's transition edge based on the current change gradient curve of each channel's transition edge interval data; Channel transition abnormalities are identified based on the maximum transition rate, transition duration, and transition edge jitter of each channel.

8. The integrated circuit testing method according to claim 7, wherein: Calculating the impedance spectrum fluctuation rate data based on the power supply voltage signal data in step S4 includes: Calculate the total circuit current based on the shunt characteristic data of each channel; Calculate the equivalent total impedance data through the power supply voltage signal data and the integrated circuit to be tested; Based on the equivalent total impedance data and the shunt characteristic data of each channel, the channel instantaneous impedance distribution calculation is performed to obtain the instantaneous impedance sequence of each channel; Calculate the impedance mean of each channel based on the instantaneous impedance sequence of each channel; Calculate the impedance standard deviation of each channel based on the instantaneous impedance sequence and impedance mean of each channel; The impedance spectrum fluctuation rate of each channel in the integrated circuit to be tested is calculated based on the impedance mean value and the standard deviation of the impedance of each channel to generate impedance spectrum fluctuation rate data.

9. The integrated circuit testing method according to claim 1, wherein: In step S4, health assessment is performed based on the electromagnetic field signal data of each channel, channel jump abnormality events, and impedance spectrum fluctuation rate data, and the integrated circuit test result data obtained includes: The abnormal channels of the integrated circuit to be tested are grouped according to the abnormal channel jump events to obtain a test abnormal channel group; Perform abnormal channel electromagnetic field coupling analysis on the abnormal channel group tested using electromagnetic field signal data of each channel to obtain channel electromagnetic coupling abnormal pattern data; Based on the channel electromagnetic coupling abnormal mode data, impedance spectrum fluctuation rate data and channel jump abnormal events, single channel fault type rule matching is performed to generate single channel fault type data; The health of the integrated circuit to be tested is evaluated through single-channel fault type data, and then the fault is located to obtain the integrated circuit test result data.

10. An integrated circuit testing system, characterized in that: For executing the integrated circuit testing method according to claim 1, the integrated circuit testing system comprises: The probe initialization module is used to power on the IC to be tested and obtain initialization test configuration data; analyze the probe point status according to the initialization test configuration data, compare the probe contact standards, and generate a probe contact quality assessment code; The dynamic frequency band allocation module is used to perform probe channel allocation processing based on the probe contact quality assessment code to obtain probe channel signal allocation data; perform non-magnetic field scattering parameter measurement based on the probe channel signal allocation data, and perform magnetic field excitation frequency band analysis to generate magnetic field excitation avoidance frequency band data; A magnetic field environment response module is used to apply a static vector magnetic field environment to the integrated circuit under test based on the magnetic field excitation avoidance frequency band data, and then perform dynamic circuit channel test processing to obtain circuit test characteristic response data; wherein the circuit test characteristic response data includes electromagnetic field signal data of each channel, electrical characteristic signal data of each channel, and power supply voltage signal data; The circuit channel test module is used to identify channel jump abnormal events based on the electrical characteristic signal data of each channel; calculate the impedance spectrum fluctuation rate data based on the power supply voltage signal data; and perform health assessment based on the electromagnetic field signal data of each channel, channel jump abnormal events, and impedance spectrum fluctuation rate data to obtain integrated circuit test result data; The fault correlation analysis module is used to map the functional modules according to the integrated circuit test result data, and perform cross-module fault correlation detection to obtain functional module fault correlation data.

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