A current source circuit, a clock source circuit, and a clock source generation device

Abstract

The embodiment of the present disclosure provides a current source circuit, a clock source circuit and a clock source generation device, comprising: a bias current generation circuit and a temperature coefficient balancing circuit; the bias current generation circuit comprises: a current adjusting module and an output module; and is used for generating a bias current with a corresponding positive temperature coefficient; the current adjusting module comprises: a first triode and a second triode; and is used for adjusting a bias voltage applied to the first triode and the second triode according to the preset area ratio, so as to obtain a first current with a target current value; the output module is used for outputting a bias current; and the temperature coefficient balancing circuit is used for generating a current with a negative temperature coefficient, and adjusting the temperature coefficient of the bias current. The current source circuit provided by the present disclosure can generate a bias current with a positive coefficient, adjust the temperature coefficient of the bias current through a current with a negative temperature coefficient, and guarantee the stability of the output bias current.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of analog integrated circuit design, and in particular to a current source circuit, a clock source circuit and a clock source generation device. BACKGROUND

[0002] Clock source is a core element for providing accurate time reference and timing control, and has a very wide range of applications. Relaxation oscillators based on traditional resistor-capacitor (RC) circuits are widely used in clock design of microcontroller units (MCUs) and other circuits due to their characteristics. However, the devices in the clock source circuit have specific temperature coefficients, and within a certain temperature fluctuation range, the characteristic values of the devices will change. The heat generated during the operation of the clock source will also affect the devices in the circuit, thereby affecting the frequency of the clock signal, making it difficult to meet the higher precision clock demand. At present, the main solution to this problem is to collect the temperature of the main chip in the oscillator, and change the analog voltage of the variable capacitor according to the temperature, so as to change the capacitance value, thereby adjusting the output clock frequency. However, this technology has the defect of complex circuit structure, and requires an additional temperature-voltage conversion control module to change the capacitance value, increasing the complexity and cost of circuit design, and also limiting its application scenarios to some extent. In summary, there is an urgent need for a circuit that can adjust the temperature coefficient and ensure stable bias current output. SUMMARY

[0003] The present disclosure provides a current source circuit, a clock source circuit and a clock source generation device to adjust the temperature coefficient of the bias current and output stable bias current.

[0004] Based on the above problems, in a first aspect, the present disclosure provides a current source circuit, comprising: a bias current generation circuit and a temperature coefficient balancing circuit;

[0005] The bias current generation circuit comprises: a current adjusting module and an output module; the bias current generation circuit is configured to generate a bias current with a corresponding positive temperature coefficient;

[0006] The current adjusting module comprises: a first triode and a second triode; the first triode and the second triode are two symmetrical transistors with a preset area ratio; the current adjusting module is configured to adjust the bias voltage applied to the first triode and the second triode according to the preset area ratio, to obtain a first current with a target current value;

[0007] The output module is configured to obtain the first current and output it as a bias current;

[0008] The temperature coefficient balancing circuit comprises two resistors connected in parallel with the first transistor and the second transistor respectively; and the temperature coefficient balancing circuit is configured to generate a current with a negative temperature coefficient to adjust the temperature coefficient of the bias current generated by the bias current generation circuit.

[0009] With reference to the first aspect, in a possible implementation, the bias current generation circuit further comprises a bias voltage generation module.

[0010] The bias voltage generation module is configured to convert a power supply voltage into two equal bias voltages and output the two equal bias voltages to the current adjustment module.

[0011] With reference to the first aspect, in a possible implementation, the bias voltage generation module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.

[0012] The source of the first PMOS transistor is connected to a power supply, the gate of the first PMOS transistor is connected to the output module, the gate of the second PMOS transistor, and the drain of the fourth PMOS transistor respectively, and the drain of the first PMOS transistor is connected to the source of the third PMOS transistor.

[0013] The source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor.

[0014] The gate of the third PMOS transistor is connected to the output module, the gate of the fourth PMOS transistor, and the drain of the second NMOS transistor respectively, and the drain of the third PMOS transistor is connected to one end of the first resistor and the gate of the first NMOS transistor.

[0015] The drain of the fourth PMOS transistor is connected to one end of the second resistor.

[0016] The drain of the first NMOS transistor is connected to the other end of the first resistor and the gate of the third NMOS transistor respectively, the gate of the drain of the first NMOS transistor is connected to the gate of the second NMOS transistor, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor.

[0017] The drain of the second NMOS transistor is connected to the other end of the second resistor, and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor.

[0018] The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the third NMOS transistor is connected to the current adjustment module.

[0019] The source of the fourth NMOS tube is connected with the current regulation module.

[0020] In combination with the first aspect, in a possible implementation, the current regulation module further includes a third resistor.

[0021] The emitter of the first transistor is connected with the bias voltage generation module, the base of the first transistor is connected with the collector of the first transistor and grounded.

[0022] One end of the third resistor is connected with the bias voltage generation module, and the other end of the third resistor is connected with the emitter of the second transistor.

[0023] The base of the second transistor is connected with the collector of the second transistor and grounded.

[0024] In combination with the first aspect, in a possible implementation, the output module includes a fifth PMOS tube and a sixth PMOS tube.

[0025] The source of the fifth PMOS tube is connected with a power supply, the drain of the fifth PMOS tube is connected with the sixth PMOS tube, and the gate of the fifth PMOS tube is connected with the bias voltage generation module.

[0026] The gate of the sixth PMOS tube is connected with the bias voltage generation module, and the drain of the sixth PMOS tube serves as an output end of the current source circuit and outputs a bias current.

[0027] In combination with the first aspect, in a possible implementation, the temperature coefficient balance circuit includes a fourth resistor and a fifth resistor.

[0028] One end of the fourth resistor is connected with the collector of the first transistor and grounded, and the other end of the fourth resistor is connected with the emitter of the first transistor.

[0029] One end of the fifth resistor is connected with one end of the third resistor, and the other end of the fifth resistor is connected with the collector of the second transistor and grounded.

[0030] In combination with the first aspect, in a possible implementation, the temperature coefficient balance circuit further includes a start-up circuit.

[0031] The start-up circuit is configured to generate an initial excitation input to the bias current generation circuit to start the bias current generation circuit in the case that the current source circuit is powered on.

[0032] In a possible implementation of the first aspect, the starting circuit comprises a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor.

[0033] The source of the seventh PMOS transistor is connected to a power supply, the gate of the seventh PMOS transistor is connected to the bias current generation circuit, and the drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the eighth PMOS, respectively.

[0034] The source of the eighth PMOS transistor is connected to a power supply, and the drain of the eighth PMOS transistor is connected to the bias current generation circuit.

[0035] The gates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are connected and grounded.

[0036] The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor; the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; and the source of the ninth NMOS transistor is grounded.

[0037] The second aspect of the present disclosure also provides a clock source circuit, comprising: a current source module, a first comparator module, a second comparator module, and a logic control module.

[0038] The current source module comprises the current source circuit of any one of the first aspect, for outputting bias currents to the first comparator module and the second comparator module, respectively.

[0039] The first comparator module comprises a first comparator, a first capacitor, and a first switching device; the first capacitor is used for charging according to the bias current; the first comparator is used for comparing the voltage of the first capacitor with a reference voltage and outputting a first electric signal according to the comparison result; and the first switching device is used for controlling the charging and discharging state of the first capacitor according to the control signal output by the logic control module.

[0040] The second comparator module comprises a second comparator, a second capacitor, and a second switching device; the second capacitor is used for charging according to the bias current; the second comparator is used for comparing the voltage of the second capacitor with a reference voltage and outputting a second electric signal according to the comparison result; and the second switching device is used for controlling the charging and discharging state of the second capacitor according to the control signal output by the logic control module.

[0041] The logic control module is configured to shape an oscillation waveform according to the first electrical signal and the second electrical signal, and output a control signal according to a preset logic to control the first capacitor and the second capacitor to alternately charge and discharge.

[0042] The third aspect of the present disclosure further provides a clock source generation apparatus, comprising the clock source circuit of the second aspect.

[0043] The present disclosure has the following beneficial effects:

[0044] The present disclosure provides a current source circuit, a clock source circuit and a clock source generation apparatus, comprising: a bias current generation circuit and a temperature coefficient balancing circuit; the bias current generation circuit comprises: a current adjustment module and an output module; and is configured to generate a bias current with a corresponding positive temperature coefficient; the current adjustment module comprises: a first triode and a second triode; the first triode and the second triode are two symmetrical transistors with a preset area ratio; the current adjustment module is configured to adjust a bias voltage applied to the first triode and the second triode according to the preset area ratio, to obtain a first current with a target current value; the output module is configured to obtain the first current and output the first current as a bias current; and the temperature coefficient balancing circuit comprises two paths of resistors connected in parallel with the first triode and the second triode respectively; the temperature coefficient balancing circuit is configured to generate a current with a negative temperature coefficient, to adjust the temperature coefficient of the bias current in the bias current generation circuit. The current source circuit provided by the present disclosure can generate a bias current with a positive coefficient, and adjust the temperature coefficient of the bias current through a current with a negative temperature coefficient, and ensure the stability of the output bias current. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A current source circuit structure schematic diagram is provided for the present disclosure embodiment;

[0046] Figure 2 A current adjustment module structure schematic diagram is provided for the present disclosure embodiment;

[0047] Figure 3 A bias voltage generation module structure schematic diagram is provided for the present disclosure embodiment;

[0048] Figure 4 A temperature coefficient comparison diagram is provided for the present disclosure embodiment;

[0049] Figure 5 A clock source circuit structure schematic diagram is provided for the present disclosure embodiment. DETAILED DESCRIPTION

[0050] The embodiment of the present disclosure provides a current source circuit, a clock source circuit and a clock source generation device, and the preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. Moreover, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0051] The embodiment of the present disclosure provides a current source circuit, as shown in the figure, Figure 1 including a bias current generation circuit 1 and a temperature coefficient balancing circuit 2.

[0052] The bias current generation circuit 1 includes a current adjusting module 12 and an output module 13; the bias current generation circuit 1 is used to generate a bias current with a corresponding positive temperature coefficient;

[0053] As shown in the figure, Figure 2 The current adjusting module 12 includes a first triode 121 and a second triode 122; the first triode 121 and the second triode 122 are two symmetrical transistors with a preset area ratio; the current adjusting module 12 is used to adjust the bias voltage applied to the first triode 121 and the second triode 122 according to the preset area ratio, to obtain a first current with a target current value;

[0054] The output module 13 is used to obtain the first current and output it as a bias current;

[0055] The temperature coefficient balancing circuit 2 includes two paths of resistors connected in parallel with the first triode 121 and the second triode 122 respectively; the temperature coefficient balancing circuit 2 is used to generate a current with a negative temperature coefficient, to adjust the temperature coefficient of the bias current in the bias current generation circuit 1.

[0056] In the embodiment of the present disclosure, the current source circuit can provide stable current for the clock source circuit, and can isolate the interference of noise in the power supply and weaken the influence of power voltage fluctuation on the current.

[0057] The current source circuit can include a bias current generation circuit 1 and a temperature coefficient balancing circuit 2, wherein the bias current output by the bias current generation circuit 1 can be used as a reference current for the operation of the clock source circuit. Through the injection of the reference current, it can further ensure that the devices in the clock source circuit work in a preset working state, so as to realize stable clock signal output.

[0058] The bias current output by the bias current generation circuit 1 The bias current can be a current with a positive temperature coefficient, that is, the current also increases with the increase of temperature. In an ideal state, the devices in the clock source circuit also have a certain temperature coefficient. With the change of temperature, the changes of different devices due to the temperature coefficient will offset each other, so that the finally output clock signal remains stable. However, in actual application, the positive temperature coefficient of the bias current can be too large, which can cause over-compensation of the clock source circuit, so that the output clock signal also changes with temperature. To solve the above problems, the temperature coefficient balancing circuit 2 provided by the present disclosure can generate a negative temperature coefficient to adjust the temperature coefficient of the bias current, so that the temperature coefficient of the bias current and the temperature coefficient of the clock source circuit match each other, so that the output clock signal is not affected by temperature change, and the output clock signal is stable.

[0059] The current adjusting module 12 can include two transistors with a preset area ratio, which can be a first transistor 121 and a second transistor 122. The bias voltage is applied to the two transistors, and a corresponding voltage difference can be generated according to the area ratio, so as to generate a first current with a corresponding current value in the bias current generating circuit 1.

[0060] The output module 13 can obtain the first current and output it to the clock source circuit as the bias current of the clock source circuit.

[0061] In another embodiment of the present disclosure, as shown in Figure 1 The bias current generating circuit 1 further includes a bias voltage generating module 11.

[0062] The bias voltage generating module 11 is configured to convert the power supply voltage into two equal bias voltages and output them to the current adjusting module 12.

[0063] In the embodiment of the present disclosure, the bias current generating circuit 1 can be composed of the bias voltage generating module 11, the current adjusting module 12 and the output module 13.

[0064] The bias voltage generation module 11 can include a plurality of metal oxide semiconductor field effect transistors (MOS, Metal-Oxide-Semiconductor Field-Effect Transistor), specifically, a P-type channel metal oxide semiconductor field effect transistor (PMOS, P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) and an N-type channel metal oxide semiconductor field effect transistor (NMOS, N-channel Metal-Oxide-Semiconductor Field-Effect Transistor). Through the special connection relationship between the MOS tubes, the power supply voltage can be converted into two equal bias voltages, and the two bias voltages are provided to the current regulation module 12.

[0065] In yet another embodiment of the present disclosure, as shown in Figure 3 The bias voltage generation module 11 includes a first PMOS tube 1101, a second PMOS tube 1102, a third PMOS tube 1103, a fourth PMOS tube 1104, a first resistor 1105, a second resistor 1106, a first NMOS tube 1107, a second NMOS tube 1108, a third NMOS tube 1109, and a fourth NMOS tube 1110.

[0066] The source of the first PMOS tube 1101 is connected to the power supply, the gate of the first PMOS tube 1101 is connected to the output module 13, the gate of the second PMOS tube 1102, and the drain of the fourth PMOS tube 1104, respectively, and the drain of the first PMOS tube 1101 is connected to the source of the third PMOS tube 1103.

[0067] The source of the second PMOS tube 1102 is connected to the power supply, and the drain of the second PMOS tube 1102 is connected to the source of the fourth PMOS tube 1104.

[0068] The gate of the third PMOS tube 1103 is connected to the output module 13, the gate of the fourth PMOS 1104, and the drain of the second NMOS tube 1108, respectively, and the drain of the third PMOS tube 1103 is connected to one end of the first resistor 1105 and the gate of the first NMOS tube 1107.

[0069] The drain of the fourth PMOS tube 1104 is connected to one end of the second resistor 1106.

[0070] The drain of the first NMOS transistor 1107 is connected to the other end of the first resistor 1105 and the gate of the third NMOS transistor 1109, the drain and the gate of the first NMOS transistor 1107 are connected to the gate of the second NMOS transistor 1108, and the source of the first NMOS transistor 1107 is connected to the drain of the third NMOS transistor 1109;

[0071] The drain of the second NMOS transistor 1108 is connected to the other end of the second resistor 1106, and the source of the second NMOS transistor 1108 is connected to the drain of the fourth NMOS transistor 1110;

[0072] The gate of the third NMOS transistor 1109 is connected to the gate of the fourth NMOS transistor 1110, and the source of the third NMOS transistor 1109 is connected to the current regulating module 12;

[0073] The source of the fourth NMOS transistor 1110 is connected to the current regulating module 12.

[0074] In the embodiment of the present disclosure, the first PMOS transistor 1101 and the second PMOS transistor 1102 constitute a current mirror structure, the gates of the first PMOS transistor 1101 and the second PMOS transistor 1102 are connected, the gate voltages of the two MOS transistors are the same, and the sources are connected to the power supply, so that if the sizes of the first PMOS transistor 1101 and the second PMOS transistor 1102 are the same and they work in the saturation region, the drain currents of the first PMOS transistor 1101 and the second PMOS transistor 1102 are the same. Similarly, the third PMOS transistor 1103 and the fourth PMOS transistor 1104 also constitute a corresponding current mirror structure.

[0075] Further, the gate of the first PMOS transistor 1101 is connected to the gate of the second PMOS transistor 1102 and the drain of the fourth PMOS transistor 1104, and a feedback structure is formed. Assuming that the drain current of the fourth PMOS transistor 1104 increases, the drain voltage of the fourth PMOS transistor 1104 will decrease, thereby causing the absolute values of the gate voltages of the first PMOS transistor 1101 and the second PMOS transistor 1102 to increase. The greater the absolute value of the gate voltage of the PMOS transistor, the greater the drain current, and the greater the current input to the source of the fourth PMOS transistor 1104, so that the drain voltage of the fourth PMOS transistor 1104 rises and the drain current decreases. Similarly, when the drain current of the fourth PMOS transistor 1104 decreases, the feedback structure can also prevent the drain current from decreasing. By feeding back the drain voltage of the fourth PMOS transistor 1104 to the gate of the first PMOS transistor 1101, a negative feedback loop is formed to suppress fluctuations in the circuit.

[0076] Further, the first NMOS transistor 1107 and the second NMOS transistor 1108, and the third NMOS transistor 1109 and the fourth NMOS transistor 1110 also form the same current mirror structure. Through the current mirror relationship, the source voltage of the third NMOS transistor 1109 and the source voltage of the fourth NMOS transistor 1110 can be clamped to the same value as the two-way bias voltage output to the current regulation module 12.

[0077] In yet another embodiment of the present disclosure, as shown in Figure 2 The current regulation module 12 further comprises a third resistor 123.

[0078] The collector of the first transistor 121 is connected to the bias voltage generation module 11, and the base of the first transistor 121 is connected to the emitter of the first transistor 121 and grounded.

[0079] One end of the third resistor 123 is connected to the bias voltage generation module 11, and the other end of the third resistor 123 is connected to the collector of the second transistor 122.

[0080] The base of the second transistor 122 is connected to the emitter of the second transistor 122 and grounded.

[0081] In the embodiment of the present disclosure, the first transistor 121 and the second transistor 122 can both be PNP type bipolar junction transistors (BJT), and the area ratio of the emitters of the two transistors can be a certain preset ratio. The first transistor 121 and the second transistor 122 obtain one-way bias voltage respectively, and according to the area ratio of the emitters, a corresponding voltage difference is generated between the first transistor 121 and the second transistor 122, which is only related to temperature and the area ratio of the emitters. And further determines the value of the current flowing through the third resistor 123. Since the forward voltage of the PNP transistor has a negative temperature coefficient, the voltage between the base and the emitter of the first transistor 121 and the second transistor 122 also has a negative temperature coefficient. Through basic derivation, it is obtained that the voltage difference between the first transistor 121 and the second transistor 122 is a positive temperature coefficient, so the voltage across the third resistor 123 is a positive temperature coefficient, thereby making the current flowing through the third resistor 123 also have a positive temperature coefficient, which can be determined by the area ratio of the emitters of the first transistor 121 and the second transistor 122.

[0082] According to the base-emitter voltage and current relationship of the BJT, the base-emitter voltage of the transistor can be obtained. Wherein, is the thermal voltage, which is proportional to the absolute temperature; is the collector current of the transistor; is the reverse saturation current of the triode. Then the voltage difference between the base-emitter of the two triodes is obtained is the base-emitter voltage of the second triode; is the base-emitter voltage of the second triode; is the base-emitter voltage of the first triode; is the ratio of the emitter area between the first triode and the second triode. Further, the current of the third resistor (i.e. the first current) is obtained is the resistance of the third resistor. According to the above formula, the size of the first current is related to the resistance, temperature and the ratio of the emitter area of the third resistor, so that the first current is proportional to the temperature with a positive temperature coefficient when the resistance and the triode are determined.

[0083] In yet another embodiment of the present disclosure, as shown in Figure 1 the output module 13 comprises a fifth PMOS tube 131 and a sixth PMOS tube 132.

[0084] The source of the fifth PMOS tube 131 is connected to the power supply, the drain of the fifth PMOS tube 131 is connected to the sixth PMOS tube 132, and the gate of the fifth PMOS tube 131 is connected to the bias voltage generation module 11.

[0085] The gate of the sixth PMOS tube 132 is connected to the bias voltage generation module 11, and the drain of the sixth PMOS tube 132 serves as the output end of the current source circuit to output the bias current.

[0086] In the embodiment of the present disclosure, the fifth PMOS tube 131 can form a current mirror circuit with the second PMOS tube 1102, and the sixth PMOS tube 132 can form a current mirror circuit with the fourth PMOS tube 1104, so as to mirror the first current to the output module 13 and output the bias current.

[0087] In yet another embodiment of the present disclosure, as shown in Figure 1 the temperature coefficient balancing circuit 2 comprises a fourth resistor 21 and a fifth resistor 22.

[0088] One end of the fourth resistor 21 is connected to the collector of the first triode 121 and grounded, and the other end of the fourth resistor 21 is connected to the emitter of the first triode 121.

[0089] One end of the fifth resistor 22 is connected to one end of the third resistor 123, and the other end of the fifth resistor 22 is connected to the collector of the second triode 122 and grounded. ​​

[0090] In the embodiment of the present disclosure, the fourth resistor 21 is connected in parallel with the first triode 121, and the fifth resistor 22 is connected in parallel with the branch composed of the third resistor 123 and the second triode 122. Since the base-emitter voltage of the triode has a negative temperature coefficient, the voltage across the fourth resistor 21 and the voltage across the fifth resistor 22 also have a negative temperature coefficient. By adjusting the resistance values of the fourth resistor 21 and the fifth resistor 22, two currents with a negative temperature coefficient can be generated in the branch where the fifth resistor 22 is located, thereby reducing the positive temperature coefficient of the current of the third resistor 123, achieving the purpose of adjusting the temperature coefficient. The current of the fifth resistor 22 , wherein, is the resistance value of the fifth resistor. Since itself has a negative temperature characteristic, the current also has a negative temperature characteristic. By setting the resistance value of the fifth resistor, the magnitude of can be controlled, thereby adjusting the temperature coefficient of the first current.

[0091] In yet another embodiment provided by the present disclosure, as shown in Figure 1 , the current source circuit further comprises a starting circuit 3.

[0092] The starting circuit 3 is configured to generate an initial excitation input to the bias current generation circuit 1 to start the bias current generation circuit 1 when the current source circuit is powered on.

[0093] In the embodiment of the present disclosure, the starting circuit 3 is configured to provide an initial excitation signal for the bias current generation circuit 1, to break the zero-current state in the bias current generation circuit 1, to turn on the MOS tube in the bias current generation circuit 1, and to establish a working current to enter a stable working state.

[0094] In yet another embodiment provided by the present disclosure, as shown in Figure 1 , the starting circuit 3 comprises a seventh PMOS tube 31, an eighth PMOS tube 32, a fifth NMOS tube 33, a sixth NMOS tube 34, a seventh NMOS tube 35, an eighth NMOS tube 36, and a ninth NMOS tube 37.

[0095] The source of the seventh PMOS tube 31 is connected to a power supply, the gate of the seventh PMOS tube 31 is connected to the bias current generation circuit 1, and the drain of the seventh PMOS tube 31 is connected to the drain of the fifth NMOS tube 33 and the gate of the eighth PMOS tube 32, respectively.

[0096] The source of the eighth PMOS tube 32 is connected to a power supply, and the drain of the eighth PMOS tube 32 is connected to the bias current generation circuit 1.

[0097] The gate of the fifth NMOS tube 33, the gate of the sixth NMOS tube 34, the gate of the seventh NMOS tube 35, the gate of the eighth NMOS tube 36 and the gate of the ninth NMOS tube 37 are connected and grounded;

[0098] The source of the fifth NMOS tube 33 is connected with the drain of the sixth NMOS tube 34; the source of the sixth NMOS tube 34 is connected with the drain of the seventh NMOS tube 35; the source of the seventh NMOS tube 35 is connected with the drain of the eighth NMOS tube 36; the source of the eighth NMOS tube 36 is connected with the drain of the ninth NMOS tube 37; and the source of the ninth NMOS tube 37 is grounded.

[0099] In the embodiment of the present disclosure, when the current source circuit is powered on, the seventh PMOS tube 31 can provide a starting circuit for each MOS tube through the current mirror structure composed of the first PMOS tube 1101, the second PMOS tube 1102 and the fifth PMOS tube 131, break the zero current state and establish an initial current to enter a normal working state. The eighth PMOS tube 32 can provide a starting current at the drain of the third PMOS tube 1103 to establish an initial current in the branch of the bias current generation circuit 1, and further make the bias current generation circuit 1 enter a normal working state.

[0100] As shown in Figure 4 , a simulation comparison diagram of the temperature coefficient of the traditional current source and the temperature coefficient of the current source of the present disclosure. The abscissa in the figure is the temperature value, in units of Celsius (℃); the ordinate is the current value, in units of microamperes (μA). The upper curve is the curve of the current of the present disclosure changing with temperature, and the lower curve is the curve of the current of the traditional current source changing with temperature. It can be seen that the slope of the current curve of the present disclosure changing with temperature is significantly smaller than that of the traditional current source, which shows that the temperature coefficient of the current source of the present disclosure is significantly lower than that of the traditional current source, and the present disclosure achieves the goal of adjusting the temperature coefficient.

[0101] The present disclosure also provides a clock source circuit, as shown in Figure 5 , comprising: a current source module 41, a first comparator module 42, a second comparator module 43 and a logic control module 44;

[0102] The current source module 41 comprises the current source circuit provided in any of the above embodiments, for outputting bias currents to the first comparator module 42 and the second comparator module 43, respectively;

[0103] The first comparator module 42 comprises a first comparator 421, a first capacitor 422 and a first switch device 423; the first capacitor 422 is used to charge according to the bias current; the first comparator is used to compare the voltage of the first capacitor 422 with a reference voltage, and output a first electric signal according to the comparison result; the first switch device 423 is used to control the charging and discharging state of the first capacitor 422 according to the control signal output by the logic control module 44;

[0104] The second comparator module 43 comprises a second comparator 431, a second capacitor 432 and a second switch device 433; the second capacitor 432 is used to charge according to the bias current; the second comparator is used to compare the voltage of the second capacitor 432 with a reference voltage, and output a second electric signal according to the comparison result; the second switch device 433 is used to control the charging and discharging state of the second capacitor 432 according to the control signal output by the logic control module 44;

[0105] The logic control module 44 is used to shape a shock waveform according to the first electric signal and the second electric signal, and output a control signal according to a preset logic to control the first capacitor 422 and the second capacitor 432 to alternately charge and discharge.

[0106] In the embodiment of the present disclosure, as shown in Figure 5 The logic control module 44 can comprise two NAND gates, the input ends of the first NAND gate 441 respectively acquire the output signal of the first comparator 421 and the output signal of the second NAND gate 442, and the output end of the first NAND gate 441 is connected with the first switch device 423. The input ends of the second NAND gate respectively acquire the output signal of the second comparator and the output signal of the first NAND gate 441, and the output end of the second NAND gate 442 is connected with the second switch device 433, thereby forming an SR Latch structure.

[0107] The bias current output by the current source circuit is input to the two comparator modules respectively, and it is assumed that in the initial state, the first capacitor 422 is charged, the second capacitor 432 is discharged, the first comparator outputs a high level, and the second comparator outputs a low level. With the bias current charging the first capacitor 422, the voltage of the first capacitor 422 gradually rises, and when the voltage of the first capacitor 422 rises to the reference voltage , the level of the first comparator output is flipped to low level, the output end of the first NAND gate 441 outputs high level, the first switch device 423 is turned on, and the first capacitor 422 is discharged. At the same time, since the inputs of the second NAND gate 442 are all high level, the second NAND gate 442 outputs low level, the second switch device 433 is turned off, and the second capacitor 432 starts to charge. Until the voltage of the second capacitor 432 reaches the reference voltage, the output state of the second comparator is flipped, the second capacitor 432 starts to discharge, and the first capacitor 422 charges. Through the above process, a continuous oscillation signal can be obtained from the output of the first NAND gate 441, and through the final stage buffer circuit in the logic control module 44, a square wave can be output, and a clock signal can be obtained.

[0108] The final stage buffer circuit can include two-stage inverters and a high level / low level (H / L) output buffer 445. The first-stage inverter is implemented by using a third NAND gate 443, one input end of the third NAND gate 443 inputs high level, and the other input end is connected with the output end of the first NAND gate 441, for inverting the signal output by the first NAND gate 441; and the second-stage inverter is implemented by using a NOT gate 444.

[0109] It should be noted that the capacitors and other devices in the clock source circuit also have temperature coefficients, and the temperature coefficients of the current sources can be matched by configuring the resistors and transistors in the current sources, so as to reduce the interference of temperature change on the clock signal output by the clock source.

[0110] The present disclosure also provides a clock source generation device, including the clock source circuit in the above embodiments.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware, or can be implemented by means of software and necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.), and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

[0112] Those skilled in the art can understand that the drawings are only schematic of a preferred embodiment, and the modules or processes in the drawings are not necessarily required for implementing the present disclosure.

[0113] Those skilled in the art can understand that the modules in the device in the embodiments can be distributed in the device in the embodiments according to the description of the embodiments, or can be changed to be located in one or more devices different from the embodiments. The modules in the above embodiments can be combined into one module, or can be further split into multiple sub-modules.

[0114] The sequence numbers of the embodiments of the present disclosure are only for description, and do not represent advantages or disadvantages of the embodiments.

[0115] Obviously, various modifications and variations of the present disclosure can be made by those skilled in the art without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure include modifications and variations of this disclosure within its scope. The modifications and variations are intended to come within the scope of the claims of the present disclosure and their equivalents.

Claims

1. A current source circuit, characterized in that, include: Bias current generation circuit and temperature coefficient balancing circuit; The bias current generation circuit includes: a current adjustment module, an output module, and a bias voltage generation module; the bias current generation circuit is used to generate a bias current with a corresponding positive temperature coefficient. The current regulation module includes: a first transistor and a second transistor; the first transistor and the second transistor are two symmetrical transistors with a preset area ratio; the current regulation module is used to adjust the bias voltage applied to the first transistor and the second transistor according to the preset area ratio to obtain a first current with a target current value; The output module is used to acquire the first current and output it as a bias current; The bias voltage generation module is used to convert the power supply voltage into two equal bias voltages and output them to the current regulation module. The temperature coefficient balancing circuit includes two resistors connected in parallel with the first transistor and the second transistor, respectively; the temperature coefficient balancing circuit is used to generate a current with a negative temperature coefficient and adjust the temperature coefficient of the bias current in the bias current generation circuit. The bias voltage generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The source of the first PMOS transistor is connected to the power supply, the gate of the first PMOS transistor is connected to the output module, the gate of the second PMOS transistor and the drain of the fourth PMOS transistor, and the drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to the output module, the gate of the fourth PMOS transistor, and the drain of the second NMOS transistor, respectively. The drain of the third PMOS transistor is connected to one end of the first resistor and the gate of the first NMOS transistor, respectively. The drain of the fourth PMOS transistor is connected to one end of the second resistor; The drain of the first NMOS transistor is connected to the other end of the first resistor and the gate of the third NMOS transistor, the drain and gate of the first NMOS transistor are connected to the gate of the second NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the third NMOS transistor. The drain of the second NMOS transistor is connected to the other end of the second resistor, and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the third NMOS transistor is connected to the current regulation module. The source of the fourth NMOS transistor is connected to the current regulation module.

2. The current source circuit as described in claim 1, characterized in that, The current regulation module further includes: a third resistor; The emitter of the first transistor is connected to the bias voltage generation module, and the base of the first transistor is connected to the collector of the first transistor and grounded. One end of the third resistor is connected to the bias voltage generation module, and the other end of the third resistor is connected to the emitter of the second transistor. The base of the second transistor is connected to the collector of the second transistor and grounded.

3. The current source circuit as described in claim 1, characterized in that, The output module includes: a fifth PMOS transistor and a sixth PMOS transistor; The source of the fifth PMOS transistor is connected to the power supply, the drain of the fifth PMOS transistor is connected to the sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the bias voltage generation module. The gate of the sixth PMOS transistor is connected to the bias voltage generation module, and the drain of the sixth PMOS transistor serves as the output terminal of the current source circuit, outputting bias current.

4. The current source circuit as described in claim 2, characterized in that, The temperature coefficient balancing circuit includes: a fourth resistor and a fifth resistor; One end of the fourth resistor is connected to the collector of the first transistor and grounded, and the other end of the fourth resistor is connected to the emitter of the first transistor. One end of the fifth resistor is connected to one end of the third resistor, and the other end of the fifth resistor is connected to the collector of the second transistor and grounded.

5. The current source circuit as described in claim 1, characterized in that, It also includes a startup circuit; The startup circuit is used to generate an initial excitation input to the bias current generation circuit when the current source circuit is powered on, thereby starting the bias current generation circuit.

6. The current source circuit as described in claim 5, characterized in that, The startup circuit includes: a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The source of the seventh PMOS transistor is connected to the power supply, the gate of the seventh PMOS transistor is connected to the bias current generation circuit, and the drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the eighth PMOS transistor. The source of the eighth PMOS transistor is connected to the power supply, and the drain of the eighth PMOS transistor is connected to the bias current generation circuit. The gates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are connected to and grounded. The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor; the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; and the source of the ninth NMOS transistor is grounded.

7. A clock source circuit, characterized in that, include: The module consists of a current source module, a first comparator module, a second comparator module, and a logic control module. The current source module includes the current source circuit according to any one of claims 1-6, for outputting bias current to the first comparator module and the second comparator module respectively; The first comparator module includes: a first comparator, a first capacitor, and a first switching device; the first capacitor is used to charge according to the bias current; the first comparator is used to compare the voltage of the first capacitor with a reference voltage and output a first electrical signal according to the comparison result; the first switching device is used to control the charging and discharging state of the first capacitor according to the control signal output by the logic control module. The second comparator module includes: a second comparator, a second capacitor, and a second switching device; the second capacitor is used to charge according to the bias current; the second comparator is used to compare the voltage of the second capacitor with a reference voltage and output a second electrical signal according to the comparison result; the second switching device is used to control the charging and discharging state of the second capacitor according to the control signal output by the logic control module. The logic control module is used to shape an oscillation waveform based on the first electrical signal and the second electrical signal; and to output a control signal according to a preset logic to control the first capacitor and the second capacitor to charge and discharge alternately.

8. A clock source generation device, characterized in that, Includes the clock source circuit as described in claim 7.

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