Memory access method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of micro-architecture, and discloses a memory access method, electronic equipment and a storage medium. The memory access method comprises the steps that the electronic equipment can adopt different modes to configure an ODT function corresponding to a first memory based on whether data to be accessed by an XPU and stored in the first memory meet a first condition (the first condition is used for indicating the reliability requirement of the data). For example, under the condition that the first data to be accessed does not meet the first condition, the ODT function can be started, and the resistance value of the ODT is configured to be the rated resistance value under the first working condition; under the condition that the second data to be accessed meets the first condition, the electronic equipment can close the ODT function or open the ODT function and configure the resistance value of the ODT to be larger than the rated resistance value under the first working condition. Therefore, the data reliability can be improved through the ODT matching impedance when data with relatively high reliability guarantee requirements are accessed; and the ODT power consumption can be reduced when data with relatively low reliability requirements are accessed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of micro-architecture, and in particular to a memory access method, an electronic device and a storage medium. BACKGROUND

[0002] In the design of a modern system on a chip (SOC), by integrating a neural processing unit (NPU), a graphics processing unit (GPU) and other various types of special-purpose processors and other intellectual property (IP) cores with large bandwidth requirements, the data processing capability of the chip has been significantly improved.

[0003] Among them, these IP cores usually perform a large number of access operations on the memory outside the SOC (which can be referred to as off-chip memory) during operation, such as reading data from a double data rate synchronous dynamic random access memory (DDR DRAM) or storing data in the DDR DRAM. In the case where the amount of data accessed by the IP core is large, the power consumption of the IP core in accessing data from the off-chip memory is high. SUMMARY

[0004] To solve the above problems, the present application provides a memory access method, an electronic device and a storage medium.

[0005] In a first aspect, the present application provides a memory access method applied to an electronic device, the method comprising: detecting a first data access request, the first data access request being used to access first data in a first memory of the electronic device, the reliability requirement of the first data not meeting a first condition; reading the first data from the first memory in a first working condition, wherein an on-die termination (ODT) function of the first memory is turned on, and an ODT corresponding to the first memory has a first resistance value, the first working condition indicating at least one of that a working temperature of a first chip where the ODT is located is in a first temperature interval or that a working voltage of the first chip is in a first voltage interval; detecting a second data access request, the second data access request being used to access second data in the first memory, the reliability requirement of the second data meeting the first condition; and reading the second data from the first memory in the first working condition, wherein the ODT function corresponding to the first memory is turned off, or the ODT function corresponding to the first memory is turned on and the ODT has a second resistance value, the second resistance value being greater than the first resistance value.

[0006] In some embodiments, the first condition can be used to indicate a reliability requirement of the data. Wherein the reliability requirement of the first data does not satisfy the first condition, it is used to indicate that the electronic device has a higher reliability requirement for the first data. The reliability requirement of the second data satisfies the first condition, which is used to indicate that the electronic device has a lower reliability requirement for the second data.

[0007] In some embodiments, the first resistance value can be a rated resistance value corresponding to the ODT in the first working condition. The rated resistance value can be an experimental value or an empirical value. For example, after the developer determines different rated resistance values corresponding to the ODT in different working conditions of the first chip through experiments or experience, the one-to-one correspondence between the different rated resistance values and the corresponding working conditions can be stored in various ways (such as a corresponding table, a functional relationship, etc.).

[0008] In some embodiments, in the process of returning the first data read from the DDR DRAM to the IP core, the impedance can be matched through the first resistance value of the ODT in the DDR physical layer (double data rate physical layer, DDR PHY), thereby reducing the reflection of the signal energy transmitted by the DDR DRAM to the IP core when reaching the DDR PHY, and ensuring the integrity and reliability of the first data received by the IP core.

[0009] In some embodiments, when the electronic device accesses the second data with a lower reliability requirement, the ODT function is already in a closed state when the DDR DRAM transmits the second data to the DDR PHY, which can save power consumption. Or, when the DDR DRAM transmits the second data to the DDR PHY, since the working voltage of the ODT will not change and the power is “working voltage / resistance 2 ”, the ODT resistance value is adjusted to the second resistance value, which can save power consumption.

[0010] In this way, based on the above-mentioned manner, both the ODT can match the impedance when accessing the first data with a higher reliability requirement to reduce signal reflection and improve data integrity and reliability, and the ODT power consumption can be reduced when accessing the second data with a lower reliability requirement, thereby saving the overall power consumption in the memory access task related system.

[0011] In a possible implementation of the first aspect, the first condition includes: a type of the data is a preset type, and a storage area of the data in the first memory is a preset storage area, wherein the preset type includes a weight parameter of an operator in a neural network model.

[0012] In some embodiments, the first condition is used to indicate a reliability requirement of the data. For example, the electronic device has a lower reliability requirement for a weight parameter of an operator in the neural network model; or the electronic device can also store data (e.g., the weight parameter) with a lower reliability requirement in a preset storage area.

[0013] In a possible implementation of the first aspect, the reliability requirement of the first data does not satisfy the first condition, including: the type of the first data is not a preset type, or the storage area of the first data in the first memory is not a preset storage area. The reliability requirement of the second data satisfies the first condition, including: the type of the second data is the preset type, or the storage area of the second data in the first memory is the preset storage area.

[0014] In a possible implementation of the first aspect, the electronic device includes a first processor and a second processor; and the reading of the first data from the first memory in the first working condition includes: the first processor sends first information to the second processor, the first information indicating that the reliability requirement of the first data does not satisfy the first condition; the second processor starts an ODT function in response to the first information, and configures the resistance value of the ODT corresponding to the first memory as a first resistance value; and the first processor reads the first data from the first memory.

[0015] In some embodiments, the first processor can be an NPU, a GPU, an audio processing unit (APU), or the like; and the second processor can be a central processor or a microprocessor.

[0016] In some embodiments, after receiving the first information, the second processor can immediately configure in the register corresponding to the ODT, so as to start the ODT function and configure the resistance value of the ODT as the first resistance value.

[0017] In this way, based on the above manner, the ODT can be matched to reduce signal reflection and improve the integrity and reliability of the data when accessing the first data with a higher reliability requirement.

[0018] In a possible implementation of the first aspect, the configuration of the resistance value of the ODT corresponding to the first memory as the first resistance value includes: the second processor obtains the first resistance value corresponding to the first working condition from a first correspondence relationship, where the first correspondence relationship includes a one-to-one correspondence relationship between a plurality of working conditions and a plurality of resistance values, the plurality of working conditions include the first working condition, and the plurality of resistance values include the first resistance value corresponding to the first working condition; and the second processor configures the resistance value of the ODT as the first resistance value.

[0019] In some embodiments, the first correspondence relationship can be a correspondence table storing different working conditions and corresponding specific rated values; or, the first correspondence relationship can also be a function relationship for representing the correspondence relationship between different working conditions and corresponding rated resistance values. The present application does not make any limitation in this regard.

[0020] In a possible implementation of the first aspect, the electronic device includes a first processor and a second processor; and the reading of the second data from the first memory in the first working condition includes: the first processor sending second information to the second processor, the second information indicating that the reliability requirement of the second data meets the first condition; the second processor, in response to the second information, closing the ODT function or configuring the resistance value of the ODT corresponding to the first memory as a second resistance value; and the first processor reading the second data from the first memory.

[0021] In some embodiments, the second information can be an interrupt signal or a notification message.

[0022] In some embodiments, after receiving the second information, the second processor can immediately configure in the register corresponding to the ODT, so as to close the ODT function or open the ODT function and configure the resistance value of the ODT as the second resistance value.

[0023] In this way, based on the above-mentioned manner, the ODT power consumption can be reduced when accessing the second data with a lower reliability requirement, and thus the overall power consumption in the memory access task related system can be saved.

[0024] In a possible implementation of the first aspect, the configuring of the resistance value of the ODT corresponding to the first memory as the second resistance value includes: the second processor obtaining a first resistance value corresponding to the first working condition from a first correspondence relationship, wherein the first correspondence relationship includes a one-to-one correspondence relationship between a plurality of working conditions and a plurality of resistance values, the plurality of working conditions include the first working condition, and the plurality of resistance values include the first resistance value corresponding to the first working condition; and the second processor adjusting the resistance value of the ODT as the second resistance value greater than the first resistance value.

[0025] In some embodiments, since the working voltage of the ODT does not change and the power is "working voltage / resistance 2 ", increasing the resistance value of the ODT can save the power consumption.

[0026] In a possible implementation of the first aspect, the electronic device includes a first processor; and the reading of the first data from the first memory in the first working condition includes: the first processor obtaining the first resistance value corresponding to the first working condition from a first correspondence relationship, where the first correspondence relationship includes a one-to-one correspondence relationship between a plurality of working conditions and a plurality of resistance values, the plurality of working conditions include the first working condition, and the plurality of resistance values include the first resistance value corresponding to the first working condition; the first processor enabling the ODT function and configuring the resistance value of the ODT as the first resistance value; and the first processor reading the first data from the first memory.

[0027] In some embodiments, the first processor for accessing the first data can also be configured directly in the register corresponding to the ODT, so as to enable the ODT function and configure the resistance value of the ODT as the first resistance value. In this way, the interaction process between the first processor and the second processor can be reduced, and thus the resource consumption can be reduced.

[0028] In a possible implementation of the first aspect, the electronic device includes a first processor; and the reading of the second data from the first memory in the first working condition includes: the first processor disabling the ODT function, or configuring the resistance value of the ODT corresponding to the first memory as a second resistance value; and the first processor reading the second data from the first memory. The configuring of the resistance value of the ODT corresponding to the first memory as the second resistance value includes: the first processor obtaining the first resistance value corresponding to the first working condition from a first correspondence relationship, where the first correspondence relationship includes a one-to-one correspondence relationship between a plurality of working conditions and a plurality of resistance values, the plurality of working conditions include the first working condition, and the plurality of resistance values include the first resistance value corresponding to the first working condition; and the first processor adjusting the resistance value of the ODT to the second resistance value greater than the first resistance value.

[0029] In some embodiments, the first processor for accessing the second data can also be configured directly in the register corresponding to the ODT, so as to disable the ODT function, or enable the ODT function and configure the resistance value of the ODT as the second resistance value. In this way, the interaction process between the first processor and the second processor can be reduced, and thus the resource consumption can be reduced.

[0030] In a possible implementation of the first aspect, the method further includes: after the reading of the second data is completed, enabling the ODT function, or adjusting the resistance value of the ODT from the second resistance value to the first resistance value.

[0031] In some embodiments, if the electronic device disables the ODT function when accessing the second data, the electronic device can re-enable the ODT function after the reading of the second data is completed. Or, if the electronic device enables the ODT function and adjusts the resistance value of the ODT to the second resistance value when accessing the second data, the electronic device can re-adjust the resistance value of the ODT to the first resistance value after the reading of the second data is completed.

[0032] In this way, the electronic device can reconfigure the ODT to a working state matching the current working condition of the first chip, so that when subsequent access to other data with higher reliability requirements is performed, impedance can be matched through the ODT to reduce signal reflection and improve signal integrity.

[0033] In a possible implementation of the first aspect, the electronic device includes a first processor and a second processor; and the adjusting the resistance value of the ODT from the second resistance value to the first resistance value after the second data reading is completed includes: the first processor sending third information to the second processor after the second data reading is completed, the third information indicating that the second data reading is completed; and the second processor enabling the ODT function or configuring the resistance value of the ODT corresponding to the first memory to the first resistance value in response to the third information.

[0034] In some embodiments, the third information can be an interrupt signal or a notification message.

[0035] In some embodiments, after receiving the third information, the second processor can immediately configure in the register corresponding to the ODT, so as to enable the ODT function, or enable the ODT function and configure the resistance value of the ODT to the first resistance value.

[0036] In a second aspect, the present application provides an electronic device, including a memory and a processor, the memory being coupled to the processor. The memory is configured to store computer program codes / instructions; and the computer program codes / instructions, when executed by the processor, cause the processor to perform the memory access method mentioned in the present application.

[0037] In a third aspect, the present application provides a readable storage medium, the readable storage medium storing instructions, the instructions, when executed on an electronic device, causing the electronic device to perform the memory access method mentioned in the present application.

[0038] In a fourth aspect, the present application provides a computer program product, including computer instructions, the computer instructions, when executed on a processor, causing the processor to implement the memory access method mentioned in the present application.

[0039] The advantages of the second aspect to the fourth aspect described above can be referred to the related description of the first aspect and various possible implementations, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 According to some embodiments, a structural schematic diagram of reading data from a DDR DRAM by various special-purpose processors is shown;

[0041] Figure 2 According to some embodiments of the present application, a flowchart of a memory access method is shown;

[0042] Figure 3 According to some embodiments of the present application, a structural diagram of adjusting ODT power consumption is shown.

[0043] Figure 4 According to some embodiments of the present application, a flow diagram of adjusting ODT power consumption is shown.

[0044] Figure 5 According to some embodiments of the present application, a flow diagram of another memory access method is shown.

[0045] Figure 6 According to some embodiments of the present application, a hardware structure diagram of an electronic device is shown. DETAILED DESCRIPTION

[0046] The illustrative embodiments of the present application include but are not limited to a memory access method, an electronic device and a storage medium.

[0047] In order to make the purpose, embodiments and advantages of the present application clearer, the embodiments of the present application are described in further detail below.

[0048] It should be noted that the SOC of the electronic device can include at least one IP core, such as various processors including a central processing unit (CPU), a micro processing unit (MPU), a GPU, an NPU, an audio processing unit (APU) or a video processing unit (VPU).

[0049] It should be noted that the off-chip memory of the electronic device can include but is not limited to a DDR DRAM, a low power double data rate (LPDDR), a three-dimensional dynamic random access memory (3DDRAM), a high bandwidth memory (HBM) and the like. The memory access method mentioned in the present application can be introduced below taking the off-chip memory as an example of the DDR DRAM.

[0050] It should be noted that the present application does not limit the scenarios applicable to the data read from the off-chip memory by the IP core. For example, the IP core can read the weight parameters of the operators in the image processing related neural network model, the weight parameters of the operators in the audio processing related neural network model and the like from the off-chip memory.

[0051] As described in the background, the IP core has high power consumption when performing a large number of access operations on an off-chip memory. For ease of understanding, the following describes the source of power consumption in the memory access process, taking the process of reading data from a DDR DRAM by an IP core as an example. Figure 1

[0052] As shown in Figure 1 , in the SOC of an electronic device, the task scheduler inside various processors (which can be represented by XPU, such as NPU, GPU, etc.) can send a DMA request to a direct memory access (DMA) controller according to processing requirements, so as to access the data stored in the DDR DRAM.

[0053] Next, the network-on-chip (NOC) can forward the DMA request initiated by the XPU to the corresponding DDR controller. The NOC is a communication architecture used to connect various components inside the chip and can function as a bus. In addition, the SOC can include multiple DDR controllers, each of which is responsible for managing a DDR physical layer (DDR PHY) and the DDR DRAM connected thereto.

[0054] When the NOC transmits the DMA request to a certain DDR controller, the DDR controller parses the request and sends digital signals such as read commands and address information to the connected DDR PHY. The DDR PHY can convert these digital signals into physical information conforming to the DDR DRAM protocol to successfully read data in the DDR DRAM. For example, the DDR PHY can convert single-ended digital signals into differential signals required by the DDR DRAM, or the DDR PHY can insert an accurate clock signal into the digital signal to match the clock requirements of the DDR DRAM.

[0055] In the process of returning the read data to the XPU, the on-die termination (ODT) in the DDR PHY can be used to match the impedance, thereby reducing signal reflection and ensuring signal integrity. Specifically, in the system shown in Figure 1 , if the characteristic impedance of the signal transmission path between the interface from the DDR DRAM to the DDR PHY does not match the impedance at the end of the DDR PHY, part of the signal energy sent by the DDR DRAM to the XPU will be reflected back to the DDR DRAM, thereby affecting the integrity and reliability of the data read by the XPU. In the system shown in Figure 1 , the ODT in the DDR PHY can be used to match the impedance, thereby reducing signal reflection and ensuring signal integrity.In the system, the ODT function can be turned on and a proper ODT resistance value can be set, so that the characteristic impedance of the signal transmission path between the DDR DRAM and the DDR PHY is matched with the impedance at the end of the DDR PHY, thereby reducing the signal energy transmitted by the DDR DRAM to the XPU that is reflected when reaching the DDR PHY. The less the signal energy reflected back, the more complete the signal energy transmitted to the XPU. That is, the less the signal energy reflected back, the higher the integrity and reliability of the data read by the XPU.

[0056] The characteristic impedance of the signal transmission path is related to the working conditions of the internal device (e.g., SOC) of the electronic device, such as the working temperature and the working voltage, and the ODT resistance value is also related to the working conditions of the internal device (e.g., SOC) of the electronic device, such as the working temperature and the working voltage. For example, the manufacturer can pre-store a corresponding table of the corresponding relationship between the resistance value of the current model ODT and the working conditions (e.g., the working temperature range and / or the working voltage range) of the SOC in the document information. During the operation of the electronic device, the electronic device can find the corresponding ODT resistance value in the corresponding table based on the current SOC working condition every certain period of time, and configure the ODT resistance value accordingly, so that the ODT resistance value can be matched with the current working temperature and working voltage.

[0057] However, although the ODT can ensure data integrity when working, it will generate a large power consumption, resulting in a high overall power consumption of the memory access task. Moreover, with the increase in the number of DDR channels (e.g., the channel formed by the DDR controller, the DDR PHY, and the corresponding DDR DRAM in the above embodiment), Figure 1 The power consumption accumulated by multiple ODTs can even reach 200 mw. In particular, when the working rate of the input / output interface of the DDR DRAM is low (e.g., lower than 3200 MT / S), the proportion of the power consumption (e.g., 60 mw) generated by the ODT in the small overall power consumption (e.g., 100 mw) generated by the memory access task related system is higher.

[0058] It can be understood that, due to the feedback correction mechanism of the multi-layer neural network layer in part of the algorithms / models, the existence of some non-key weight parameters in a large number of weight parameters in part of the neural network models, and the certain fault tolerance of part of the algorithms / models (e.g., recommendation system), the reliability requirement for part of the data is low during the execution of the task by the XPU.

[0059] For example, for some weight parameters in a large-scale neural network model task, when the XPU reads the weight parameters in the DDR DRAM, even if the signal energy sent by the DDR DRAM to the XPU is reflected when it reaches the DDR PHY, causing the data transmitted to the XPU to be incomplete and biased, the feedback mechanism of the neural network layer can correct this bias without affecting the final result. It can be seen that during the execution of the task, the XPU may exist in a case where the reliability requirement for the weight parameters in the neural network model operator is low.

[0060] It should be noted that the neural network model mentioned in the present application can include but is not limited to: an image processing neural network model, which can be used for image classification, target detection, or face recognition, etc. on input image data; a natural language neural network model, which can be used for speech recognition, voice interaction, etc. on input audio data; a recommendation system neural network model, which can be used for related content recommendation on user input keywords, or for personalized recommendation based on user's historical use records; a traffic prediction neural network model, which can be used for path planning on input real-time traffic flow, road topology, etc. In addition to the above, the neural network model mentioned in the present application can also include a financial risk assessment neural network model, a medical diagnosis neural network model, or an autonomous driving neural network model, etc. The type and application scenario of the neural network model are not limited in the present application.

[0061] It can be understood that any type of neural network model can be a complex structure composed of multiple operators, which define the specific operation logic in the neural network model and are the basic elements of the neural network model. In addition, the weight parameter is a learnable variable in the operator, which can be used to realize the function of the operator or the transmission strength between different operators.

[0062] Exemplarily, the operators of the neural network model and the corresponding weight parameters can include, but are not limited to, any one of the following: a convolution operator, which can be used to extract local features such as image edges, textures, etc., wherein the weight parameters of a standard convolution operator can include a convolution kernel or a bias term, etc., and the weight parameters of a deformable convolution operator can further include a convolution kernel, a bias term or an offset, etc.; a batch normalization operator, which can be used to normalize the input of a network layer to alleviate the problem of internal covariate shift, wherein the weight parameters of the batch normalization operator can include a scaling parameter and a translation parameter; a fully connected operator, which can be used to connect all neurons of a previous layer to all neurons of a current layer to realize global feature integration, wherein the weight parameters in the fully connected operator can include a weight matrix or a bias vector, etc.; a recurrent operator, which can be used to capture the temporal dependence in a sequence through recursive calculation, wherein the weight parameters of the recurrent operator can include a linear transformation matrix, a recurrent transformation matrix or a bias vector, etc. In addition, the neural network model operators mentioned in the present application can also include an attention operator, etc., and the weight parameters in the operators can also be the weight parameters in the attention operator, etc., which are not limited in the present application.

[0063] Therefore, the present application provides a memory access method. In the method, the electronic device can configure the ODT function (for example, turn on / off the ODT function, configure different resistance values for the ODT, etc.) corresponding to the first memory in different ways based on whether the data to be accessed in the first memory meets the first condition (the first condition indicates the reliability requirement of the data).

[0064] For example, in the case that the first data to be accessed does not meet the first condition (indicating that the reliability requirement of the data to be accessed is higher), the electronic device can turn on the ODT function corresponding to the first memory; in the case that the second data to be accessed meets the first condition (indicating that the reliability requirement of the data to be accessed is lower), the electronic device can turn off the ODT function corresponding to the first memory.

[0065] For another example, in the case that the first data to be accessed does not meet the first condition, the electronic device can turn on the ODT function corresponding to the first memory and configure the resistance value of the ODT corresponding to the first memory as the rated resistance value in the first working condition; in the case that the second data to be accessed meets the first condition, the electronic device can turn on the ODT function corresponding to the first memory and configure the resistance value of the ODT corresponding to the first memory to be greater than the rated resistance value in the first working condition.

[0066] Based on the above method, the ODT impedance can be matched when accessing data with high reliability requirement to reduce signal reflection and improve data integrity and reliability, and the ODT power consumption can be reduced when accessing data with low reliability requirement, thereby saving the overall power consumption in the system related to the memory access task.

[0067] The first working condition can be used to indicate at least one of that the working temperature of the first chip (e.g., SOC) where the ODT is located is in the first temperature range or that the working voltage of the first chip is in the first working voltage. The first resistance value can be a rated resistance value corresponding to the ODT of the first chip in the first working condition.

[0068] It should be noted that the rated resistance value can be an experimental value or an empirical value. For example, after the developer determines different rated resistance values corresponding to the ODT of the first chip in different working conditions through experiments or experience, the one-to-one correspondence between the different rated resistance values and the corresponding working conditions can be stored in the electronic device in various ways. For example, the different working conditions and the corresponding specific rated values are directly stored in the electronic device; for another example, a functional relationship between the different working conditions and the corresponding rated resistance values is stored in the electronic device. The present application does not limit this.

[0069] It should be noted that the rated resistance value is related to at least one of the working temperature or the working voltage in the working condition. Therefore, the one-to-one correspondence between the working temperature in the different working conditions and the corresponding rated resistance value, or the one-to-one correspondence between the working voltage in the different working conditions and the corresponding rated resistance value, or the one-to-one correspondence between the working voltage and the working temperature in the different working conditions and the corresponding rated resistance value can be stored in the electronic device. The present application does not limit this.

[0070] Based on the above, in a case where the first data to be accessed does not satisfy the first condition, the electronic device can detect that the first chip is in the first working condition (e.g., the working voltage is in the first voltage range and the working temperature is in the first temperature range). Then, the electronic device can obtain the first resistance value of the ODT corresponding to the first working condition in the first correspondence relationship having a plurality of one-to-one correspondences, and adjust the resistance value of the ODT to the first resistance value. For example, the first resistance value is found in the correspondence table (as an example of the first correspondence relationship), or the first resistance value is calculated through the functional relationship (as another example of the first correspondence relationship). It can be understood that the first correspondence relationship includes the one-to-one correspondence between the plurality of working conditions (including the first working condition) mentioned above and the plurality of rated resistance values (including the first resistance value corresponding to the first working condition).

[0071] Alternatively, in a case where the second data to be accessed satisfies the first condition, the electronic device can detect that the first chip is in the first working condition (e.g., the working voltage is in the first voltage range and the working temperature is in the first temperature range). Then, the electronic device can obtain the first resistance value of the ODT corresponding to the first working condition in the first correspondence relationship having a plurality of one-to-one correspondences, and adjust the resistance value of the ODT to the second resistance value greater than the first resistance value.

[0072] It can be understood that when accessing data with low reliability requirement, the working voltage of ODT does not change and the power is "working voltage / resistance 2 ", so configuring the actual resistance value of ODT to a second resistance value greater than the first resistance value will also reduce the power consumption generated by ODT.

[0073] Therefore, based on the above method, when accessing data with low reliability requirement, the electronic device can reduce the power consumption of ODT and further save the overall power consumption in the memory access task related system by turning off the ODT function or increasing the ODT resistance value.

[0074] In other embodiments, when the electronic device detects that the second data reading is complete, the electronic device can also adjust the ODT to a working state matched with the first working condition to avoid subsequent access to other data with high reliability requirement. For example, when accessing the above-mentioned second data with low reliability requirement, if the ODT function is turned off, the electronic device can turn on the ODT function after the second data reading is complete. Alternatively, when accessing the above-mentioned second data with low reliability requirement, if the resistance value of ODT is adjusted to a second resistance value greater than the first resistance value, the electronic device can also adjust the resistance value of ODT from the second resistance value to the first resistance value after the second data reading is complete.

[0075] It can be understood that the above-mentioned memory access method of the present application can be applied to any electronic device. The electronic device includes but is not limited to a mobile station (MS), a mobile terminal (MT), etc. For example, the electronic device can be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a desktop computer, a laptop computer, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in self driving, a terminal in remote medical surgery, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, etc. The specific form of the electronic device is not limited in the embodiments of the present application.

[0076] The memory access method mentioned in the embodiments of the present application will be briefly introduced below based on the flowchart shown in Figure 2 . The memory access method can be applied to an electronic device, such as any electronic device mentioned above, such as a computer.Figure 2 As shown, specifically, the method is as follows:

[0077] S201: detecting a first data access request, wherein the first data access request is used to access first data in a first memory of the electronic device, and a reliability requirement of the first data does not satisfy a first condition.

[0078] In some embodiments, the first memory can include, but is not limited to, DDR DRAM, LPDDR, 3D DRAM, or HBM, etc. The first data access request can be a DMA request.

[0079] In some embodiments, the first condition can be used to indicate the reliability requirement of the data. For example, the first condition can include: the type of the data is a preset type (such as the weight parameter of the operator in the neural network model), or the storage area of the data in the first memory is a preset storage area. For example, the electronic device has a lower reliability requirement for the weight parameter of the operator in the neural network model; or the electronic device can also store data with a lower reliability requirement (such as the weight parameter) in a preset storage area.

[0080] Therefore, the reliability requirement of the first data does not satisfy the first condition, which can represent that the type of the first data is not a preset type, or that the storage area of the first data in the first memory is not a preset storage area. That is, the electronic device has a higher reliability requirement for the first data. For example, the first data can be input data of a neural network model, such as image data required by the GPU when running an image processing neural network model, audio data required by the GPU when running a natural language neural network model, etc.; for another example, the first data can also be a configuration file required by the electronic device when running an application, for example, the configuration file can include gateway information, server information, or log records, etc.; for another example, the first data can also be an encryption key or an integer required by the electronic device when performing an encryption task. The type of the first data is not limited in the present application.

[0081] In some embodiments, as shown, Figure 3 As shown, taking the first memory as DDR DRAM and the first data access request as a DMA request as an example, the process of memory access is exemplarily introduced. In Figure 3 When a processor (which can be represented by XPU, such as NPU, GPU, etc.) needs to access the first data when performing a task, the DMA controller in the XPU can detect the DMA request sent by the task scheduler for accessing the first data, and transmit the DMA request to the DDR DRAM in turn via the NOC bus, the DDR controller and the DDR PHY, so as to read the first data in the DDR DRAM.

[0082] S202: reading first data from the first memory in the first working condition. Wherein, the ODT function corresponding to the first memory is enabled, and the resistance value of the ODT corresponding to the first memory is the first resistance value.

[0083] In some embodiments, the first working condition is used to indicate at least one of that the working temperature of the first chip (e.g., SOC) where the ODT is located is in the first temperature interval or that the working voltage of the first chip is in the first voltage interval. For example, the electronic device can read the working voltage monitored by the power management unit integrated in the SOC, or can also read the working temperature monitored by the on-chip temperature sensor integrated in the SOC. Wherein, the first chip can be the SOC.

[0084] In some embodiments, as shown in Figure 3 The XPU (as an example of the first processor) can also send the first information (e.g., an interrupt signal or a notification message) to the MCU or CPU (as an example of the second processor) for indicating that the reliability requirement of the first data does not meet the first condition. Then, the second processor can enable the ODT function and configure the resistance value of the ODT as the first resistance value in response to the first information. For example, the second processor can detect that the first chip where the ODT is located is in the first working condition, and obtain the first resistance value corresponding to the first working condition from the first correspondence relationship (e.g., a correspondence table or a function relationship). Then, the second processor configures the resistance value of the ODT in the register to configure the resistance value of the ODT as the first resistance value. Finally, after the ODT function is enabled and the resistance value of the ODT is configured as the first resistance value, the XPU can read the first data from the first memory (e.g., DDR SDRAM).

[0085] Wherein, the task of the second processor for configuring the resistance value of the ODT in the register can be executed in parallel with the memory access task performed by the NOC, the DDR controller and the DDR PHY in the memory access process.

[0086] It can be understood that, in the example shown in Figure 3 In some embodiments, the ODT function is configured by the CPU. In other embodiments, the ODT function can also be configured by the XPU accessing the first data. Specifically, the XPU can detect that the first chip where the ODT is located is in the first working condition, and obtain the first resistance value corresponding to the first working condition from the first correspondence relationship. Then, the XPU configures the related data of the ODT in the register to enable the ODT function and configure the resistance value of the ODT as the first resistance value. Finally, after the ODT function is enabled and the resistance value of the ODT is configured as the first resistance value, the XPU can read the first data from the first memory (e.g., DDR SDRAM). In this way, the interaction process between the XPU and the CPU can be reduced, and thus the resource consumption can be reduced.

[0087] Thus, based on the above configuration process, in the process of returning the first data read from the DDR DRAM to the XPU, the impedance can be matched by the first resistance value of the ODT in the DDR PHY, so as to reduce the reflection of the signal energy transmitted by the DDR DRAM to the XPU when reaching the DDR PHY, and ensure the integrity and reliability of the first data received by the XPU.

[0088] S203: A second data access request is detected, wherein the second data access request is used to access second data in the first memory, and the reliability requirement of the second data meets a first condition.

[0089] In some embodiments, the second data access request can be a DMA request.

[0090] In some embodiments, the reliability requirement of the second data meeting the first condition can mean that the type of the second data is a preset type (such as the weight parameter of the operator in the neural network model), or the storage area of the second data in the first memory is a preset storage area. That is, the reliability requirement of the electronic device for the second data is low. For example, the second data can be the weight parameter of the convolution operator, the weight parameter of the activation function operator, the weight parameter of the full connection operator, etc. in the neural network model (such as an image processing neural network model, a natural language neural network model, etc.).

[0091] In some embodiments, as described above Figure 3 When a certain processor (which can be represented by XPU, such as NPU, GPU, etc.) needs to access the second data when performing a task, the DMA controller in the XPU can detect the DMA request sent by the task scheduler for accessing the second data, and transmit the DMA request to the DDR DRAM in turn via the NOC bus, the DDR controller and the DDR PHY, so as to read the second data in the DDR DRAM.

[0092] S204: In the first working condition, the second data is read from the first memory, wherein the ODT function corresponding to the first memory is closed, or the ODT function corresponding to the first memory is opened and the resistance value of the ODT is a second resistance value, and the second resistance value is greater than the first resistance value.

[0093] It is understood that the present application does not specifically limit the magnitude of the second resistance. For example, the second resistance may be N times the first resistance (N>1 and N is a preset multiple); for another example, the second resistance may be the first resistance plus a preset value (e.g., 5Ω, 10Ω, etc.); for another example, the second resistance may be the maximum resistance that the ODT can support adjustment; for another example, the second resistance may be a rated resistance corresponding to other operating conditions (greater than the first resistance). For example, if the first correspondence with multiple one-to-one correspondences is a correspondence table, after the electronic device obtains the first resistance corresponding to the first operating condition in the correspondence table, the electronic device may also directly search the correspondence table for any rated resistance greater than the first resistance as the second resistance.

[0094] In some embodiments, as Figure 3 As shown, the task scheduler in the XPU (as an example of the first processor) can also report the second information (such as an interrupt signal or notification information) to the CPU or MPU (as an example of the second processor) of the electronic device. The second processor can turn off the ODT function or control the resistance of the ODT to be configured as a second resistance in response to the received second information. For example, the second processor can detect that the first chip (such as SOC) where the ODT is located is in a first operating condition, and obtain the first resistance corresponding to the first operating condition from a first corresponding relationship (such as a corresponding table or a functional relationship). Then, the second processor configures the resistance of the ODT in a register to configure the resistance of the ODT to a second resistance greater than the first resistance. Finally, after the ODT function is turned off or the resistance of the ODT is configured to the second resistance, the XPU can read the second data from the first memory (such as DDRSDRAM).

[0095] The task of configuring the ODT-related data in the register of the second processor and the memory access task performed by the NOC, the DDR controller and the DDRPHY during the memory access process may be executed in parallel.

[0096] Understandably, Figure 3In the illustrated example, the ODT function is configured by the CPU. In other embodiments, the ODT function can also be configured by the XPU by accessing the second data. Specifically, the XPU can directly configure the relevant data of the ODT in the register to turn off the ODT function or configure the resistance of the ODT to the second resistance. For example, the XPU can detect that the first chip where the ODT is located is in the first working condition, and obtain the first resistance corresponding to the first working condition from the first correspondence relationship. Then, the XPU configures the relevant data of the ODT in the register to turn on the ODT function and configure the resistance of the ODT to the second resistance. Finally, after the ODT function is turned off or the resistance of the ODT is configured to the second resistance, the XPU can read the second data from the first memory (such as DDR SDRAM). In this way, the interaction process between the XPU and the CPU can be reduced, and thus the resource consumption can be reduced.

[0097] In this way, through the above configuration process, when the DDR DRAM transmits the second data to the DDR PHY, the ODT function is already turned off or the resistance of the ODT is already adjusted to the second resistance, and thus the low ODT power consumption can be achieved.

[0098] In this way, based on the above method, when accessing data with high reliability requirement, the ODT can match the impedance to reduce signal reflection and improve data integrity and reliability; and when accessing data with low reliability requirement, the ODT power consumption can be reduced, and thus the overall power consumption of the system related to the memory access task can be saved.

[0099] The above method will be described below with reference to the memory access system shown in Figure 3 The memory access system shown in Figure 4 The process of reducing the ODT power consumption will be described in detail with reference to the flowchart shown in Figure 4 The method includes the following steps.

[0100] S401: The task scheduler of the XPU sends a second data access request to the DMA controller, and sends second information to the CPU, where the second information is used to indicate that the reliability requirement of the second data satisfies a first condition.

[0101] In some embodiments, the second data access request can be a DMA request; and the second information can be an interrupt signal or a notification message.

[0102] In some embodiments, the task scheduler inside the XPU can distinguish the task types. For example, the task types can include a model parameter reading task, an input data reading task, etc., where the model parameter reading task can be used to read the weight parameters of the operators in the neural network model, and the input data reading task can be used to read the input data of the operators in the neural network model. When the task scheduler determines that the model parameter reading task is currently being executed (e.g., by parsing the data packet header or protocol field in the second data access request to identify the task type), the task scheduler of the XPU can send the second information to the CPU.

[0103] S402: After the CPU receives the second information, the ODT resistance value is increased or the ODT function is turned off based on the configuration of the DDR PHY register.

[0104] In some embodiments, the CPU can configure the related data of the ODT in the register corresponding to the ODT (e.g., the register in the DDR PHY), so as to turn off the ODT function or control the ODT resistance value to increase to the second resistance value. For details, refer to S204 in the above Figure 2 .

[0105] In this way, through the above S401 and S402, in the case where the reliability requirement of the XPU for the second data to be accessed is low, the electronic device can reduce the power consumption of the ODT, thereby saving the overall power consumption in the memory access task related system.

[0106] S403: The task scheduler of the XPU sends third information to the CPU after the second data reading is completed, where the third information is used to indicate that the second data reading is completed.

[0107] In some embodiments, the third information can be an interrupt signal or a notification message.

[0108] In some embodiments, when the DMA controller transmits all the second data to the task scheduler of the XPU, the DMA controller can send a notification to the task scheduler of the XPU that the second data reading is completed. Then, the task scheduler of the XPU can send the third information to the MPU or the CPU (as an example of the second processor) after the second data reading is completed.

[0109] S404: After the CPU receives the third information, the ODT resistance value is restored or the ODT function is turned on based on the configuration of the DDR PHY register.

[0110] In some embodiments, if the operation performed in S402 is to turn off the ODT function, after the CPU receives the third information, the CPU can configure the relevant data of the ODT in the register corresponding to the ODT, thereby turning on the ODT function. Alternatively, if the operation performed in S402 is to increase the resistance value of the ODT, after the CPU receives the third information, the CPU can configure the relevant data of the ODT in the register corresponding to the ODT, thereby reducing the resistance value of the ODT from the second resistance value to the first resistance value.

[0111] In other embodiments, after receiving the third information, the CPU can also detect the current working condition of the first chip again. Then, the CPU can find the third resistance value of the ODT corresponding to the current working condition in the first correspondence relationship, and configure the resistance value of the ODT as the third resistance value. The present application does not limit this.

[0112] In this way, based on S403 to S404, the electronic device can also reconfigure the ODT to a working state matching the current working condition of the first chip after accessing the second data, so that when subsequently accessing other data with higher reliability requirements, the impedance can be matched through the ODT to reduce signal reflection and improve signal integrity.

[0113] The following will be described in conjunction with Figure 5 the embodiments shown in the drawings. The method can be applied to electronic devices, such as the computer mentioned above and any electronic device. As shown in Figure 5 the drawings, specifically, the method is as follows:

[0114] S501: A data access request is detected, and the data access request is used to access data in a first memory.

[0115] In some embodiments, the data access request can be a DMA request; the first memory can include but is not limited to DDR DRAM, LPDDR, 3D DRAM, or HBM, etc.

[0116] S5021: In the case where the reliability requirement of the data accessed by the data access request does not meet the first condition, the ODT function is turned on and the ODT resistance value is configured as the rated resistance value corresponding to the current working condition.

[0117] In some embodiments, the first condition can be used to indicate the reliability requirement of the data. When the reliability requirement of the data that the electronic device needs to access does not meet the first condition, it means that the electronic device has a higher reliability requirement for the data.

[0118] In some embodiments, when the electronic device accesses data with higher reliability requirements, the electronic device can obtain the rated resistance value of ODT corresponding to the current working condition in the first correspondence relationship (such as a correspondence table or a function relationship) with multiple one-to-one correspondence relationships, and configure the resistance value of ODT as the rated resistance value corresponding to the current working condition. For details, please refer to S201 and S202 in Figure 2 .

[0119] S5022: reading data whose reliability requirements do not meet the first condition from the first memory.

[0120] In this way, based on the configuration process of S502 described above, in the process of returning the data with higher reliability requirements read from the DDR DRAM to the XPU, the impedance can be matched through the ODT in the DDR PHY, thereby reducing signal reflection and improving data integrity and reliability.

[0121] S5031: in the case where the reliability requirements of the data accessed by the data access request meet the first condition, turning off the ODT function, or turning on the ODT function and configuring the ODT resistance value to be greater than the rated resistance value corresponding to the current working condition.

[0122] In some embodiments, when the reliability requirements of the data accessed by the electronic device meet the first condition, it means that the electronic device has lower reliability requirements for the data.

[0123] In some embodiments, when the electronic device accesses data with lower reliability requirements, the electronic device can directly turn off the ODT function to save ODT power consumption. Alternatively, the electronic device can obtain the rated resistance value of ODT corresponding to the current working condition in the first correspondence relationship (such as a correspondence table or a function relationship) with multiple one-to-one correspondence relationships, turn on the ODT function, and configure the resistance value of ODT to be greater than the rated resistance value under the current working condition. For details, please refer to S203 and S204 in Figure 2 .

[0124] S5032: reading data whose reliability requirements meet the first condition from the first memory.

[0125] In this way, through the configuration process of S5031 described above, when the DDR DRAM transmits data with lower reliability requirements to the DDR PHY, the ODT function is already in the off state or the ODT resistance value has been increased, thereby reducing the low ODT power consumption.

[0126] S5033: after the reading of the data whose reliability requirements meet the first condition is completed, turning on the ODT function, or configuring the ODT resistance value to be the rated resistance value corresponding to the current working condition.

[0127] In some embodiments, if the electronic device turns off the ODT function when accessing the data whose reliability requirement meets the first condition, the electronic device can turn on the ODT function again after the data reading is completed. Or, if the electronic device turns on the ODT function and configures the ODT resistance value to be greater than the rated resistance value corresponding to the current working condition when accessing the data whose reliability requirement meets the first condition, the electronic device can reconfigure the ODT resistance value to be the rated resistance value corresponding to the current working condition after the data reading is completed. For details, refer to S403 and S404 in the above Figure 4 .

[0128] In this way, based on the above S5033, the electronic device can also reconfigure the ODT to the working state matched with the current working condition after accessing the data with lower reliability requirement, so that when accessing other data with higher reliability requirement subsequently, the impedance can be matched through the ODT to reduce signal reflection and improve signal integrity.

[0129] In some embodiments, the present application also provides a readable storage medium. The readable storage medium stores instructions. When the instructions are executed on an electronic device, the electronic device performs the memory access method mentioned in the present application.

[0130] In some other embodiments, the present application also provides a computer program product. The computer program product includes computer instructions. When the computer instructions are executed on a processor, the processor implements the memory access method mentioned in the present application.

[0131] In some other embodiments, the present application also provides an electronic device. The electronic device includes a memory and a processor. The memory is coupled to the processor. The memory is configured to store computer program codes / instructions. When the computer program codes / instructions are executed by the processor, the processor implements the memory access method mentioned in the present application.

[0132] As shown in Figure 6 , an example of the hardware structure of the electronic device 1200 is illustrated. As shown in Figure 6 , the electronic device 1200 can include one or more processors 1202, a system control logic unit 1201 connected to at least one of the processors 1202, a system memory 1205 connected to the system control logic unit 1201, a memory 1203 connected to the system control logic unit 1201, and a network interface 1207 connected to the system control logic unit 1201.

[0133] It can be understood that the structure shown in the embodiments of the present application does not constitute a unique realizable manner of the electronic device 1200. In other embodiments of the present application, the electronic device 1200 can include more or fewer components than shown, or combine certain components, or split certain components, or different arrangement of components. The components shown can be realized in hardware, software or a combination of software and hardware.

[0134] The processor 1202 can include one or more single-core or multi-core processors. In some embodiments, the processor 1202 can include any combination of general-purpose processors and special-purpose processors (e.g., application processors, baseband processors, etc.). For example, the processor 1202 can include, but is not limited to, CPUs, NPUs, and GPUs, etc. It can be understood that in the embodiments of the present application, the processor 1202 can be configured to execute executable instructions 1204 stored in the memory 1203 to implement the memory access method of the embodiments of the present application. When at least one of the processors 1202 executes the instructions, the electronic device 1200 implements the memory access method of the embodiments of the present application.

[0135] The system control logic unit 1201 can include any suitable interface controllers to provide any suitable interface to at least one of the processors 1202 and / or any suitable device or component in communication with the system control logic unit 1201. The system control logic unit 1201 can include one or more memory controllers to provide an interface to the system memory 1205. The system memory 1205 can be used to load and store data and / or instructions. In some embodiments, the system memory 1205 of the electronic device 1200 can include any suitable volatile memory, such as suitable dynamic random access memory.

[0136] The memory 1203 can include one or more tangible, non-transitory computer-readable media used to store data and / or instructions. In some embodiments, the memory 1203 can include any suitable volatile memory and / or any suitable non-volatile storage device. For example, the memory 1203 can include random access memory (RAM), cache memory, and / or read-only memory (ROM). For example, the memory can include, but is not limited to, DDR DRAM, LPDDR, 3D DRAM, or HBM, etc.

[0137] The memory 1203 can include a portion of the storage resources installed on the device of the electronic device 1200, or it can be accessed by the device, but not necessarily part of the device. For example, the memory 1203 can be accessed via the network interface 1207 through the network.

[0138] In particular, system memory 1205 and memory 1203 can include temporary and permanent copies of instructions 1204, respectively. Instructions 1204 can include those that, when executed by at least one of processors 1202, cause electronic device 1200 to implement the memory access methods of embodiments of the present application. In some embodiments, instructions 1204, hardware, firmware, and / or software components thereof can additionally / alternatively be located in system control logic 1201, network interface 1207, and / or processors 1202.

[0139] Network interface 1207 can include a transceiver to provide a radio interface for electronic device 1200 to communicate with any other suitable device (e.g., front end modules, antennas, etc.) over one or more networks. In some embodiments, network interface 1207 can be integrated with other components of electronic device 1200. For example, network interface 1207 can be integrated with at least one of processors 1202, system memory 1205, memory 1203, and firmware devices (not shown) having instructions.

[0140] Network interface 1207 can further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, network interface 1207 can be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.

[0141] Electronic device 1200 can further include input / output (I / O) device 1206. Input / output device 1206 can include a user interface to enable a user to interact with electronic device 1200 and a peripheral component interface to enable peripheral components to interact with electronic device 1200. In some embodiments, electronic device 1200 also includes sensors to determine at least one of environmental conditions and location information related to electronic device 1200.

[0142] In some embodiments, the user interface can include, without limitation, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., still and / or video cameras), a flashlight (e.g., a light emitting diode flash), and a keypad.

[0143] In some embodiments, the peripheral component interface can include, without limitation, a non-volatile memory port, an audio jack, and a power interface.

[0144] In some embodiments, the sensors can include, but are not limited to, a gyroscope sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit can also be part of or interact with the network interface 1207 to communicate with components of a positioning network (e.g., global positioning system (GPS) satellites).

[0145] Embodiments disclosed herein can be implemented in hardware, software, firmware, or combinations thereof. Embodiments of the application can be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0146] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as a digital signal processor, microcontroller, a programmable logic device or microprocessor.

[0147] Program code can be implemented in a high level procedural or object oriented programming language to communicate with a processing system. Program code can be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0148] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) medium, which can be read and executed by one or more processors. For example, the instructions can be distributed over the network or by other computer readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including without limitation, a floppy disk, an optical disc, an optical compact disc, a magnetic optical disc, read-only memory (ROM), random access memory (RAM), a magnetic or optical card, or a tangible, machine-readable storage medium. Accordingly, a machine-readable medium includes any medium that is capable of storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0149] In the drawings, some of the structures or method features can be shown in particular arrangements and / or orders. However, it should be understood that such specific arrangements and / or orders can not be required. Instead, these features can be arranged in a different manner and / or order than shown in the illustrative drawings, in some embodiments. Additionally, inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments, and in some embodiments, such feature can not be included or can be combined with other features.

[0150] It should be noted that each unit / module mentioned in the embodiments of the devices of the present application is a logical unit / module, and in physical aspect, one logical unit / module can be one physical unit / module, or a part of a physical unit / module, or be realized in a combination of multiple physical unit / modules, and the physical realization of these logical units / modules is not the most important, and the combination of the functions realized by these logical units / modules is the key to solve the technical problems proposed in the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned embodiments of the devices of the present application do not introduce the units / modules which are not closely related to solving the technical problems proposed in the present application, which does not mean that there are no other units / modules in the above-mentioned embodiments of the devices.

[0151] It should be noted that in the examples and descriptions of the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0152] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the present application.

Claims

1. A memory access method, applied to an electronic device, characterized in that: The method comprises: detecting a first data access request, where the first data access request is for accessing first data in a first memory of the electronic device, and a reliability requirement of the first data does not meet a first condition; Under a first operating condition, the first data is read from the first memory, wherein an ODT function corresponding to the first memory is enabled, and a resistance value of the ODT corresponding to the first memory is a first resistance value, and the first operating condition indicates at least one of an operating temperature of a first chip where the ODT is located is within a first temperature range or an operating voltage of the first chip is within a first voltage range; detecting a second data access request, where the second data access request is for accessing second data in the first memory, and a reliability requirement of the second data meets the first condition; Under the first working condition, the second data is read from the first memory, wherein the ODT function corresponding to the first memory is turned off, or the ODT function corresponding to the first memory is turned on and the resistance of the ODT is a second resistance, and the second resistance is greater than the first resistance.

2. The method according to claim 1, characterized in that The first condition includes: the type of data is a preset type, and the storage area of ​​the data in the first memory is a preset storage area, wherein the preset type includes the weight parameters of the operator in the neural network model.

3. The method according to claim 2, characterized in that The reliability requirement of the first data does not meet the first condition, including: the type of the first data is not the preset type, or the storage area of ​​the first data in the first memory is not the preset storage area; The reliability requirement of the second data meets the first condition, including: the type of the second data is the preset type, or the storage area of ​​the second data in the first memory is the preset storage area.

4. The method according to claim 1, wherein The electronic device includes a first processor and a second processor; And the reading of the first data from the first memory under the first working condition includes: The first processor sends first information to the second processor, where the first information indicates that a reliability requirement of the first data does not meet the first condition; The second processor enables the ODT function in response to the first information, and configures the ODT resistance corresponding to the first memory to the first resistance; The first processor reads the first data from the first memory.

5. The method according to claim 4, characterized in that The step of configuring the resistance value of the ODT corresponding to the first memory to be the first resistance value includes: The second processor obtains the first resistance value corresponding to the first operating condition from a first corresponding relationship, wherein the first corresponding relationship includes a one-to-one correspondence between multiple operating conditions and multiple resistance values, the multiple operating conditions include the first operating condition, and the multiple resistance values ​​include the first resistance value corresponding to the first operating condition; The second processor configures the resistance value of the ODT to be the first resistance value.

6. The method according to claim 1, characterized in that The electronic device includes a first processor and a second processor; And the reading of the second data from the first memory under the first working condition includes: The first processor sends second information to the second processor, where the second information indicates that a reliability requirement of the second data satisfies the first condition; The second processor disables the ODT function or configures the resistance value of the ODT corresponding to the first memory to the second resistance value in response to the second information; The first processor reads the second data from the first memory.

7. The method according to claim 6, characterized in that The configuring the resistance value of the ODT corresponding to the first memory to the second resistance value includes: The second processor obtains the first resistance value corresponding to the first operating condition from a first corresponding relationship, wherein the first corresponding relationship includes a one-to-one correspondence between multiple operating conditions and multiple resistance values, the multiple operating conditions include the first operating condition, and the multiple resistance values ​​include the first resistance value corresponding to the first operating condition; The second processor adjusts the resistance of the ODT to a second resistance greater than the first resistance.

8. The method according to claim 1, characterized in that The electronic device includes a first processor; and, in the first operating condition, reading the first data from the first memory includes: The first processor obtains the first resistance value corresponding to the first operating condition from a first corresponding relationship, wherein the first corresponding relationship includes a one-to-one correspondence between multiple operating conditions and multiple resistance values, the multiple operating conditions include the first operating condition, and the multiple resistance values ​​include the first resistance value corresponding to the first operating condition; The first processor enables the ODT function and configures the resistance value of the ODT to be the first resistance value; The first processor reads the first data from the first memory.

9. The method according to claim 1, characterized in that The electronic device includes a first processor; and, under the first operating condition, reading the second data from the first memory includes: The first processor turns off the ODT function, or configures the ODT resistance value corresponding to the first memory to the second resistance value; The first processor reads the second data from the first memory; The step of configuring the resistance value of the ODT corresponding to the first memory to the second resistance value includes: The first processor obtains the first resistance value corresponding to the first operating condition from a first corresponding relationship, wherein the first corresponding relationship includes a one-to-one correspondence between multiple operating conditions and multiple resistance values, the multiple operating conditions include the first operating condition, and the multiple resistance values ​​include the first resistance value corresponding to the first operating condition; The first processor adjusts the resistance of the ODT to a second resistance greater than the first resistance.

10. The method according to any one of claims 1 to 9, characterized in that The method further comprises: After the second data is read, the ODT function is enabled, or the resistance value of the ODT is adjusted from the second resistance value to the first resistance value.

11. The method according to claim 10, characterized in that The electronic device includes a first processor and a second processor; and after the second data is read, adjusting the resistance of the ODT from the second resistance to the first resistance includes: The first processor sends third information to the second processor after the second data reading is completed, wherein the third information indicates that the second data reading is completed; The second processor enables the ODT function or configures the ODT resistance corresponding to the first memory to the first resistance in response to the third information.

12. An electronic device, characterized in that: include: A memory and a processor, wherein the memory is coupled to the processor; the memory is used to store computer program code / instructions; when the computer program code / instructions are executed by the processor, the processor implements the memory access method according to any one of claims 1 to 11.

13. A readable storage medium, characterized in that: The readable storage medium stores instructions, which, when executed on an electronic device, enable the electronic device to execute the memory access method according to any one of claims 1 to 11.

14. A computer program product, characterized in that include: A computer instruction, when the computer instruction is executed on a processor, causes the processor to implement the memory access method according to any one of claims 1 to 11.

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