Half-bridge power module structure

Abstract

The invention provides a half-bridge power module structure. The half-bridge power module structure comprises a first surface and a second surface which are oppositely arranged, the terminal area is located on the second surface; the terminal area comprises a power terminal area and a signal terminal area; a chip layer and a wiring layer are arranged in the half-bridge power module structure, and the chip layer comprises an upper power chip and a lower power chip; the power terminal area comprises a first power terminal, a second power terminal and a third power terminal; the signal terminal area comprises a first signal terminal and a second signal terminal; the heat dissipation layer is located between the chip layer and the first surface or arranged on the first surface; an insulating layer is arranged between the wiring layer and the heat dissipation layer; the projection of the terminal area and the chip layer in the direction from the second surface to the first surface falls within the range of the heat dissipation layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a half-bridge power module structure. Background Art

[0002] Power modules are widely used in new energy vehicles, new energy power generation, smart grids, transportation electrification and other fields. With the development of the industry, the miniaturization of power modules has become an inevitable trend, which has also brought about an increase in heat dissipation requirements. In order to enhance the heat dissipation capacity, top heat dissipation packaging is often used. However, the power terminals of the top heat dissipation package are led out from the side, which occupies a large area. Figure 1 Infineon's top-cooling TOLT package is a plastic-encapsulated single-tube structure. The power terminals and signal terminals of the power device are led out from the side of the plastic package, resulting in the package size being much larger than the power chip size, reducing space utilization.

[0003] Therefore, how to solve the problem of excessive space occupied by power modules has become a focus of those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a half-bridge power module structure, which can solve the problem that the power module occupies too large an area.

[0005] In order to achieve the above object, the present invention provides a half-bridge power module structure, wherein the half-bridge power module structure includes a first surface and a second surface arranged opposite to each other;

[0006] a terminal area, located on the second surface;

[0007] The terminal area includes a power terminal area and a signal terminal area, and the power terminal area and the signal terminal area are located on different sides of the second surface;

[0008] The half-bridge power module structure includes a chip layer and a wiring layer, wherein the chip layer includes at least two power chips, namely an upper power chip and a lower power chip; the upper power chip and the lower power chip each include a first pole, a second pole and a third pole;

[0009] The power terminal area includes a first power terminal, a second power terminal and a third power terminal;

[0010] The signal terminal area includes a first signal terminal and a second signal terminal;

[0011] The first power terminal is connected to the first electrode of the upper power chip through the wiring layer;

[0012] The second power terminal is connected to the second pole of the upper power chip and the first pole of the lower power chip through the wiring layer;

[0013] The third power terminal is connected to the second electrode of the lower power chip through the wiring layer;

[0014] The first signal terminal is connected to the third electrode of the upper power chip through the wiring layer;

[0015] The second signal terminal is connected to the third electrode of the lower power chip through the wiring layer;

[0016] a heat dissipation layer, located between the chip layer and the first surface or disposed on the first surface;

[0017] There is an insulating layer between the wiring layer and the heat dissipation layer, or the wiring layer also serves as the heat dissipation layer;

[0018] A direction from the second surface to the first surface is defined as a first direction. Along the first direction, projections of the terminal area and the chip layer fall within a range where the heat dissipation layer is located.

[0019] In an optional solution, the power terminal area and the signal terminal area are arranged on two opposite sides of the second surface.

[0020] In an optional solution, the upper / lower power chip is a vertical MOSFET, the first pole is the drain, which is on the lower surface of the upper / lower power chip; the second pole is the source, which is on the upper surface of the upper / lower power chip; and the third pole is the gate, which is on the upper surface of the upper / lower power chip.

[0021] In an optional solution, the upper / lower power chip is a planar MOSFET, the first pole is the drain, which is on the upper surface of the upper / lower power chip, the second pole is the source, which is on the upper surface of the upper / lower power chip; the third pole is the gate, which is on the upper surface of the upper / lower power chip.

[0022] In an optional solution, the upper / lower power chip is a planar HEMT, the first electrode is the drain, which is on the upper surface of the upper / lower power chip, the second electrode is the source, which is on the upper surface of the upper / lower power chip; and the third electrode is the gate, which is on the upper surface of the upper / lower power chip.

[0023] In an optional solution, the upper / lower power chip is a vertical IGBT, the first pole is the collector, which is on the lower surface of the upper / lower power chip; the second pole is the emitter, which is on the upper surface of the upper / lower power chip; and the third pole is the gate, which is on the upper surface of the upper / lower power chip.

[0024] In an optional solution, the signal terminal area further includes a third signal terminal and a fourth signal terminal; the second poles of the upper power chip and the lower power chip each include a first portion and a second portion of equal potential, the projections of the first portions of the upper power chip and the lower power chip in the first direction are both located in the power terminal area, and the projections of the second portions of the upper power chip and the lower power chip in the first direction are both located in the signal terminal area;

[0025] A first portion of the upper power chip is connected to the second power terminal through the wiring layer, and a second portion of the upper power chip is connected to the third signal terminal through the wiring layer;

[0026] A first portion of the lower power chip is connected to the third power terminal through the wiring layer, and a second portion of the lower power chip is connected to the fourth signal terminal through the wiring layer.

[0027] In an optional solution, the chip layer includes an upper pre-driver chip and a lower pre-driver chip, and both the upper pre-driver chip and the lower pre-driver chip include a first electrode, a second electrode, a third electrode, and a fourth electrode;

[0028] The third electrode of the upper power chip is connected to the first electrode of the upper pre-driver chip, and the second electrode of the upper power chip is connected to the second electrode of the upper pre-driver chip; the third electrode of the upper pre-driver chip is connected to the first signal terminal, and the fourth electrode of the upper pre-driver chip is connected to the third signal terminal;

[0029] The third pole of the lower power chip is connected to the first pole of the lower pre-driver chip, and the second pole of the lower power chip is connected to the second pole of the lower pre-driver chip; the third pole of the lower pre-driver chip is connected to the second signal terminal, and the fourth pole of the lower pre-driver chip is connected to the fourth signal terminal.

[0030] In an optional solution, the fourth pole and the second pole of the upper pre-driver chip are the same pole or two independent poles; and / or,

[0031] The fourth pole and the second pole of the lower pre-driver chip are the same pole or two independent poles.

[0032] In an optional solution, the heat dissipation layer is a continuous whole, or is composed of two isolated sub-heat dissipation layers, and the two sub-heat dissipation layers correspond to the upper power chip and the lower power chip respectively.

[0033] The beneficial effects of the present invention are:

[0034] The present invention leads the power terminals and signal terminals out from the surface of the module (rather than from the side), thereby increasing the ratio of the chip area to the package area and increasing the power density; the electrical connection and heat dissipation of the power module structure are not on the same surface, which can decouple the electrical connection design and the heat dissipation design, thereby improving the electrical and thermal performance of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which like reference numerals generally represent like components.

[0036] Figure 1 It is Infineon's TOLT package in the existing technology.

[0037] Figure 2 FIG. 1 is a top view of a half-bridge power module structure according to an embodiment of the present invention.

[0038] Figure 3 FIG. 1 is a bottom view of a half-bridge power module structure according to an embodiment of the present invention.

[0039] Figure 4 FIG. 1 is a top view of a half-bridge power module structure based on a vertical power chip according to an embodiment of the present invention.

[0040] Figure 5 FIG. 1 is an area distribution diagram of a top side view of a half-bridge power module structure having two opposite signal terminal areas according to an embodiment of the present invention.

[0041] Figure 6 FIG1 is a top side view of a half-bridge power module having two opposite signal terminal areas according to an embodiment of the present invention.

[0042] Figure 7 FIG. 4 is a cross-sectional view of a half-bridge power module structure containing two wiring layers according to an embodiment of the present invention.

[0043] Figure 8 FIG. 1 is a schematic diagram of a vertical power chip according to an embodiment of the present invention.

[0044] Figure 9 FIG. 1 is a schematic diagram of a planar power chip according to an embodiment of the present invention.

[0045] Figure 10 It is a top view of a half-bridge power module structure based on a planar power chip in one embodiment of the present invention.

[0046] Figure 11 This is a bottom side view of a half-bridge power module structure in which a heat dissipation layer is divided into two sub-heat dissipation layers according to an embodiment of the present invention.

[0047] Figure 12 FIG. 1 is a cross-sectional view of a half-bridge power module structure in which the second wiring layer also serves as a heat dissipation layer in an embodiment of the present invention.

[0048] Figure 13 FIG. 4 is a schematic diagram of a pre-driver chip according to an embodiment of the present invention.

[0049] Figure 14 FIG. 4 is a side view of a half-bridge power module including a pre-driver chip according to an embodiment of the present invention.

[0050] Figure 15 FIG. 1 is a top view of a half-bridge power module structure including three half-bridges according to an embodiment of the present invention.

[0051] Figure 16 FIG. 1 is a bottom side view of a half-bridge power module structure including three half-bridges according to an embodiment of the present invention.

[0052] Figure 17 FIG. 1 is a top view of a half-bridge power module structure including three half-bridges according to an embodiment of the present invention.

[0053] Description of reference numerals:

[0054] 1-first surface; 2-second surface; 20-terminal area; 21-power terminal area; 22-signal terminal area; 23-first power terminal; 24-second power terminal; 25-first signal terminal; 26-second signal terminal; 27-third signal terminal; 28-fourth signal terminal; 29-third power terminal; 301-upper power chip; 302-lower power chip; 4-first wiring layer; 5-second wiring layer; 6-third wiring layer; 7-fourth wiring layer; 8-insulating layer; 9-heat dissipation layer; 10-upper pre- Driver chip; 11-lower pre-driver chip; 31-first pole of upper power chip; 32-second pole of upper power chip; 321-first part of the second pole of upper power chip; 322-second part of the second pole of upper power chip; 33-third pole of upper power chip; 101-first pole of upper pre-driver chip; 102-second pole of upper pre-driver chip; 103-third pole of upper pre-driver chip; 104-fourth pole of upper pre-driver chip; 100-first half bridge; 200-second half bridge; 300-third half bridge. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings. However, it should be noted that the technical solutions of the present invention can be implemented in a variety of different forms and are not limited to the specific embodiments described herein. The drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Example

[0060] Reference Figures 2 to 17 , this embodiment provides a half-bridge power module structure, the half-bridge power module structure includes a first surface 1 and a second surface 2 arranged opposite to each other;

[0061] a terminal area 20 located on the second surface 2;

[0062] The terminal area 20 includes a power terminal area 21 and a signal terminal area 22 , and the power terminal area 21 and the signal terminal area 22 are located on different sides of the second surface 2 ;

[0063] The half-bridge power module structure includes a chip layer and a wiring layer. The chip layer includes at least two power chips, namely an upper power chip 301 and a lower power chip 302. The upper power chip 301 and the lower power chip 302 each include a first pole 31, a second pole 32 and a third pole 33.

[0064] The power terminal area 21 includes a first power terminal 23, a second power terminal 24 and a third power terminal 29;

[0065] The signal terminal area 22 includes a first signal terminal 25 and a second signal terminal 26;

[0066] The first power terminal 23 is connected to the first electrode 31 of the upper power chip 301 through the wiring layer;

[0067] The second power terminal 24 is connected to the second pole 32 of the upper power chip 301 and the first pole 31 of the lower power chip 302 through the wiring layer;

[0068] The third power terminal 29 is connected to the second electrode 32 of the lower power chip 302 through the wiring layer;

[0069] The first signal terminal 25 is connected to the third electrode 33 of the upper power chip 301 through the wiring layer; the second signal terminal 26 is connected to the third electrode 33 of the lower power chip 302 through the wiring layer;

[0070] a heat dissipation layer 9, located between the chip layer and the first surface 1 or disposed on the first surface 1;

[0071] There is an insulating layer 8 between the wiring layer and the heat dissipation layer 9, or the wiring layer also serves as the heat dissipation layer 9;

[0072] A direction from the second surface 2 to the first surface 1 is defined as a first direction. Along the first direction, the projections of the terminal area 20 and the chip layer fall within the range of the heat dissipation layer 9 .

[0073] Specifically, in this embodiment, the power terminal area 21 and the signal terminal area 22 are arranged on two opposite sides of the second surface 2. Figure 5 and Figure 6The signal terminal area 22 can be further divided into two sub-signal terminal areas, and the two sub-signal terminal areas can be arranged opposite to each other.

[0074] The upper / lower power chip 301 / 302 (meaning the upper power chip 301 or the lower power chip 302) can be a vertical MOSFET, then the first pole 31 is the drain, which is on the lower surface of the upper / lower power chip 301 / 302; the second pole 32 is the source, which is on the upper surface of the upper / lower power chip 301 / 302; the third pole 33 is the gate, which is on the upper surface of the upper / lower power chip.

[0075] The upper / lower power chip 301 / 302 can be a planar MOSFET, then the first electrode 31 is the drain, on the upper surface of the upper / lower power chip, the second electrode 32 is the source, on the upper surface of the upper / lower power chip 301 / 302; the third electrode 33 is the gate, on the upper surface of the upper / lower power chip 301 / 302.

[0076] The upper / lower power chip 301 / 302 can be a planar HEMT, in which case the first electrode 31 is a drain electrode, located on the upper surface of the upper / lower power chip 301 / 302; the second electrode 32 is a source electrode, located on the upper surface of the upper / lower power chip 301 / 302; and the third electrode 33 is a gate electrode, located on the upper surface of the upper / lower power chip 301 / 302.

[0077] The upper / lower power chip 301 / 302 can be a vertical IGBT, then the first pole 31 is the collector, which is on the lower surface of the upper / lower power chip 301 / 302; the second pole 32 is the emitter, which is on the upper surface of the upper / lower power chip 301 / 302; the third pole 33 is the gate, which is on the upper surface of the upper / lower power chip 301 / 302.

[0078] In this embodiment, the signal terminal area 22 also contains a third signal terminal 27 and a fourth signal terminal 28; the second poles 32 of the upper power chip 301 and the lower power chip 302 both include a first part 321 and a second part 322 of equal potential, and the projections of the first part 321 of the upper power chip 301 and the lower power chip 302 in the first direction are both located in the power terminal area 21, and the projections of the second part 322 of the upper power chip 301 and the lower power chip 302 in the first direction are both located in the signal terminal area 22; the first part 321 of the upper power chip 301 is connected to the second power terminal 24 through the wiring layer, and the second part 322 of the upper power chip 301 is connected to the third signal terminal 27 through the wiring layer; the first part 321 of the lower power chip 302 is connected to the third power terminal 29 through the wiring layer, and the second part 322 of the lower power chip 302 is connected to the fourth signal terminal 28 through the wiring layer.

[0079] In this embodiment, the chip layer includes an upper pre-driver chip 10 and a lower pre-driver chip 11, and the upper pre-driver chip 10 and the lower pre-driver chip 11 both include a first pole 101, a second pole 102, a third pole 103, and a fourth pole 104; the third pole 33 of the upper power chip 301 is connected to the first pole 101 of the upper pre-driver chip 10, the second pole 32 of the upper power chip 301 is connected to the second pole 102 of the upper pre-driver chip 10; the third pole 103 of the upper pre-driver chip 10 is connected to The first signal terminal 25 and the fourth electrode 104 of the upper pre-driver chip 10 are connected to the third signal terminal 27; the third electrode 33 of the lower power chip 302 is connected to the first electrode 101 of the lower pre-driver chip 11, and the second electrode 32 of the lower power chip 302 is connected to the second electrode 102 of the lower pre-driver chip 11; the third electrode 103 of the lower pre-driver chip 11 is connected to the second signal terminal 26, and the fourth electrode 104 of the lower pre-driver chip 11 is connected to the fourth signal terminal 28. The first electrode 101 of the upper pre-driver chip 10 or the lower pre-driver chip 11 is the driving gate, the second electrode 102 is the driving source, the third electrode 103 is the signal gate, and the fourth electrode 104 is the signal source. The driving source and signal source can be connected within the upper / lower pre-driver chip. When the driving source and the signal source are connected inside the upper / lower pre-driver chip, the fourth pole 104 and the second pole 102 of the upper / lower pre-driver chip are the same pole. When the driving source and the signal source are not connected inside the upper / lower pre-driver chip, the fourth pole 104 and the second pole 102 of the upper / lower pre-driver chip are two independent poles.

[0080] In this embodiment, the wiring layer can be two layers, divided into the first wiring layer 4 and the second wiring layer 5, or four layers, divided into the first wiring layer 4, the second wiring layer 5, the third wiring layer 6 and the fourth wiring layer 7.

[0081] In this embodiment, an insulation layer 8 is arranged between the wiring layer (the second wiring layer 5 or the fourth wiring layer 7) close to the first surface 1 and the heat dissipation layer 9, or, referring to Figure 12 , the wiring layer (the second wiring layer 5 or the fourth wiring layer 7) close to the first surface 1 is also the heat dissipation layer 9.

[0082] In this embodiment, the heat dissipation layer 9 is a continuous whole. In another embodiment, referring to Figure 11 , the heat dissipation layer 9 is composed of two isolated sub-heat dissipation layers, which correspond to the upper power chip 301 and the lower power chip 302 respectively, and dissipate heat for the upper power chip 301 and the lower power chip 302 respectively.

[0083] Referring to Figures 15 to 17 , it is the upper side view of the power module structure containing three half bridges, which are the first half bridge 100, the second half bridge 200 and the third half bridge 300 respectively.

[0084] The rest of the power module structure is covered by an insulation material. The insulation material can be epoxy resin, PP, FR4, BT, ABF and the like. The materials of the first power terminal 23, the second power terminal 24, the third power terminal 29, the first signal terminal 25, the second signal terminal 26, the third signal terminal 27 and the fourth signal terminal 28 can be copper, gold and other materials with conductive properties.

[0085] In this embodiment, the power terminals and the signal terminals are led out from the surface of the module (instead of from the side), which increases the proportion of the chip area to the packaging area and increases the power density. The electrical connection and the heat dissipation of the power module structure are not on the same surface, which can decouple the design of the electrical connection and the heat dissipation, and improve the electrical and thermal performance of the module.

[0086] In this embodiment, by redefining the module structure and designing the terminal area and the heat dissipation area, the purpose of increasing the power density and improving the electrical and thermal performance of the module is achieved.

[0087] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or modification made by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A half-bridge power module structure, characterized in that: The half-bridge power module structure includes a first surface and a second surface arranged opposite to each other; a terminal area, located on the second surface; The terminal area includes a power terminal area and a signal terminal area, and the power terminal area and the signal terminal area are located on different sides of the second surface; The half-bridge power module structure includes a chip layer and a wiring layer, wherein the chip layer includes at least two power chips, namely an upper power chip and a lower power chip; the upper power chip and the lower power chip each include a first pole, a second pole and a third pole; The power terminal area includes a first power terminal, a second power terminal and a third power terminal; The signal terminal area includes a first signal terminal and a second signal terminal; The first power terminal is connected to the first electrode of the upper power chip through the wiring layer; The second power terminal is connected to the second pole of the upper power chip and the first pole of the lower power chip through the wiring layer; The third power terminal is connected to the second electrode of the lower power chip through the wiring layer; The first signal terminal is connected to the third electrode of the upper power chip through the wiring layer; The second signal terminal is connected to the third electrode of the lower power chip through the wiring layer; a heat dissipation layer, located between the chip layer and the first surface or disposed on the first surface; There is an insulating layer between the wiring layer and the heat dissipation layer, or the wiring layer also serves as the heat dissipation layer; A direction from the second surface to the first surface is defined as a first direction. Along the first direction, projections of the terminal area and the chip layer fall within a range where the heat dissipation layer is located.

2. The half-bridge power module structure according to claim 1, characterized in that: The power terminal area and the signal terminal area are arranged on two opposite sides of the second surface.

3. The half-bridge power module structure according to claim 1, wherein: The upper / lower power chip is a vertical MOSFET, the first electrode is the drain, located on the lower surface of the upper / lower power chip; the second electrode is the source, located on the upper surface of the upper / lower power chip; The third electrode is a gate, which is located on the upper surface of the upper / lower power chip.

4. The half-bridge power module structure according to claim 1, wherein: The upper / lower power chip is a planar MOSFET, the first electrode is the drain, located on the upper surface of the upper / lower power chip, and the second electrode is the source, located on the upper surface of the upper / lower power chip; The third electrode is a gate, which is located on the upper surface of the upper / lower power chip.

5. The half-bridge power module structure according to claim 1, wherein: The upper / lower power chip is a planar HEMT, the first electrode is a drain electrode, located on the upper surface of the upper / lower power chip, and the second electrode is a source electrode, located on the upper surface of the upper / lower power chip; The third electrode is a gate, which is located on the upper surface of the upper / lower power chip.

6. The half-bridge power module structure according to claim 1, wherein: The upper / lower power chip is a vertical IGBT, the first electrode is the collector, located on the lower surface of the upper / lower power chip; the second electrode is the emitter, located on the upper surface of the upper / lower power chip; The third electrode is a gate, which is located on the upper surface of the upper / lower power chip.

7. The half-bridge power module structure according to claim 1, wherein: The signal terminal area further includes a third signal terminal and a fourth signal terminal; the second poles of the upper power chip and the lower power chip each include a first portion and a second portion of equal potential, the projections of the first portion of the upper power chip and the lower power chip in the first direction are both located in the power terminal area, and the projections of the second portion of the upper power chip and the lower power chip in the first direction are both located in the signal terminal area; A first portion of the upper power chip is connected to the second power terminal through the wiring layer, and a second portion of the upper power chip is connected to the third signal terminal through the wiring layer; A first portion of the lower power chip is connected to the third power terminal through the wiring layer, and a second portion of the lower power chip is connected to the fourth signal terminal through the wiring layer.

8. The half-bridge power module structure according to claim 1, wherein: The chip layer comprises an upper pre-driver chip and a lower pre-driver chip, and both the upper pre-driver chip and the lower pre-driver chip comprise a first electrode, a second electrode, a third electrode, and a fourth electrode; The third electrode of the upper power chip is connected to the first electrode of the upper pre-driver chip, and the second electrode of the upper power chip is connected to the second electrode of the upper pre-driver chip; the third electrode of the upper pre-driver chip is connected to the first signal terminal, and the fourth electrode of the upper pre-driver chip is connected to the third signal terminal; The third pole of the lower power chip is connected to the first pole of the lower pre-driver chip, and the second pole of the lower power chip is connected to the second pole of the lower pre-driver chip; the third pole of the lower pre-driver chip is connected to the second signal terminal, and the fourth pole of the lower pre-driver chip is connected to the fourth signal terminal.

9. The half-bridge power module structure according to claim 8, characterized in that: The fourth pole and the second pole of the upper pre-driver chip are the same pole or two independent poles; and / or, The fourth pole and the second pole of the lower pre-driver chip are the same pole or two independent poles.

10. The half-bridge power module structure according to claim 1, wherein: The heat dissipation layer is a continuous whole, or is composed of two isolated sub-heat dissipation layers, and the two sub-heat dissipation layers correspond to the upper power chip and the lower power chip respectively.

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