Method for actively discharging intermediate circuit capacitor of pulse inverter

Abstract

The invention relates to a circuit arrangement (1) for actively discharging an intermediate circuit capacitor (C) of a pulse inverter (2), comprising a pulse inverter (2) having three half-bridges (HB1-HB3), a gate driver arrangement (GS1-GS6) for high-voltage-side transistors (S1-S3) and low-voltage-side transistors (S4-S6), and at least one control unit (3), the half-bridge (HB1) has a gate driver component (GB1) associated with the gate driver component (GB1) such that during an active discharge, at least one low-voltage-side transistor (S4) of the half-bridge (HB1) is permanently switched on, and wherein the corresponding high-voltage-side transistor (S1) is controlled in a clocked manner by means of the associated gate driver component (GB1) such that the high-voltage-side transistor is temporarily switched on or operated in a linear manner, and wherein the gate driver component (GB1) is associated with the high-voltage-side transistor (S1). Only the gate driver component (GS1) of the corresponding high-side transistor (S1) of the gate driver components (GS1-GS3) of the high-side transistors (S1-S3) has redundant voltage supplies (U1, U2).

Description

Technical Field

[0001] The invention relates to a method and a circuit arrangement for actively discharging an intermediate circuit capacitor of a pulse-controlled inverter. Background Art

[0002] Especially in hazardous situations, the intermediate circuit capacitors of pulse-controlled inverters must be discharged quickly to a contact voltage of <60 V.

[0003] One possibility is a series circuit consisting of a semiconductor switching element and a resistor, whereby the discharge occurs via the resistor. However, this requires two additional components. Therefore, various approaches have been proposed for integrating active discharge circuits into pulse-controlled inverters.

[0004] Such circuit arrangements are known, for example, from DE 10 2021 111 773 A1 or DE 10 2017 121 579 A1, in which the high-side and low-side transistors of at least one half-bridge are operated in linear operation.

[0005] DE 10 2021 103 299 A1 discloses a control device for a three-phase inverter of a vehicle drive motor, in which all low-side transistors are permanently switched on for active discharge, while high-side transistors are switched on alternately to distribute heat losses uniformly. Summary of the Invention

[0006] The object of the present invention is to improve a method for actively discharging an intermediate circuit capacitor of a pulse-controlled inverter and to implement a corresponding circuit arrangement in such a way that the circuit expenditure is reduced while maintaining high reliability.

[0007] The above-mentioned technical problem is solved by a method for actively discharging an intermediate circuit capacitor of a pulse-controlled inverter having the features according to the invention, and a circuit arrangement for actively discharging an intermediate circuit capacitor of a pulse-controlled inverter having the features according to the invention. Further advantageous embodiments of the invention are provided in the present invention.

[0008] In a method for actively discharging an intermediate circuit capacitor of a pulse-controlled inverter, at least one low-side transistor is permanently turned on during the active discharge process. The pulse-controlled inverter has three half-bridges, wherein gate driver components are provided for the high-side transistors and the low-side transistors. In addition, the corresponding high-side transistor of the permanently turned-on low-side transistor is controlled in a clocked manner by the gate driver component provided therefor, so that the high-side transistor is temporarily turned on. Alternatively, the corresponding high-side transistor operates in a linear manner, so that the high-side transistor behaves like a resistor. In this case, only the gate driver component of the corresponding high-side transistor in the gate driver component of the high-side transistor has a redundant voltage supply. Preferably, one voltage is provided by the high-side (e.g., by a switch controller), and the other voltage is provided by the vehicle power supply (e.g., by a DC / DC converter on the vehicle side).

[0009] If only one low-side transistor is switched on, only the gate driver components of this low-side transistor must have a redundant voltage supply. This increases the reliability of the active discharge, reducing the circuitry overhead. In contrast, in the circuit arrangement according to DE 10 2021 103 299 A1, all gate driver components must have a redundant voltage supply.

[0010] In one embodiment, all low-side transistors are permanently switched on. Only low-side transistors associated with redundantly powered high-side transistors are also redundantly powered. Since all low-side transistors are permanently switched on, the connected electric motor is actively short-circuited and thus generates no torque.

[0011] In a method for actively discharging an intermediate circuit capacitor of a pulse-controlled inverter, the load on the semiconductors is reduced.

[0012] In another embodiment, the clocking of the corresponding high-side transistor is designed so that the intermediate circuit capacitor discharges at a constant power. In this case, the pulse on-time in the PWM clocking signal for the gate driver component is continuously increased to set a constant discharge power.

[0013] For the same discharge time, the peak power at the start of charging can be reduced (compared to the discharge process according to the prior art). This embodiment does not rely on a redundant voltage supply and constitutes an independent invention. Alternatively, a constant discharge current can also be set, in which case the pulse on time must also be extended.

[0014] In another embodiment, the voltage on the intermediate circuit capacitor and / or the corresponding high-side transistor is detected, wherein it is determined from the voltage profile whether the discharge process is started and / or interrupted. For example, if the voltage on the intermediate circuit capacitor does not change, it indicates a fault. For example, the high-side transistor is not switched on, or the main contactor of the high-voltage battery is erroneously closed, so that the intermediate circuit capacitor is continuously recharged.

[0015] For protection of the components, it is preferred to interrupt the active discharge process and to repeat the active discharge process after a predetermined time. It is possible to repeat the attempt a predetermined number of times, wherein the discharge process is finally interrupted.

[0016] The circuit arrangement for active discharge of an intermediate circuit capacitor of a pulse inverter comprises a pulse inverter having three half-bridges, a gate driver assembly for high-side transistors and low-side transistors and at least one control unit, wherein the control unit is designed such that, in the active discharge process, at least one low-side transistor of a half-bridge is permanently switched on, wherein the corresponding high-side transistor of the half-bridge is controlled in a clocked manner by the gate driver assembly assigned to it, so that the high-side transistor is temporarily switched on or operated in a linear mode, wherein only the corresponding gate driver assembly of the high-side transistor of the gate driver assemblies of the high-side transistors has a redundant voltage supply.

[0017] With regard to other design proposals, full reference is made to the preceding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0018] The application is explained in more detail below on the basis of preferred embodiments. In the drawings:

[0019] Figure 1 A schematic diagram of a circuit arrangement for active discharge of an intermediate circuit capacitor of a pulse inverter is shown,

[0020] Figure 2 A schematic diagram of the voltage at the intermediate circuit capacitor in the case of constant discharge power is shown, and

[0021] Figure 3 A schematic diagram of the voltage at the intermediate circuit capacitor in the case of constant discharge current is shown. DETAILED DESCRIPTION

[0022] Figure 1A circuit arrangement 1 for active discharge of an intermediate circuit capacitor C of a pulse inverter 2 is shown schematically. The pulse inverter 2 has three half bridges HB1-HB3, which have high-side transistors S1-S3 and low-side transistors S4-S6, respectively. Free-wheeling diodes D are arranged in parallel to the high-side transistors S1-S3 and the low-side transistors S4-S6, respectively. The half bridges HB1-HB3 have a center tap, for example, which is led to a motor. The high-side transistors S1-S3 and the low-side transistors S4-S6, respectively, are equipped with gate driver assemblies GS1-GS6, which obtain control commands S from a control unit 3. The control unit 3 is integrated, for example, in a control device of the pulse inverter 2. Furthermore, a voltage measuring device 4 is provided, which detects the voltage U on the intermediate circuit capacitor C C Furthermore, a further voltage measuring device 5 is provided, which detects the voltage on the high-side transistor S1 of the first half bridge HB1. The gate driver assemblies GS1-GS6 each have a first voltage supply, which is preferably realized at high voltage. For this purpose, at least one linear controller 6 or a similar component is provided, which reduces the high voltage to an operating voltage of the gate driver assemblies GS1-GS6. Here, too, a plurality of components can be provided, which are each assigned to one gate driver assembly GS1-GS6 or to a group of gate driver assemblies GS1-GS6. For the sake of clarity, only one linear controller 6 is shown in the figure, to the output of which a first voltage supply U1 is applied. The gate driver assembly GS1 of at least the high-side transistor S1 and the gate driver assembly GS4 of the low-side transistor S4 have a second voltage supply U2, which is provided, for example, by at least one DC / DC converter 7, wherein the input of the DC / DC converter 7 is connected to a 12 V or 24 V vehicle electrical system battery, for example. The DC / DC converter 7 is preferably an electrically isolated DC / DC converter 7. The gate driver assemblies GS5 and GS6 of the other low-side transistors S5, S6 can also have the second voltage supply U2 here.

[0023] The intermediate circuit capacitor C should be actively discharged, for example, in the event of a crash. For this purpose, a not shown main contactor is opened and the high-voltage battery is separated from the intermediate circuit capacitor C. Furthermore, the control unit 3 controls at least the gate driver assembly GS4 of the low-side transistor S4, so that the low-side transistor S4 is permanently switched on. The low-side transistors S5, S6 are preferably also permanently switched on, so that the motor is in active short circuit. Furthermore, the gate driver assembly GS1 of the high-side transistor S1 is controlled in a clocked manner, so that this high-side transistor is temporarily switched on and the intermediate circuit capacitor C is discharged. The clocking is implemented here in such a way that a limit value of the high-side transistor S1 is maintained.

[0024] The redundant voltage supply for gate driver components GS1 and GS4-GS6 offers two advantages. Active discharge is possible even in the event of a voltage supply failure (e.g., a failure of the switch controller 6 or a failure of the DC / DC converter 7). Another advantage is that if the intermediate circuit capacitor C is significantly discharged and the voltage supply U1 from the high-voltage side fails, discharge to 0 V is not possible. However, this can be achieved using the voltage supply U2 from the vehicle electrical system.

[0025] By analyzing the voltage U across the intermediate circuit capacitor C C , it can be checked whether the active discharge has started and is not interrupted (for example because the high-voltage contactor is still closed). In this case, the active discharge is interrupted, ie the high-side transistor S1 is blocked.

[0026] exist Figure 2 The voltage U across the intermediate circuit capacitor C is shown in FIG. 1 when the clock control is controlled so that the discharge power is constant. C Voltage curve as a function of time t.

[0027] exist Figure 3 The voltage U across the intermediate circuit capacitor C is shown in FIG. 1 when the clock control is controlled so that the discharge current is constant. C Voltage curve as a function of time t.

[0028] Reference Signs List

[0029] 1 Circuit device

[0030] 2-pulse inverter

[0031] 3 Control unit

[0032] 4 Voltage measuring device

[0033] 5 Voltage measuring device

[0034] 6 Linear Controller

[0035] 7 DC / DC converters

[0036] HB1-HB3 half-bridge

[0037] S1-S6 transistors

[0038] S control instruction

[0039] GS1-GS6 Gate Driver Assemblies

[0040] D Freewheeling diode

[0041] C Intermediate circuit capacitor

[0042] U1 first voltage supply

[0043] U2 second voltage supply

[0044] U C voltage

Claims

1. A method for actively discharging an intermediate circuit capacitor (C) of a pulse-controlled inverter (2), wherein: The pulse inverter (2) has three half-bridges (HB1-HB3), wherein gate driver components (GS1-GS6) are provided for high-side transistors (S1-S3) and low-side transistors (S4-S6), wherein during an active discharge process, at least one low-side transistor (S4) of the half-bridge circuit (HB1) is permanently switched on, wherein the corresponding high-side transistor (S1) is controlled in a clocked manner by the gate driver component (GS1) provided therewith, so that the high-side transistor is temporarily switched on, or the high-side transistor (S1) is controlled in a linear operation, wherein only the gate driver component (GS1) of the corresponding high-side transistor (S1) among the gate driver components (GS1-GS3) of the high-side transistors (S1-S3) has a redundant voltage supply (U1, U2).

2. The method according to claim 1, characterized in that All low-side transistors ( S4 - S6 ) are permanently switched on.

3. The method according to claim 1 or 2, characterized in that The clocking of the corresponding high-side transistor ( S1 ) is designed such that the intermediate circuit capacitor (C) is discharged at a constant power.

4. The method according to claim 1 or 2, characterized in that The clocking of the corresponding high-side transistor ( S1 ) is designed such that the intermediate circuit capacitor (C) is discharged with a constant discharge current.

5. The method according to any one of the preceding claims, characterized in that Detection of the voltage (U) across the intermediate circuit capacitor (C) and / or the corresponding high-side transistor (S1) C ), wherein it is determined based on the voltage curve whether the discharge process is started and / or interrupted.

6. The method according to claim 5, characterized in that Active discharging is interrupted if the discharging process has not started and / or if the discharging process is interrupted.

7. The method according to claim 6, characterized in that Active discharge is resumed after a predetermined time.

8. A circuit arrangement for actively discharging an intermediate circuit capacitor (C) of a pulse-controlled inverter (2), comprising a pulse-controlled inverter (2) having three half-bridges (HB1-HB3), gate driver components (GS1-GS6) for high-side transistors (S1-S3) and low-side transistors (S4-S6), and at least one control unit (3), wherein: The control unit (3) is designed so that during an active discharge process, at least one low-voltage side transistor (S4) of a half-bridge (HB1) is permanently switched on, wherein the corresponding high-voltage side transistor (S1) is controlled in a clock-controlled manner by a gate driver component (GB1) equipped therewith, so that the high-voltage side transistor is temporarily switched on or operated in a linear manner, wherein only the gate driver component (GS1) of the corresponding high-voltage side transistor (S1) among the gate driver components (GS1-GS3) of the high-voltage side transistors (S1-S3) has a redundant voltage supply (U1, U2).

9. The circuit arrangement according to claim 8, characterized in that The control unit is designed such that, in the case of active discharging, all low-side transistors ( S4 - S6 ) are permanently switched on.

10. The circuit arrangement according to claim 8 or 9, characterized in that The circuit arrangement (1) has at least one voltage measuring device (5) for detecting the voltage (U) across the intermediate circuit capacitor (C) and / or the corresponding high-side transistor (S1) C) .

11. A method for actively discharging an intermediate circuit capacitor (C) of a pulse-controlled inverter (2), wherein: The pulse-controlled inverter (2) has three half-bridges (HB1-HB3), wherein gate driver components (GS1-GS6) are provided for high-side transistors (S1-S3) and low-side transistors (S4-S6), wherein during an active discharge process, at least one low-side transistor (S4) of the half-bridge circuit (HB1) is permanently switched on, wherein the corresponding high-side transistor (S1) is controlled in a clocked manner by the gate driver component (GS1) provided therewith, so that the high-side transistor is temporarily switched on, or the high-side transistor (S1) is controlled in a linear operation, wherein the clocking of the corresponding high-side transistor (S1) is designed so that the intermediate circuit capacitor (C) is discharged at a constant power.

Images