Idle tone mitigation using clock jitter

Abstract

The invention relates to idle tone mitigation using clock jitter. A circuit includes a capacitive micro-electromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal; a voltage controlled oscillator (VCO) coupled to the capacitive MEMS microphone, where the VCO is configured to generate a frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate a random number; and a phase modulator configured to generate a phase modulated clock signal by sampling a phase of the clock signal according to a random number modulation system, where the FTD converter is configured to generate a digital signal according to the frequency modulated signal and the phase modulated clock signal, and configured to sample the digital signal by the phase modulated clock signal to generate a digital output signal of the FTD converter.

Description

Technical Field

[0001] The present invention relates generally to circuits and, in a particular embodiment, to circuits including a capacitive microelectromechanical system (MEMS) microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the MEMS microphone. Background Art

[0002] Today, microelectromechanical system (MEMS) microphones are widely used in electronic devices due to their small format factor and low cost. Traditionally, the analog output of a microphone is converted into a digital output signal by a voltage-encoding-based system that uses an analog-to-digital converter (ADC) to convert the microphone's output voltage into a digital output signal.

[0003] Voltage-controlled oscillator (VCO-ADC)-based ADCs are a promising alternative to conventional voltage-encoding-based systems and are well-suited for low-cost digital microphone applications, such as MEMS microphones. For example, in a capacitive MEMS microphone system equipped with a VCO-ADC readout circuit, the MEMS microphone generates a voltage in response to sound pressure. This voltage modulates the oscillator frequency of the VCO in the VCO-ADC readout circuit. A frequency-to-digital (FTD) converter then measures the oscillator frequency at a sampling rate defined by the system's sampling clock signal. While VCO-ADCs offer advantages over conventional voltage-encoding-based systems, their use in MEMS microphone systems still presents challenges. Summary of the Invention

[0004] According to an embodiment, a circuit includes: a capacitive microelectromechanical system (MEMS) microphone configured to output a voltage signal in response to a sound signal; and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the capacitive MEMS microphone and configured to generate a digital output signal proportional to the voltage signal, wherein the VCO-ADC includes: a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone and configured to output a frequency-modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate a random number; and a phase modulator configured to generate a phase-modulated clock signal by modulating the phase of a system sampling clock signal with the random number, wherein the FTD converter is configured to generate a digital signal based on the frequency-modulated signal and the phase-modulated clock signal, and is configured to generate the digital output signal of the FTD converter by sampling the digital signal using the phase-modulated clock signal.

[0005] According to an embodiment, a circuit includes: a capacitive microelectromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal; a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, wherein the VCO is configured to generate a frequency-modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate a random number; and a phase modulator configured to generate a phase-modulated clock signal by modulating the phase of a system sampling clock signal according to the random number, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0006] According to an embodiment, a method of operating a microelectromechanical system (MEMS) microphone system includes: generating a voltage signal by the MEMS microphone in response to a sound signal; generating a frequency modulation signal by a voltage controlled oscillator (VCO) coupled to the MEMS microphone, the frequency modulation signal having a frequency proportional to the voltage signal; converting the frequency modulation signal by a frequency to digital (FTD) converter coupled to the VCO into a digital signal; generating a random number by a random number generator; modulating the phase of a system sampling clock signal by a phase modulator according to the random number to generate a phase modulated clock signal; and sampling the digital signal by the phase modulated clock signal to generate a digital output signal of the FTD converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 The diagram illustrates a microelectromechanical system (MEMS) microphone system in an embodiment, which includes a capacitive MEMS microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC);

[0009] Figure 2 The random number generator in the embodiment is illustrated;

[0010] Figure 3A The phase modulator in the embodiment is shown;

[0011] Figure 3B The embodiment of the invention is shown in FIG. Figure 3A Operation of the phase modulator in;

[0012] Figure 4A A frequency to digital (FTD) converter in an embodiment is shown;

[0013] Figure 4B The embodiment of the invention is shown in FIG.Figure 4A The output of the FTD converter in;

[0014] Figure 5A A phase modulator in another embodiment is shown;

[0015] Figure 5B The diagram shows an embodiment of the Figure 5A The clock signal used in the phase modulator of

[0016] Figure 6 illustrates the output of a MEMS microphone system in response to a mechanical shock in an embodiment;

[0017] Figure 7A and Figure 7B illustrates the performance of the disclosed MEMS microphone system in an embodiment;

[0018] Figure 8 illustrates the performance of the disclosed MEMS microphone system in another embodiment; and

[0019] Figure 9 A flow chart of a method of operating a MEMS microphone system in an embodiment is illustrated. DETAILED DESCRIPTION

[0020] The manufacture and use of the examples disclosed herein are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific examples discussed are merely illustrative of specific ways to manufacture and use the present invention and do not limit the scope of the invention. Throughout the discussion herein, unless otherwise indicated, the same or similar reference numerals in different figures represent the same or similar components. For simplicity, the details of components with the same or similar reference numerals will not be described again.

[0021] The present invention will be described with reference to examples in a specific context, and in particular, a MEMS microphone system including a capacitive MEMS microphone and a VCO-ADC readout circuit.

[0022] Figure 1 The figure shows a system diagram of a MEMS microphone system 100 in an embodiment, which includes a capacitive MEMS microphone and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC). Note that for simplicity, not all features of the MEMS microphone system 100 are shown.

[0023] like Figure 1 As shown, the MEMS microphone system 100 includes a capacitive MEMS microphone 103 configured to generate an output voltage V in response to a sound signal. g .existFigure 1 In an example, the capacitive MEMS microphone 103 is or includes a capacitor, wherein one or more membranes of the capacitor vibrate in response to sound pressure to generate an output voltage V g A high voltage bias (e.g., a +12V voltage) is supplied to the capacitive MEMS microphone 103 to bias the capacitive MEMS microphone 103. The high voltage bias can be provided by a voltage source 101 (e.g., a charge pump circuit) coupled between the capacitive MEMS microphone 103 and a reference node 129, which is configured to be coupled to a reference voltage (such as electrical ground). The output terminal of the capacitive MEMS microphone 103 is coupled to a node 104. A high ohmic resistor 105 (e.g., having a resistance on the order of gigaohms) is coupled between the node 104 and the node 106. In the illustrated embodiment, a bias voltage V is provided at the node 106. bias To set the operating point (eg, quiescent frequency) of the MEMS microphone system 100. As an example, the bias voltage V at the node 106 is bias This may be provided by a bias circuit 107. The bias circuit 107 is designed to generate a suitable bias voltage for the capacitive MEMS microphone 103. Bias circuits are known and used in MEMS microphone systems and will not be discussed in detail here.

[0024] exist Figure 1 In FIG, input stage circuit 109 is coupled between node 104 and an input terminal of a voltage controlled oscillator (VCO) 113. Figure 1 In the example of FIG. 1 , input stage circuit 109 is a source follower circuit including a transistor. The gate terminal of the transistor is coupled to node 104. The drain terminal of the transistor is coupled to a supply voltage node 111, which is configured to receive a supply voltage (e.g., +3V, +5V, etc.) of MEMS microphone system 100. The source terminal of the transistor is coupled to an input terminal of VCO 113. In some embodiments, input stage circuit 109 (e.g., a source follower circuit) provides a buffered voltage to VCO 113 that has a voltage difference with the output voltage V of capacitive MEMS microphone 103. g Proportional voltage value.

[0025] The VCO 113 is configured to generate an output signal f vco Output signal f vco The frequency is determined by the output voltage V of the capacitive MEMS microphone 103 g In some embodiments, the output signal f generated by the VCO 113 is modulated (eg, controlled). vco The frequency and output voltage V g is proportional to, therefore, the output signal f of the VCO 113 vco Also known as frequency modulated signal fvco In an example embodiment, VCO 113 is a ring oscillator, although any other suitable type of VCO may be used as VCO 113. Voltage controlled oscillators, such as ring oscillators, are known and used in the art, and therefore are not discussed in detail here.

[0026] Still refer to Figure 1 The output terminal 114 of the VCO 113 is coupled to the input terminal of a frequency-to-digital (FTD) converter 115. The FTD converter 115 is configured to convert the frequency modulated signal f to a digital signal at an output terminal 116 of the FTD converter 115. vco In some embodiments, the FTD converter 115 is configured to convert the FTD signal into a digital output signal y[n] (eg, a multi-bit digital signal). vco and phase modulated clock signal f clk_jittered Generate digital signals (see e.g. Figure 4B 430), and is configured to modulate the clock signal f by using a phase clk_jittered The digital signal is sampled to generate a digital output signal y[n]. Phase modulation clock signal f clk_jittered Details of the FTD converter 115 are discussed below.

[0027] exist Figure 1 In the embodiment, the MEMS microphone system 100 further includes a random number generator 121 and a phase modulator 123. The random number generator 121 is configured to generate a random number. The generated random number is sent to the phase modulator 123. The phase modulator 123 receives the random number and the system sampling clock signal f clk , and modulate the system sampling clock signal f according to the random number clk The phase of the clock signal f is generated by clk_jittered Then, the phase modulated clock signal f clk_jittered is sent to the clock input terminal of the FTD converter 115. More details are discussed below.

[0028] In some embodiments, Figure 1 Components within the area bounded by dashed line 150 in FIG. 1 are integrated into a semiconductor die, such as a portion of an application-specific integrated circuit (ASIC) or ASIC. Input stage circuit 109, VCO 113, FTD converter 115, random number generator 121, phase modulator 123, and system clock source 125 may be collectively referred to as a VCO-ADC, a VCO-ADC readout circuit, or a VCO-ADC circuit with a phase modulator.

[0029] Figure 2 The random number generator 200 in the embodiment is shown. The random number generator 200 can be used asFigure 1 The random number generator 121 in FIG. The random number generator 200 is a linear feedback shift register (LFSR) random number generator including a plurality of registers 201 connected in series. The output terminals of some registers 201 are combined by a logic circuit 203, and the output of the logic circuit 203 is used as a feedback bit sent to the input terminal of the leftmost register 201. At the beginning of operation, each register 201 of the LFSR random number generator 200 is initialized with a corresponding initial value (e.g., bit "0" or bit "1"), and the value of the register 201 is shifted to the right during operation. As will be readily understood by those skilled in the art, the LFSR random number generator 200 can be used to generate a random binary sequence or a multi-bit random number. Figure 2 The LFSR random number generator 200 in FIG. 2 is only a non-limiting example. Other LFSR random number generators and other non-LFSR types of random number generators are also possible and can be used as Figure 1 These and other variations are fully intended to be included within the scope of this disclosure.

[0030] Figure 3A The phase modulator 300 in the embodiment is shown. The phase modulator 300 can be used as Figure 1 The phase modulator 123 in FIG. Figure 3A As shown, the phase modulator 300 includes a delay chain 303 including a plurality of delay circuits 305 (e.g., buffers, inverters, etc.) coupled in series, wherein an input terminal 301 of the delay chain 303 is coupled to a system sampling clock signal f generated by the system clock source 125. clk (See also Figure 1 In an embodiment where an inverter is used in the delay circuit, two inverters connected in series may be used as the delay circuit 305. The system clock source 125 may include an oscillator, a phase-locked loop (PLL), a combination thereof, etc., and is configured to generate a highly accurate digital clock signal (e.g., f clk In some embodiments, the system clock source 125 is omitted in the VCO-ADC, and the system sampling clock signal f clk Provided by another clock source outside the VCO-ADC.

[0031] The phase modulator 300 further includes a multiplexer 307. An input terminal of the multiplexer 307 is coupled to output terminals of the plurality of delay circuits 305. For example, the delay chain 303 may include M delay circuits 305, and the output terminals of the M delay circuits 305 are connected to corresponding input terminals of the multiplexer 307. In other words, in some embodiments, the system sampling clock signal f clkThe M delayed versions of the signal are sent to the input terminal of the multiplexer 307, each delayed version having a value that is consistent with the system sampling clock signal f clk Same frequency but different phase.

[0032] The control terminal 302 of the multiplexer 307 is coupled to Figure 1 The output terminal of the random number generator 121 in the control terminal 302. The control signal (e.g., random number) applied at the control terminal 302 may have N bits, such that N=log2M. In some embodiments, the multiplexer 307 is configured to select a clock signal at one of the input terminals of the multiplexer 307 based on the random number at the control terminal 302, and output the selected clock signal as the phase modulated clock signal f at the output terminal 309. clk_jittered . Figure 3A The output terminal 309 corresponds to Figure 1 The output terminal 124 of the phase modulator 123.

[0033] Figure 3B The embodiment of the invention is shown in FIG. Figure 3B The operation of the phase modulator 300 in Figure 3B In the system, the sampling clock signal f clk This is illustrated by clock signal 311, which has a period T. Figure 3B In the example, without loss of generality, assume that the system sampling clock signal f clk The effective edge of is the rising edge. The system sampling clock signal f clk One of the rising edges of is marked with an upward pointing arrow. The delay chain 303 of the phase modulator 300 generates the system sampling clock signal f clk M delayed versions of , each with a different delay (or equivalently a different phase). To avoid clutter, Figure 3B A plurality of dashed lines 313 are illustrated in FIG. 1 to show the relationship between the system sampling clock signal f and the system sampling clock signal f, which is marked with an upward pointing arrow. clk The rising edge of the corresponding system sampling clock signal f clk Based on the random number at the control terminal 302, the system sampling clock signal f clk One of the delayed versions of is selected and used as the phase modulated clock signal f clk_jittered .

[0034] Note that the random number generator 121 is clocked with the system sampling clock signal f clk The random number is generated at the same frequency as the frequency of the system sampling clock signal f. clkFor each rising edge of , the random number generator 121 generates a corresponding random number, and based on the corresponding random number, the system sampling clock signal f clk One of the delayed versions of is selected as the phase modulated clock signal f clk_jittered As a result, the phase modulated clock signal f clk_jittered Each rising edge of the system sampling clock signal f clk In other words, the phase modulator 300 introduces random phase delay (eg, jitter) into the system sampling clock signal f clk Each rising edge of the phase modulated clock signal f is generated clk_jittered .

[0035] In some embodiments, the maximum delay D of the delay chain 303 max Less than the system sampling clock signal f clk The period T, the maximum delay D of the delay chain 303 max Calculated as D max =M×D, where M is the number of delay circuits 305 and D is the time delay of each delay circuit 305. For example, D max <T or D max <T / 2. Note that Figure 4A Some of the dashed lines 313 are compared to the system sampling clock signal f marked with an upward pointing arrow. clk The corresponding rising edge of the clock signal arrives early. This seemingly "non-causal" behavior can be achieved in hardware design by delaying the system sampling clock signal f clk , and the delayed system sampling clock signal f clk Processed as system sampling clock signal f clk , while simultaneously converting the original (non-delayed) system sampling clock signal f clk is fed to the delay chain 303 of the phase modulator 300 .

[0036] Figure 1 The frequency to digital (FTD) converter 400 in an embodiment is shown. The FTD converter 400 can be used as Figure 1 The FTD converter 115 in FIG. Figure 4A The VCO 113 in Figure 4A 1 is shown to illustrate the connections of the FTD converter 400 , it being understood that the VCO 113 is not part of the FTD converter 400 .

[0037] like Figure 4B As shown, the FTD converter 400 includes a counter 401 and a register 403. The input terminal of the counter 401 is coupled to the frequency modulation signal f generated by the VCO 113. vcoThe RESET terminal of the counter 401 is coupled to the phase modulated clock signal f clk_jittered The counter 401 is configured to receive the phase modulated clock signal f clk_jittered The frequency modulated signal f between adjacent valid edges (such as rising or falling edges) vco The number of cycles in the oscillator (also called oscillator periods) is counted.

[0038] The output of the counter 401 as a multi-bit digital signal is sent to the register 403. The clock terminal of the register 403 is coupled to the phase modulated clock signal f clk_jittered The register 403 is configured to phase modulate the clock signal f clk_jittered The multi-bit digital signal is latched at the output of the counter 401 at the active edge of the phase modulated clock signal f clk_jittered The multi-bit digital signal at the output of the counter 401 is sampled at the valid edge of , and the sampled value is output as the digital output signal y[n] of the FTD converter 400.

[0039] Figure 4B The embodiment of the invention is shown in FIG. Figure 5A The output of the FTD converter in Figure 1 , the signal 410 in the top subgraph illustrates the output of the VCO 113, which is a frequency modulated signal f vco The signal 420 in the middle sub-graph illustrates the output of the phase modulator 123, which is the phase modulated clock signal f clk_jittered Signal 430 illustrates the output of counter 401 in FTD converter 400. Figure 5A As shown in the figure, the counter output is phase modulated clock signal f clk_jittered is reset to zero at the rising edge of the counter 401, and then vco At the next rising edge, the output signal of the counter 401 is latched into the register 403, and the counter 401 is reset to zero again.

[0040] Figure 5B The phase modulator 300A in another embodiment is shown. The phase modulator 300A can be used as Figure 5A The phase modulator 123 in the phase modulator 300A includes a plurality of clock signal generators 511 (eg, 511_1, 511_2, ..., and 511_M). Each clock signal generator 511 generates a clock signal having the same frequency as the system sampling clock signal f clk The clock signal generated by the clock signal generator 511 is a clock signal with the same frequency but different duty cycle. Figure 5B Indicated as f clk1 、fclk2 ,...,f clkM .

[0041] Figure 5A The diagram shows the embodiment of the Figure 1 The clock signal f generated by the clock generator 511 in clk1 、f clk2 ,...,f clkM .like Figure 6 As shown in the figure, the clock signal f clk1 、f clk2、 ,...,f clkM have the same frequency. However, due to different duty cycles, the clock signal f clk1 、f clk2 ,...,f clkM The active edge (e.g. rising edge) of the clock signal f is not aligned, but clk1 、f clk2 ,...,f clkM There is a time delay between the active edges of

[0042] Refer again Figure 6 The phase modulator 300A further includes a multiplexer 517. The output terminals 512 (e.g., 512_1, 512_2, ..., 512_M) of the clock signal generator 511 are connected to the input terminals of the multiplexer 517. The control terminal 516 of the multiplexer is connected to Figure 6 The random number generator 121 output terminal in the phase modulator 300 is similar to the above discussion. The random number generator 121 is used to generate a random number signal with the system sampling clock signal f clk The random number is generated at the same frequency as the system sampling clock signal f clk The random number is used to select the clock signal f clk1 、f clk2 ,...,f clkM The selected clock signal is output as a phase modulated clock signal f at the output terminal 518 of the multiplexer 517. clk_jittered Therefore, random numbers are used to introduce random delays (such as random phase delays or jitter) into the system sampling clock signal f clk The active edge of the clock is used to generate the phase modulated clock signal f clk_jittered .

[0043] During operation of the MEMS microphone system 100 , when no sound is applied to the capacitive MEMS microphone 103 , the VCO 113 is biased by the bias voltage V biasThe VCO 113 oscillates at a certain stationary frequency, with this bias voltage setting the operating point of the VCO 113 via the high-ohmic resistor 105. In the event of a mechanical shock or a very strong audio signal, the MEMS membrane of the capacitive MEMS microphone 103 may collapse, and as a result, the VCO 113 may be suddenly brought out of its operating point. Given the long time constant imposed by the high-ohmic resistor 105 together with the MEMS capacitance, it may take several seconds for the MEMS microphone 103 to recover to the appropriate bias point.

[0044] Figure 1 The output of the MEMS microphone system 100 in the embodiment is shown in FIG. Figure 7A , curve 601 shows the output voltage V of the capacitive MEMS microphone 103 g Curve 603 shows the output signal f of VCO 113. vco , curve 605 shows the digital output signal y[n] of the FTD converter 115. Figure 7B At the time T1 indicated by the arrow in FIG, a mechanical shock or a strong audio signal causes the MEMS membrane to temporarily collapse, resulting in the output voltage V g After time T1, the output voltage V g The output signal f of the VCO 113 is gradually swept to the nominal bias point. vco Also sweeps slowly in frequency through a large frequency span.

[0045] During this frequency sweep, the VCO 113 can be set to a value close to the system sampling clock signal f clk When this happens, the system sampling clock signal f clk and the VCO output signal f vco The low-frequency tone generated by the beat between beat =f vco -N i ×f clk ) may fall into the audio frequency band and produce audible howling. This audible howling is unpleasant to the listener and should be suppressed. Note that in the above equation for the beat signal, f vco and f clk Used to represent the frequencies of their corresponding signals of the same name.

[0046] There are different solutions to the problem of audible howling. The presently disclosed MEMS microphone system 100 provides advantages over other solutions. To understand the advantages of the embodiments disclosed herein, consider a device similar to Figure 7AThe reference MEMS microphone system is a MEMS microphone system of the MEMS microphone system 100 in FIG. 1 , but without the random number generator 121 and without the phase modulator 123. The reference MEMS microphone system converts the system sampling clock signal f clk To suppress audible howling, the reference MEMS microphone system outputs the signal V g A random low-level noise shaping analog signal is added to dither the output signal of the MEMS microphone 103. In this way, the VCO 113 is slightly modulated by the random noise and is sampled using the system sampling clock signal f clk After sampling, the aliased tones (eg, audible howling) are masked by noise, thereby minimizing the psychoacoustic effects of the tones.

[0047] However, the aforementioned dither solution for the reference MEMS microphone system has several drawbacks. For example, it requires a digital-to-analog converter (DAC) to generate the analog random noise signal, and the DAC may also require coupling circuitry to the highly sensitive input nodes of the reference MEMS microphone system, which degrades sensitivity and the overall noise budget. Furthermore, the dither solution reduces the dynamic range of the MEMS microphone because the noise signal is always present in the reference MEMS microphone system during operation. Furthermore, the dither solution requires a spectrally shaped random noise generator.

[0048] The embodiments disclosed herein are based on the observation that low-frequency tones (e.g., audible howling) do not occur in the VCO 113 itself, but rather in the sampling process. Dithering solutions modulate the VCO 113 with an analog random noise signal to mitigate the low-frequency tones during sampling. However, the embodiments disclosed herein do not alter the operation of the VCO 113, but instead use a clock signal (e.g., f) whose phase has been intentionally modulated by a random sequence. clk_jittered ) samples the output of the FTD converter 115. In the illustrated embodiment, random number generator 121 introduces random errors into the digital output signal y[n] of the MEMS microphone system 100 via phase modulator 123. These errors decorrelate the swept VCO frequency from the system sampling clock, which has the effect of randomizing the howling that now appears as noise. The errors introduced by modulating the phase of the system sampling clock signal produce a first-order noise-shaped error sequence at the output of the FTD converter 115, independent of the spectral content of the random sequence. Thus, the embodiments disclosed herein avoid the shortcomings of dither solutions used in reference MEMS microphone systems, thereby suppressing audible howling without adversely affecting the sensitivity, overall noise budget, and dynamic range of the MEMS microphone system. Furthermore, the disclosed embodiments do not require DAC circuitry or noise-shaping circuitry, saving production costs and energy consumption.

[0049] Figure 7B and Figure 7A The performance of the disclosed MEMS microphone system 100 in an embodiment is illustrated. The disclosed VCO-ADC is implemented in an application specific integrated circuit (ASIC) and tested in a MEMS microphone system having a capacitive MEMS microphone. Figure 7B and Figure 7A Figure 1 shows the relationship between the ASIC-level noise and the system clock sweep obtained when no sound signal is applied to the capacitive MEMS microphone. For comparison, Figure 7B and Figure 7A The figures are shown without and with the addition of the system sampling clock signal f. clk The phase jitter of the MEMS microphone system performance. Figure 7B and Figure 7A The x-axis shows the system sampling clock signal f clk The y-axis shows the integrated noise in the application bandwidth (in this case the audio bandwidth) at the ASIC output, measured in dBFS for each sampling frequency in the frequency sweep range. Figure 7B In this case, no clock jitter (e.g., phase jitter) is applied, and the system samples the clock signal f clk is sent to the clock input terminal of the FTD converter 115. Figure 8 In the embodiment, the phase modulator 123 and the random number generator 121 are used to apply clock jitter to generate a phase modulated clock signal f clk_jettered , and the phase modulated clock signal f clk_jettered Sent to the clock input terminal of the FTD converter 115.

[0050] exist Figure 8 In the example, it can be observed that for certain values ​​of the system sampling clock frequency, if no phase jitter is applied, noise peaks appear (e.g. due to f as mentioned previously). vco With f clk Integer multiple relationship between ). Figure 8 When jitter is added to the system sampling clock signal f clk Thus, potential audible howling caused by microphone vibration or strong audio signals will be suppressed by the disclosed embodiments.

[0051] Figure 8 The performance of the disclosed MEMS microphone system 100 in another embodiment is illustrated. Figure 8 The obtained ASIC level noise is shown in relation to the input signal level. Figure 8In the test, an input signal (e.g., a 1 kHz tone) is applied at the capacitive MEMS microphone input. A defined system sampling clock frequency is set. The level of the input signal is swept from 40 dB SPL to 130 dB SPL. For each input signal level, the integrated noise in the application bandwidth (in this case, the audio bandwidth) is measured in dBFS at the ASIC output. The noise level measured at the VCO-ADC output (e.g., the digital output of the FTD converter 115) represents the noise contribution from different noise sources (such as flicker noise, thermal noise, etc.). Figure 9 , curve 803 shows the phase jitter when no phase jitter is added to the system sampling clock signal f clk , while curve 801 shows the noise level when jitter is added to the system sampling clock signal f clk The noise level measured at . Figure 9 It can be observed that curves 801 and 803 overlap above the normal operating range of input signal levels, and there are some differences between curves 801 and 803 only at extremely large input signal levels outside the normal operating range. Figure 9 The disclosed circuit is used to sample the clock signal f to the system. clk Adding phase jitter has a negligible effect on the measurement noise level above the normal operating range.

[0052] Figure 9 FIG2 is a flow chart illustrating a method 1000 of operating a MEMS microphone system in an embodiment. It should be understood that ​ The embodiment methods shown are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: ​ The steps shown.

[0053] Reference ​ At block 1010, a MEMS microphone generates a voltage signal in response to an acoustic signal. At block 1020, a frequency-modulated signal having a frequency proportional to the voltage signal is generated by a voltage-controlled oscillator (VCO) coupled to the MEMS microphone. At block 1030, the frequency-modulated signal is converted to a digital signal by a frequency-to-digital (FTD) converter coupled to the VCO. At block 1040, a random number generator generates a random number. At block 1050, a phase modulator modulates the phase of a system sampling clock signal according to the random number to generate a phase-modulated clock signal. At block 1060, the digital signal is sampled by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0054] Embodiments can achieve the following advantages. The disclosed VCO-ADC circuit with phase modulator can be implemented as a compact, purely digital circuit and does not require sensitive analog circuitry that interferes with the MEMS interface. The dynamic range of the VCO-ADC circuit is not impaired by random phase jitter injected into the system sampling clock signal. The random sequence generated by the random number generator does not need to be noise-shaped; therefore, a simple random number generator (such as an LFSR register) is sufficient. Compared to dithering solutions, the disclosed embodiments achieve reduced area and power consumption.

[0055] Examples of the invention are summarized here. Other examples can also be understood from the overall description and claims submitted here.

[0056] Example 1. In an embodiment, a circuit includes: a capacitive microelectromechanical system (MEMS) microphone configured to output a voltage signal in response to a sound signal; and a voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) coupled to the capacitive MEMS microphone and configured to generate a digital output signal proportional to the voltage signal, wherein the VCO-ADC includes: a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone and configured to output a frequency-modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate a random number; and a phase modulator configured to generate a phase-modulated clock signal by modulating the phase of a system sampling clock signal with the random number, wherein the FTD converter is configured to generate a digital signal based on the frequency-modulated signal and the phase-modulated clock signal, and is configured to generate the digital output signal of the FTD converter by sampling the digital signal using the phase-modulated clock signal.

[0057] Example 2. The circuit of Example 1, further comprising: an input stage circuit coupled between the first terminal of the capacitive MEMS microphone and the VCO; a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, wherein the node is configured to receive a bias voltage for the capacitive MEMS microphone; and a charge pump circuit coupled to the second terminal of the capacitive MEMS microphone.

[0058] Example 3. The circuit of Example 1, wherein the phase modulated clock signal has the same frequency as the system sampling clock signal, wherein active edges of the phase modulated clock signal are shifted by different amounts of time from corresponding active edges of the system sampling clock signal according to a random number.

[0059] Example 4. The circuit of Example 3, wherein the random number generator is configured to generate the random numbers at a frequency of the phase modulated clock signal.

[0060] Example 5. The circuit of Example 3, wherein the FTD converter includes a counter configured to count a number of cycles in the frequency modulated signal between adjacent active edges of the phase modulated clock signal, wherein the digital signal generated by the FTD converter is an output of the counter.

[0061] Example 6. The circuit of Example 5, wherein the phase modulator comprises: a delay chain comprising a plurality of delay circuits coupled in series, wherein an input terminal of the delay chain is coupled to a system sampling clock signal; and a multiplexer, wherein an input terminal of the multiplexer is coupled to output terminals of the plurality of delay circuits, wherein a control terminal of the multiplexer is coupled to an output terminal of a random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase modulation clock signal based on a random number at the control terminal.

[0062] Example 7. The circuit of Example 5, wherein the phase modulator comprises: a plurality of clock signal generators configured to generate a plurality of clock signals, wherein the plurality of clock signals have the same frequency as the system sampling clock signal but have different duty cycles; and a multiplexer, wherein an input terminal of the multiplexer is coupled to output terminals of the plurality of clock signal generators, wherein a control terminal of the multiplexer is coupled to an output terminal of a random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase modulated clock signal based on a random number at the control terminal.

[0063] Example 8. In an embodiment, a circuit includes: a capacitive microelectromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal; a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, wherein the VCO is configured to generate a frequency-modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate a random number; and a phase modulator configured to generate a phase-modulated clock signal by modulating the phase of a system sampling clock signal according to the random number, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0064] Example 9. The circuit of Example 8, wherein the capacitive MEMS microphone includes a capacitor.

[0065] Example 10. The circuit of Example 9, further comprising: a source follower circuit coupled between the first terminal of the capacitive MEMS microphone and the VCO; a charge pump circuit coupled to the second terminal of the capacitive MEMS microphone; and a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, wherein the node is configured to receive a bias voltage for the capacitive MEMS microphone.

[0066] Example 11. The circuit of Example 8, wherein the phase modulator is configured to generate the phase modulated clock signal by shifting active edges of the system sampling clock signal by different amounts of time determined by a random number.

[0067] Example 12. The circuit of Example 11, wherein the FTD converter is configured to generate the digital signal by counting a number of cycles in the frequency modulated signal between adjacent active edges of the phase modulated clock signal.

[0068] Example 13. The circuit of Example 12, wherein the random number generator is configured to generate the random numbers at a frequency that is the same as a frequency of a system sampling clock signal.

[0069] Example 14. The circuit of Example 8, wherein the phase modulator is configured to generate a phase-modulated clock signal by selecting a candidate clock signal from a plurality of candidate clock signals as the phase-modulated clock signal at an active edge of the system sampling clock signal based on a random number, the plurality of candidate clock signals having the same frequency as the system sampling clock signal but having different duty cycles.

[0070] Example 15. The circuit of Example 14, wherein the random number generator is configured to generate the random numbers for corresponding active edges of a system sampling clock signal.

[0071] Example 16. The circuit of Example 15, wherein the random number generator is a linear feedback shift register (LFSR) random number generator.

[0072] Example 17. In an embodiment, a method of operating a microelectromechanical system (MEMS) microphone system includes: generating a voltage signal by the MEMS microphone in response to a sound signal; generating a frequency modulation signal by a voltage-controlled oscillator (VCO) coupled to the MEMS microphone, the frequency modulation signal having a frequency proportional to the voltage signal; converting the frequency modulation signal into a digital signal by a frequency-to-digital (FTD) converter coupled to the VCO; generating a random number by a random number generator; modulating the phase of a system sampling clock signal by a phase modulator according to the random number to generate a phase-modulated clock signal; and sampling the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

[0073] Example 18. The method of Example 17, wherein the modulating comprises: shifting, by a phase modulator, active edges of the system sampling clock signal by different amounts of time determined by a random number.

[0074] Example 19. The method of Example 18, wherein converting comprises counting, by a counter of the FTD converter, a number of cycles in the frequency modulated signal between adjacent active edges of the phase modulated clock signal.

[0075] Example 20. The method of Example 19, wherein generating the random number comprises generating the random number by a random number generator at a frequency that is the same as a frequency of a system sampling clock signal.

[0076] Although the present invention has been described with reference to illustrative examples, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples and other examples of the present invention will be apparent to those skilled in the art upon reference to the specification. Therefore, the appended claims are intended to cover any such modifications or examples.

Claims

1. A circuit comprising: a capacitive micro-electromechanical system (MEMS) microphone configured to output a voltage signal in response to a sound signal; as well as A voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC) is coupled to the capacitive MEMS microphone and configured to generate a digital output signal proportional to the voltage signal, wherein the VCO-ADC comprises: a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone and configured to output a frequency-modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital FTD converter coupled to an output terminal of the VCO; a random number generator configured to generate random numbers; and a phase modulator configured to generate a phase-modulated clock signal by modulating the phase of a system sampling clock signal with the random number, wherein the FTD converter is configured to generate a digital signal based on the frequency-modulated signal and the phase-modulated clock signal, and is configured to generate a digital output signal of the FTD converter by sampling the digital signal using the phase-modulated clock signal.

2. The circuit according to claim 1, further comprising: an input stage circuit coupled between the first terminal of the capacitive MEMS microphone and the VCO; a resistor coupled between the first terminal of the capacitive MEMS microphone and a node, wherein the node is configured to receive a bias voltage for the capacitive MEMS microphone; as well as A charge pump circuit is coupled to the second terminal of the capacitive MEMS microphone.

3. The circuit of claim 1 , wherein the phase modulated clock signal has the same frequency as the system sampling clock signal, wherein active edges of the phase modulated clock signal are shifted from corresponding active edges of the system sampling clock signal by different amounts of time according to the random number. 4 . The circuit of claim 3 , wherein the random number generator is configured to generate the random number at a frequency of the phase-modulated clock signal.

5. The circuit of claim 3 , wherein the FTD converter comprises a counter configured to count a number of cycles in the frequency modulated signal between adjacent active edges of the phase modulated clock signal, wherein the digital signal generated by the FTD converter is an output of the counter.

6. The circuit of claim 5 , wherein the phase modulator comprises: a delay chain comprising a plurality of delay circuits coupled in series, wherein an input terminal of the delay chain is coupled to the system sampling clock signal; as well as a multiplexer, wherein an input terminal of the multiplexer is coupled to output terminals of the plurality of delay circuits, wherein a control terminal of the multiplexer is coupled to an output terminal of the random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase-modulated clock signal based on the random number at the control terminal.

7. The circuit of claim 5 , wherein the phase modulator comprises: a plurality of clock signal generators configured to generate a plurality of clock signals, wherein the plurality of clock signals have the same frequency as the system sampling clock signal but have different duty cycles; as well as a multiplexer, wherein an input terminal of the multiplexer is coupled to output terminals of the plurality of clock signal generators, wherein a control terminal of the multiplexer is coupled to an output terminal of the random number generator, wherein the multiplexer is configured to select a clock signal at one of the input terminals of the multiplexer as the phase-modulated clock signal based on the random number at the control terminal.

8. A circuit comprising: a capacitive micro-electromechanical system (MEMS) microphone configured to generate a voltage signal in response to an acoustic signal; a voltage controlled oscillator (VCO) coupled to the capacitive MEMS microphone, wherein the VCO is configured to generate a frequency modulation signal having a frequency proportional to the voltage signal; a frequency-to-digital FTD converter coupled to an output terminal of the VCO; a random number generator configured to generate random numbers; as well as a phase modulator configured to generate a phase-modulated clock signal by modulating the phase of a system sampling clock signal according to the random number, wherein the FTD converter is configured to generate a digital signal according to the frequency-modulated signal and the phase-modulated clock signal, and is configured to sample the digital signal by the phase-modulated clock signal to generate a digital output signal of the FTD converter.

9. The circuit of claim 8, wherein the capacitive MEMS microphone comprises a capacitor.

10. The circuit of claim 9, further comprising: a source follower circuit coupled between the first terminal of the capacitive MEMS microphone and the VCO; a charge pump circuit coupled to the second terminal of the capacitive MEMS microphone; as well as A resistor is coupled between the first terminal of the capacitive MEMS microphone and a node, wherein the node is configured to receive a bias voltage for the capacitive MEMS microphone.

11. The circuit of claim 8, wherein the phase modulator is configured to generate the phase-modulated clock signal by shifting active edges of the system sampling clock signal by different amounts of time determined by the random number. 12 . The circuit of claim 11 , wherein the FTD converter is configured to generate the digital signal by counting a number of cycles in the frequency modulated signal between adjacent active edges of the phase modulated clock signal.

13. The circuit of claim 12, wherein the random number generator is configured to generate the random numbers at a frequency that is the same as a frequency of the system sampling clock signal.

14. The circuit of claim 8 , wherein the phase modulator is configured to generate the phase-modulated clock signal by selecting a candidate clock signal from a plurality of candidate clock signals as the phase-modulated clock signal at an active edge of the system sampling clock signal based on the random number, the plurality of candidate clock signals having the same frequency as the system sampling clock signal but having different duty cycles. 15 . The circuit of claim 14 , wherein the random number generator is configured to generate random numbers for corresponding active edges of the system sampling clock signal.

16. The circuit of claim 15, wherein the random number generator is a linear feedback shift register (LFSR) random number generator.

17. A method of operating a micro-electromechanical system (MEMS) microphone system, the method comprising: generating a voltage signal by the MEMS microphone in response to the sound signal; generating a frequency modulation signal by a voltage controlled oscillator (VCO) coupled to the MEMS microphone, the frequency modulation signal having a frequency proportional to the voltage signal; converting the frequency modulated signal into a digital signal by a frequency-to-digital (FTD) converter coupled to the VCO; Generate random numbers using a random number generator; The phase modulator modulates the phase of the system sampling clock signal according to the random number to generate a phase modulated clock signal; as well as The digital signal is sampled by the phase modulated clock signal to generate a digital output signal of the FTD converter.

18. The method of claim 17, wherein the modulating comprises: The active edge of the system sampling clock signal is shifted by the phase modulator by different amounts of time determined by the random number.

19. The method of claim 18, wherein the converting comprises: The number of cycles in the frequency modulated signal between adjacent active edges of the phase modulated clock signal is counted by a counter of the FTD converter.

20. The method of claim 19, wherein generating the random number comprises: The random number is generated by the random number generator at a frequency that is the same as a frequency of the system sampling clock signal.

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