Large-exposure-field photoetching technology implementation method and chip-level chip interconnection method

By combining a projection system with a reduction ratio of 0.1 to 2.5 times with an alignment offset distance, a large-size exposure field lithography technology was realized, overcoming the exposure field limitations of traditional lithography machines and enabling the interconnection of high-density integrated circuits.

CN120802569AActive Publication Date: 2025-10-17BEIJING ZHONGKE BIANAN INTEGRATED CIRCUIT TECHNOLOGY CO LTD
7 Cites 1 Cited by

Patent Information

Application Number
CN202510840429.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-06-20
Publication Date
2025-10-17
Estimated Expiration
2045-06-20

AI Technical Summary

Technical Problem

The maximum exposure field size limitation of traditional lithography machines cannot meet the needs of manufacturing larger chips, and existing technologies are difficult to achieve interconnection of high-density integrated circuits.

Method used

A projection system with a scaling factor of 0.1 to 2.5x is used to align and offset multiple original graphic units by using alignment marks on the substrate and offset by a set distance. Combined with lateral or longitudinal stepping, high-density interconnection of multiple original graphic units is achieved.

Benefits of technology

It enables the formation of large-size exposure fields, solves the exposure field limitations of traditional lithography machines, improves the efficiency of lithography processes, and realizes high-density interconnection of multiple large chips.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The invention discloses a photoetching technology implementation method with a large exposure field, a chip-level chip interconnection method and photoetching equipment. The photoetching technology implementation method with the large exposure field is applied to photoetching equipment, the photoetching equipment comprises a projection system with a reduction ratio of 0.1-2.5 times, and the method comprises the following steps: loading a to-be-exposed substrate with a pattern on an objective table, aligning through an alignment mark on the substrate, and offsetting a set offset distance; executing first exposure, and transferring a preset pattern of the mask to a first exposure area of the substrate through a projection system; the substrate or the mask plate is transversely stepped by M times of the transverse size of the original pattern unit or longitudinally stepped by N times of the longitudinal size of the original pattern unit, second exposure is executed, and the preset pattern is transferred to a second exposure area of the substrate through the projection system; and continuously executing transverse stepping or longitudinal stepping and second exposure until the exposure of the target area on the substrate is completed. According to the scheme, a large-size exposure field can be formed, and high-density interconnection of integrated circuits is realized.
Need to check novelty before this filing date? Find Prior Art