Signal conditioning circuits, conditioning equipment and testing systems

Abstract

This application relates to the technical field of vehicle signal testing, and in particular to a signal conditioning circuit, conditioning device, and testing system. The circuit includes a first processing module, a first protection module, a second processing module, a second protection module, a power supply module, and a third protection module. Specifically: the first processing module modulates the initial PWM signal output from the NI chassis into a target PWM signal that conforms to the voltage acquisition range of the ECU; the first protection module provides overvoltage protection for the first processing module; the second processing module converts the control signal output from the ECU into a target control signal that conforms to the voltage acquisition range of the NI chassis; the second protection module provides overcurrent protection for the second processing module; the power supply module provides the corresponding operating voltages for the first and second processing modules; and the third protection module provides overvoltage and overcurrent protection for the power supply module. The solution of this application can improve the stability of digital signals during HIL testing.

Description

Technical Field

[0001] This application relates to the technical field of vehicle signal testing, and in particular to a signal conditioning circuit, conditioning equipment and testing system. Background Technology

[0002] Currently, HIL (Hardware-in-the-loop) testing is a widely used technology in the automotive testing field. HIL testing typically employs an NI chassis and test boards; the NI chassis simulates automotive equipment or electrical systems and outputs corresponding status signals, while the test boards facilitate the transmission of various signals between the NI chassis and the vehicle's ECU (Hardware-in-the-loop Electronic Control Unit). The NI chassis is manufactured by National Instruments (NI) and is used to integrate and manage various modular instruments and data acquisition devices.

[0003] The interaction between the NI chassis and the ECU involves both digital and analog signals. For the digital signal interaction, the voltage ranges of the input signals for the NI chassis and the ECU differ. This necessitates that the digital processing module in the test board be able to process the digital signals exchanged between the NI chassis and the ECU, ensuring that both the NI chassis and the ECU receive signals within their respective voltage acquisition ranges. However, the complex environment of automotive testing environments may contain numerous interference factors, potentially causing overvoltage or overcurrent in the circuitry, which can severely impact the quality of the digital signals.

[0004] Therefore, how to improve the stability of digital signals during HIL testing is an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a signal conditioning circuit, conditioning device, and testing system that can improve the quality of digital signals during HIL testing.

[0006] In a first aspect, this application provides a signal conditioning circuit, the circuit comprising a first processing module, a first protection module, a second processing module, a second protection module, a power supply module, and a third protection module, wherein:

[0007] The first processing module is used to receive the initial PWM signal output by the NI chassis and modulate the initial PWM signal into a target PWM signal within a first threshold range, wherein the first threshold range is the voltage acquisition range of the ECU; the first protection module is used to perform overvoltage protection on the first processing module.

[0008] The second processing module is used to receive the digital control signal output by the ECU and convert the control signal into a target control signal within a second threshold range, where the second threshold range is the voltage acquisition range of the NI chassis; the second protection module is used to provide overcurrent protection for the second processing module.

[0009] The power supply module is used to provide the first processing module and the second processing module with their respective operating voltages; the third protection module is used to provide overvoltage and overcurrent protection for the power supply module.

[0010] In one embodiment, the first processing module includes an inverter, a first N-channel MOSFET, a second P-channel MOSFET, and a third N-channel MOSFET, wherein:

[0011] The gate of the first MOSFET is connected to the NI chassis and is used to input the initial PWM signal; the drain of the first MOSFET is connected to the output terminal of the power module and is used to input the operating voltage VDD; the source of the first MOSFET is grounded.

[0012] The input terminal of the inverter is connected to the drain of the first MOS transistor; the output terminal of the inverter is connected to the gate of both the second MOS transistor and the gate of the third MOS transistor.

[0013] The drain of the second MOSFET is connected to the operating voltage VDD provided by the power module, and the source of the third MOSFET is grounded; the source of the second MOSFET and the drain of the third MOSFET are connected to the output terminal of the first processing module, and the output terminal of the first processing module is connected to the input terminal of the ECU.

[0014] In one embodiment, the input terminal of the first processing module is further connected to a voltage regulator module, wherein:

[0015] The voltage regulator module includes a first Zener diode and a Schottky diode; the first Zener diode and the Schottky diode are connected in anti-series, the anode of the first Zener diode is connected to the gate of the first MOSFET, and the anode of the Schottky diode is grounded.

[0016] In one embodiment, the drain of the second MOSFET is connected to the power module, which provides a variable voltage VDD-SW to the drain of the second MOSFET.

[0017] In one embodiment, the first protection module includes a first voltage-dividing resistor and a second voltage-dividing resistor, wherein:

[0018] The first voltage divider resistor is connected in series between the output terminal of the NI chassis and the gate of the first MOS transistor; one end of the second voltage divider resistor is connected to the gate of the first MOS transistor, and the other end is grounded.

[0019] In one embodiment, the second processing module includes a non-reverse buffer, the second protection module is connected to the output of the ECU and the input of the non-reverse buffer, and the output of the non-reverse buffer is connected to the NI chassis.

[0020] In one embodiment, the second protection module includes a protection resistor and a second Zener diode, wherein:

[0021] The protection resistor is connected in series between the output terminal of the NI chassis and the input terminal of the non-reverse buffer. The cathode of the second Zener diode is connected to the input terminal of the non-reverse buffer, and the anode of the second Zener diode is grounded.

[0022] In one embodiment, the third protection module includes a fuse and a varistor, and the initial voltage is input to the input terminal of the power module after passing through the fuse.

[0023] One end of the varistor is connected to the input terminal of the power module, and the other end is grounded.

[0024] In a second aspect, this application provides a conditioning device, the device including a power board and a conditioning board, wherein the power board and the conditioning board are configured with signal conditioning circuits as described in any one of the first aspects above.

[0025] Thirdly, this application provides a test system, which includes an NI chassis, an ECU, and a conditioning device as described in the second aspect, wherein the conditioning device is used for signal interaction between the NI chassis and the ECU.

[0026] In the aforementioned signal conditioning circuit, conditioning equipment, and testing system, the first processing module modulates the initial PWM signal output from the NI chassis into a target PWM signal within a first threshold range. Since the first threshold range is the voltage acquisition range of the ECU, the target PWM signal modulated by the first processing module can be received by the ECU. The second processing module converts the control signal output from the ECU into a target control signal within a second threshold range. Since the second threshold range is the voltage acquisition range of the NI chassis, the target control signal processed by the second processing module can be received by the NI chassis.

[0027] Since the initial voltage and current input to the power module may fluctuate unstablely, and short circuits in the first and / or second processing modules can cause large voltages or currents within the power module, potentially damaging it, the third protection module provides overvoltage and overcurrent protection, ensuring stable operating voltages for the first and second processing modules and reducing the probability of module damage. The first protection module provides overcurrent protection, reducing the impact of large currents on components within the first processing module and stabilizing the target PWM signal output. The second protection module provides overvoltage protection, reducing the likelihood of overvoltage damage and improving operational stability. This application's solution, through two levels of overvoltage and overcurrent protection, enhances the stability of the conditioning circuit, ensuring stable signal transmission between the NI chassis and the ECU. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a simplified schematic diagram of the signal conditioning circuit in one embodiment;

[0030] Figure 2 This is a schematic diagram of the structure of the first processing module in one embodiment;

[0031] Figure 3 This is a schematic diagram of the structure of the second processing module in one embodiment;

[0032] Figure 4 This is a schematic diagram of the power module structure in one embodiment;

[0033] Figure 5 This is a schematic diagram of the conditioning device in one embodiment. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0036] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0037] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0038] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0039] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0040] In one exemplary embodiment, this application provides a signal conditioning circuit that can be applied to perform signal conditioning and transmission between two devices or two systems; wherein, signal conditioning refers to conditioning the output signal of the output party to conform to the voltage and / or current range of the signal received by the receiver, thereby enabling normal signal transmission between the output party and the receiver.

[0041] In a typical scenario, the signal conditioning circuit provided in this application can be used for automotive on-board testing. In automotive on-board testing, the NI chassis is used to simulate on-board equipment or on-board electrical systems and can output corresponding status signals. The interaction between the NI chassis and the on-board ECU (Electronic Control Unit) involves both digital and analog signals. Regarding the digital signal interaction process, the voltage ranges of the input signals for the NI chassis and the ECU are different. This requires the digital processing module in the test board to process the digital signals interacting between the NI chassis and the ECU, ensuring that both the NI chassis and the ECU receive signals within their respective voltage acquisition ranges. Furthermore, due to the complex environment of the automotive testing environment, there may be many interference factors; for example, this could cause overvoltage or overcurrent, which would severely affect the quality of the digital signals.

[0042] In one exemplary embodiment, such as Figure 1 As shown, this application provides a signal conditioning circuit, which includes a first processing module, a second processing module, and a power supply module. The first processing module receives an initial PWM signal output from an NI chassis and modulates the initial PWM signal into a target PWM signal within a first threshold range, where the first threshold range is the voltage acquisition range of the ECU. The second processing module receives a digital control signal output from the ECU and converts the control signal into a target control signal within a second threshold range, where the second threshold range is the voltage acquisition range of the NI chassis. The power supply module provides the corresponding operating voltage to the first and second processing modules.

[0043] In this embodiment, the first processing module modulates the initial PWM signal output from the NI chassis into a target PWM signal within a first threshold range. Since the first threshold range is the voltage acquisition range of the ECU, the target PWM signal modulated by the first processing module can be received by the ECU. The second processing module converts the control signal output by the ECU into a target control signal within a second threshold range. Since the second threshold range is the voltage acquisition range of the NI chassis, the target control signal processed by the second processing module can be received by the NI chassis.

[0044] Furthermore, to improve the stability of signal transmission between the NI chassis and the ECU, the signal conditioning circuit in this embodiment further includes a first protection module, a second protection module, and a third protection module. (Refer to...) Figure 1The first protection module is connected to the output terminal of the NI chassis and the input terminal of the first processing module, and is used to provide overvoltage protection for the first processing module. The second protection module is connected to the output terminal of the ECU and the input terminal of the second processing module, and is used to provide overcurrent protection for the second processing module. The third protection module is connected to the input terminal of the power supply module, and is used to provide overvoltage and overcurrent protection for the power supply module.

[0045] In this embodiment, the initial voltage and current input to the power module may fluctuate unstablely, and a short circuit in the first processing module and / or the second processing module may cause a large voltage or current to be generated within the power module, thus posing a risk of damage to the power module. The third protection module can provide overvoltage and overcurrent protection for the power module, thereby ensuring that the operating voltage provided by the power module to the first and second processing modules remains stable and reducing the probability of damage to the power module itself. The first protection module can provide overcurrent protection for the first processing module, thereby reducing the impact of large currents on the components within the first processing module and stabilizing the target PWM signal output by the first processing module. The second protection module can provide overvoltage protection for the second processing module, reducing the probability of the second processing module being damaged by overvoltage, thereby improving the stability of the second processing module's operation. The solution of this application improves the stability of the conditioning circuit during operation through two levels of overvoltage and overcurrent protection, thereby ensuring the stability of the signal transmitted between the NI chassis and the ECU.

[0046] In one embodiment, such as Figure 2 As shown, the first processing module includes an inverter NF, an N-channel first MOSFET Q1, a P-channel second MOSFET Q2, and an N-channel third MOSFET Q3; wherein: the gate (G) of the first MOSFET A1 is connected to the output terminal of the NI chassis and is used to input the initial PWM signal; wherein, the high-level voltage of the initial PWM signal is VCC; the drain (D) of the first MOSFET Q1 is connected to the output terminal of the power supply module and is used to input the operating voltage VDD; wherein, the voltage VCC is greater than the first voltage VDD; the source ... S) grounded; the input terminal of inverter NF is connected to the drain (D) of the first MOSFET Q1; the output terminal of inverter NF is simultaneously connected to the gate (G) of the second MOSFET Q2 and the gate (G) of the third MOSFET Q3; the drain (D) of the second MOSFET Q2 is connected to the operating voltage VDD provided by the power supply module, and the source (S) of the third MOSFET Q3 is grounded; the source (S) of the second MOSFET Q2 and the drain (D) of the third MOSFET Q3 are connected to the output terminal of the first processing module, and the output terminal of the first processing module is connected to the input terminal of the ECU.

[0047] The working principle of the first processing module is as follows: When the initial PWM signal is high, the gate (G) input of the first MOSFET Q1 is high, thus making the drain (D) and source (S) of the first MOSFET Q1 conduct. At this time, the input of the inverter NF is low, so the output of the inverter NF is high, and thus the high level is simultaneously input to the gates (G) of the second MOSFET Q2 and the third MOSFET Q3. When the gate (G) input of the second MOSFET Q2 is high, the drain (D) and source (S) of the second MOSFET Q2 cannot conduct; while when the gate (G) input of the third MOSFET Q3 is high, the drain (D) and source (S) of the third MOSFET Q3 can conduct. Since the source (S) of the first MOSFET Q1 is grounded, the output of the first processing module is low at this time.

[0048] When the initial PWM signal is low, the gate (G) input of the first MOSFET Q1 is low, therefore the drain (D) and source (S) of the first MOSFET Q1 cannot conduct. At this time, the input of the inverter NF is high (VDD), so the output of the inverter NF is low, and thus the low level is simultaneously input to the gates (G) of the second MOSFET Q2 and the third MOSFET Q3. When the gate (G) input of the second MOSFET Q2 is low, the drain (D) and source (S) of the second MOSFET Q2 conduct; while when the gate (G) input of the third MOSFET Q3 is low, the drain (D) and source (S) of the third MOSFET Q3 cannot conduct. Since the drain (D) of the second MOSFET Q2 is connected to the operating voltage VDD, the output of the first processing module is high at this time, and the high voltage value is the operating voltage VDD. In other words, the initial PWM signal is a high-level waveform signal with voltage VCC. After modulation by the first processing module, a high-level waveform signal with voltage VDD is obtained, which is the target PWM signal. In one example, the operating voltage VCC is +12V and the operating voltage VDD is +5V.

[0049] Furthermore, such as Figure 2 As shown, the input terminal of the first processing module is also connected to a voltage regulator module, which includes a first Zener diode D1 and a Schottky diode D2. The first Zener diode D1 and the Schottky diode D2 are connected in anti-series. The anode of the first Zener diode D1 is connected to the gate (G) of the first MOSFET Q1, and the anode of the Schottky diode D2 is grounded. The first Zener diode D1 and the Schottky diode are connected between the gate (G) of the first MOSFET Q1 and the reference ground. The interaction between the two can play a voltage regulation role, thereby keeping the voltage input to the gate (G) of the first MOSFET Q1 stable.

[0050] Furthermore, referring to Figure 2The second MOSFET Q2 is also connected to a filter capacitor C1. One end of the filter capacitor C1 is connected to the drain (D) of the second MOSFET Q2, and the other end is grounded. The filter capacitor C1 can filter the operating voltage VDD input to the first processing module, thereby keeping the input operating voltage VDD stable.

[0051] Furthermore, referring to Figure 2 A current source is connected in series between the drain (D) of the first MOSFET Q1 and the operating voltage VDD, and a voltage source is connected between the drain (D) of the first MOSFET Q1 and the input terminal of the inverter NF.

[0052] In one example, such as Figure 2 As shown, the first protection module includes a first voltage divider resistor R1 and a second voltage divider resistor R2. The first voltage divider resistor R1 is connected in series between the output terminal of the NI chassis and the gate (G) of the first MOSFET Q1. One end of the second voltage divider resistor R2 is connected to the gate (G) of the first MOSFET Q1, and the other end is grounded. The first and second voltage divider resistors can achieve voltage division, and the effective voltage division ratio is R1 / (R1+R2). Since the initial high-level voltage of the PWM signal is VCC, the high level input to the gate (G) of the first MOSFET Q1 is VCC*R1 / (R1+R2).

[0053] Since the first voltage divider resistor R1 and the second voltage divider resistor achieve the function of voltage division, the voltage input to the first MOSFET Q1 is reduced. Therefore, the current in the circuit is reduced, thus providing overcurrent protection for the first processing module.

[0054] Furthermore, such as Figure 2 As shown, the drain (D) of the second MOSFET is connected to the power supply module, which provides a variable voltage VDD-SW to the drain (D) of the second MOSFET. Since the high-level voltage value of the target PWM signal output by the first processing module is determined by the input voltage of the drain (D) of the second MOSFET Q2, the high-level voltage value of the target PWM signal actually output by the first processing module can be easily adjusted by inputting a variable voltage VDD-SW to the drain (D) of the second MOSFET Q2.

[0055] It is understood that the structure of the first processing module described above can also take other forms, and is not limited to the forms already mentioned in the above embodiments; for example, the first MOS transistor Q1 in the structure of the first processing module described above can be equivalently replaced with an NPN transistor, the second MOS transistor Q2 can be equivalently replaced with a PNP transistor, and the third MOS transistor Q3 can also be equivalently replaced with an NPN transistor.

[0056] Furthermore, a diode D0 is connected between the gate of the first MOSFET Q1 and the operating voltage VDD, wherein the anode of the diode D0 is connected to the gate of the first MOSFET Q1, and the cathode is connected to one end of the input operating voltage VDD.

[0057] Furthermore, the aforementioned first processing module can also be replaced by an existing integrated chip, such as an MCP1404T-E / SN, which can be used to replace the first processing module. The MCP1404T-E / SN chip includes two independent input and output paths, and each input and output path can be used to replace the aforementioned first processing module.

[0058] In one embodiment, reference Figure 3 The second processing module includes a non-reverse buffer H1. The second protection module is connected to the output of the ECU and the input of the non-reverse buffer H1. The output of the non-reverse buffer H1 is connected to the NI chassis.

[0059] Specifically, the non-reverse buffer H1 functions to improve the signal's driving capability, enabling it to drive larger loads; and to isolate the front-end (ECU) from the rear-end load (NI chassis), preventing front-end overload. The non-reverse buffer H1 also performs level conversion, allowing its output to adapt to signals from different voltage systems. In this application, the non-reverse buffer H1 converts the voltage of the control signal output by the ECU into a target control signal within a second threshold range, ensuring the target control signal meets the voltage acquisition range of the NI chassis. Furthermore, the non-reverse buffer H1 also reduces signal attenuation and suppresses noise interference, resulting in a more stable target control signal output to the NI chassis after passing through the non-reverse buffer H1.

[0060] In one embodiment, reference Figure 3 The second protection module includes a protection resistor R1 and a second Zener diode D3; wherein, the protection resistor R1 is connected in series between the output terminal of the NI chassis and the input terminal of the non-reverse buffer H1, the cathode of the second Zener diode D3 is connected to the input terminal of the non-reverse buffer H1, and the anode of the second Zener diode D3 is grounded.

[0061] Specifically, the protection resistor R1 can limit the magnitude of the current input to the non-reverse buffer H1, thereby providing overcurrent protection for the non-reverse buffer H1; and the second Zener diode D3 can regulate the voltage of the control signal input to the input terminal of the non-reverse buffer H1, so that the high level in the input control signal remains stable.

[0062] In one embodiment, the power supply module is used to convert the input initial voltage into the corresponding operating voltages for the first processing module and the second processing module, and to supply power to the first processing module and the second processing module. Where the operating voltages of the first processing module and the second processing module are different, the power supply module may include at least two voltage conversion modules, namely a first voltage conversion module and a second voltage conversion module; the first voltage conversion module is used to convert the initial voltage into the operating voltage VDD corresponding to the first processing module; the second voltage conversion module is used to convert the initial voltage into the operating voltage corresponding to the second processing module.

[0063] Furthermore, referring to Figure 4 The initial voltage is first input to the third protection module, and then distributed to each voltage conversion module through the third protection module. Both the first and second voltage conversion modules can be implemented using integrated voltage conversion chips; wherein, the first voltage conversion module corresponds to voltage conversion chip U1, and the second voltage conversion module corresponds to voltage conversion chip U2.

[0064] Specifically, refer to Figure 4 The third protection module includes a fuse FU and a varistor RV. The first terminal of the fuse FU is used to input the initial voltage, and the second terminal of the fuse FU is connected to the input terminals of both the first and second voltage conversion modules. One end of the varistor RV is connected to the second terminal of the fuse FU, and the other end is grounded. Furthermore, the power module also includes a connector for receiving an externally input variable voltage VCC-SW and providing the variable voltage VCC-SW to the first processing module.

[0065] In one exemplary embodiment, refer to Figure 5 This application provides a conditioning device, which includes a power supply board, a conditioning board, and a backplane. The conditioning board is configured with a first processing module and a second processing module as disclosed in the above-described signal conditioning circuit embodiments. The conditioning board has multiple inputs and multiple outputs, meaning it has multiple first and second processing modules; and the number of first and second processing modules is the same. The power supply board is configured with a power module as disclosed in the above-described signal conditioning circuit embodiments. The backplane connects the power supply board and the conditioning board. On one hand, the backplane provides input and output signals from the NI chassis and / or ECU to the conditioning board through designated input and output terminals. On the other hand, the power module supplies power to each of the first and second processing modules in the conditioning board through pre-defined traces on the backplane.

[0066] In one exemplary embodiment, this application provides a testing system; the testing system includes a first object device, a second object device, and a conditioning device as disclosed in the conditioning device embodiments described above; the conditioning device is used for signal interaction between the first object device and the second object device. In a typical example scenario, the first object device may be an NI chassis in HIL testing, and the second object device may be an on-board ECU in HIL testing.

[0067] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A signal conditioning circuit, characterized in that, The circuit includes a first processing module, a first protection module, a second processing module, a second protection module, a power supply module, and a third protection module, wherein: The first processing module is used to receive the initial PWM signal output by the NI chassis and modulate the initial PWM signal into a target PWM signal within a first threshold range, wherein the first threshold range is the voltage acquisition range of the ECU; the first protection module is used to perform overvoltage protection on the first processing module. The first processing module includes an inverter, an N-channel first MOSFET, a P-channel second MOSFET, and an N-channel third MOSFET, wherein: The gate of the first MOSFET is connected to the NI chassis and is used to input the initial PWM signal; the drain of the first MOSFET is connected to the output terminal of the power module and is used to input the operating voltage VDD; the source of the first MOSFET is grounded. The input terminal of the inverter is connected to the drain of the first MOS transistor; the output terminal of the inverter is connected to the gate of both the second MOS transistor and the gate of the third MOS transistor. The drain of the second MOSFET is connected to the operating voltage VDD provided by the power module, and the source of the third MOSFET is grounded; the source of the second MOSFET and the drain of the third MOSFET are connected to the output terminal of the first processing module, and the output terminal of the first processing module is connected to the input terminal of the ECU; The second processing module is used to receive the digital control signal output by the ECU and convert the control signal into a target control signal within a second threshold range, where the second threshold range is the voltage acquisition range of the NI chassis; the second protection module is used to provide overcurrent protection for the second processing module. The power supply module is used to provide the first processing module and the second processing module with their respective operating voltages; the third protection module is used to provide overvoltage and overcurrent protection for the power supply module. The drain of the second MOSFET is connected to the power module, which provides a variable voltage VDD-SW to the drain of the second MOSFET so as to dynamically adjust the high-level voltage amplitude of the target PWM signal output according to the model of the ECU.

2. The signal conditioning circuit according to claim 1, characterized in that, The second MOSFET is also connected to a filter capacitor, one end of which is connected to the drain of the second MOSFET and the other end is grounded.

3. The signal conditioning circuit according to claim 2, characterized in that, The input terminal of the first processing module is also connected to a voltage regulator module, wherein: The voltage regulator module includes a first Zener diode and a Schottky diode; the first Zener diode and the Schottky diode are connected in anti-series, the anode of the first Zener diode is connected to the gate of the first MOSFET, and the anode of the Schottky diode is grounded.

4. The signal conditioning circuit according to claim 1, characterized in that, The first processing module and the second processing module operate at different voltages.

5. The signal conditioning circuit according to claim 1, characterized in that, The first protection module includes a first voltage divider resistor and a second voltage divider resistor, wherein: The first voltage divider resistor is connected in series between the output terminal of the NI chassis and the gate of the first MOS transistor; one end of the second voltage divider resistor is connected to the gate of the first MOS transistor, and the other end is grounded.

6. The signal conditioning circuit according to claim 1, characterized in that, The second processing module includes a non-reverse buffer, the second protection module is connected to the output of the ECU and the input of the non-reverse buffer, and the output of the non-reverse buffer is connected to the NI chassis.

7. The signal conditioning circuit according to claim 6, characterized in that, The second protection module includes a protection resistor and a second Zener diode, wherein: The protection resistor is connected in series between the output terminal of the NI chassis and the input terminal of the non-reverse buffer. The cathode of the second Zener diode is connected to the input terminal of the non-reverse buffer, and the anode of the second Zener diode is grounded.

8. The signal conditioning circuit according to claim 7, characterized in that, The third protection module includes a fuse and a varistor. The initial voltage is input to the input terminal of the power module after passing through the fuse. One end of the varistor is connected to the input terminal of the power module, and the other end is grounded.

9. A conditioning device, characterized in that, The device includes a power board and a conditioning board, wherein the power board and the conditioning board are configured with a signal conditioning circuit as described in any one of claims 1-8.

10. A testing system, characterized in that, Includes an NI chassis, an ECU, and the conditioning device as described in claim 9, wherein: The conditioning device is used for signal interaction between the NI chassis and the ECU.

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