Abnormality processing method, apparatus, device, medium, and program product

Abstract

The application provides an exception processing method, device, equipment, medium and program product. Applied to the technical field of server, the method comprises: in the case that it is determined that a first thread block running on a processor exists a page fault exception, interrupting the running of the first thread block; running a second thread block on the processor, wherein the second thread block is determined from a plurality of standby thread blocks; and in response to the current time being a target time, merging a plurality of to-be-migrated pages causing the page fault exception as batch migration pages, and migrating the batch migration pages from an extended storage space to a storage unit of the processor in batches, the plurality of to-be-migrated pages comprising at least one of the following data: data causing the page fault exception for running the first thread block, and data causing the page fault exception for running the second thread block.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, in particular to the technical field of high parallel processing and virtual memory management, and more particularly to an exception processing method and device, electronic equipment, storage medium and program product. BACKGROUND

[0002] High concurrency tasks can be executed by using general-purpose graphics processors to be applied to high-throughput and low-latency scenarios. For example, it can be applied to recommendation, human-computer interaction, network social interaction and other scenarios with high real-time requirements.

[0003] However, in the process of executing high concurrency tasks, the problem of task processing exception also increases, such as incomplete task execution, inaccurate processing result, and high response delay of part of the task, etc. How to quickly and effectively perform exception processing has become a research focus. SUMMARY

[0004] Therefore, the present application provides an exception processing method and device, electronic equipment, storage medium and program product.

[0005] One aspect of the present application provides an exception processing method, comprising: interrupting the running of a first thread block of a processor in a case where it is determined that the first thread block exists a page fault exception, wherein the first thread block comprises a plurality of thread bundles, the first thread block exists a page fault exception indicating that the plurality of thread bundles all exist a page fault exception, and a thread bundle exists a page fault exception indicating that the data required for running the thread bundle is stored in an extended storage space; running a second thread block on the processor, wherein the second thread block is determined from a plurality of standby thread blocks; and in response to the current time being a target time, merging a plurality of to-be-migrated pages that cause the page fault exception as batch-migrated pages, and migrating the batch-migrated pages from the extended storage space to a storage unit of the processor in batches, wherein the plurality of to-be-migrated pages comprise at least one of the following data: data that causes the page fault exception for running the first thread block, and data that causes the page fault exception for running the second thread block.

[0006] Another aspect of the present application provides an exception handling apparatus, comprising: an interrupting module configured to interrupt running of a first thread block of a processor in a case where it is determined that the first thread block has a page fault exception, wherein the first thread block comprises a plurality of thread bundles, the first thread block having the page fault exception indicates that all of the plurality of thread bundles have the page fault exception, and a thread bundle having the page fault exception indicates that data required for running the thread bundle is stored in an extended storage space; an activating module configured to run a second thread block on the processor, wherein the second thread block is determined from a plurality of standby thread blocks; and a migrating module configured to, in response to a current time being a target time, combine a plurality of to-be-migrated pages that cause the page fault exception as batch-migrated pages, and migrate the batch-migrated pages from the extended storage space to a storage unit of the processor in batches, wherein the plurality of to-be-migrated pages comprise at least one of the following data: data that causes the page fault exception for running the first thread block, and data that causes the page fault exception for running the second thread block.

[0007] Another aspect of the present application provides an electronic device, comprising: one or more processors; a memory configured to store one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method as described above.

[0008] Another aspect of the present application provides a computer-readable storage medium storing computer-executable instructions that, when executed, perform a method as described above.

[0009] Another aspect of the present application provides a computer program product comprising computer-executable instructions that, when executed, perform a method as described above. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram of a processor according to an embodiment of the present application is shown;

[0012] Figure 2 A flowchart of an exception handling method according to an embodiment of the present application is shown;

[0013] Figure 3A A flowchart of an exception handling method according to an embodiment of the present application is shown;

[0014] Figure 3B A flowchart of an exception handling method according to an embodiment of the present application is shown;

[0015] Figure 4A A migration flowchart of to-be-migrated pages according to a related example of the present application is shown;

[0016] Figure 4B A migration flowchart of a to-be-migrated page according to an embodiment of the present application is shown.

[0017] Figure 5 A schematic diagram of determining an action evaluation result according to an embodiment of the present application is shown.

[0018] Figure 6 A block diagram of an exception handling apparatus according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely exemplary and is not intended to limit the scope of the application. In the following detailed description of embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that one or more embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present application.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "including" "comprising" and the like are meant to be inclusive, but not limiting to the components, steps, operations and / or the features that are recited.

[0021] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be further understood that the terms used herein should be interpreted as having a meaning that is consistent with the understanding of those terms by those skilled in the relevant art and that the terms should not be interpreted in an overly legal or overly formal sense unless expressly so defined herein.

[0022] In instances where expressions such as "at least one of A, B, and C, etc." are used, in general, it should be interpreted to include any one of A, B, or C, and also include a combination of at least one of A, B, and C (for example, a system that has A, B, and C each alone, a system that has A and B but not C, a system that has A and C but not B, a system that has B and C but not A, and / or a system that has A, B, and C together, etc.).

[0023] Graphics processors are widely used in servers and data centers to undertake large-scale computing tasks (such as graphics processing, deep learning, graph computing, etc.). However, the device memory capacity of traditional discrete graphics processors is limited, and it is difficult to process large-scale applications (such as social network analysis, recommendation system). In order to solve this problem, the present application proposes a virtual memory management (Unified Virtual Memory, referred to as UVM) mechanism. UVM allows central processors and graphics processors to share the same virtual address space through demand paging (Demand Paging), automatically migrates data, reduces the burden of manual memory management, and improves the portability and ease of use of programs.

[0024] The relationship between the virtual memory management technology and the thread block running will be further embodied by the introduction of the processor below. Figure 1 The relationship between the virtual memory management technology and the thread block running will be further embodied by the introduction of the processor below.

[0025] Figure 1 A schematic diagram of a processor according to an embodiment of the present application is shown.

[0026] As shown in Figure 1 , the processor 100 can include a general-purpose graphics processing unit (General-Purpose Computing on Graphics Processing Units, referred to as GPGPU), which is a kind of general-purpose computing task that uses a graphics processor to process graphics tasks.

[0027] As shown in Figure 1 , the processor 100 can include a plurality of streaming multiprocessors (Streaming Multiprocessor, referred to as SM, also referred to as computing unit) 110 and a memory unit 120.

[0028] Exemplarily, the SM is the basic computing unit of the general-purpose graphics processor, including an instruction scheduler, a register, a computing core, etc. These general-purpose computing can have nothing to do with graphics processing. Due to the powerful parallel processing capability and programmable pipeline of the general-purpose graphics processor, the streaming multiprocessor can process non-graphic data.

[0029] As shown in Figure 1 , a plurality of thread blocks 111 (Thread Block, referred to as TB) can be run in parallel on each streaming multiprocessor 110. Each thread block includes a plurality of thread bundles 111-1 (Warps). A thread bundle 111-1 includes a plurality of threads, which are schematically shown by a pipeline.

[0030] Optionally, the thread bundle 111-1 is the minimum unit running on the SM, usually 32 threads are 1 thread bundle. Each thread bundle 111-1 runs in a Single Instruction Multiple Threads (SIMT) mode.

[0031] Exemplarily, the threads in the thread bundle 111-1 access a virtual memory address based on a task request, and a Translation Lookaside Buffer (TLB) traverses a physical memory address mapped with the virtual memory address from a page table based on the virtual memory address. So as to call data to be executed by the threads from a physical memory page stored in the storage unit 120 of the processor 100 based on the physical memory address, to run the threads.

[0032] If the data is not stored in the storage unit 120 of the processor 100, and the data is stored in a virtual memory space extension storage space, it is determined that the thread has a page fault exception. The to-be-migrated page including the data stored in the extension storage space can be migrated to the storage unit 120 of the processor 100 through a Peripheral Component Interconnect Express (PCIe), and the thread can be interrupted during the migration process.

[0033] The extension storage space can include a disk but is not limited thereto, and can also include a storage unit configured on a central processing unit.

[0034] The processor is described above. The following describes an exception handling method of a page fault exception.

[0035] Figure 2 A flowchart of an exception handling method according to an embodiment of the present application is shown.

[0036] As shown in Figure 2 The method includes operations S210-S230.

[0037] In operation S210, in a case where it is determined that a first thread block running on a processor has a page fault exception, the running of the first thread block is interrupted.

[0038] In operation S220, a second thread block is run on the processor.

[0039] In operation S230, in response to a current time being a target time, a plurality of to-be-migrated virtual memory pages causing the page fault exception are merged as batch migration pages, and the batch migration pages are batch-migrated from a virtual memory space extension storage space to a storage unit of the processor.

[0040] The first thread block can include a plurality of thread bundles, the first thread block existing the page fault exception indicates that the plurality of thread bundles all exist the page fault exception, and the thread bundle existing the page fault exception indicates that data required for running the thread bundle is stored in the extended storage space.

[0041] Optionally, the extended storage space can include an extended storage space in the server other than a storage unit configured on the processor. Compared with reading data directly from the storage unit configured on the processor, it takes a longer time to read data from the extended storage space.

[0042] Optionally, the extended storage space can include a disk but is not limited thereto, and can also include a storage unit configured on a central processing unit.

[0043] During running of the thread bundle, a physical memory address of data required for running the thread bundle is queried from a page table based on a virtual memory address. A storage location of the data is determined based on the physical storage address.

[0044] The first thread block existing the page fault exception indicates that the plurality of thread bundles of the first thread block all exist the page fault exception, and the thread bundle existing the page fault exception indicates that the data required for running the thread bundle is stored in the extended storage space.

[0045] Interrupting running of the first thread block can mean blocking the first thread block. That is, suspending the first thread block running on the processor.

[0046] After interrupting the first thread block, a second thread block can be determined from a plurality of standby thread blocks to run the second thread block on the processor, thereby reducing idle time of the processor and improving resource utilization.

[0047] A predetermined time length can be used to merge a plurality of to-be-migrated pages to form a batch migration page, so as to batch migrate the batch migration page from the extended storage space to the storage unit of the processor.

[0048] The plurality of to-be-migrated pages include at least one of the following data: data causing the page fault exception for running the first thread block, and data causing the page fault exception for running the second thread block.

[0049] By switching the first thread block with the second thread block, the idle time of the processor can be reduced, and the batch migration page collected within a predetermined time period can include data required for running the first thread block and the second thread block, thereby adapting to an exception processing mechanism of the virtual memory, improving the number of to-be-migrated pages in the batch migration page, and further reducing performance degradation caused by migrating the batch migration page.

[0050] The above describes the exception processing method as a whole. In the following, the method will be described in detail through the following Figure 3A and 3BThe examples provided further illustrate the advantages of the exception handling method provided in the present application.

[0051] Figure 3A A flowchart of an exception handling method according to examples of the present application is shown.

[0052] As shown in Figure 3A "A Fault, B Fault, C Fault" are trigger signals of page fault events, and the pages to be migrated, including "Page A, Page B, Page C", need to be handled.

[0053] When the processor runs the first thread block, a plurality of pages to be migrated of the first thread block within a predetermined time length are collected, including Page A and Page B. After Page A and Page B are merged into a batch of batch migration pages, the batch migration pages are migrated to the storage unit of the processor for repair.

[0054] Because the time length between the exception determination time of the page to be migrated Page C and the exception determination time of Page A and Page B exceeds the predetermined time length, Page C is merged into the next batch of migration pages. The batches of batch migration pages are executed in series, and the migration is strictly executed according to the batch processing order in real time, that is, Batch N+1 is processed only after Batch N is processed. After the batch migration pages including Page A and Page B are processed, the batch migration pages including Page C can be processed.

[0055] Figure 3B A flowchart of an exception handling method according to an embodiment of the present application is shown.

[0056] As shown in Figure 3B When the processor runs the first thread block TB1, a plurality of pages to be migrated of the first thread block TB1 within a predetermined time length are collected, such as Page A and Page B. In the case where it is determined that all thread bundles in the first thread block TB1 have a page fault exception, the running of the first thread block TB1 is interrupted, and the first thread block TB1 is switched by using the second thread block TB2. The idle time of the processor can be reduced, and the batch migration pages collected within the predetermined time length can include the pages to be migrated Page A and Page B causing the failure of running the first thread block TB1 and the page to be migrated Page C causing the failure of running the second thread block TB2. Thus, the exception handling mechanism of the virtual memory is adapted, the number of pages to be migrated in the batch migration pages is increased, and the performance degradation problem caused by migrating the pages to be migrated is reduced.

[0057] Compared with related examples, the processor idle time is reduced, and the processor resource utilization is improved by using the exception processing method provided in the embodiments of the present disclosure. In addition, the data amount of the pages to be migrated in the batch migration page is increased due to the increased switching frequency between the thread blocks in the same period, thereby improving the migration efficiency, and the frequency of exception processing is improved.

[0058] The advantages of the present application are further illustrated by examples above. How to determine that the first thread block has a page fault exception will be described below.

[0059] According to the embodiments of the present application, before the operation S210 as shown in the figure, Figure 2 The exception processing method can further include: determining that the first thread block has a page fault exception in a case where it is determined that the plurality of thread bundles belonging to the first thread block all have a page fault exception.

[0060] The first thread block runs on the processor provided in the embodiments of the present disclosure, and the first thread block includes M thread bundles, and each thread bundle includes X threads. The X threads can execute the same instruction to process different data. M and X are both positive integers greater than 1.

[0061] In a case where any one of the X threads has a page fault exception, because the X threads all execute the same instruction, the processing of all the X threads will be delayed due to the thread having a page fault exception. Therefore, it is determined that the thread bundle has a page fault exception, and the running of the thread bundle is interrupted.

[0062] In a case where the M thread bundles belonging to the first thread block all have a page fault exception, it can be determined that the first thread block has a page fault exception, and the first thread block is interrupted. In a case where any one of the M thread bundles belonging to the first thread block runs normally, the first thread block is not interrupted.

[0063] According to the embodiments of the present application, the exception processing method provided in the embodiments of the present application is adapted to the actual SIMT execution mode, and can improve the accuracy and granularity of exception processing, improve the task execution efficiency, and improve the running stability.

[0064] According to the embodiments of the present application, determining whether the plurality of thread bundles belonging to the first thread block all have a page fault exception can include: querying the data required by the target thread running on the processor from the page table based on the virtual memory address of the target thread to obtain a query result. In a case where the query result indicates that the data required by the target thread is stored in the extended storage space, it is determined that the thread bundle to which the target thread belongs has a page fault exception, and the execution of the thread bundle to which the target thread belongs is interrupted.

[0065] The plurality of threads in the thread bundle respectively process different data according to the same instruction.

[0066] Each target thread processes the respective task and the data required by the task independently. Optionally, a virtual memory address can be used to query a page table. The page table represents the mapping relationship between the virtual memory address and the physical memory address. In the case that the query result of any thread indicates that the data is stored in the extended storage space, it is determined that the thread has a page fault exception. In this case, it is determined that the thread bundle to which the target thread belongs has a page fault exception, and the execution of the thread bundle to which the target thread belongs is interrupted.

[0067] In the case that the query result indicates that the data is stored in the storage unit of the processor, the normal operation is performed.

[0068] According to the embodiments of the present application, in the parallel processing of the processor, a plurality of threads with the same instruction and different data to be processed are merged into a thread bundle for processing, thereby improving the parallel capability, and in the case that any one target thread has a page fault exception, the thread bundle to which the target thread belongs is determined to have a page fault exception, and the problem of delay of other threads in the same thread bundle is avoided.

[0069] The above describes how to determine that the first thread block has a page fault exception, and the following describes how to interrupt the first thread block.

[0070] According to the embodiments of the present application, for the operation S210 shown in FIG. 2, interrupting the running of the first thread block can include: saving the context of the first thread block to the global memory. Figure 2

[0071] The context of the first thread block represents the running state of the first thread block.

[0072] Optionally, the context can be stored in the shared memory or the global memory. The global memory can refer to a storage space configured outside the processor and accessible by the processor, and the shared memory can refer to a storage space configured on the processor. The shared memory has low latency but limited capacity; the global memory has high latency but large capacity. The storage location of the context can be flexibly set according to actual conditions.

[0073] Optionally, the interruption of the first thread block can be completed by dynamically switching the context. For example, when all the thread bundles of the first thread block in the active state are interrupted due to the page fault, the standby thread block can be switched to, and the standby thread block is used as the second thread block to continue running on the processor.

[0074] Specifically, the context of the first thread block can be saved, and the scheduler of the GPU can be used to manage and mark the state, for example, mark it as an interrupted state, to complete the interruption.

[0075] Optionally, the global memory can be a storage space outside the processor and accessible by the processor. The interruption of the first thread block can be completed by switching the context.​

[0076] According to the embodiments of this application, the interruption of the first thread block is completed by processing the context of the first thread block, which simplifies the interruption method and improves processing efficiency.

[0077] The interruption of the first thread block was explained above. The activation of the second thread block will be explained below.

[0078] According to embodiments of this application, for example, Figure 2 The operation S220 shown, which runs a second thread block on the processor, may include: migrating the data required to run the second thread block and the context of the second thread block to the processor's memory. The context of the second thread block is used to characterize the running state of the second thread block.

[0079] A spare thread block can refer to a thread block that is in an inactive state. When a spare thread block is designated as the second thread block, the context of the second thread block is loaded from global memory into the processor's memory location.

[0080] Optionally, in addition to the context supporting the execution of the second thread block, it also includes the data to be processed for the execution of the second thread block. The pages to be migrated, including the data to be processed, can be migrated together to the processor's memory.

[0081] According to the embodiments of this application, by migrating the context and the page to be migrated to the processor's storage unit, the inactive standby thread block is converted into an active second thread block, so that the second thread block runs on the processor. The activation method is simple and the activation content is comprehensive and effective, improving activation efficiency and the stability of thread block switching.

[0082] The above text explained how to activate the second thread block; the following text will explain how to determine the batch migration page.

[0083] According to embodiments of this application, for example, Figure 2 The operation S230 shown, responding to the current time as the target time, merges multiple pages to be migrated that caused page faults in the first thread block and the second thread block, as batch migration pages. This includes: if the data volume of the determined multiple pages to be migrated exceeds a predetermined data volume threshold, sorting the multiple pages to be migrated according to the time of fault determination to obtain a time-sorted result. Based on the time-sorted result, multiple pages to be migrated that meet the predetermined data volume threshold are selected as batch migration pages. The remaining pages to be migrated are selected as the next batch of batch migration pages.

[0084] The current time can be taken as the target time if the time length between the current time and the migration time of the previous batch of migrated pages meets a predetermined time length. A plurality of to-be-migrated pages determined within the predetermined time length can be merged as a batch of migrated pages. The plurality of to-be-migrated pages can also be candidate batch of migrated pages. The data amount of the candidate batch of migrated pages is determined. If the data amount exceeds a predetermined data amount threshold, a part of the plurality of to-be-migrated pages is selected as a batch of migrated pages. The plurality of to-be-migrated pages can be randomly selected, but this is not limited. The plurality of to-be-migrated pages can also be sorted according to the abnormal determination time to obtain a time sorting result. Based on the time sorting result, the to-be-migrated pages that occur earlier at the abnormal determination time are merged into the current batch of migrated pages to process and recover the fault earlier based on the early response of the task request. In this way, the task processing effect is improved.

[0085] According to another embodiment of the present application, in response to the current time being the target time, the plurality of to-be-migrated pages with page fault exceptions are merged as a batch of migrated pages. The plurality of to-be-migrated pages can also be merged as a batch of migrated pages if the data amount of the plurality of to-be-migrated pages determined does not exceed a predetermined data amount threshold.

[0086] The data amount is further used as a limitation condition while the predetermined time length is used as a merging limitation condition for the batch of migrated pages. In this way, the plurality of to-be-migrated pages are processed in batches, and the data amount threshold is used for limitation to reduce resource occupancy and improve processing efficiency.

[0087] The general method for determining a batch of migrated pages is described above. How to migrate the batch of migrated pages will be described below.

[0088] According to an embodiment of the present application, the batch of migrated pages are batch-migrated from the extended storage space to the storage unit of the processor, which can include: in a case where the free capacity of the storage unit of the processor meets the batch of migrated pages, locking the target page table entry in the lock page table to prevent write operation on the target page table entry, and batch-migrating the batch of migrated pages from the extended storage space to the storage unit of the processor; and updating the mapping relationship between the virtual memory address and the physical memory address of the target page table entry in the page table.

[0089] Locking the target page table entry in the page table can mean limiting the "write" operation on the target page table entry in the page table. The mapping relationship between the virtual memory address and the physical memory address of the target page table entry in the page table can be updated after the batch migration of the batch of migrated pages is completed. The target page table entry in the page table can be unlocked after the page table is updated. The fault repair is completed. After the SM on the processor is idle, the thread block corresponding to the batch of migrated pages can be restarted.

[0090] According to the batch migration operation of the batch migration page provided in the embodiment of the present application, the page table can be updated simultaneously when the batch migration page completes migration, thereby realizing linkage operation and avoiding new exceptions caused by inconsistent migration and updating.

[0091] The above describes how to perform batch migration, and the following describes how to improve the processing efficiency of batch migration.

[0092] According to the preferred example of the present application, in the process of performing operation S230 as shown in Figure 2 The exception handling method can further include: evaluating the plurality of physical memory pages stored in the storage unit to obtain a management page evaluation result. In a case where the management page evaluation result indicates that the target physical memory page is not adapted to the target thread block, the target physical memory page is taken as an evicted page and is migrated from the storage unit of the processor to the extended storage space.

[0093] The target physical memory page is allocated for use by the target thread block, and the target thread block is a thread block that runs in parallel with the first thread block or the second thread block on the processor.

[0094] Optionally, the physical memory pages are all stored in the storage unit of the processor. The capacity of the storage unit is fixed. Before each batch migration page is migrated in, storage space needs to be vacated in the storage unit, for example, by migrating an existing physical memory page, which forms serialization.

[0095] Figure 4A A migration flowchart of a to-be-migrated page according to related examples of the present application is shown.

[0096] As shown in Figure 4A The to-be-migrated page Page A and the to-be-migrated page Page B respectively cause a page fault exception and are stored in the extended storage space and need to be migrated to the storage unit of the processor. The physical memory page Page X and the physical memory page Page Y are stored in the storage unit of the processor and need to be migrated to the extended storage space. Because the capacity of the storage unit is fixed, when the storage unit is full, the physical memory page Page X needs to be migrated out first, then the to-be-migrated page Page A is migrated in, then the physical memory page Page Y is migrated out, and then the to-be-migrated page Page B is migrated in. This series of operations are executed in series.

[0097] When the storage unit is full, when a new to-be-migrated page is migrated in, the old physical memory page needs to be migrated out first to vacate space.

[0098] The pre-migration of the physical memory page with low usage frequency or not adapted to the thread block running provided in the embodiment of the present application can improve the page migration efficiency by using the pre-migration mechanism.

[0099] The mismatch between the target physical memory page and the target thread block can be understood as: the data contained in the target physical memory page is no longer accessed, or the access frequency of the data contained in the target physical memory page is lower than a predetermined threshold.

[0100] Figure 4B A schematic diagram of the migration process of a page to be migrated according to an embodiment of this application is shown.

[0101] like Figure 4B As shown, the first thread block TB1 and the target thread block TBT are run in parallel in the processor. When the first thread block TB1 switches to the second thread block TB2, within a predetermined time period, before determining the pages to be migrated, including the page to be migrated Page-TB1 of the first thread block TB1 and multiple pages to be migrated Page-TB2 of the second thread block TB2, the target physical memory page Page-TBT that is not compatible with the target thread block TBT is determined in advance, and the target physical memory page Page-TBT is migrated from the storage unit to the extended storage space in advance.

[0102] Target physical memory pages that are incompatible with the target thread block are identified in advance and migrated, thereby dynamically expanding the storage space of the storage unit and avoiding hard serial execution of migration-in and migration-out operations.

[0103] When the processor's memory is detected to be full, even without page migration requests, the target physical memory pages are migrated in advance, freeing up usable storage space. This allows for an immediate batch migration of pages, thereby reducing the serialization of page migration and improving management efficiency.

[0104] The previous section explained how to migrate batch migration pages. The following section will explain how to determine the second thread block from the standby thread block.

[0105] According to embodiments of this application, when performing such Figure 2 Before the operation S220 shown, the exception handling method may further include: determining a second thread block from the standby thread block.

[0106] Optionally, determining the second thread block from the standby thread blocks may include: sorting multiple standby thread blocks based on the priority of the tasks to be executed in the standby thread blocks, obtaining a thread block sorting result. The second thread block is then determined from the standby thread blocks based on the thread block sorting result. However, this is not limited to this. Candidate standby thread blocks may also be determined from the standby thread blocks based on the thread block sorting result. If some of the data required to determine the candidate standby thread blocks is already stored in the processor's memory, the candidate standby thread blocks are used as the second thread block.

[0107] The determining the second thread block from the standby thread blocks based on the thread block sorting result can include: sorting the plurality of standby thread blocks according to priority to obtain the thread block sorting result; taking the standby thread block with the highest priority as a candidate standby thread block; and taking the candidate standby thread block as the second thread block directly.

[0108] Optionally, whether the part of data required by the candidate standby thread block is stored in the storage unit of the processor can also be identified, and in a case where it is determined that the part of data required by the candidate standby thread block is stored in the storage unit of the processor, the candidate standby thread block is taken as the second thread block. In a case where it is determined that the data required by the candidate standby thread block is not stored in the storage unit of the processor, the screening is continued according to the thread block sorting result until the standby thread block is obtained, which is taken as the second thread block.

[0109] Compared with the manner of directly taking the standby thread block with the highest priority as the second thread block, the determination that the part of data required by the candidate standby thread block is stored in the storage unit of the processor can reduce the migration data amount of the batch migration page used to run the second thread block, improve the processing speed, avoid the problem that the determined second thread block cannot run on the processor due to the need for the batch migration page, and further cause the processor to continue to be idle.

[0110] The above describes how to determine the second thread block from the standby thread blocks. The following describes how to determine the number of standby thread blocks.

[0111] According to an embodiment of the present application, the number of standby thread blocks can be determined as a fixed value. However, it is not limited thereto. The number of standby thread blocks can also be determined as dynamically adjustable.

[0112] According to a preferred embodiment of the present application, the specific manner of setting the number of standby thread blocks as dynamically adjustable can include the following operation: determining the number of standby thread blocks based on the running state information of the processor and the hardware index of the processor in a historical period.

[0113] The running state information of the processor and the hardware index of the processor in the historical period can be used to estimate the number of configured standby thread blocks in the current period.

[0114] The running state information of the processor can represent the running performance of the processor, and the hardware index of the processor can represent the maximum capacity of the supportable resources of the processor.

[0115] Based on the running state information of the processor in the historical period and the hardware indicators of the processor, the number of the configurable spare thread blocks in the current period is estimated, which can comprehensively consider multiple factors together to ensure the scalability and dynamic adjustment of the spare threads, reduce the idle time of the processor through dynamic switching of the thread blocks, improve the frequency of batch merging, and ultimately improve the resource utilization. In addition, the load processing capacity and the stability of the processor running performance can be improved through the running state information.

[0116] According to the embodiments of the present application, the number of spare thread blocks can be determined by function fitting. For example, the running state information of the processor in the historical period and the hardware indicators of the processor are taken as parameters and substituted into the evaluation function to obtain the number of spare thread blocks.

[0117] According to another embodiment of the present application, the prediction method of action evaluation model can also be used. For example, based on the running state information and the hardware indicators, the state features are obtained. Based on the state features, the number of spare thread blocks is evaluated to obtain the action evaluation result for adjusting the number of spare thread blocks. Based on the historical number of spare thread blocks in the historical period and the action evaluation result, the number of spare thread blocks in the current period is obtained.

[0118] Specifically, the state features can be input into the action evaluation model to obtain the action evaluation result for adjusting the number of spare thread blocks. For example, the number of spare thread blocks configured in the historical period includes Y. Based on the action evaluation result, a predetermined number of spare thread blocks can be added or reduced based on Y to obtain the number of spare thread blocks in the current period .

[0119] According to another optional embodiment of the present application, the state features can be input into the action evaluation model to obtain the thread block number evaluation result representing the number of spare thread blocks.

[0120] Compared with the method of directly obtaining the thread block number evaluation result, based on the action evaluation result and the number of spare thread blocks configured in the historical period, the number of spare thread blocks in the current period is determined together, which can fine-tune the number of spare thread blocks configured in the historical period by using the action evaluation result, improve the expansion flexibility, reduce the prediction error based on the number of spare thread blocks configured in the historical period, and further avoid the problem of large error caused by direct determination.

[0121] According to the embodiments of the present application, based on the running state information and the hardware indicators, the state features can be obtained, which can include: respectively extracting the running state information and the hardware indicators to obtain running state features and indicator features. The running state features and the indicator features are fused to obtain the state features.

[0122] Figure 5 A schematic diagram of determining an action evaluation result is shown.

[0123] As shown in Figure 5 The running state information 510 and the hardware indicators 520 can be input into the feature extraction module M510 respectively to obtain running state features 530 and indicator features 540. The running state features 530 and the indicator features 540 are input into the fusion module M520 for feature fusion to obtain state features 550. The state features 550 are input into the action evaluation model M530 to obtain an action evaluation result 560.

[0124] Optionally, the fusion module can include a concatenation or point multiplication module. The feature extraction module M510 can include an encoder-decoder, a convolutional neural network, a long short-term memory network. The action evaluation model can include at least one of a convolutional neural network, a large language model, and a random forest model, which will not be described here.

[0125] The action evaluation model M530 is used to estimate the action evaluation result, improving the processing efficiency.

[0126] According to an embodiment of the present application, the running state information 510 can include at least one of, for example, a page processing performance identification result, a page access attribute identification result, and a thread running performance identification result. The hardware indicators can include at least one of a processing indicator and a hardware resource indicator.

[0127] Specifically, the processing performance of the physical memory page to be migrated can be identified to obtain a page processing performance identification result. The page processing performance identification result can include an early reclamation rate or an early reclamation rate ratio.

[0128] Identifying the processing performance of the physical memory page to be migrated can include determining the proportion of early reclamation in a unit of time. Or determining the change amount of the proportion of early reclamation of physical memory pages in a unit of time. The lower the page processing performance identification result, the more the concurrency needs to be improved.

[0129] The access attribute of the physical memory page is identified to obtain a page access attribute identification result. The page access attribute identification result can include at least one of the following: the access frequency of the physical memory page, the proportion of shared physical memory pages. The access frequency of the physical memory page can reflect the load pressure, and the higher the concurrency needs to be improved. The higher the proportion of shared physical memory pages, the more the concurrency needs to be improved.

[0130] For example, identifying the access attribute of the physical memory page can include determining the proportion of physical memory pages accessed by multiple thread blocks among the total accessed physical memory pages. Or determining the total number of physical memory pages in a unit of time.

[0131] The performance of thread blocks running on the processor is identified, yielding thread performance identification results. These results may include the switching frequency of thread blocks. A higher switching frequency indicates greater switching overhead, necessitating a reduction in concurrency.

[0132] Identifying the performance of thread blocks running on a processor can include the number of thread block context switches per unit time.

[0133] Determine the processing metrics and hardware resource metrics for batch migration pages. Based on at least one of the processing metrics and hardware resource metrics, determine the hardware metrics.

[0134] Batch migration page processing metrics can include the total number of pages migrated in a single batch and the merging time of batch migration pages. Hardware resource metrics can include the duration of processor hardware resource usage.

[0135] According to the embodiments of this application, reference factors affecting concurrency are determined based on actual operating conditions, and then the number of standby thread blocks is evaluated by comprehensively referring to these reference factors, so that the evaluation is accurate and effective.

[0136] According to an optional embodiment of this application, reinforcement learning can also be used to optimize and train the action evaluation model used to evaluate the number of standby thread blocks based on state features and obtain action evaluation results for adjusting the number of standby thread blocks, so as to improve the relevance and intelligence of the action evaluation model.

[0137] Continue to refer to Figure 5 Based on the current performance monitoring result 570 for the current time period and the historical performance monitoring result 580 for historical time periods, the model evaluation result 590 can be determined. Based on the model evaluation result 590, the action evaluation model M530 is optimized and trained to obtain the optimized action evaluation model.

[0138] According to embodiments of this application, determining the model evaluation result based on the current performance monitoring results for the current time period and the historical performance monitoring results for historical time periods may include: determining a first evaluation result for task execution performance indicators based on the amount of tasks processed in the current and historical time periods respectively; determining a second evaluation result for unreasonable management indicators based on the change rate of premature reclamation rate of physical memory pages to be migrated in the current and historical time periods respectively; determining a third evaluation result for resource usage indicators based on the resource usage monitoring results for the current time period; and determining the model evaluation result based on the first, second, and third evaluation results.

[0139] Optionally, determining the resource occupation monitoring result can comprise: determining a context switching duration of the thread block; determining a context switching frequency of the thread block; determining a bandwidth occupation rate for transmitting the context; and determining the resource occupation monitoring result based on the switching duration, the switching frequency and the bandwidth occupation rate.

[0140] Optionally, determining the model evaluation result based on the first evaluation result, the second evaluation result and the third evaluation result can comprise: performing data conversion on the first evaluation result and the second evaluation result respectively to determine a first target value representing performance gain and a second target value representing management performance loss; determining a third target value representing resource occupation based on the sub-evaluation results for the time occupation indicator and the bandwidth resource occupation indicator in the third evaluation result; obtaining a target value by combining the first target value, the second target value and the third target value; and obtaining the model evaluation result based on the target value and an evaluation threshold.

[0141] The first evaluation result can be used as a core indicator for measuring the instantaneous change of the processor computing performance, and is defined as the difference between the average number of instructions executed per cycle in adjacent monitoring periods. The current cycle instruction throughput can be used as the processed task amount, and the change value relative to the last cycle instruction throughput can be used as the first evaluation result.

[0142] The first evaluation result can be subjected to data conversion, so as to obtain a first target value representing performance gain.

[0143] For example, the first evaluation result = the number of instructions in the current period - the number of instructions in the historical period. .

[0144] The second evaluation result The second evaluation result can comprise a premature rate.

[0145] The premature rate Premature Rate refers to the proportion of physical memory pages in the processor that are removed in advance, and is used to measure the performance loss caused by unreasonable recycling strategies. The definition formula can be seen in formula (1).

[0146] Formula (1)

[0147] The data conversion on the second evaluation result to determine a second target value representing management performance loss can comprise: determining a premature rate proportion based on the premature rate. The premature rate proportion refers to the change amount of the premature rate removed in advance per unit time. The premature rate proportion can be used as the second target value ΔEvictionRate, and the calculation method can be seen in formula (2). The increase of the premature rate proportion indicates the increase of the recycling decision error rate.

[0148] Formula (2)

[0149] The third assessment result can characterize the resource usage monitoring results. For example, it can include monitoring results from at least one of the following dimensions: sub-assessment results for time usage indicators, frequency penalty factors, and sub-assessment results for bandwidth resource usage indicators.

[0150] Sub-evaluation results for time occupancy metrics It can be determined using the following formula (3).

[0151] ;Formula (3)

[0152] Where ContextSize represents the amount of context data in a single thread block, MemoryBandwidth represents the processor's global memory bandwidth, and CyclesPerTransfer represents the number of processor clock cycles consumed per data transfer operation.

[0153] Frequency penalty factor It can be determined using the following formula (4).

[0154] ;Formula (4)

[0155] Among them, ContextSwitchCount represents the number of thread block context switches within the monitoring window, and MonitoringCycles represents the fixed monitoring cycle.

[0156] Sub-evaluation results for bandwidth resource usage metrics It can be determined using the following formula (5).

[0157] ;Formula (5)

[0158] MemBWUtil represents the global memory bandwidth utilization.

[0159] The third evaluation result can be calculated using formula (6) to obtain the third target value. .

[0160] ;Formula (6)

[0161] in, This represents the third target value. This indicates the sub-evaluation results for the time occupancy indicator. Represents the frequency penalty factor. This indicates the sub-evaluation results for the bandwidth resource usage indicator.

[0162] The target value can be calculated according to the following formula (7).

[0163] Formula (7)

[0164] Wherein, the first target value is represented by ΔIPC. The second target value is represented by ΔIPCT. The third target value is represented by ΔIPCU. The target value is represented by ΔIPC. The weight is represented by w.

[0165] The target value can be compared with an evaluation threshold. When the target value is greater than the evaluation threshold, the model evaluation result indicates that the evaluation performance of the current action evaluation model is good, and optimization is not required. When the target value is less than the evaluation threshold, the model evaluation result indicates that the evaluation performance of the current action evaluation model is poor, and optimization can be performed to improve the evaluation performance of the action evaluation model.

[0166] According to the model training method provided in the embodiments of the present application, the monitoring results of the current period and the adjacent historical period can be compared, so that the model evaluation result is combined with the actual situation and is real and effective. In addition, the model evaluation result combines reference evaluation data considered from different angles, so that the reference of the model evaluation result is comprehensive and effective, and thus the training efficiency is high and the precision of the trained model is high when the model evaluation result is used for optimization.

[0167] Figure 6 A block diagram of an exception handling apparatus according to an embodiment of the present application is shown.

[0168] As shown in Figure 6 The exception handling apparatus 600 of the embodiments of the present application includes an interrupt module 610, an activation module 620, and a migration module 630.

[0169] The interrupt module 610 is configured to interrupt the running of a first thread block in a case where it is determined that the first thread block of the processor has a page fault exception, wherein the first thread block includes a plurality of thread bundles, the first thread block having the page fault exception indicates that all of the plurality of thread bundles have the page fault exception, and a thread bundle having the page fault exception indicates that data required for running the thread bundle is stored in an extended storage space. In an embodiment, the interrupt module 610 can be configured to perform the operation S210 described above, and details are not repeated here.

[0170] The activation module 620 is configured to run a second thread block on the processor, wherein the second thread block is determined from a plurality of standby thread blocks. In an embodiment, the activation module 620 can be configured to perform the operation S220 described above, and details are not repeated here.

[0171] The migration module 630 is configured to, in response to the current time being the target time, merge a plurality of to-be-migrated pages causing the page fault exception as batch-migrated pages, and migrate the batch-migrated pages from the extended storage space to the storage unit of the processor in batches, wherein the plurality of to-be-migrated pages include at least one of the following data: data causing the page fault exception for running the first thread block, and data causing the page fault exception for running the second thread block. In an embodiment, the migration module 630 can be configured to perform the operation S230 described above, and details are not described herein again.

[0172] According to an embodiment of the present application, the exception processing apparatus 600 further includes a thread block sorting module, a candidate determining module, and a second thread block determining module.

[0173] The thread block sorting module is configured to sort the plurality of standby thread blocks based on priorities of tasks to be executed by the standby thread blocks, to obtain a thread block sorting result.

[0174] The candidate determining module is configured to determine a candidate standby thread block from the standby thread blocks based on the thread block sorting result.

[0175] The second thread block determining module is configured to, in a case where part of data required for running the candidate standby thread block has been stored in a physical memory page, determine the candidate standby thread block as the second thread block, wherein the physical memory page is stored in the storage unit of the processor.

[0176] According to an embodiment of the present application, the activation module 620 includes an activation submodule.

[0177] The activation submodule is configured to migrate data required for running the second thread block and a context of the second thread block to the storage unit of the processor, wherein the context of the second thread block is used to represent a running state of the second thread block.

[0178] According to an embodiment of the present application, the interrupt module 610 includes a context saving submodule.

[0179] The context saving submodule is configured to save a context of the first thread block to a global memory, wherein the context of the first thread block represents a running state of the first thread block.

[0180] According to an embodiment of the present application, the migration module 630 includes a time sorting submodule and a first management page migration submodule.

[0181] The time sorting submodule is configured to, in a case where a data amount of the plurality of to-be-migrated pages exceeds a predetermined data amount threshold, sort the plurality of to-be-migrated pages according to a time when the exception is determined, to obtain a time sorting result.

[0182] The first management page migration submodule is configured to, based on the time sequence result, migrate, as a batch migration page, the plurality of to-be-migrated pages that satisfy the predetermined data amount threshold.

[0183] According to an embodiment of the present application, the migration module 630 further comprises a second management page migration submodule.

[0184] The second management page migration submodule is configured to, in a case where the data amount of the determined plurality of to-be-migrated pages does not exceed the predetermined data amount threshold, merge the plurality of to-be-migrated pages as a batch migration page.

[0185] According to an embodiment of the present application, the exception handling apparatus 600 further comprises a page evaluation module and a pre-migration module.

[0186] The page evaluation module is configured to evaluate the plurality of to-be-migrated pages stored in the storage unit to obtain a page evaluation result.

[0187] The pre-migration module is configured to, in a case where the page evaluation result indicates that the target physical memory page is not suitable for the target thread block, migrate the target physical memory page as an evicted page from the storage unit of the processor to the extended storage space, wherein the target physical memory page is allocated for use by the target thread block, and the target thread block is a thread block that runs in parallel with the first thread block or the second thread block on the processor.

[0188] According to an embodiment of the present application, the migration module 630 comprises a lock submodule and an update submodule.

[0189] The lock submodule is configured to, in a case where it is determined that the storage unit of the processor has storage space for a batch migration page, lock a target page table entry in the page table to prevent a write operation on the target page table entry, and batch migrate the batch migration page from the extended storage space to the storage unit of the processor.

[0190] The update submodule is configured to update a mapping relationship between a virtual memory address and a physical memory address of a target page table entry in the page table.

[0191] According to an embodiment of the present application, the exception handling apparatus 600 further comprises a query module and a bundle page fault exception determination module.

[0192] The query module is configured to, based on a virtual memory address of a target thread, query data required by the target thread running on the processor from a page table to obtain a query result, wherein the page table represents a mapping relationship between a virtual memory address and a physical memory address.

[0193] The bundle page fault exception determination module is configured to determine that a thread bundle to which the target thread belongs has a page fault exception when the query result indicates that data required by the target thread is stored in the extended storage space, and interrupt execution of the thread bundle to which the target thread belongs, wherein the plurality of threads in the thread bundle process different data according to the same instruction respectively.

[0194] According to an embodiment of the present application, the number of spare thread blocks configured on the processor is determined by a spare block determination module.

[0195] The spare block determination module is configured to determine the number of spare thread blocks based on the running state information of the processor and the hardware indicators of the processor within a historical period.

[0196] According to an embodiment of the present application, the spare block determination module comprises a state feature determination submodule, an action evaluation submodule, and a spare block determination submodule.

[0197] The state feature determination submodule is configured to obtain state features based on the running state information and the hardware indicators.

[0198] The action evaluation submodule is configured to evaluate the number of spare thread blocks based on the state features to obtain an action evaluation result for adjusting the number of spare thread blocks.

[0199] The spare block determination submodule is configured to obtain the number of spare thread blocks in the current period based on the historical number of spare thread blocks within the historical period and the action evaluation result.

[0200] According to an embodiment of the present application, the state feature determination submodule comprises a feature extraction unit and a fusion unit.

[0201] The feature extraction unit is configured to perform feature extraction on the running state information and the hardware indicators respectively to obtain running state features and indicator features.

[0202] The fusion unit is configured to perform feature fusion on the running state features and the indicator features to obtain the state features.

[0203] According to an embodiment of the present application, the exception handling device 600 further comprises a first identification module, a second identification module, a third identification module, a fourth identification module, a state determination module, a fifth identification module, and a hardware determination module.

[0204] The first identification module is configured to identify the processing performance of the physical memory page to be migrated to obtain a page processing performance identification result.

[0205] The second identification module is configured to identify the access attribute of the physical memory page to obtain a page access attribute identification result.

[0206] The third identification module is configured to identify running performance of the thread block running on the processor to obtain a thread running performance identification result.

[0207] The state determination module is configured to obtain running state information based on the page processing performance identification result, the page access attribute identification result, and the thread running performance identification result.

[0208] The fifth identification module is configured to determine a processing index and a hardware resource index of the batch migration page.

[0209] The hardware determination module is configured to determine a hardware index based on the processing index and the hardware resource index.

[0210] According to an embodiment of the present application, the abnormality processing apparatus 600 comprises a model evaluation module and an optimization module.

[0211] The model evaluation module is configured to determine a model evaluation result based on a current performance monitoring result of a current period and a historical performance monitoring result of a historical period.

[0212] The optimization module is configured to perform optimization training on the action evaluation model based on the model evaluation result to obtain an optimized action evaluation model, wherein the action evaluation model is configured to evaluate the number of standby thread blocks based on state features to obtain an action evaluation result for adjusting the number of standby thread blocks.

[0213] According to an embodiment of the present application, the model evaluation module comprises a first evaluation submodule, a second evaluation submodule, a third evaluation submodule, and a fourth evaluation submodule.

[0214] The first evaluation submodule is configured to determine a first evaluation result for a task execution performance index based on respective processed task amounts of the current period and the historical period.

[0215] The second evaluation submodule is configured to determine a second evaluation result for an unreasonable management index based on respective premature recycling rate change rates of the batch migration pages of the current period and the historical period.

[0216] The third evaluation submodule is configured to determine a third evaluation result for a resource occupation index based on a resource occupation monitoring result of the current period.

[0217] The fourth evaluation submodule is configured to determine the model evaluation result based on the first evaluation result, the second evaluation result, and the third evaluation result.

[0218] According to an embodiment of the present application, the fourth evaluation submodule comprises a first conversion unit, a second conversion unit, a fusion unit, and an evaluation determination unit.

[0219] The first conversion unit is configured to perform data conversion on the first evaluation result and the second evaluation result respectively, to determine a first target value representing performance gain and a second target value representing management performance loss.

[0220] The second conversion unit is configured to determine a third target value representing resource occupation based on a sub-evaluation result for the time occupation index and a sub-evaluation result for the bandwidth resource occupation index in the third evaluation result.

[0221] The fusion unit is configured to obtain a target value by fusing the first target value, the second target value and the third target value.

[0222] The evaluation determination unit is configured to obtain a model evaluation result based on the target value and an evaluation threshold.

[0223] According to embodiments of the present application, any of the interruption module 610, the activation module 620 and the migration module 630 can be combined in one module / unit / sub-unit for implementation, or any of the modules / units / sub-units can be split into multiple modules / units / sub-units. Alternatively, at least part of the functions of one or more of the modules / units / sub-units can be combined with at least part of the functions of other modules / units / sub-units, and implemented in one module / unit / sub-unit. According to embodiments of the present application, at least one of the interruption module 610, the activation module 620 and the migration module 630 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on board, a system on package, an application specific integrated circuit (ASIC), or any other reasonable manner of hardware or firmware that can be integrated or packaged into a circuit, or implemented in any one of software, hardware and firmware or in a proper combination of any of them. Alternatively, at least one of the interruption module 610, the activation module 620 and the migration module 630 can be at least partially implemented as a computer program module that can perform corresponding functions when executed.

[0224] The present application also provides a computer readable storage medium, which can be included in the device / apparatus / system described in the above embodiments, or can exist separately without being assembled into the device / apparatus / system. The above computer readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present application.

[0225] According to an embodiment of the present application, the computer readable storage medium can be a non-transitory computer readable storage medium, for example, can include, but is not limited to, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present application, a computer readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in connection with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present application, the computer readable storage medium can include one or more memory devices other than the ROM and / or the RAM described above.

[0226] Embodiments of the present application also include a computer program product, which includes a computer program containing program codes for executing the methods shown in the flowcharts. When the computer program product is run in a computer system, the program codes are used to make the computer system implement the control method of the electronic device provided by the embodiments of the present application.

[0227] The above functions defined in the system / device / module / unit of the embodiments of the present application are performed when the computer program is executed by the processor. According to an embodiment of the present application, the system, device, module, unit, etc. described above can be implemented by computer program modules.

[0228] According to an embodiment of the present application, the program codes of the computer program for executing the embodiments of the present application can be written in any combination of one or more programming languages, and specifically, these computer programs can be implemented by using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The programming languages include, but are not limited to, such as Java, C++, python, “C” language or similar programming languages. The program codes can be executed completely on a user computing device, partially on a user device, partially on a remote computing device, or completely on a remote computing device or server. In the case involving a remote computing device, the remote computing device can be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, connected to the Internet through an Internet service provider).

[0229] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0230] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

Claims

1. An abnormality processing method characterized by comprising: The method comprises: interrupting running of a first thread block of the processor in a case where it is determined that the first thread block exists a page fault exception, wherein the first thread block comprises a plurality of thread bundles, the first thread block existing the page fault exception represents that all of the plurality of thread bundles exist the page fault exception, and the thread bundle existing the page fault exception represents that data required for running the thread bundle is stored in an extended storage space; running a second thread block on the processor, wherein the second thread block is determined from a plurality of backup thread blocks; and in response to a current time being a target time, merging a plurality of to-be-migrated pages that cause the page fault exception as batch migration pages, and migrating the batch migration pages from the extended storage space to a storage unit of the processor in batches, wherein the to-be-migrated pages comprise at least one of the following data: data that causes the page fault exception for running the first thread block, and data that causes the page fault exception for running the second thread block. The number of the backup thread blocks configured on the processor is determined by the following operations: obtaining a state feature based on running state information of the processor and a hardware index of the processor in a historical period; evaluating the number of the backup thread blocks based on the state feature to obtain an action evaluation result for adjusting the number of the backup thread blocks; and obtaining the number of the backup thread blocks in a current period based on a historical number of the backup thread blocks in the historical period and the action evaluation result.

2. The method of claim 1, wherein, The method further comprises: sorting the plurality of backup thread blocks based on priorities of tasks to be executed by the backup thread blocks to obtain a thread block sorting result; determining a candidate backup thread block from the backup thread blocks based on the thread block sorting result; and in a case where it is determined that part of data required for running the candidate backup thread block has been stored in the storage unit of the processor, taking the candidate backup thread block as the second thread block.

3. The method of claim 1, wherein, Running a second thread block on the processor comprises: migrating data required for running the second thread block and a context of the second thread block to a storage unit of the processor, wherein the context of the second thread block is used to represent a running state of the second thread block.

4. The method of claim 1, wherein, Interrupting running of the first thread block comprises: saving a context of the first thread block to a global memory, wherein the context of the first thread block represents a running state of the first thread block.

5. The method of claim 1, wherein, The response to the current time being the target time, merging the plurality of to-be-migrated pages that cause the page fault exception as the batch migration pages comprises: in a case where a data amount of the determined plurality of to-be-migrated pages exceeds a predetermined data amount threshold, sorting the plurality of to-be-migrated pages according to an exception determination time to obtain a time sorting result; based on the time sorting result, taking the plurality of to-be-migrated pages that satisfy the predetermined data amount threshold as the batch migration pages.

6. The method of claim 5, wherein, The response to the current time being the target time, merging the plurality of to-be-migrated pages that cause the page fault exception as the batch migration pages further comprises: In a case where it is determined that the data amount of the plurality of to-be-migrated pages does not exceed the predetermined data amount threshold, the plurality of to-be-migrated pages are merged as the batch-migrated pages.

7. The method according to claim 5 or 6, characterized in that, The method further includes: evaluating a plurality of physical memory pages stored in a storage unit of the processor to obtain a page evaluation result; and in a case where the page evaluation result indicates that a target physical memory page is not suitable for a target thread block, migrating the target physical memory page from the storage unit of the processor to the extended storage space as an evicted page, wherein the target physical memory page is allocated for use by the target thread block, and the target thread block is a thread block that runs in parallel with the first thread block or the second thread block on the processor.

8. The method of claim 1, wherein, The method further includes: in a case where it is determined that the free capacity of the storage unit of the processor satisfies the batch-migrated pages, locking a target page table entry in a page table to prevent write operations on the target page table entry, and migrating the batch-migrated pages from the extended storage space to the storage unit of the processor; and updating a mapping relationship between a virtual memory address and a physical memory address of the target page table entry in the page table.

9. The method of claim 1, wherein, The method further includes: querying, based on a virtual memory address of a target thread, data required by the target thread running on the processor from a page table to obtain a query result, wherein the page table represents a mapping relationship between a virtual memory address and a physical memory address; and in a case where the query result indicates that the data required by the target thread is stored in the extended storage space, determining that a thread bundle to which the target thread belongs has a page fault exception, and interrupting execution of the thread bundle to which the target thread belongs, wherein a plurality of threads in the thread bundle respectively process different data according to the same instruction.

10. The method of claim 1, wherein, The method further includes: respectively performing feature extraction on the running state information and the hardware indicator to obtain running state features and indicator features; and performing feature fusion on the running state features and the indicator features to obtain the state features.

11. The method of claim 1 or 10, wherein, The method further includes: identifying a processing performance of a to-be-migrated physical memory page to obtain a page processing performance identification result; identifying an access attribute of a physical memory page to obtain a page access attribute identification result; identifying a running performance of a thread block running on the processor to obtain a thread running performance identification result; and obtaining the running state information based on the page processing performance identification result, the page access attribute identification result, and the thread running performance identification result; determining a processing indicator and a hardware resource indicator of the batch-migrated pages; and determining the hardware indicator based on the processing indicator and the hardware resource indicator.

12. The method of claim 10, wherein, The method includes: determining a model evaluation result based on a current performance monitoring result of a current time period and a historical performance monitoring result of a historical time period; and determining a model evaluation result based on a current performance monitoring result of a current time period and a historical performance monitoring result of a historical time period; and Based on the model evaluation result, the action evaluation model is optimized and trained to obtain an optimized and trained action evaluation model, wherein the action evaluation model is used to evaluate the number of the standby thread blocks based on the state features to obtain an action evaluation result for adjusting the number of the standby thread blocks.

13. The method of claim 12, wherein, The model evaluation result is determined based on the current performance monitoring result of the current period and the historical performance monitoring result of the historical period, including: Based on the processed task amount of each of the current period and the historical period, a first evaluation result for a task execution performance indicator is determined; Based on the premature reclamation rate change rate of the batch migration pages of each of the current period and the historical period, a second evaluation result for an unreasonable management indicator is determined; Based on the resource occupation monitoring result of the current period, a third evaluation result for a resource occupation indicator is determined; and The model evaluation result is determined based on the first evaluation result, the second evaluation result, and the third evaluation result.

14. The method of claim 13, wherein, The model evaluation result is determined based on the first evaluation result, the second evaluation result, and the third evaluation result, including: The first evaluation result and the second evaluation result are respectively data-converted to determine a first target value representing performance gain and a second target value representing management performance loss; Based on the sub-evaluation results for the time occupation indicator and the bandwidth resource occupation indicator in the third evaluation result, a third target value representing resource occupation is determined; According to the first target value, the second target value, and the third target value, a target value is obtained; and Based on the target value and an evaluation threshold, the model evaluation result is obtained.

15. An exception handling apparatus, comprising: an interrupt module configured to interrupt running of a first thread block of a processor in a case where it is determined that the first thread block has a page fault exception, wherein the first thread block includes a plurality of thread bundles, the first thread block having the page fault exception indicates that all of the plurality of thread bundles have the page fault exception, and a thread bundle having the page fault exception indicates that data required for running the thread bundle is stored in an extended storage space; an activation module configured to run a second thread block on the processor, wherein the second thread block is determined from a plurality of standby thread blocks; and a migration module configured to, in response to a current time being a target time, combine a plurality of to-be-migrated pages that cause the page fault exception as batch migration pages, and migrate the batch migration pages from the extended storage space to a storage unit of the processor in batches, wherein the to-be-migrated pages include at least one of data that causes the page fault exception for running the first thread block and data that causes the page fault exception for running the second thread block. The number of standby thread blocks configured on the processor is determined by a standby block determination module, including: a standby block determination module configured to determine the number of the standby thread blocks based on running state information of the processor and hardware indicators of the processor in a historical period; and The standby block determination module includes: a state feature determination submodule, configured to determine a state feature based on the running state information and the hardware indicator; an action evaluation submodule, configured to evaluate the number of the standby thread blocks based on the state feature, and obtain an action evaluation result for adjusting the number of the standby thread blocks; a standby block determination submodule, configured to determine the number of the standby thread blocks in a current time period based on a historical number of the standby thread blocks in a historical time period and the action evaluation result. 16.An electronic device, comprising: one or more processors; memory storing one or more programs, when the one or more programs are executed by the one or more processors, cause the one or more processors to implement the method according to any one of claims 1-14.

17. A computer-readable storage medium, characterized in that, The computer readable storage medium stores executable instructions, which when executed by a processor, cause the processor to implement the method according to any one of claims 1-14.

18. A computer program product, characterised in that, The computer program product comprises a computer program, which when executed by a processor, implements the method according to any one of claims 1-14.

Images