Methods for handling forced assignment statements based on wire meshes, electronic devices and media

Abstract

This invention relates to the field of digital simulation technology, and more particularly to a method, electronic device, and medium for processing forced assignment statements based on nets. The method, during the compilation phase, first obtains the bits of the target net affected by the forced assignment statement, then obtains the bit information and driver list of the corresponding top-level module for each bit, and records them in a preset database file. Each driver is then transferred bit by bit to the corresponding bit of the top-level module. During the simulation phase, when a forced assignment statement occurs, a forced assignment state is applied to the corresponding bit of the top-level module based on the preset database file, and the corresponding signal value is updated to the signal value corresponding to the forced assignment statement. This invention reduces the time and memory overhead required for forced assignment statements during digital simulation.

Description

Technical Field

[0001] This invention relates to the field of digital simulation technology, and in particular to a method for processing forced assignment statements based on nets, an electronic device, and a medium. Background Technology

[0002] Forced assignment statements can forcibly modify signal values ​​during digital simulation, ensuring that any value driven by the circuit cannot affect the forcibly assigned signal value. In chip design scenarios with a large number of layers and complex data content at some levels, nets may be connected to various modules via ports. During digital simulation, to maintain the forcibly assigned signal value at each port of each module, it is necessary to locate the ports of each module connected to the net. However, since each module may have a driver for the current net, existing technologies, when implementing forced assignment statements during digital simulation, require assigning a forcibly modified state and the forcibly modified signal value to the corresponding ports of all modules connected to the net. In complex designs, this is time-consuming and consumes a significant amount of memory. Therefore, reducing the time required for forced assignment statements and minimizing memory overhead during digital simulation is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a method, electronic device, and medium for processing forced assignment statements based on wire meshes, which reduces the time and memory overhead required for forced assignment statements during digital simulation.

[0004] According to a first aspect of the present invention, a method for processing forced assignment statements based on nets is provided, comprising:

[0005] Step S1: During the compilation phase, obtain the bits {A1, A2, ..., A...} of the target nets in the chip design that are affected by the forced assignment statements. n ,...,A N}, A n The target net is the nth bit affected by the forced assignment statement, where n ranges from 1 to N, and N is the total number of bits affected by the forced assignment statement. The target net is a net that is set with a forced assignment statement and is connected to the input port of the target module or the input port of the submodule instantiation of the target module.

[0006] Step S2: Obtain each A n The corresponding top module bit information B n And A n The corresponding driver list {C1 n C2 n ,...,C i n ,...,Cf(n) n} and record it to the preset database file, C i n For A n The corresponding i-th driver, where i ranges from 1 to f(n), and f(n) is A n The corresponding total number of drivers;

[0007] Step S3: Assign each C bit in the chip design. i n Transfer to the corresponding B n The compiled files are generated, and then the simulation phase begins.

[0008] Step S4: During the simulation phase, the simulation process is executed based on the compiled file. When the forced assignment statement occurs, the forced assignment statement identifier and each A are used to perform the simulation. n Query the preset database file to obtain each A n Corresponding B n ;

[0009] Step S5: For each B n Apply a forced assignment state to B n The corresponding signal value is updated to B in the forced assignment statement. n The corresponding signal value.

[0010] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0011] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0012] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the present invention provides a method, electronic device, and medium for processing net-based forced assignment statements, achieving considerable technological advancement and practicality, and possessing broad industrial application value. It has at least the following beneficial effects:

[0013] This invention first obtains the bits affected by the forced assignment statement in the target net during the compilation phase, then obtains the bit information and driver list of the corresponding top-level module for each bit, and records them in a preset database file. Each driver is then transferred bit by bit to the corresponding bit of the top-level module. During the simulation phase, when the forced assignment statement occurs, the bit of the corresponding top-level module is forced to a specific state based on the preset database file, and the corresponding signal value is updated to the signal value specified in the forced assignment statement. By adjusting the connection method between drivers and signals and recording the optimization target of the forced assignment statement, this invention achieves significant optimization by requiring only one assignment to force the state and assign the forced modified signal value information. This reduces the time and memory overhead required for forced assignment statements during digital simulation. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 The flowchart illustrates the method for processing forced assignment statements based on wire meshes, as provided in this embodiment of the invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] This invention provides a method for processing forced assignment statements based on nets, such as... Figure 1 As shown, it includes:

[0018] Step S1: During the compilation phase, obtain the bits {A1, A2, ..., A...} of the target wire in the chip design that are affected by the forced assignment statement. n ,...,A N}, A n The target net is the nth bit affected by the forced assignment statement, where n ranges from 1 to N, and N is the total number of bits affected by the forced assignment statement. The target net is a net that is set with a forced assignment statement and is connected to the input port of the target module or the input port of a submodule of the target module.

[0019] It should be noted that N≥1, meaning that in chip design, the bit affected by the forced assignment statement for the target net can be a single bit or multiple bits. A1,A2,...,A n ,...,A N The bits can be continuous, discontinuous, or partially continuous and partially discontinuous. For example, the target net width is 64 bits, and the bits affected by the forced assignment statement are bits 0-31. It is understood that the object optimized by this invention is a net that satisfies the setting of a forced assignment statement and is connected to the input port of the target module or the input port of a submodule instantiated from the target module. An input port refers to a port where signal values ​​flow from outside the module to the module.

[0020] Step S2: Obtain each A n The corresponding top module bit information B n And A n The corresponding driver list {C1 n C2 n ,...,C i n ,...,C f(n) n} and record it to the preset database file, C i n For A n The corresponding i-th driver, where i ranges from 1 to f(n), and f(n) is A n The total number of corresponding drivers.

[0021] It should be noted that A n The corresponding driver is capable of changing A. n The corresponding driving signal. f(n)≥0, that is, A n The corresponding top-level module driver may not exist, may be one, or may be multiple.

[0022] Step S3: Assign each C bit in the chip design. i n Transfer to the corresponding B n The compiled files are generated, and then the simulation phase begins.

[0023] It should be noted that, through the processing in step S3, for the net affected by the forced assignment statement, all drivers that may affect the signal value in the entire chip design are transferred to the top signal. It is understood that steps S1-S3 are executed during the compilation phase, and steps S4-S5 are executed during the simulation phase.

[0024] Step S4: During the simulation phase, the simulation process is executed based on the compiled file. When the forced assignment statement occurs, the forced assignment statement identifier and each A are used to perform the simulation. n Query the preset database file to obtain each A n Corresponding B n .

[0025] It should be noted that during the simulation phase, the simulation runs normally. When a forced assignment statement occurs, it triggers an event that acts on the target net, specifically through steps S4-S5.

[0026] Step S5: For each B n Apply a forced assignment state to B n The corresponding signal value is updated to B in the forced assignment statement. n The corresponding signal value.

[0027] It should be noted that since all drivers are transferred to the corresponding top-level signals, when the signal values ​​of these drivers change and are transmitted to the corresponding top-level signals, they will be blocked by the forced assignment state. The direction towards the sub-modules are all input ports, ensuring that the signal values ​​transmitted by the nets associated with all sub-modules in the entire chip design are the signal values ​​assigned by the forced assignment statement, thereby achieving the effect of the forced assignment statement.

[0028] This invention significantly improves the performance of forced assignment statements by adjusting the connection method between the driver and the signal, and the net object on which the forced assignment statement operates, provided that the simulation function is correct. The improvement is even more significant in complex designs. Furthermore, since applying the forced state and retaining the forced assignment signal value also require memory overhead, memory usage can be greatly reduced even in complex designs.

[0029] As one embodiment, step S1 includes:

[0030] Step S11: During the compilation phase, the modules with mandatory assignment statements in the chip design are identified as target modules.

[0031] Among them, the forced assignment statement is usually a statement containing "force".

[0032] Step S12: If the forced assignment statement is applied to a net and the net is connected to the input port of the target module or the input port of a submodule instantiated by the target module, then the net applied by the forced assignment statement is determined as the target net.

[0033] It should be noted that the object optimized in the embodiments of the present invention must satisfy the requirement that the net acted upon by the forced assignment statement is connected to the input port of the target module or the input port of the submodule instantiation of the target module.

[0034] Step S12: Obtain the bits {A1, A2, ..., A} of the target net in the chip design that are affected by the forced assignment statement. n ,...,A N}

[0035] It should be noted that the bits that are affected are explicitly recorded in the forced assignment statement. Therefore, the bits affected by the forced assignment statement of the target net can be obtained directly based on the forced assignment statement corresponding to the target net.

[0036] As one embodiment, in step S2, each A is obtained. n The corresponding top module bit information B n ,include:

[0037] Step S21, based on A n Traverse outwards from the target module port or the input port of the target module's submodule instantiation to obtain each A. n The corresponding top module bit information B n .

[0038] It should be noted that each A n Bit information B corresponding to only one top module n .

[0039] As one embodiment, in step S2, each A is obtained. n The corresponding driver list {C1 n C2 n ,...,C i n ,...,C f(n) n},include:

[0040] Step S22: Obtain each A in the chip design n All connected module ports and signals.

[0041] It should be noted that by analyzing the code files corresponding to the chip design, it is possible to obtain the details of each A. n All connected module ports and signals.

[0042] Step S33: Traverse the chip design and obtain each A n List of all connected module ports and signals, and their corresponding drivers {C1} n C2 n ,...,C i n ,...,C f(n) n}

[0043] It should be noted that by traversing the code files corresponding to the chip design, it is possible to obtain each A... n A list of all connected module ports and corresponding drivers for each signal, for each A. n The driver list corresponding to all connected module ports and signals can contain one or more drivers, or it can be empty.

[0044] As one embodiment, step S3 includes:

[0045] Step S31: For each C in the chip design... i n Transfer bit by bit to the corresponding B n .

[0046] It should be noted that step S31 performs bit-by-bit processing on the drive transfer operation, but in some scenarios, for multiple consecutive B... n Entries belonging to the same top-level module, with consecutive bits and identical driver lists, can be combined for overall operation. This reduces the number of jumps and further improves the efficiency of forced assignment statement processing while ensuring the correctness of the result.

[0047] As one embodiment, step S3 includes:

[0048] Step C31: If there are multiple consecutive B... n If multiple consecutive B's belong to the same top-level module, have consecutive bits, and have the same driver list, then these multiple consecutive B's will be... n Merge them into a single bit range.

[0049] Step C32: Transfer the entire driving force corresponding to all bits in the bit range to the corresponding bit range.

[0050] Step C33: Remove B that does not belong to the bit interval. n Each corresponding C i n Transfer bit by bit to the corresponding B n .

[0051] It should be noted that steps C31-C32 achieve the processing of multiple consecutive B values. n Entries belonging to the same top-level module, with consecutive bits and identical driver lists, can be combined for overall operation. This reduces the number of jumps and further improves the efficiency of forced assignment statement processing while ensuring the correctness of the result.

[0052] It should be noted that the forced assignment statement can be applied to the entire simulation phase or only to a portion of the simulation phase. If it is necessary to apply only to a portion of the simulation phase, a time period corresponding to the forced assignment statement needs to be set in the chip design. In such a scenario, as an example, the interval between steps S3 and S4 includes:

[0053] Step S10: If the chip design has a time period corresponding to the forced assignment statement, then steps S4-S5 are executed within the time period, and the simulation process is executed outside the time period according to the original chip design under the invalid state of the forced assignment statement.

[0054] It should be noted that if the chip design includes a time period for the forced assignment statement, then within that time period, the forced assignment statement is implemented based on the transferred driver and a preset database file. Outside of the time period, the simulation process must be executed according to the original chip design under the invalid state of the forced assignment statement. The time period for the forced assignment statement can be flexibly set according to specific application requirements.

[0055] In this embodiment of the invention, during the compilation phase, the bits affected by the forced assignment statement of the target net are first obtained, then the bit information and driver list of the corresponding top-level module are obtained for each bit, and recorded in a preset database file. Each driver is then transferred bit by bit to the corresponding bit of the top-level module. During the simulation phase, when the forced assignment statement occurs, the bit of the corresponding top-level module is forced to a specific state based on the preset database file, and the corresponding signal value is updated to the signal value corresponding to the forced assignment statement. By adjusting the connection method between drivers and signals and recording the optimization target of the forced assignment statement, this invention achieves a significant optimization by requiring only one assignment to force the state and the signal value information to be forcibly modified. This reduces the time and memory overhead required for forced assignment statements during digital simulation.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0057] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0058] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0059] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for processing forced assignment statements based on wire meshes, characterized in that, include: Step S1: During the compilation phase, obtain the bits {A1, A2, ..., A...} of the target nets in the chip design that are affected by the forced assignment statements. n ,...,A N }, A n The target net is the nth bit affected by the forced assignment statement, where n ranges from 1 to N, and N is the total number of bits affected by the forced assignment statement. The target net is a net that is set with a forced assignment statement and is connected to the input port of the target module or the input port of the submodule instantiation of the target module. Step S2: Obtain each A n The corresponding top module bit information B n And A n The corresponding driver list {C1 n C2 n ,...,C i n ,...,C f(n) n } and record it to the preset database file, C i n For A n The corresponding i-th driver, where i ranges from 1 to f(n), and f(n) is A n The corresponding total number of drivers; Step S3: Assign each C bit in the chip design. i n Transfer to the corresponding B n The compiled files are generated, and then the simulation phase begins. Step S4: During the simulation phase, the simulation process is executed based on the compiled file. When the forced assignment statement occurs, the forced assignment statement identifier and each A are used to perform the simulation. n Query the preset database file to obtain each A n Corresponding B n ; Step S5, for each B n Apply a forced assignment state to B n The corresponding signal value is updated to B in the forced assignment statement. n The corresponding signal value.

2. The method according to claim 1, characterized in that, Step S1 includes: Step S11: During the compilation stage, the modules with forced assignment statements in the chip design are identified as target modules; Step S12: If the forced assignment statement is applied to a net and the net is connected to the input port of the target module or the input port of a submodule of the target module, then the net applied by the forced assignment statement is determined as the target net. Step S12: Obtain the bits {A1, A2, ..., A} of the target net in the chip design that are affected by the forced assignment statement. n ,...,A N } 3. The method according to claim 1, characterized in that, In step S2, each A is obtained. n The corresponding top module bit information B n ,include: Step S21, based on A n Traverse outwards from the target module port or the input port of the target module's submodule instantiation to obtain each A. n The corresponding top module bit information B n .

4. The method according to claim 1 or 2, characterized in that, In step S2, each A is obtained. n The corresponding driver list {C1 n C2 n ,...,C i n ,...,C f(n) n },include: Step S22: Obtain each A in the chip design n All connected module ports and signals; Step S23: Traverse the chip design and obtain each A n List of all connected module ports and signals, and their corresponding drivers {C1} n C2 n ,...,C i n ,...,C f(n) n } 5. The method according to claim 1, characterized in that, Step S3 includes: Step S31: For each C in the chip design... i n Transfer bit by bit to the corresponding B n .

6. The method according to claim 1, characterized in that, Step S3 includes: Step C31: If there are multiple consecutive B... n If multiple consecutive B's belong to the same top-level module, have consecutive bits, and have the same driver list, then these multiple consecutive B's will be... n Merge into a single bit range; Step C32: Transfer the entire driving force corresponding to all bits in the bit range to the corresponding bit range; Step C33: Remove B that does not belong to the bit interval. n Each corresponding C i n Transfer bit by bit to the corresponding B n .

7. The method according to claim 1, characterized in that, The interval between step S3 and step S4 includes: Step S10: If the chip design has a time period corresponding to the forced assignment statement, then steps S4-S5 are executed within the time period, and the simulation process is executed outside the time period according to the original chip design under the invalid state of the forced assignment statement.

8. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-7.

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