H2P branch prediction chip circuit architecture based on BrPerceptron

Abstract

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit processor micro-architecture design, in particular to a BrPerceptron-based H2P branch prediction chip circuit architecture. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] With the rapid development of heterogeneous computing and intelligent terminals, processor architecture faces more stringent demands for higher throughput and lower latency in scenarios such as autonomous driving and real-time edge inference. Although superscalar design and out-of-order execution technology greatly improves instruction-level parallelism, the uncertainty of control flow remains a core bottleneck that restricts performance. Under the von Neumann architecture, the pipeline needs to continuously deal with the control hazard problem caused by branch instructions: the instruction fetch unit frequently stalls due to waiting for branch resolution results, and the pipeline flush caused by incorrect prediction further exacerbates performance loss.

[0004] In traditional solutions, static branch prediction (such as always jump / not jump) has low hardware cost, but the average accuracy is less than 65%, which is difficult to adapt to dynamic program behavior; dynamic predictors (such as two-bit saturating counters, Gshare) improve accuracy through historical pattern learning, but are limited by branch aliasing (Alias) and insufficient history depth, with a sharp increase in misprediction rate in long cycle loops or indirect jump scenarios. For example, indirect branches have a branch target buffer (BTB) hit rate of less than 70% due to dynamic changes in target addresses, while perceptron predictors can capture non-linear patterns, but their hardware overhead (such as weight table storage) limits large-scale deployment. Especially in high-performance multi-core processors, branch density increases significantly with the number of threads, and the convergence of predictor throughput and timing is highlighted. Existing hybrid prediction architectures (such as TAGE-SC-L) optimize long-range associations through multi-level history tables, but due to the fixed threshold mechanism, they are difficult to adapt to program phase changes, with a misjudgment rate of more than 15% in burst noise branches (such as random number driven conditions), in addition, chip area and power consumption constraints are tightened under advanced processes, and existing predictors cannot achieve a more fine-grained trade-off between accuracy, latency, and energy efficiency. SUMMARY

[0005] To solve the problems of the prior art, the present application provides a BrPerceptron-based H2P branch prediction chip circuit architecture, which realizes high-precision prediction for H2P (Hard To Predict) branch instructions and significantly improves the branch prediction efficiency of RISC-V superscalar processors.

[0006] To achieve the above purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a BrPerceptron-based H2P branch prediction chip circuit architecture.

[0008] A BrPerceptron-based H2P branch prediction chip circuit architecture comprises:

[0009] A context-sensitive variable tracking mechanism is used to construct a variable operation trajectory of a program, a basic block partition algorithm is used to construct a program execution path topology based on the variable operation trajectory, multi-dimensional correlation detection is performed based on the program execution path topology to determine whether it is an H2P branch, and when it is determined to be an H2P branch, H2P control register enabling code is inserted to enable a BrPerceptron predictor.

[0010] The BrPerceptron predictor comprises a fully connected layer and a plurality of sub-channels, each of which comprises a data input module, a feature extraction module and a result prediction module connected in sequence, the feature extraction module comprises an encoding layer, an embedding layer, a convolution layer and a pooling layer connected in sequence, the input of the encoding layer is part of the PC bit and the jump direction, and the result prediction module uses a fully connected layer to perform multi-level feature fusion on the output of the pooling layer of each sub-channel and output a prediction result.

[0011] As a further limitation of the first aspect of the present application, the context-sensitive variable tracking mechanism is used to construct a variable operation trajectory of a program, comprising:

[0012] An improved depth-first AST traversal algorithm is used to maintain a definition-use chain for each variable, and context information is recorded in a stack structure to record the function call chain and the loop nesting level; a feature set containing modulus operation, random number generation, external input and pointer reference is defined, and a dynamic feature recognition algorithm based on syntax pattern matching is used to identify the composite feature containing array access and modulus operation; a function summary technique is used to realize inter-process data flow tracking, and the actual parameters of the call point are dynamically associated with the formal parameters through a parameter binding mechanism.

[0013] As a further limitation of the first aspect of the present application, a basic block partition algorithm is used to construct a program execution path topology based on the variable operation trajectory, comprising:

[0014] Each basic block follows the single-entry single-exit principle, and the maximum code length is limited to N instructions;

[0015] For a loop structure, Tarjan's strongly connected component algorithm is used to identify a natural loop, and a feature vector containing features such as iteration variable and boundary type is extracted;

[0016] The loop boundary types are divided into static and dynamic types, wherein the dynamic boundary is defined as a loop termination condition containing data-dependent computation, and the control influence relationship between branch nodes is identified by calculating the nearest control decision point.

[0017] As a further limitation of the first aspect of the application, the multi-dimensional correlation detection according to the program execution path topology determines whether it is an H2P branch, including:

[0018] In the data dependency dimension, the variable definition chain of the conditional expression is analyzed by formal analysis to identify the dependency relationship containing dynamic computation characteristics, in the control flow dimension, whether the branch is located inside the dynamic boundary loop is detected, and the relevance of the branch condition to the loop control variable is verified, in the historical correlation dimension, the cross-branch variable influence graph is constructed, and whether the branch condition is affected by the historical execution state is determined by the transitive closure calculation, only when the branch satisfies the three conditions of data dependency, control flow dependency and historical correlation at the same time, it is finally determined as an H2P branch.

[0019] As a further limitation of the first aspect of the application, in the encoding layer, the PC is left shifted by 1 bit and the direction is subjected to a bit or operation to obtain the BrIndex of each PC, and the BrIndex is subjected to a hash operation to reduce the bit width, and for each sub-channel, the BrIndex with reduced bit width is combined into a BrIndex sequence in the order of the latest branch insertion in the front.

[0020] As a further limitation of the first aspect of the application, the embedding layer takes the BrIndex sequence as input and converts it into a vector;

[0021] The convolution layer performs convolution operation on the input vector, each sub-channel uses 1D convolution, and each convolution layer has multiple feature extractors to identify the features of the input data;

[0022] The pooling layer uses sum-pooing sum pooling to downsample the output of each sub-channel convolution layer, and gradually increases the downsample strength with the increase of the sequence length.

[0023] As a further limitation of the first aspect of the application, when using an offline training model, the result obtained after normalization and sigmoid activation represents the value corresponding to the BrIndex after hash operation, and the value is stored and indexed by the BrIndex after hash operation to obtain the corresponding value.

[0024] As a further limitation of the first aspect of the application, the fully connected layer contains N parallel processing units, each processing unit establishes global connection with all output channels of the feature extraction module through a learnable weight matrix, realizes comprehensive perception and nonlinear combination of cross-dimension features, and adjusts the activation value distribution according to real-time input through dynamic batch normalization.

[0025] As a further limitation of the first aspect of the application, a three-stage pipeline design is adopted, the first stage calculates the indexes and hash values of TAGE-EC and BrPerceptron in parallel, the second stage synchronously accesses the TAGE history table, the EC correction table and the SRAM weight table of BrPerceptron, a dual-port SRAM design is adopted to support 2 read operations per cycle, and the bandwidth matches the dual-issue requirement of the superscalar processor; the third stage dynamically selects the prediction result according to the H2P identification, if the current branch is labeled as H2P, the output of BrPerceptron is preferred, otherwise, the TAGE-EC result is used.

[0026] In a second aspect, the application provides a BrPerceptron-based H2P branch prediction method.

[0027] A BrPerceptron-based H2P branch prediction method includes the following processes:

[0028] A context-sensitive variable tracking mechanism is used to construct the variable operation trajectory of the program, a basic block division algorithm is used to construct the program execution path topology based on the variable operation trajectory, and a multi-dimensional correlation detection is performed based on the program execution path topology to determine whether it is an H2P branch, and when it is determined to be an H2P branch, the BrPerceptron predictor is enabled.

[0029] The BrPerceptron predictor includes a fully connected layer and a plurality of sub-channels, each sub-channel includes a data input module, a feature extraction module and a result prediction module connected in sequence, the feature extraction module includes an encoding layer, an embedding layer, a convolution layer and a pooling layer connected in sequence, the input of the encoding layer is part of the PC bit and the jump direction, and the result prediction module uses a fully connected layer to perform multi-level feature fusion on the output of the pooling layer of each sub-channel and output a prediction result.

[0030] Compared with the prior art, the application has the following advantages:

[0031] 1. The application proposes a BrPerceptron architecture based on neural network, which significantly improves the H2P branch prediction accuracy, through multi-sub-channel feature extraction (32 / 64 / 128-bit history sequence) and Sum-Pooling noise suppression technology, in the Mibenchqsort test, the MPKI (mis-prediction per thousand instructions) is reduced by 26.67% (11.51→8.44), the number of false predictions is reduced by 26.7% (2747→2013), and the prediction advantage of data-dependent branches is verified.

[0032] 2、The application designs dynamic hardware integration and three-stage pipeline optimization, realizes high-throughput and low-delay prediction, separates the offline training and online inference through an architecture, stores the pre-calculated convolution results to SRAM, compresses the hardware delay to 3 periods (F1-F3), meets the 250MHz high-frequency timing requirement, in SPEC2017 test, compared with TAGE-SC-L predictor, the average MPKI is reduced by 7.8%, and the peak prediction accuracy is increased to 95.3%.

[0033] 3、The application proposes an H2P branch automatic labeling algorithm, and realizes software and hardware collaborative optimization. Based on joint analysis of data flow and control flow, data dependency type branches are accurately identified, BrPerceptron is enabled (MHCR bit 19 control) through inline assembly dynamic switching, the code insertion overhead is only 2 instructions, and the influence on CPI is less than 0.1%. In the complex control flow scene, the area of the branch prediction unit is only increased by 12.3% (UMC 55nm process).

[0034] 4、The application adopts a low-power design strategy, and considers performance and energy efficiency, through clock gating and non-active sub-channel hibernation technology, the static power consumption is reduced by 78%, the overall power consumption is controlled to be 31.9664mW (UMC 55nm), in the edge computing scene, the energy efficiency ratio is 0.52DMIPS / mW, which is increased by 40% compared with the traditional scheme.

[0035] 5、The application verifies the driving optimization, provides a high energy efficiency solution for the RISC-V ecology, in FPGA prototype verification, the processor carrying BrPerceptron successfully starts the Linux system and passes the PCIE peripheral test, the Coremark measured performance is 5.29189 (iterations / sec) / MHz, which is increased by 1.94% compared with the baseline C910 architecture, and is suitable for AI accelerator and Internet of Things terminal and other high requirement scenes.

[0036] 6、The application realizes efficient system integration through FPGA prototype verification, runs at 50MHz clock on the Xilinx Virtex UltraScale platform, occupies 722,250 LUTs, successfully starts Linux and completes PCIE peripheral communication, and the measured CoreMark performance is 5.29189 (iterations / sec) / MHz, which verifies the engineering feasibility of the scheme.

[0037] The advantages of the additional aspects of the application will be partially given in the following description, partially become obvious from the following description, or be known by the practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which form a part of this specification, are included to provide a further understanding of the application and are incorporated herein by reference. The embodiments of the present application, as described herein, are shown by way of illustration and not of limitation.

[0039] Figure 1 A schematic diagram of the principle of BrPerceptron for an exemplary embodiment of the present application;

[0040] Figure 2 Convolution hardware optimization for an exemplary embodiment of the present application;

[0041] Figure 3 H2P automatic labeling algorithm for an exemplary embodiment of the present application;

[0042] Figure 4 BrPerceptron branch predictor enable control bit for an exemplary embodiment of the present application;

[0043] Figure 5 Automatic labeling insertion code example for an exemplary embodiment of the present application;

[0044] Figure 6 Disassembly part example for an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0045] The present application will be further described with reference to the drawings and examples.

[0046] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0047] The embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0048] Embodiment 1:

[0049] The present implementation proposes a BrPerceptron-based H2P branch prediction chip circuit architecture, which will be introduced first. The technical terms and related concepts involved in this processing scheme are as follows:

[0050] RISC-V, Reduced Instruction Set Computing-V, refers to an open reduced instruction set computing architecture;

[0051] CPU, Central Processing Unit, Central Processing Unit;

[0052] BPU, Branch Predict Unit, refers to a branch prediction unit;

[0053] BHR, Branch History Registor, refers to a branch history register;

[0054] GHR, Global History Registor, refers to a global history register;

[0055] BHT, Branch History Table, refers to a branch history table;

[0056] BTB, Branch Target Buffer, refers to a branch target buffer;

[0057] PHT, Pattern History Table, refers to a pattern history table;

[0058] H2P branch, Hard to Predict, refers to a branch that is difficult to predict.

[0059] The present application proposes a BrPerceptron convolutional neural network architecture (referred to as BrPerceptron architecture), which can learn to ignore irrelevant branches and identify relevant branches anywhere in the global branch history, thereby maintaining high efficient prediction function even if the branch history has long time noise. The principle of BrPerceptron convolutional neural network architecture is as follows Figure 1 , the sub-module of the main network in the neural network term is usually called branch, in order to avoid confusion with the naming of branch prediction research, the sub-module is named sub-channel in the present application, BrPerceptron is composed of n (which can be configured according to needs) sub-channels and fully connected layers, wherein each sub-channel can be divided into data input (used for input data), feature extraction and result prediction three modules. The overall design idea is to use BrPerceptron neural network architecture to infer the unknown variables of H2P branch through global history, to use multi-sub-channel parallel feature extraction mode, and each sub-channel maintains branch history sequence (32 / 64 / 128 bits) of different lengths, covering short cycle and long-range association mode.

[0060] According to the BrPerceptron architecture described above, the feature extraction module is mainly divided into four modules: the encoding layer, the embedding layer, the convolution layer and the pooling layer. The input of the encoding layer is part of the PC bit and the jump direction, which is encoded according to the PC direction and marked as BrIndex. The specific implementation is to perform a bit OR operation on the 16-bit PC left shifted by 1 bit and the 1-bit jump direction to generate a 17-bit unique identifier BrIndex=(PC<<1)|direction, which enhances the branch context representation capability. For each sub-channel, the BrIndex is combined into a BrIndex sequence according to the order of inserting the latest branch into the front, and the lengths L of the respective sequences of the three sub-channels are defined as 32, 64 and 128, respectively, to cover short-term and long-range correlation patterns. The BrIndex sequence of each length is updated and maintained. The present application uses 16-bit PC bits, and the range represented by each BrIndex is 216+1-1 through combination.

[0061] The embedding layer takes the BrIndex sequence as input and converts it into a vector. For each sub-channel, the input is composed of part of the PC bit and the jump direction connection, so the input size of each sub-channel is the PC bit width plus 1. As known from the construction of the trace in section 3.2.2, the embedding layer combines the PC part bit and the jump direction into a vector. For a vector group, the number of rows is determined by the number of BrIndex inputs, and the number of columns is determined by the dimension of the embedding layer. Compared with another common encoding method, one-hot code, using the embedding layer encoding can use a fixed dimension, while the dimension of one-hot code will increase with the increase of BrIndex number, causing an exponential explosion. In the present application, the dimension of the embedding layer is set to 16.

[0062] The convolution layer performs convolution operation on the input vector. BrPerceptron uses 1D convolution for each sub-channel, which includes 3 feature extractors (to capture local historical correlation) and the convolution width is set to 2 (to identify adjacent branch jump correlation, such as continuous jump in loop body). Each convolution layer has multiple feature extractors to identify the features of the input data. The convolution width is used to control the number of adjacent features. For branch prediction, the more the number of feature extractors, the more branch history features can be learned independently. The larger the convolution width, the farther the branch sequence can be identified, but the hardware area and frequency performance need to be considered. For the output of each feature extractor, in order to prevent the problem of gradient disappearance, the data is concentrated in the linear region of the activation function to avoid entering the saturation region, and the Batch Normalization normalization operation is performed on the data to convert its value to a standard normal distribution, so as to find the optimal solution without affecting the prediction performance. In order to avoid all components being linear functions, the data after normalization will be sent to the activation function, and the present application selects Sigmoid as the activation function.

[0063] The pooling layer will use sum-pooling sum pooling to down-sample the output of each sub-channel convolutional layer. The core design idea of this layer is to make the BrPerceptron more robust to branch history changes, eliminate the sensitivity of features to the absolute position in the history sequence, and gradually increase the down-sampling strength as the sequence length increases, that is, proportionally increase the width and stride of the pooling layer (the width and stride of the three sub-channel pooling layers are 5, 10, and 20, respectively).

[0064] In the present embodiment, the result prediction module adopts a multi-level feature fusion architecture design. The first fully connected network includes N parallel processing units. Each unit establishes a global connection with all output channels of the front-end feature extraction module through a learnable weight matrix, realizes comprehensive perception and nonlinear combination of cross-dimension features, and adopts He initialization strategy for parameter initialization to ensure the stability of the activation value distribution in the forward propagation process. The network introduces a batch normalization processing layer after the first fully connected layer, standardizes and calibrates the activation value by dynamically calculating the statistics of the training batch, cooperates with the trainable scale factor and offset parameters, effectively controls the gradient propagation scale, and accelerates the model convergence. The normalized output is processed by a rectified linear unit (ReLU) activation function, which enhances the nonlinearity of feature representation through a threshold filtering mechanism, and produces a sparse activation pattern to improve the generalization ability of the model. The final classification layer adopts a single neuron fully connected structure, uses a Sigmoid activation function to compress the output to the 0-1 probability interval, and sets the threshold to 0.5 (>0.5 predicts jump, otherwise does not jump).

[0065] In the present embodiment, the implementation of hardware needs to consider the rate, resource and other limitations to minimize storage and delay overhead, and the optimization is as follows:

[0066] In the hardware implementation process of the embedding layer, if the above design is followed, with an embedding layer dimension of 16 and a 16-bit PC as an example, a 216x16 LUT lookup table needs to be maintained. This size is unacceptable in hardware, so in the hardware design of the present application, the 17-bit BrIndex will be polynomial hashed (CRC16) first, reducing the 16-bit width to 10-bit width. At this time, the embedding layer only needs to maintain a 1024x16 LUT table item in hardware, greatly reducing the storage cost.

[0067] In the actual hardware implementation of the convolutional layer, real-time convolution operation will consume a lot of time, so when the offline training model is used, the value corresponding to the BrIndex after the current hash operation is obtained after normalization and sigmoid activation. Only a 1024x1 table item needs to be maintained in hardware to store this value. The corresponding value is obtained by indexing the BrIndex after the hash operation, avoiding the performance loss of real-time convolution operation and the 16-dimensional inner product of each convolution operation, such asFigure 2 as shown.

[0068] In the present implementation, in order to realize the BrPerceptron convolutional neural network architecture, H2P Trace is constructed, and the specific method comprises:

[0069] Based on the SPEC 2017 test set, the test suite is composed of 43 benchmark tests, and corresponds to the Speed and Rate versions respectively. Compared with SPEC 2006, the number of dynamic instructions of this version is 10 times higher, and the scale and complexity are extremely high, so the program at this scale makes the test time increase dramatically. For computer architecture research, cycle-level (corresponding to cycle-level in hardware design) simulation is usually required, but at this level of detail, the simulation speed is usually sacrificed. According to statistics, even the fastest simulator (such as gem5) needs several weeks or months to complete the SPEC 2017 execution.

[0070] Based on this problem, Sherwood proposed the SimPoint tool, which aims to compress the program into representative areas, and simulate in these areas to accurately simulate the overall behavior while significantly reducing the simulation time. SimPoint first divides the target program into several equal-length program segments according to the execution order, and calculates the basic block vector (BBV) for each segment area. The vector records the execution frequency of each basic block in the area, and constructs a quantitative representation of program behavior. For high-dimensional BBV features, linear transformation is used to compress them to a low-dimensional space of about 16 dimensions. Based on the reduced feature vector, an improved K-means clustering algorithm is used to perform multi-granularity division on the program segments, and the cluster number K is dynamically adjusted within the preset maximum value range to obtain the optimal division. In each cluster, a most representative program segment is selected as the Simpoint. These selected segments can accurately reflect the overall behavior characteristics of the program with lower time overhead (usually only 1%-3% of the instructions of the original program need to be simulated).

[0071] The present application will generate simpoints in pinball format based on SPEC2017 using Intel's Pinplay tool, the version of Pinplay is v3.7 and the version of SimPoint is 3.2. Firstly, the input benchmark is analyzed using the Pinplay tool, including setting the interval of each block (such as Intervals: 30 million Instructions each, setting 30,000,000 instructions for each block), etc., to generate the BBV file (Basic Block Vector) required for SimPoint analysis, and then the BBV file is analyzed using the SimPoint tool, according to the selection of each stage simulation point, the starting instruction of each simulation point and the block weight are output.

[0072] Through the above operation, the present application analyzes 3 benchmarks (gcc_r, leela_r, perlbench_r) in the SPEC2017 suite.

[0073] Based on the pinball format simpoints generated by the above 3 benchmarks, H2P instructions are constructed. Firstly, Intel Pinplay is used to compile to generate Pin plug-in link file (tracer.so) for recording branch instruction flow, the main operation is to classify the instructions using Intel XED library (XED_CATEGORY_COND_BR, XED_CATEGORY_UNCOND_BR, XED_CATEGORY_CALL, etc.), which can distinguish direct / indirect branches, and through the replay function of the Pinplay tool, the simpoints generated above are executed using tracer.so, since the file is large, bzip2 is used to compress it, and the trace file (*.bz format) containing branch information based on simpoints is generated, the present application defines that each branch record occupies 18 bytes (including 8 bytes pc, 8 bytes target address, 1 byte whether to jump, 1 byte branch type).

[0074] From the definition of H2P branch, the H2P branch instruction performs poorly in the TAGE-SC-L predictor due to the existence of noise in the global branch history, and the prediction accuracy is much lower than that of the remaining branch instructions, so the trace file containing branch information generated based on simpoints is used as the input of the TAGE-SC-L predictor, and the misprediction number per thousand instructions (MPKI) is used as the core index, the higher the MPKI, the more difficult the branch is to predict, the results of multiple input sets running in the TAGE-SC-L predictor are counted, the branch with the greatest impact is selected by the greedy algorithm, and the MPKI of the highest branch is counted as the H2P branch instruction, and the PC value is saved.

[0075] Since the BrPerceptron architecture needs to be trained offline to obtain appropriate weights, the H2P PC obtained above needs to be converted to a format more suitable for training. The input of BrPerceptron requires PC and branch jump history, so the bz2 format trace generated above is used as input, and only the PC address and jump direction in the original trace18Byte are retained. The PC address is 64 bits and the jump direction is 65 bits, which has a large data bit width. The lower 30 bits of the PC can cover a 1GB addressing space, which basically meets the size of most program code segments, so the 65 bits are compressed to only retain the lower 30 bits of the PC and 1 bit of the jump direction as a History table entry. In addition to saving the PC and jump direction, the PC address of the H2P instruction is also obtained in the above, so the high 30 bits of the History table entry are compared with the PC address of the H2P instruction to generate an index of the H2P branch instruction, which indicates the relative position of the H2P instruction in the History table entry.

[0076] In order to facilitate data storage and subsequent fast access, the entire data is saved in HDF5 format to quickly obtain the 1000th branch information. For example, only by writing "history = hdf5_file ['history']

[1000] \ pc = (history >> 1) & 0x3FFFFFFF \ direction = history & 0x1" in the code can the lower 30 bits of the PC and the jump direction be restored.

[0077] In order to verify the reliability of the BrPerceptron model, the above constructed trace is used as input to predict using the TAGE-SC-L predictor and the BrPerceptron predictor proposed by the present application, respectively, and the prediction accuracy of the two predictors at the current PC is counted, and MPKI is used as the final evaluation index, where Tage represents the Tage-SC-L predictor, and Br represents the BrPerceptron predictor. Only part of the comparison is listed.

[0078] According to the data comparison, the BrPerceptron predictor is superior to the Tage-SC-L predictor in overall performance under the H2P branch, with an average branch prediction accuracy of 91.35% (90.03% for Tage-SC-L), and the average MPKI (prediction error times per thousand instructions) is reduced from 5.29116 for Tage-SC-L to 4.87725, a total reduction of 0.41391 (about 7.8%). Although the MPKI of the BrPerceptron predictor increases slightly at individual addresses (such as 0x405b55 and 0x41ff70), it performs significantly better in most scenarios.

[0079] Since the BrPerceptron branch predictor mainly processes H2P branch instructions, and the identification of H2P instructions depends on the context of the entire program, it is difficult to identify H2P instructions by hardware, therefore, a BrPerceptron dedicated H2P control register design and H2P branch identification algorithm is proposed, which identifies H2P branch instructions and inserts H2P control register enable code, and then the hardware uses the BrPerceptron branch predictor to predict H2P instructions.

[0080] The conditions of H2P branches are affected by previous data-dependent branches and variable loops, so it is necessary to identify two conditional branches, one of which (H2P) is separated by a data-dependent loop, and the conditions of the two branches are related, the algorithm needs to find such a pattern: a data-dependent branch A, followed by a data-dependent loop, and after the loop, a branch B whose condition variable is affected by A. Based on the above analysis, an H2P branch automatic labeling algorithm is designed, the overall principle of which is joint analysis based on control flow features and data dependency, and the branch structure conforming to the H2P pattern is identified through static program analysis. The core architecture is composed of three analysis modules working together. As shown in Figure 3 the system first constructs the variable operation trajectory of the program through enhanced data flow analysis, then generates a control flow graph with semantic annotations based on context-aware control flow modeling, and finally determines whether it is an H2P branch through a multi-dimensional correlation detection module.

[0081] Data flow analysis: Construct Def-Use Chain for each variable, track the propagation path of condition variables (e.g. loop counter, array index). Identify dynamic computation features (e.g. modulo operation, random number generation), and mark the branch instructions affected by them. For example, if the branch condition contains arr[i] % 3 == 0, it is determined as a data-dependent branch. Control flow modeling: Identify natural loops by Tarjan algorithm, detect dynamic boundary conditions (e.g. for (i = 0; i < vec[k]; i++)). Construct Post-Dominator Tree, analyze the control dependency between branches. Correlation determination: If the condition variable of branch B is affected by upstream branch A, and A and B are dynamically loop-isolated, mark B as H2P branch. For example, in quicksort, the outer loop boundary is determined by the partition result, and the inner branch is marked as H2P.

[0082] More specifically, at the data flow analysis level, the present application designs a context-sensitive variable tracking mechanism. Through an improved depth-first AST traversal algorithm, the system maintains a Def-Use Chain for each variable, with context information recorded in a stack structure to represent the function call chain and loop nesting level. This design effectively solves the variable shadowing problem caused by scope nesting in traditional methods. For example, when processing double nested loops, the variable definitions in the inner loop will record the context information of the outer loop. To further identify dynamic computation features, the system defines a feature set containing modulo operation, random number generation, external input, and pointer reference, and develops a dynamic feature recognition algorithm based on syntax pattern matching. This algorithm can accurately detect complex features such as uvec[k] % 3 > 0, which contains array access and modulo operation. To meet the needs of cross-process analysis, the present application uses function abstraction technology to realize inter-process data flow tracking, and dynamically associates the actual parameters of the call site with the formal parameters through a parameter binding mechanism.

[0083] The control flow modeling module constructs an accurate program execution path topology based on an improved basic block partitioning algorithm. Each basic block follows the single-entry single-exit principle, with a maximum code length limit of 10 instructions to ensure analysis granularity. For loop structures, the system applies Tarjan's strongly connected component algorithm to identify natural loops, and extracts feature vectors containing iteration variables, boundary types, and other features. In particular, the present application distinguishes between static and dynamic loop boundary types, with dynamic boundaries defined as loop termination conditions containing data-dependent computations. For example, in the for j in range(vvec[k]) structure, since the loop boundary depends on the array element value, the system marks it as a dynamic boundary loop. To establish control dependency relationships, the present application introduces the post-dominator tree theory, and identifies the control influence relationships between branch nodes by calculating the nearest control decision point.

[0084] The multi-dimensional correlation detection module is the core innovation point of the present application, which adopts a triple judgment standard to comprehensively evaluate the branch prediction difficulty. Firstly, in the data dependency dimension, the system identifies the dependency relationship containing dynamic calculation characteristics by formalizing the variable definition chain of the conditional expression. Secondly, in the control flow dimension, the algorithm detects whether the branch is located inside the dynamic boundary loop and verifies its relevance with the loop control variable. Finally, in the historical correlation dimension, the system constructs a cross-branch variable influence graph and calculates the transmission closure to determine whether the branch condition is affected by the historical execution state. Only when the branch meets the three conditions of data dependency, control flow dependency and historical correlation at the same time, it is finally judged as an H2P branch. The three-dimensional judgment model theoretically guarantees the completeness of the detection result, and the structural induction method proves that it can cover all potential H2P branches reachable in CFG.

[0085] The H2P branch instruction accounts for a very small proportion of all branch instructions in the entire running program, so we need to use the TAGE-EC main predictor in most cases, and only enable the BrPerceptron branch predictor when the H2P instruction is labeled. Therefore, the present application will set an H2P control register, which is used to configure the processor in the C910 machine mode hardware configuration register (MHCR), mainly used to configure whether to enable BTB, BHT, etc. The bit width of this register is 64 bits, and there are many reserved bits in it. The present application will use the MHCR as the BrPerceptron branch predictor enable control bit, and the specific configuration is as follows Figure 4 .

[0086] In order to enable it in hardware through this register, the BrPerceptron branch predictor is enabled when the program executes to this point. Therefore, the above algorithm will insert an inline assembly after identifying the H2P instruction, and the program will become the following Figure 5 , where the inline assembly is automatically identified and inserted by the tool.

[0087] After embedding the inline assembly, compile and disassemble the test case to verify it. First, compile it using the Xuantie-900-gcc-elf-newlib-x86_64-V2.2.4 provided by Xuantie to compile the chain, execute the command:

[0088] “~ / Xuantie-900-gcc-elf-newlib-x86_64-V2.2.4 / bin / riscv64-unknown-elf-gcc-obranch branch.c”, generate the executable file branch.

[0089] After the executable file branch is disassembled, the parameters are configured as "-S -Mnumeric", the function of the -S option is to display the source code and assembly code mixedly, and the corresponding relationship between the C code and the corresponding assembly instruction can be seen. -Mnumeric is to display the register name in the form of numbers. Execute the command:

[0090] "~ / Xuantie-900-gcc-elf-newlib-x86_64-V2.2.4 / bin / riscv64-unknown-elf-objdump -S -Mnumeric branch>branch.obj", generate branch.obj disassembly code.

[0091] Part of the disassembly is as follows Figure 6 In the branch.obj file, find the customFunction function, and the red box part is the inserted H2P control register instruction. The compiler optimizes the written inline assembly, the lui is a high immediate number loading instruction, the syntax is "lui rd, imm20", the main function is to write the immediate number left shifted by 12 bits into the rd destination register, and the corresponding instruction in branch.obj is 0x81 left shifted by 12 bits, that is, multiplied by 212, finally 0x81000 is written into the x5 register; addiw is a low 32-bit signed immediate number addition instruction, the syntax is "addiw rd, rs1, imm12", the main function is to add the low 12 bits of the immediate number to the value in the rs1 register and send it to the rd destination register, the corresponding instruction in branch.obj is 511 in decimal, which is converted to hexadecimal as 0x1ff, and 0x81000 in x5 is added to 0x811ff, which meets the expectation.

[0092] The application proposes a dynamic hardware integration and pipeline optimization strategy, adopts a three-stage pipeline design, F1 stage (parameter calculation): parallel calculation of the index and hash value of TAGE-EC and BrPerceptron. For example, the BrIndex of BrPerceptron is generated in the instruction fetch stage (IF) and is transmitted to the prediction unit through the pipeline register; F2 stage (table access): synchronous access to the TAGE history table, the EC correction table and the SRAM weight table of BrPerceptron, a dual-port SRAM design is adopted to support 2 read operations per cycle, and the bandwidth matches the dual transmission requirement of the superscalar processor; F3 stage (result arbitration): dynamically select the prediction result according to the H2P identifier. If the current branch is marked as H2P (controlled through the MHCR register), the output of BrPerceptron is preferred; otherwise, the TAGE-EC result is used. The arbitration logic delay control is within 1ns, meeting the 250MHz clock frequency requirement.

[0093] The application also carries out dynamic enabling hardware design, MHCR register expansion: multiplexing the reserved bit (bit 19) of the RISC-V machine mode hardware configuration register (MHCR), dynamically switching the BrPerceptron enabling state through the csrw 0x7D0,x5 instruction. Code insertion optimization: the compiler inserts inline assembly before the H2P branch to trigger the predictor switching. This operation only increases 2 instruction overhead, and the CPI influence is less than 0.1%.

[0094] The application also proposes an energy-efficient low-power design clock gating technology and a dynamic voltage adjustment strategy. The clock gating technology, that is, the clock signal of the inactive sub-channel is dynamically closed, and the static power consumption is reduced by 78%. For example, in the sequential code segment, only the 32-bit history sub-channel is powered. An adaptive sleep strategy is adopted: if the H2P branch is not hit for 100 consecutive periods, the BrPerceptron power supply is turned off. The dynamic voltage adjustment, that is, the power supply voltage is dynamically adjusted according to the predictor load (0.9V-1.1V), and the power consumption is reduced to 1.2mW in the idle state. In the UMC 55nm process, the overall power consumption is controlled to be 31.9664mW, and the energy efficiency ratio is 0.52DMIPS / mW.

[0095] The present embodiment also proposes an H2P branch prediction system for chip hardware circuit design, including the following processes:

[0096] The predictor enabling unit is configured to: construct a variable operation trajectory of a program based on a context-sensitive variable tracking mechanism, construct a program execution path topology based on a basic block division algorithm according to the variable operation trajectory, perform multi-dimensional correlation detection to determine whether it is an H2P branch according to the program execution path topology, and enable the BrPerceptron predictor when it is determined to be an H2P branch.

[0097] The branch prediction unit is configured as: the BrPerceptron predictor includes a full connection layer and a plurality of sub-channels, each of the sub-channels includes a data input module, a feature extraction module and a result prediction module connected in sequence, the feature extraction module includes an encoding layer, an embedding layer, a convolution layer and a pooling layer connected in sequence, the input of the encoding layer is part of PC bits and a jump direction, and the result prediction module adopts a full connection layer to perform multi-level feature fusion on the output of the pooling layer of each sub-channel and output a prediction result.

[0098] To sum up, the application aims at the dynamic behavior characteristics of the HardtoPredict (H2P) branch instruction, realizes the adaptive performance improvement of the Branch Prediction Unit (BPU) through the collaborative optimization of the neural network architecture and the hardware pipeline, deeply integrates the machine learning algorithm and the low-power circuit design technology, is suitable for the fields such as high-performance computing, real-time edge inference and multi-core processor which have strict requirements on instruction-level parallelism and pipeline throughput, and provides a systematic solution for the control hazard problem under the von Neumann architecture.

[0099] The above only describes the preferred embodiments of the application and is not used to limit the application, and the application can have various changes and variations for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A H2P branch prediction chip circuit architecture based on BrPerceptron, characterized in that: include: A variable operation trace of the program is constructed based on a context-sensitive variable tracking mechanism. A program execution path topology is constructed based on the variable operation trace and a basic block partitioning algorithm. Multi-dimensional correlation detection is performed based on the program execution path topology to determine whether it is an H2P branch. If it is determined to be an H2P branch, an H2P control register enable code is inserted to enable the BrPerceptron predictor. The BrPerceptron predictor includes a fully connected layer and multiple sub-channels. Each sub-channel includes a data input module, a feature extraction module and a result prediction module connected in sequence. The feature extraction module includes a coding layer, an embedding layer, a convolution layer and a pooling layer connected in sequence. The input of the coding layer is part of the PC bit and the jump direction. The result prediction module uses a fully connected layer to perform multi-level feature fusion on the output of the pooling layer of each sub-channel and output the prediction result.

2. The BrPerceptron-based H2P branch prediction chip circuit architecture according to claim 1, characterized in that: Construct variable operation traces of the program based on the context-sensitive variable tracking mechanism, including: Through an improved depth-first AST traversal algorithm, a definition-use chain is maintained for each variable, and the context information is recorded in a stack structure as the function call chain and loop nesting level; a feature set including modular operations, random number generation, external input, and pointer references is defined, and a dynamic feature recognition algorithm based on grammatical pattern matching identifies composite features including array access and modular operations; function summary technology is used to implement inter-procedural data flow tracking, and the actual parameters of the call point are dynamically associated with the formal parameters through the parameter binding mechanism.

3. The H2P branch prediction chip circuit architecture based on BrPerceptron according to claim 1, characterized in that: Constructing a program execution path topology based on the variable operation trajectory and a basic block partitioning algorithm, including: Each basic block follows the single-entry and single-exit principle, and the maximum code length is limited to N instructions; For loop structures, Tarjan’s strongly connected component algorithm is applied to identify natural loops and extract feature vectors containing features such as iteration variables and boundary types; Loop boundary types are divided into static and dynamic categories, where the dynamic boundary is defined as the loop termination condition that includes data-dependent calculations, and the control influence relationship between branch nodes is identified by calculating the nearest control decision point.

4. The BrPerceptron-based H2P branch prediction chip circuit architecture according to claim 1, characterized in that: Perform multi-dimensional correlation detection based on the program execution path topology to determine whether it is an H2P branch, including: In the data dependency dimension, we formally analyze the variable definition chain of conditional expressions to identify dependencies that contain dynamic computational features. In the control flow dimension, we detect whether a branch is located inside a dynamic boundary loop and verify its association with the loop control variable. In the historical correlation dimension, we construct a cross-branch variable influence diagram and use transitive closure calculations to determine whether the branch condition is affected by the historical execution state. Only when a branch satisfies the three conditions of data dependency, control flow dependency, and historical correlation is it ultimately determined to be an H2P branch.

5. The BrPerceptron-based H2P branch prediction chip circuit architecture according to claim 1, characterized in that: In the coding layer, the PC is shifted left by 1 bit and bitwise ORed with the direction to obtain the BrIndex of each PC. The BrIndex is hashed to reduce the bit width. For each sub-channel, the BrIndex with reduced bit width is combined into a BrIndex sequence in the order of the latest branch being inserted first.

6. The BrPerceptron-based H2P branch prediction chip circuit architecture according to claim 5, characterized in that: The embedding layer takes the BrIndex sequence as input and converts it into a vector; The convolution layer performs convolution operations on the input vectors. Each sub-channel uses 1-dimensional convolution. Each convolution layer has multiple feature extractors to identify the features of the input data. The pooling layer will use sum-pooling to downsample the output of each sub-channel convolution layer, and gradually increase the downsampling intensity as the sequence length increases.

7. The BrPerceptron-based H2P branch prediction chip circuit architecture according to claim 6, characterized in that: When using the offline training model, the result obtained after normalization and sigmoid activation represents the value corresponding to the current hashed BrIndex. This value is stored and the corresponding value is obtained by indexing the hashed BrIndex.

8. The H2P branch prediction chip circuit architecture based on BrPerceptron according to claim 1, characterized in that: The fully connected layer contains N parallel processing units. Each processing unit establishes a global connection with all output channels of the feature extraction module through a learnable weight matrix to achieve comprehensive perception and nonlinear combination of cross-dimensional features; through dynamic batch normalization, the activation value distribution is adjusted according to real-time input.

9. The BrPerceptron-based H2P branch prediction chip circuit architecture according to claim 1, wherein: A three-stage pipeline design is adopted. The first stage parallelizes the calculation of the indexes and hash values ​​of TAGE-EC and BrPerceptron. The second stage synchronously accesses the TAGE history table, EC correction table, and BrPerceptron's SRAM weight table. A dual-port SRAM design is used to support two read operations per cycle, and the bandwidth matches the dual-issue requirements of the superscalar processor. The third stage dynamically selects the prediction result based on the H2P identifier. If the current branch is marked as H2P, the BrPerceptron output is used first; otherwise, the TAGE-EC result is used.

10. A H2P branch prediction method based on BrPerceptron, characterized in that: The following processes are included: Constructing a program variable operation trace based on a context-sensitive variable tracking mechanism, constructing a program execution path topology based on the variable operation trace and a basic block partitioning algorithm, performing multi-dimensional correlation detection based on the program execution path topology to determine whether it is an H2P branch, and enabling a BrPerceptron predictor when it is determined to be an H2P branch; The BrPerceptron predictor includes a fully connected layer and multiple sub-channels. Each sub-channel includes a data input module, a feature extraction module and a result prediction module connected in sequence. The feature extraction module includes a coding layer, an embedding layer, a convolution layer and a pooling layer connected in sequence. The input of the coding layer is part of the PC bit and the jump direction. The result prediction module uses a fully connected layer to perform multi-level feature fusion on the output of the pooling layer of each sub-channel and output the prediction result.

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