Circuit board test point determination method and electronic equipment

Abstract

The invention provides a circuit board test point determination method and electronic equipment, which can be applied to the technical field of circuit boards. The circuit board test point determination method comprises the steps that a test point determination program obtains design data for a target circuit board, and the design data comprises physical information of at least one routing network; for any one routing network, under the condition that the name of any one routing network fails to be matched with a first naming rule in a first naming rule base, matching the attribute information of any one routing network with an attribute rule to obtain an attribute matching result; according to the attribute matching result, determining the network type of any one of a first type of network and a second type of network, and responding to the condition that the network type of any one of the routing networks is the first type of network, and according to the test point layout rule and the position of any one of the routing networks relative to the target circuit board, determining the network type of any one of the routing networks is one of the first type of network and the second type of network. And determining a test point position for any one routing network.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board, in particular to a circuit board test point determination method and electronic equipment. BACKGROUND

[0002] Printed Circuit Board (PCB) is a carrier for electrical connection of electronic components, and is an important electronic component, which supports electronic components and provides circuit connection for electronic components in electronic equipment.

[0003] After the design of the PCB, test points need to be added on the PCB to facilitate the detection of the electrical properties and soldering of the components of the PCB. However, the method of adding test points in related examples generally adopts manual addition, which is prone to omission and low efficiency. SUMMARY

[0004] In view of the above problems, the present application provides a circuit board test point determination method and electronic equipment.

[0005] According to a first aspect of the present application, a circuit board test point determination method is provided, the method comprising: a test point determination program obtaining design data for a target circuit board, wherein the design data comprises physical information of at least one wiring network, and the physical information comprises at least one of the following: name, attribute information; for any wiring network, if the name of the any wiring network fails to match a first naming rule in a first naming rule library, matching the attribute information of the any wiring network with an attribute rule to obtain an attribute matching result; determining a network type of the any wiring network according to the attribute matching result, wherein the network type is one of a first type network and a second type network; and in response to the network type of the any wiring network being the second type network, determining a test point position for the any wiring network according to a test point layout rule and a position of the any wiring network relative to the target circuit board.

[0006] The second aspect of the present application provides a circuit board test point determination device, the device comprising: an acquisition module configured to acquire design data for a target circuit board, wherein the design data comprises physical information of at least one trace network, and the physical information comprises at least one of a name and attribute information; a matching module configured to, for any trace network, match attribute information of the any trace network with an attribute rule in a case where a name of the any trace network fails to match a first naming rule in a first naming rule library, to obtain an attribute matching result; a first determination module configured to determine a network type of the any trace network according to the attribute matching result, wherein the network type is one of a first type network and a second type network; and a second determination module configured to, in response to the network type of the any trace network being the second type network, determine a test point position for the any trace network according to a test point layout rule and a position of the any trace network relative to the target circuit board.

[0007] The third aspect of the present application provides an electronic device comprising: one or more processors; and a memory configured to store one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement steps of the method.

[0008] The fourth aspect of the present application further provides a computer-readable storage medium having stored thereon a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implement steps of the method.

[0009] The fifth aspect of the present application further provides a computer program product comprising a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implement steps of the method.

[0010] The present application can automatically exclude a first type network, for example, a forbidden layout network, and accurately layout test points on a second type network, for example, a permitted layout network, by acquiring a name and attribute information in circuit board design data, sequentially matching the name and attribute information, automatically identifying a network type of a trace network according to a matching result, and intelligently determining a test point position for the trace network belonging to the second type network in combination with a test point layout rule and a position of the trace network, thereby realizing automatic arrangement of test points and helping to improve efficiency and accuracy of circuit board testing. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above content and other purposes, features and advantages of the present application will be more apparent from the following description of the embodiments of the present application with reference to the accompanying drawings.

[0012] Figure 1 A schematic diagram of adding test points on a circuit board is shown.

[0013] Figure 2 An application scenario diagram of the circuit board test point determination method, apparatus, electronic device, storage medium and program product according to embodiments of the present application is shown.

[0014] Figure 3 A flowchart of the circuit board test point determination method according to embodiments of the present application is shown.

[0015] Figure 4 A flowchart of determining a network type according to embodiments of the present application is shown.

[0016] Figure 5 A schematic diagram of determining a test point position according to embodiments of the present application is shown.

[0017] Figure 6 A schematic diagram of adding a test point according to embodiments of the present application is shown.

[0018] Figure 7 A flowchart of the circuit board test point determination method according to another embodiment of the present application is shown.

[0019] Figure 8 A structural block diagram of the circuit board test point determination apparatus according to embodiments of the present application is shown.

[0020] Figure 9 A block diagram of an electronic device suitable for implementing the circuit board test point determination method according to embodiments of the present application is shown. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present application, and is not intended to limit the scope of the present application. Throughout the specification, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that one or more embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the concept of the present application.

[0022] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present application. The terms "include" and "have" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present specification, and should not be interpreted in an idealized or excessively formal manner.

[0024] In the case of using expressions such as "at least one of A, B, and C", it is generally intended that the inclusion of at least one of A, B, or C should be interpreted to mean that the inclusion of A, B, or C is sufficient, but that the inclusion of more than one of A, B, or C is not required. For example, "a system having at least one of A, B, and C" should be interpreted to mean that the system includes A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B and C together, but not necessarily second, third, or greater multiples of A, B, and C.

[0025] Terminology:

[0026] Short stub or stub, refers to a non-essential branch or end of the signal transmission path unmatched wiring, that is, the signal is not intended to pass through the path or the line head, these line heads may cause signal integrity problems, such as signal reflection or impedance discontinuity, thereby affecting the performance of the circuit.

[0027] Circuit test (In-Circuit Test, ICT), a test method for detecting the assembly quality of the circuit board, mainly through the Bed of Nails to connect the test points on the circuit board, detect the electrical properties of components and whether there are open circuit, short circuit and other problems in welding.

[0028] Prohibited layout area: In order to prevent the test point from being too close to the device and causing detection failure, a prohibited layout area will be added to the device during device packaging to avoid such situations and ensure that the test point cannot be added under the device or at a close distance.

[0029] Wiring network: refers to the collection of all conductive elements with electrical connection relationship in the circuit board, including wires, pads, vias, copper skins, etc. These elements form an electrical whole through physical connection and together complete the function of signal transmission or power supply.

[0030] In the application scenario of cloud computing, servers as the core carrier, bear the core tasks of data storage, computing processing, service response, etc. Whether it is daily social communication, online entertainment, transaction, or big data analysis, artificial intelligence training, all rely on the efficient operation of the server.

[0031] With the increasing amount of data, higher requirements are put forward for the computing power, storage efficiency and signal transmission rate of servers. For example, the signal transmission rate of PCB in the server has been improved from 1Gbps to 32Gbps, such as PCIe5.0 (Peripheral Component Interconnect Express 5.0) signal. The sensitivity of high-speed signals to line integrity has increased significantly, and even 0.5mm stub can cause signal reflectivity to exceed-10dB, leading to test misjudgment or system crash. As the interface of ICT test, the reasonable layout of test points directly affects the feasibility of production test and the integrity of system signals.

[0032] In one of the related examples, the layout of test points relies on manual addition. Before adding, set the test point addition standard (such as test point size), and then manually add test points one by one on the network signal outside the prohibited layout area.

[0033] Figure 1 A schematic diagram of adding test points on a circuit board is shown.

[0034] As shown in Figure 1 , the circuit board 100 includes a wiring network and a prohibited layout area, the wiring network includes, for example, a first wiring network 111, a second wiring network 112, and the like, and the prohibited layout area includes, for example, an area 121, an area 122, an area 123. When adding test points, test points are added at wiring paths or vias outside the prohibited layout area. For example, test point a is added at the wiring path of the first wiring network 111, and test point b is added at the wiring path of the second wiring network 112.

[0035] However, this method relies on manual marking addition, which is easy to miss the mark; in addition, the manual addition of test point layout is discrete, and manual addition is prone to errors (such as inappropriate test point position, difficult to detect, missing) and low efficiency and other problems.

[0036] In another related example, the layout of the test points can also be added by a program. First, manually mark the prohibited test network in advance, for example, all high-speed signal networks in the PCB, so as to not add test points to the network when running the program. Then manually set the test point addition standard (for example, the size information of the test point) and the execution mode (for example, added to the trace path or the via) in advance, and during the running of the program, the test points will be added according to the manually marked prohibited test network and prohibited layout area. However, this method still has the following problems: it cannot guarantee that all trace networks can add test points, and for a complex single board, usually there are hundreds of trace networks without test points added, and then manual addition is required. In addition, after generating the test points, manual adjustment is often required, such as manually adding missed test points, deleting or adjusting the position of unreasonable test points, and the like, which is tedious and inefficient. In addition, this method needs to manually mark the trace network that does not allow test points to be added before running the program, and it is difficult to intelligently optimize according to different design requirements and scenarios, and it is also difficult to adapt to complex PCB layout and wiring conditions. For the case of high test point coverage rate, this method is difficult to meet.

[0037] In view of the above technical problems, the embodiments of the present application provide a circuit board test point determination method, comprising: obtaining design data for a target circuit board, wherein the design data comprises physical information of at least one trace network, and the physical information comprises at least one of the following: name, attribute information; for any trace network, in the case that the name of the any trace network fails to match a first naming rule in a first naming rule library, matching the attribute information of the any trace network with an attribute rule to obtain an attribute matching result; determining a network type of the any trace network according to the attribute matching result, wherein the network type is one of a first type network and a second type network; and in response to the network type of the any trace network being the second type network, determining a test point position for the any trace network according to a test point layout rule and a position of the any trace network relative to the target circuit board. By adopting the technical scheme of automatically identifying the network type according to the physical information of the trace network, and then intelligently determining the test point position for the trace network of the second type network in combination with the test point layout rule and the position of the trace network, the method can automatically exclude the prohibited layout network, without manual marking, and can accurately layout the test points on the allowed layout network, realizing the automatic arrangement of the test points, and helping to improve the efficiency and accuracy of the circuit board test.

[0038] Figure 2 An application scenario diagram of the circuit board test point determination method, apparatus, electronic device, storage medium and program product according to the embodiments of the present application is shown.

[0039] As Figure 2As shown, the application scenario 200 according to this embodiment can include a first terminal device 201, a second terminal device 202, a third terminal device 203, a network 204 and a server 205. The network 204 is a medium for providing communication links between the first terminal device 201, the second terminal device 202, the third terminal device 203 and the server 205. The network 204 can include various connection types, such as wired, wireless communication links or optical fiber cables, etc.

[0040] The user can use the first terminal device 201, the second terminal device 202, the third terminal device 203 to interact with the server 205 through the network 204 to receive or send messages, etc.

[0041] The first terminal device 201, the second terminal device 202, the third terminal device 203 can be various electronic devices with display screens and supporting web browsing, including but not limited to smartphones, tablet computers, laptop computers and desktop computers, etc. The first terminal device 201, the second terminal device 202, the third terminal device 203 can be installed with an application for designing circuit boards. After the user completes the circuit board design using the application for designing circuit boards on the first terminal device 201, the second terminal device 202, the third terminal device 203, design data for the circuit board will be generated. The design data can include electrical connections and physical information, physical layout data, etc.

[0042] The server 205 can be a server providing various services, which can analyze and process the received circuit board design data, and feed back the processing results (such as test point position information, etc.) to the terminal device.

[0043] It should be noted that the circuit board test point determination method provided in the embodiments of the present application can be generally executed by the server 205. Correspondingly, the circuit board test point determination apparatus provided in the embodiments of the present application can be generally arranged in the server 205. The circuit board test point determination method provided in the embodiments of the present application can also be executed by a server or a server cluster different from the server 205 and capable of communicating with the first terminal device 201, the second terminal device 202, the third terminal device 203 and / or the server 205. Correspondingly, the circuit board test point determination apparatus provided in the embodiments of the present application can also be arranged in a server or a server cluster different from the server 205 and capable of communicating with the first terminal device 201, the second terminal device 202, the third terminal device 203 and / or the server 205. Alternatively, the circuit board test point determination method provided in the embodiments of the present application can also be executed by the first terminal device 201, the second terminal device 202 or the third terminal device 203, or by other terminal devices different from the first terminal device 201, the second terminal device 202 or the third terminal device 203. Correspondingly, the circuit board test point determination apparatus provided in the embodiments of the present application can also be arranged in the first terminal device 201, the second terminal device 202 or the third terminal device 203, or in other terminal devices different from the first terminal device 201, the second terminal device 202 or the third terminal device 203.

[0044] For example, the design data of the circuit board can originally be stored in any one of the first terminal device 201, the second terminal device 202 or the third terminal device 203 (for example, the first terminal device 201, but not limited thereto), or on an external storage device and can be imported into the first terminal device 201. Then, the first terminal device 201 can execute the circuit board test point determination method provided in the embodiments of the present application locally, or send the design data of the circuit board to other terminal devices, a server or a server cluster, and execute the circuit board test point determination method provided in the embodiments of the present application by the other terminal devices, the server or the server cluster receiving the design data of the circuit board.

[0045] It should be understood that Figure 2 The numbers of the first terminal device, the second terminal device, the third terminal device, the network and the server in the above scenarios are only illustrative. Any number of terminal devices, networks and servers can be provided according to implementation needs.

[0046] The circuit board test point determination method provided in the embodiments of the present application will be described in detail below based on the scenarios described above. Figure 2 Figures 3-7 The circuit board test point determination method provided in the embodiments of the present application will be described in detail below based on the scenarios described above.

[0047] Figure 3 ​A flowchart of a circuit board test point determination method according to an embodiment of the present application is shown.

[0048] As shown in Figure 3 The circuit board test point determination method of this embodiment includes operations S310-S340.

[0049] In operation S310, the test point determination program acquires design data for the target circuit board, wherein the design data includes physical information of at least one trace network.

[0050] The design data can include a complete design file of the PCB to be analyzed or tested. For example, the design data can include a PCB schematic diagram, a PCB layout and routing file (such as traces, vias, layer structure, etc.), a network table (such as electrical connection definition of a trace network), design constraint rules (such as high-speed signal length matching, impedance requirements, etc.).

[0051] A trace network can be an electrical path connecting multiple component pins on a PCB. For example, an output pin of one component is connected to an input pin of another component, and this entire path is a trace network.

[0052] The physical information can include at least one of the following: name, attribute information. The attribute information can include at least one of the following: trace information, signal transmission rate, etc. The trace information can include trace width, trace parallelism, trace length difference, impedance value, etc.

[0053] In operation S320, for any trace network, if the name of any trace network fails to match a first naming rule in the first naming rule library, the attribute information of any trace network is matched with an attribute rule to obtain an attribute matching result.

[0054] In operation S330, according to the attribute matching result, the network type of the any trace network is determined, wherein the network type is one of a first type network and a second type network.

[0055] The name is a unique identifier of the trace network, which is usually a text string and is assigned by the designer when drawing a circuit diagram or defining a system architecture. The name can generally reflect the function, attribute, etc. of the network.

[0056] The first naming rule library can be a pre-defined naming rule library for high-speed signal networks, used to determine the forbidden layout network. The first naming rule can be a naming rule for high-speed signal networks. The first naming rule can be a protocol identifier (such as PCIe, DDR) or a functional description (such as TX) in the name, used to match a type of name. For example, the first naming rule can be "PCIe" to match all high-speed signal networks containing "PCIe". The first naming rule can also be "DDR" to match all high-speed signal networks containing "DDR". The first naming rule can also be "TX" to match all high-speed signal networks containing "TX".

[0057] For example, the name containing PCIe, DDR, TX is a high-speed signal network; the name containing VCC, GND is a power network. Among them, PCIe is the abbreviation of Peripheral Component Interconnect Express, which is a high-speed serial point-to-point differential signal interface, used to connect high-performance peripherals. DDR is the abbreviation of Double Data Rate. TX is the abbreviation of Transmit, which refers to the signal of the data sending end. In high-speed serial protocols, TX is usually a differential pair. VCC is the power supply voltage of the circuit. GND is the abbreviation of Ground, which is the common reference point of the circuit and the reference of all voltages.

[0058] Matching the name of any routing network with the first naming rule in the first naming rule library can be achieved by regular expression for fast matching. In PCB design, routing networks can be divided into different types according to their electrical characteristics and functions. Common network types include high-speed signal networks, power networks, and ordinary low-speed signal networks. High-speed signal networks have high frequency (such as >100MHz), strict impedance control (such as differential 100Ω), and timing sensitivity. Power networks have characteristics such as carrying large current, low noise, and multi-node distribution. Ordinary low-speed signal networks have low frequency (such as <10MHz) and no strict impedance requirements.

[0059] Matching the attribute information of any routing network with the attribute rule to obtain an attribute matching result, and determining the network type of any routing network according to the attribute matching result can include: extracting attribute information of the routing network, and matching the attribute information such as at least one of the routing information and the signal transmission rate with the corresponding attribute rule respectively, and classifying the routing network according to the matching result.

[0060] The attribute rule can include a routing rule and a rate rule. If the physical information includes routing information, the routing information is matched with the routing rule to obtain a routing matching result. At this time, the matching result includes the routing matching result.

[0061] For example, the trace information of the trace network can be extracted, and the trace network is classified according to the trace information. Exemplarily, for example, two traces with a parallel degree greater than or equal to 95% are high-speed signal networks; the trace length difference is less than or equal to 50 mil, which is a high-speed signal network; and the impedance value is 85Ω±10%, 100Ω±10%, which is a high-speed signal network.

[0062] If the physical information includes a signal transmission rate, the signal transmission rate is matched with the rate rule to obtain a rate matching result, and the matching result includes the rate matching result. For example, the signal transmission rate of the trace network can be extracted, and the trace network is classified according to the signal transmission rate. Exemplarily, the signal transmission rate greater than or equal to 10 Gbps is a high-speed signal network; and the signal transmission rate less than 10 Gbps is a common low-speed signal network.

[0063] In operation S340, in response to the network type of any trace network being a second type network, a test point position for any trace network is determined according to the test point layout rule and the position of any trace network relative to the target circuit board.

[0064] The second type network can be a network type that is pre-set to allow layout of a test point. For example, the second type network can include a power network and a common low-speed signal network.

[0065] The test point layout rule can include a preferred layout position, for example, a trace path of a surface layer trace is preferred to be laid out, and when the surface layer trace path cannot be added (for example, the surface layer trace path is located in a prohibited layout area) or the space for addition is insufficient, a via area is added.

[0066] The test point layout rule can also include a layout rule for a power network, for example, test points on the power network are uniformly distributed on the power copper foil or trace path of the power input and output.

[0067] The position of any trace network relative to the target circuit board can be the physical distribution and path of the trace of the trace network on the PCB board. According to the specific position of the trace network, an idle position can be found on or near it to add a test point.

[0068] In response to the network type of any trace network being a second type network, according to the test point layout rule and the position of any trace network relative to the target circuit board can include: when the network type of the trace network is a common low-speed signal network, it is characterized that the test point is allowed to be laid out on the trace network, and at this time, the test point position can be determined according to the test point layout rule and the position of the trace network relative to the target circuit board.

[0069] According to the embodiment of the present application, the method further comprises: in the case that the name of any routing network matches the first naming rule in the first naming rule library successfully, determining that the any routing network is a first type network, marking the any routing network as a forbidden layout network, and not laying out test points on the routing network.

[0070] The present application can automatically exclude the first type network, for example, the forbidden layout network, and accurately layout test points on the second type network, for example, the allowed layout network, realizes the automatic arrangement of test points, and helps to improve the efficiency and accuracy of circuit board testing.

[0071] According to the embodiment of the present application, the attribute information comprises at least one of the following: routing information, signal transmission rate; the attribute rule comprises at least one of the following: routing rule, rate rule, and the attribute matching result comprises at least one of the following: routing matching result, rate matching result.

[0072] According to the embodiment of the present application, in the case that the first naming rule in the first naming rule library is not maintained in time, part of the first type network is not screened, at this time, the attribute information can be used for re-matching. Specifically, the routing information can be matched with the routing rule to obtain the routing matching result, and / or the signal transmission rate can be matched with the rate rule to obtain the rate matching result.

[0073] The routing rule comprises at least one of the following: the routing parallelism is greater than or equal to a first threshold value, the routing length is less than or equal to a second threshold value, and the impedance value meets a preset impedance threshold value; and the rate rule comprises that the signal transmission rate is greater than or equal to a preset rate threshold value.

[0074] For example, the routing rule comprises that the parallelism of two routings is greater than or equal to 95%, there is no obvious intersection or branch, and the length difference of the routings is less than or equal to 50 mil; and the impedance value is 85Ω±10% or 100Ω±10%. For example, the rate rule can comprise a rate threshold value, for example, the rate threshold value can be greater than or equal to 10 Gbps.

[0075] According to the embodiment of the present application, in the case that the attribute matching result only comprises the routing matching result, according to the attribute matching result, the network type of any routing network can comprise: in the case that the routing matching result represents that the routing information matches the routing rule successfully, determining that the network type is the first type network.

[0076] In a case where the trace matching result represents that the trace information fails to match the trace rule, the network type is determined according to a rate matching result obtained by matching the signal transmission rate with the rate rule.

[0077] Determining the network type according to the rate matching result obtained by matching the signal transmission rate with the rate rule can include: in a case where the rate matching result represents that the signal transmission rate matches the rate rule, determining the network type as the first type network; and in a case where the rate matching result represents that the signal transmission rate fails to match the rate rule, determining the network type as the second type network.

[0078] According to an embodiment of the present application, in a case where the attribute matching result only includes the rate matching result, determining the network type of any trace network according to the attribute matching result can include: in a case where the rate matching result represents that the signal transmission rate matches the rate rule, determining the network type as the first type network.

[0079] In a case where the rate matching result represents that the signal transmission rate fails to match the rate rule, the network type is determined according to a trace matching result obtained by matching the trace information with the trace rule.

[0080] Determining the network type according to the trace matching result obtained by matching the trace information with the trace rule can include: in a case where the trace matching result represents that the trace information matches the trace rule, determining the network type as the first type network; and in a case where the trace matching result represents that the trace information fails to match the trace rule, determining the network type as the second type network.

[0081] According to an embodiment of the present application, in a case where the attribute matching result includes the trace matching result and the rate matching result, determining the network type of any trace network according to the attribute matching result can include: in a case where any one of the trace matching result and the rate matching result is matching success, determining the trace network as the first type network; and in a case where the matching results of the trace matching result and the rate matching result are both matching failure, determining the trace network as the second type network.

[0082] For example, the attribute matching result includes a name matching sub-result and a trace matching sub-result, if the name matching sub-result represents that the name matching fails and the trace matching sub-result represents that the trace matching succeeds, it can be determined as the prohibited layout network.

[0083] For example, the matching result includes a name matching sub-result, a trace matching sub-result and a rate matching sub-result. If the name matching sub-result indicates that the name matching fails, the trace matching sub-result indicates that the trace matching fails, and the rate matching sub-result indicates that the rate matching fails, it can be determined that the layout network is allowed. If the name matching sub-result indicates that the name matching fails, the trace matching sub-result indicates that the trace matching fails, but the rate matching sub-result indicates that the rate matching succeeds, it can be determined that the layout network is prohibited.

[0084] According to the embodiment of the present application, the running program traverses all the trace networks in the PCB, and performs three-level matching of the name, trace information and signal transmission rate for each trace network. If any one level of matching succeeds, the network is marked as a prohibited layout network, and the via and trace associated with the network do not generate test points. The network that does not match is determined as an allowed layout network.

[0085] The present application further combines the trace information and signal transmission rate for supplementary matching after the name matching fails, and performs secondary matching through physical characteristics and electrical parameters, so as to realize more accurate high-speed signal network identification and avoid misjudgment caused by non-standard naming. In addition, on the basis of rapid screening of name matching, only the trace network with failed name matching is subjected to supplementary matching, so that the processing speed and integrity are taken into account.

[0086] According to the embodiment of the present application, after the running program traverses all the trace networks in the PCB, the above method further includes: generating a network type analysis result, the network type analysis result including a name matching result, a trace information matching result and a signal transmission rate matching result of the trace network; determining a trace network satisfying a preset condition according to the name matching result, the trace information matching result and the signal transmission rate matching result, and marking the trace network, so as to facilitate manual checking.

[0087] The preset condition can be a trace network with inconsistent matching conclusions in the name matching result, the trace information matching result and the signal transmission rate matching result. For example, for a first trace network, the name matching result indicates that the name does not match, but the trace information matching result indicates that the trace information matches, and the signal transmission rate result indicates that the signal transmission rate matches. At this time, the first trace network needs to be paid attention to.

[0088] By generating the network type analysis result and marking the trace network satisfying the preset condition, design abnormalities (such as erroneously naming a high-speed signal network as a normal signal network), insufficient rule library (the naming rule library does not cover the naming mode for a new type of network), attribute definition abnormalities (such as incorrect definition of the signal transmission rate of the trace network) and other problems in the design data can be captured according to the network type analysis result, so as to avoid potential problems caused by imperfect rules or human negligence from flowing into the next stage.

[0089] In addition, by analyzing these marked "abnormal" networks, the rule library can be continuously found and remedied, making the automation system more and more intelligent and reliable.

[0090] The power signal is the energy source of all active devices on the PCB, such as the central processor and the memory, and its stability directly determines whether the system can work normally. Compared with ordinary low-speed signals, the power signal has larger carrying current, is more sensitive to noise, has wider coverage, and needs to add more test points to monitor the global state of the power signal comprehensively. Therefore, it is necessary to further distinguish the power network from the non-power network in the allowed layout network. The non-power network is a wiring network in the allowed layout network other than the power network, which can be the above-mentioned ordinary low-speed signal network.

[0091] According to the embodiments of the present application, the second type network includes the power network and the non-power network; the method further includes: matching the name of any wiring network with the second naming rule in the second naming rule library; in response to the name of any wiring network matching the second naming rule successfully, determining the network type of any wiring network as the power network; in response to the name of any wiring network failing to match the second naming rule, determining the network type of any wiring network as the non-power network.

[0092] The second naming rule library can be a naming rule library for identifying the power network. The second naming rule can be a naming rule for the power network. The second naming rule can be a wildcard or a regular expression for matching the naming habits of the power network. For example: VDD (internal operating voltage of the chip), VSS (reference ground of the chip), VCC, GND, 3V3 (3.3-volt power network), 5V (5-volt power network), etc.

[0093] It should be noted that the second naming rule library can be customized to add naming rules according to actual conditions.

[0094] The present application further distinguishes the power network from the non-power network in the allowed layout network by matching the second naming rule library, and can perform differential test point strategies according to the network type, such as uniformly arranging multiple test points for the power network and arranging only one test point for the non-power network. In addition, further distinguishing the power network from the non-power network can also achieve precise resource allocation, avoid misusing ordinary signal test points for the power network, and reduce the overdesign of ordinary networks, thereby realizing fine control of test point generation.

[0095] According to the embodiment of the present application, in the case that the network type of any routing network is a power network, the test point position for any routing network is determined according to the test point layout rule and the position of any routing network relative to the target circuit board, which comprises: determining the target power type in the preset power types according to the voltage information of any routing network; determining the preset number of test point positions for any routing network according to the test point layout rule, the position of any routing network relative to the target circuit board and the preset number for the target power type.

[0096] The preset power type can be different types of power networks predefined according to voltage. For example, the preset power type can include a large voltage type and a small voltage type, the large voltage type can be a power network with a voltage greater than or equal to a preset voltage threshold, and the small voltage type can be a power network with a voltage less than the preset voltage threshold. The preset voltage threshold can be determined according to actual needs, for example, the preset voltage threshold can be 6V, 8V, 10V, etc.

[0097] Different types of power networks need to be laid out with different numbers of test points, and the preset number can be preconfigured for different power types. For example, a large voltage type of power network is configured with more test points, for example, 15 test points, and a small voltage type of power network is configured with fewer test points, for example, 5 test points.

[0098] Based on the voltage level, the preset power type is automatically matched, and the corresponding number of test point layout positions is dynamically generated, which not only meets the multi-point detection requirement of large current network (such as reducing contact resistance), but also avoids space waste caused by excessive testing.

[0099] Figure 4 A flowchart for determining the network type according to an embodiment of the present application is shown.

[0100] As shown in Figure 4 The determination of the network type of this embodiment includes operation S410~operation S490.

[0101] In operation S410, the physical information of the routing network is obtained. The physical information includes name, routing information, signal transmission rate.

[0102] In operation S420, it is judged whether the name matches the first naming rule. If not, operation S430 is performed; if yes, operation S490 is performed.

[0103] In operation S430, it is judged whether the routing information matches the routing rule. If not, operation S440 is performed; if yes, operation S490 is performed.

[0104] In operation S440, it is determined whether the signal transmission rate is greater than or equal to the rate threshold. If less than, operations S450 to S480 are performed; if greater than or equal to, operation S490 is performed.

[0105] In operation S450 , it is determined that the network type of any routing network is a second type network.

[0106] In operation S460, it is determined whether the name matches the second naming rule. If not, operation S470 is executed; if so, operation S480 is executed.

[0107] In operation S470 , it is determined that the network type of any routing network is a non-power network.

[0108] In operation S480 , it is determined that the network type of any routing network is a power network.

[0109] In operation S490 , it is determined that the network type of any routing network is a first type network.

[0110] Run the program to traverse all routing networks in the PCB. After completing the type classification, enter the next step of the test point location determination process.

[0111] The following combination Figure 5 The process of determining the test point locations is described in detail.

[0112] According to an embodiment of the present application, the design data includes a prohibited layout area.

[0113] Figure 5 A schematic diagram of determining the position of a test point according to an embodiment of the present application is shown.

[0114] like Figure 5 As shown in FIG. , this embodiment shows a schematic diagram of determining the test point location for any routing network 510. Specifically, the method includes: determining an allowed layout area 550 for any routing network 510 based on the relative position 520 of any routing network 510 relative to the target circuit board and a prohibited layout area 530 in the design data; and then determining a test point location 560 for any routing network 510 within the allowed layout area 550 based on a test point layout rule 540.

[0115] The prohibited layout area is a series of predefined areas on the PCB design where layout test points are prohibited, such as Figure 1 Area 121, area 122, and area 123 are shown.

[0116] Prohibited layout areas generally include:

[0117] Component body area: Especially the tall component body and the area below it, which cannot be reached by the test probe.

[0118] Mounting hole / mechanical fixture area: no electronic items can be placed around the screw holes, brackets, etc.

[0119] Board edge and cutout area: test points cannot be reliably placed too close to the board edge or in areas with internal cutouts.

[0120] By combining the actual routing position of the routing network and the forbidden layout area, first, all unusable spaces are intelligently excluded, and the corresponding allowed layout area of the routing network is accurately calculated, and then in this safe area, the optimal test point position is automatically determined according to the test point layout rule. This method effectively ensures the physical manufacturability, accessibility of the test point, and the minimum impact on the original circuit signal integrity, and realizes the automatic and accurate layout of the test point.

[0121] According to the embodiments of the application, the allowed layout area can include at least one of the following: a routing path area, a via area.

[0122] According to the test point layout rule and the position of any routing network relative to the target circuit board, the test point position in the allowed layout area can also include: in the case where the allowed layout area includes the routing path area, determining the test point position in the routing path area; in the case where the allowed layout area does not include the routing path area, or the routing path area does not meet the test point layout condition, determining the test point position in the via area.

[0123] The routing path area refers to the physical area occupied by the conductors (such as copper wires) of the routing network and the available safe space near them. That is, the wires themselves and their edges.

[0124] The via is a vertical channel connecting different PCB layers. The via area refers to the physical area occupied by the pads of the vias used by the routing network and the available safe space near them.

[0125] The test point layout condition can include whether the space is sufficient, such as whether the routing itself is wide enough, or whether there is enough space next to it to place a test pad without violating the spacing rule.

[0126] By preferentially adding test points in the routing path area of the routing network, better electrical performance and simplicity can be ensured; when the routing path area does not exist or cannot meet the space, spacing, etc. Layout conditions, then automatically select the via area of the routing network to add test points, which not only ensures the automatic layout of the test point, but also intelligently selects the best or feasible position with the minimum impact on the original design in limited space, effectively balancing testability, signal integrity and manufacturing feasibility.

[0127] According to the embodiment of the present application, the via region includes at least one via; determining the test point position in the via region can include achieving tangent layout of the test point and the via through dynamic geometric calculation. Specifically, it can include: determining test point trace information according to via size information of a target via in the at least one via and test point size information; determining the test point position according to the test point trace information.

[0128] The target via can be a specific via selected from the via region, as an object to be connected by the test point. It can be any via in the region.

[0129] The via size information can include the diameter of the via pad. The test point size information can include the diameter of the test point pad.

[0130] The test point trace information includes test point trace length and test point trace angle, and the test point trace angle is the included angle between the signal trace connecting the target via and the test point trace.

[0131] The test point trace is a branch drawn from the trace network, used to connect the test point.

[0132] The test point trace length is the physical length of the test point trace.

[0133] The following will be described in combination with Figure 6 The test point trace length and the test point trace angle are further described.

[0134] Figure 6 A schematic diagram of adding a test point according to the embodiment of the present application is shown.

[0135] As Figure 6 shown, this embodiment adds a test point 630 near a via 620 of a test point trace network 610 to be added. Among them, the line connecting the center of the test point 630 and the center of the via 620 is the test point trace 640, and the included angle α between the test point trace network 610 to be added and the test point trace 640 is the test point trace angle.

[0136] According to the embodiment of the present application, determining the test point trace information according to the via size information of a target via in the at least one via and the test point size information includes: determining the distance between the center of the target via and the center of the test point when the target via and the test point are connected, and determining the distance as the test point trace length according to the via size information and the test point size information; determining the test point trace angle according to the test point trace length and a preset included angle condition.

[0137] Determining the distance between the center of the target via and the center of the test point when the target via and the test point are connected can be the center distance when the target via and the test point are tangent.

[0138] For example, the target via has a diameter D, the test point has a diameter d, and the test point trace length is (D / 2) + (d / 2), where d can be configured according to actual conditions.

[0139] In some embodiments, the preset angle condition includes an angle between the signal trace of the target via and the test point trace being greater than or equal to 90°. The angle is prone to residual etchant during PCB manufacturing etching, leading to short circuit or signal integrity problems. Therefore, the preset angle condition can be greater than or equal to 90°, and preferably 90°.

[0140] In other embodiments, the preset angle condition can also be Figure 6 The angle shown satisfies ≥ 0;

[0141] wherein, represents a direction in which the network signal is connected to the target via, represents a direction in which the target via and the test point are connected, is the angle between , i.e., the angle between the test point trace and the network signal trace is a non-acute angle.

[0142] Determining the test point trace angle according to the test point trace length and the preset angle condition can include: preferentially adding a test point at a position where the test point trace angle is 90°, and if there is a conflict at the position, maintaining the test point trace length unchanged, adjusting the test point trace angle, re-determining the test point position, and repeating the above steps until the conflict is eliminated.

[0143] The conflict can be a pad of another element, another trace, a via, or a violation of the minimum spacing rule, etc.

[0144] Adjusting the test point trace angle can include increasing the test point trace angle, for example, the test point trace angle is increased by ≤5°.

[0145] By calculating the center distance required when the diameter of the target via and the diameter of the test point are tangent to each other according to the diameter of the target via and the diameter of the test point, and directly determining the geometric distance as the test point trace length, the method first preferentially selects a 90° vertical wiring scheme to ensure signal integrity and process specification. When the position conflicts with other elements, traces, vias due to insufficient spacing, the wiring angle can be adjusted by a small step and the position can be recalculated under the premise of keeping the test point trace length unchanged. Through cyclic iteration, a conflict-free feasible position is found. The method automatically generates a tangent layout scheme that can ensure the shortest electrical connection, the smallest impact on signal integrity, and meet the manufacturing process requirements, and realizes the dual optimization of test point layout in space and electrical performance.​

[0146] According to the embodiment of the present application, the method can further include: outputting a PCB test point coverage report after the test point determination is completed, wherein the test point coverage report can include test point configuration parameters (such as test point size information), test point addition overall profile such as high-speed network signal, power signal, general low-speed signal network coverage network total number, and the number of successfully added test points; and can further include surface layer circuit test point coverage rate, via hole tangent test point coverage rate, and unadded test point trace network details, thereby providing a basis for subsequent optimization.

[0147] The embodiment of the present application realizes closed-loop quality management and data-driven optimization of the design process by automatically generating a PCB test point coverage report after the test point layout is completed. The report not only records test point configuration parameters and addition overall profile, but also evaluates the effectiveness and manufacturability of the layout strategy through quality indicators such as surface layer test point coverage rate and via hole tangent coverage rate, and accurately exposes the detailed list of uncovered networks. This function converts the automatic layout result into quantifiable insights, directly providing decision-making basis for design rule iteration, priority adjustment, and targeted manual intervention, thereby significantly improving the testability design level and continuous optimization efficiency of the PCB.

[0148] Figure 7 A flowchart of a circuit board test point determination method according to another embodiment of the present application is shown.

[0149] As shown in Figure 7 , the test point determination method of the embodiment includes operations S710-S760.

[0150] In operation S710, a command window loading program is run, and physical information of a trace network is obtained.

[0151] In operation S720, the network type is determined according to the physical information. When the network type is a prohibited layout network, operation S731 is performed; when the network type is a power network, operations S741-S743 are performed; and when the network type is a non-power network, operations S751-S755 are performed.

[0152] In operation S731, the trace network is marked as a prohibited layout network.

[0153] In operation S741, the trace network is marked as a power network.

[0154] In operation S742, the number of test points corresponding to the power network is determined.

[0155] In operation S743, test points are added on the power network according to the number of test points.

[0156] In operation S751, the trace network is marked as a non-power network.

[0157] In operation S752, it is determined whether the non-power network has a trace region. If yes, operation S753 is performed; if no, operation S755 is performed.

[0158] In operation S753, it is determined whether the trace region meets the test point layout condition. If yes, operation S754 is performed; if no, operation S755 is performed.

[0159] In operation S754, a test point is added in the trace region.

[0160] In operation S755, a test point is added in the via region and the test point is tangent to the via.

[0161] In operation S760, according to the execution results of operation S731, operation S743, operation S754 and operation S755, a test point coverage report is generated and output.

[0162] The method for automatically generating a test point tangent to a via according to the present application can accurately exclude a high-speed signal network, avoid signal reflection and impedance discontinuity caused by adding a test point, and solve the problem of high manual marking omission rate in the related art. In addition, the tangent layout of the via and the test point in the space-stressed PCB minimizes the stub and improves signal stability. At the same time, the tangent layout enables the test point and the via to share the surrounding space, maximizing the space utilization of the PCB. Furthermore, after the test point is added automatically in the whole process, a test point coverage report is output, improving design efficiency, saving manpower, and avoiding misjudgment and misjudgment.

[0163] Based on the above circuit board test point determination method, the present application further provides a circuit board test point determination device. The following will be described in detail Figure 8 The device.

[0164] Figure 8 The structure block diagram of the circuit board test point determination device according to the embodiment of the present application is shown.

[0165] As Figure 8 shown, the circuit board test point determination device 800 of the embodiment includes an acquisition module 810, a matching module 820, a first determination module 830 and a second determination module 840.

[0166] The acquisition module 810 is configured to acquire design data for a target circuit board, wherein the design data includes physical information of at least one trace network, and the physical information includes at least one of the following: name, attribute information. In an embodiment, the acquisition module 810 can be configured to perform operation S310 described above, which will not be described here.

[0167] The matching module 820 is configured to match the attribute information of any routing network with the attribute rule to obtain an attribute matching result in a case where the name of the any routing network fails to match the first naming rule in the first naming rule library. In an embodiment, the matching module 820 can be configured to perform the operation S320 described above, and details are not described herein again.

[0168] The first determining module 830 is configured to determine a network type of the any routing network according to the attribute matching result, wherein the network type is one of a first type network and a second type network. In an embodiment, the first determining module 830 can be configured to perform the operation S330 described above, and details are not described herein again.

[0169] The second determining module 840 is configured to determine a test point position for the any routing network according to the test point layout rule and the position of the any routing network relative to the target circuit board in a case where the network type of the any routing network is the second type network. In an embodiment, the second determining module 840 can be configured to perform the operation S340 described above, and details are not described herein again.

[0170] According to an embodiment of the present application, the attribute information includes at least one of the following: routing information, signal transmission rate; the attribute rule includes at least one of the following: routing rule, rate rule, and the attribute matching result includes at least one of the following: routing matching result, rate matching result.

[0171] According to an embodiment of the present application, the matching module 820 includes a first matching sub-module and a second matching sub-module.

[0172] The first matching sub-module is configured to match the routing information with the routing rule to obtain the routing matching result.

[0173] The second matching sub-module is configured to match the signal transmission rate with the rate rule to obtain the rate matching result.

[0174] According to an embodiment of the present application, the first determining module 830 includes a first determining sub-module and a second determining sub-module.

[0175] The first determining sub-module is configured to determine the network type according to the rate matching result obtained by matching the signal transmission rate with the rate rule in a case where the attribute matching result includes the routing matching result and the routing matching result indicates that the routing information fails to match the routing rule.

[0176] The second determining sub-module is configured to determine the network type according to a wiring matching result obtained by matching the wiring information with the wiring rule, in a case where the attribute matching result comprises a rate matching result and the rate matching result indicates that the signal transmission rate fails to match the rate rule.

[0177] According to embodiments of the present application, the second type network comprises a power network and a non-power network.

[0178] According to embodiments of the present application, the circuit board test point determination apparatus further comprises a third matching sub-module, a third determining sub-module and a fourth determining sub-module.

[0179] The third matching sub-module is configured to match the name of any wiring network with a second naming rule in a second naming rule library.

[0180] The third determining sub-module is configured to determine that the network type of any wiring network is a power network, in response to the name of any wiring network matching the second naming rule successfully.

[0181] The fourth determining sub-module is configured to determine that the network type of any wiring network is a non-power network, in response to the name of any wiring network failing to match the second naming rule.

[0182] According to embodiments of the present application, the second determining module 840 comprises a fifth determining sub-module and a sixth determining sub-module.

[0183] The fifth determining sub-module is configured to determine a target power type in the preset power types according to the voltage information of any wiring network, in a case where the network type of any wiring network is a power network.

[0184] The sixth determining sub-module is configured to determine a preset number of test point positions for any wiring network according to the test point layout rule, the position of any wiring network relative to the target circuit board and the preset number of target power types.

[0185] According to embodiments of the present application, the design data comprises a prohibited layout area.

[0186] According to embodiments of the present application, the second determining module 840 comprises a seventh determining sub-module and an eighth determining sub-module.

[0187] The seventh determining sub-module is configured to determine an allowed layout area for any wiring network according to the prohibited layout area.

[0188] The eighth determining sub-module is configured to determine a test point position in the allowed layout area according to the test point layout rule and the position of any wiring network relative to the target circuit board.

[0189] According to an embodiment of the present application, the allowed layout region comprises at least one of: a trace path region, a via region.

[0190] According to an embodiment of the present application, the tenth determining sub-module comprises a first determining component and a second determining component.

[0191] The first component unit is configured to determine the test point position in the trace path region when the allowed layout region comprises the trace path region.

[0192] The second component unit is configured to determine the test point position in the via region when the allowed layout region does not comprise the trace path region or the trace path region does not satisfy the test point layout condition.

[0193] According to an embodiment of the present application, the via region comprises at least one via.

[0194] According to an embodiment of the present application, the second determining component comprises a first determining unit and a second determining unit.

[0195] The first determining unit is configured to determine test point trace information according to via size information of a target via in the at least one via and test point size information.

[0196] The second determining unit is configured to determine the test point position according to the test point trace information.

[0197] According to an embodiment of the present application, the test point trace information comprises a test point trace length and a test point trace angle, and the test point trace angle is an included angle between a signal trace of the target via and the test point trace.

[0198] According to an embodiment of the present application, the first determining unit comprises a first determining sub-unit and a second determining sub-unit.

[0199] The first determining sub-unit is configured to determine a distance between a center of the target via and a center of the test point when the target via is connected to the test point according to the via size information and the test point size information, and determine the distance as the test point trace length.

[0200] The second determining sub-unit is configured to determine the test point trace angle according to the test point trace length and a preset included angle condition, wherein the preset included angle condition comprises that the included angle between the signal trace of the target via and the test point trace is greater than or equal to 90°.

[0201] According to an embodiment of the present application, any of the modules of the obtaining module 810, the matching module 820, the first determining module 830 and the second determining module 840 can be combined in one module, or any of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of the modules can be combined with at least part of the functions of the other modules, and implemented in one module. According to an embodiment of the present application, at least one of the obtaining module 810, the matching module 820, the first determining module 830 and the second determining module 840 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on board, a system in package, an application specific integrated circuit (ASIC), or any other reasonable manner of integrating or packaging a circuit, etc. in hardware or firmware, or implemented in any one of software, hardware and firmware or in a proper combination of any of the foregoing. Alternatively, at least one of the obtaining module 810, the matching module 820, the first determining module 830 and the second determining module 840 can be at least partially implemented as a computer program module which, when executed, can perform the corresponding functions.

[0202] Figure 9 A block diagram of an electronic device suitable for implementing the circuit board test point determination method according to an embodiment of the present application is shown.

[0203] As shown in Figure 9 The electronic device 900 according to an embodiment of the present application includes a processor 901 which can perform various appropriate actions and processes according to programs stored in a read only memory (ROM) 902 or loaded from a storage portion 908 into a random access memory (RAM) 903. The processor 901 can include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special purpose microprocessor (e.g., an application specific integrated circuit (ASIC)), etc. The processor 901 can also include an on-board memory for cache use. The processor 901 can include a single processing unit or multiple processing units for executing different actions of the method processes according to embodiments of the present application.

[0204] In the RAM 903, various programs and data required for the operation of the electronic device 900 are stored. The processor 901, the ROM 902, and the RAM 903 are connected to each other via the bus 904. The processor 901 performs various operations of the method flow according to the embodiments of the present application by executing the programs in the ROM 902 and / or the RAM 903. It should be noted that the programs can also be stored in one or more memories other than the ROM 902 and the RAM 903. The processor 901 can also perform various operations of the method flow according to the embodiments of the present application by executing the programs stored in the one or more memories.

[0205] According to the embodiments of the present application, the electronic device 900 can further include an input / output (I / O) interface 905, which is also connected to the bus 904. The electronic device 900 can further include one or more of the following components connected to the input / output (I / O) interface 905: an input part 906 including a keyboard, a mouse, and the like; an output part 907 including a cathode ray tube (CRT), a liquid crystal display (LCD), and the like, and a speaker, and the like; a storage part 908 including a hard disk, and the like; and a communication part 909 including a network interface card such as a LAN card, a modem, and the like. The communication part 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the input / output (I / O) interface 905 as necessary. A removable medium 911 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like is mounted on the drive 910 as necessary, so that a computer program read therefrom is installed in the storage part 908 as necessary.

[0206] The present application also provides a computer readable storage medium, which can be included in the device / apparatus / system described in the above embodiments; or can exist separately without being assembled into the device / apparatus / system. The above computer readable storage medium carries one or more programs, when the one or more programs are executed, the method according to the embodiments of the present application is implemented.

[0207] According to an embodiment of the present application, the computer readable storage medium can be a non-transitory computer readable storage medium, for example, can include but not limited to: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this application, a computer readable storage medium can be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present application, the computer readable storage medium can include one or more of the above-described ROM 902 and / or RAM 903 and / or a memory other than the ROM 902 and the RAM 903.

[0208] Embodiments of the present application also include a computer program product, which includes a computer program containing program codes for executing the methods shown in the flowcharts. When the computer program product is run in a computer system, the program codes are used to make the computer system implement the methods provided by the embodiments of the present application.

[0209] The above-described functions defined in the system / device / apparatus of the embodiments of the present application are performed when the computer program is executed by the processor 901. According to an embodiment of the present application, the above-described system, device, module, unit, etc. can be implemented by computer program modules.

[0210] In one embodiment, the computer program can rely on a tangible storage medium such as an optical storage device, a magnetic storage device, etc. In another embodiment, the computer program can also be transmitted, distributed, and downloaded in the form of a signal on a network medium, and be downloaded and installed through the communication part 909, and / or be installed from the detachable medium 911. The program codes contained in the computer program can be transmitted by any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.

[0211] In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 909, and / or be installed from the detachable medium 911. When the computer program is executed by the processor 901, the above-described functions defined in the system of the embodiments of the present application are performed. According to an embodiment of the present application, the above-described system, device, apparatus, module, unit, etc. can be implemented by computer program modules.

[0212] According to embodiments of the present application, program code for implementing the computer programs provided by embodiments of the present application can be written in any combination of one or more programming languages, and can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Program code can execute entirely on a user's computing device, partly on the user's device, as a stand-alone software package, partly on a remote computing device, or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, such as through the Internet using an Internet Service Provider.

[0213] The computer program instructions can also be loaded onto a computer or other programmable information processing apparatus to cause a series of operations to be performed on the computer or other programmable information processing apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable information processing apparatus implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0214] Those skilled in the art will understand that features recited in the various embodiments of the present application can be combined and / or integrated in various ways, even if such combinations or integrations are not expressly noted in the present application. In particular, features recited in the various embodiments of the present application can be combined and / or integrated in ways that are not expressly noted in the present application, without departing from the spirit and teachings of the present application. All such combinations and / or integrations are within the scope of the present application.

[0215] The embodiments of the present application have been described above. However, these embodiments are merely for the purpose of illustration, and are not intended to limit the scope of the present application. Although the embodiments are described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present application, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A method for determining test points on a circuit board, characterized in that: The method comprises: The test point determination program obtains design data for a target circuit board, wherein the design data includes physical information of at least one routing network, and the physical information includes at least one of the following: a name, and attribute information; For any routing network, if the name of the routing network fails to match the first naming rule in the first naming rule library, matching the attribute information of the routing network with the attribute rule to obtain an attribute matching result; Determining a network type of any routing network according to the attribute matching result, wherein the network type is one of a first type network and a second type network; and In response to the network type of any routing network being a second type network, a test point position for the any routing network is determined according to a test point layout rule and a position of the any routing network relative to the target circuit board.

2. The method according to claim 1, characterized in that The attribute information includes at least one of the following: routing information, signal transmission rate, the attribute rule includes at least one of the following: routing rule, rate rule, the attribute matching result includes at least one of the following: routing matching result, rate matching result; The matching of the attribute information of any routing network with the attribute rule to obtain the attribute matching result includes: Matching the routing information with the routing rule to obtain the routing matching result; and / or The signal transmission rate is matched with the rate rule to obtain the rate matching result.

3. The method according to claim 2, characterized in that Determining the network type of any routing network according to the attribute matching result includes: If the attribute matching result includes the routing matching result, and the routing matching result indicates that the routing information fails to match the routing rule, determining the network type according to a rate matching result obtained by matching the signal transmission rate with the rate rule; When the attribute matching result includes the rate matching result, and the rate matching result indicates that the signal transmission rate fails to match the rate rule, the network type is determined based on a routing matching result obtained by matching the routing information with the routing rule.

4. The method according to any one of claims 1 to 3, characterized in that The second type of network includes a power supply network and a non-power supply network; The method further comprises: Matching the name of any routing network with a second naming rule in a second naming rule library; In response to a successful match between the name of any routing network and the second naming rule, determining that the network type of any routing network is a power network; In response to a failure in matching the name of any routing network with the second naming rule, determining that the network type of any routing network is a non-power network.

5. The method according to claim 4, characterized in that When the network type of any routing network is a power network, determining the test point position for any routing network according to a test point layout rule and a position of any routing network relative to the target circuit board includes: Determining a target power type among preset power types according to the voltage information of any routing network; A preset number of test point positions for any routing network is determined based on the test point layout rule, the position of any routing network relative to the target circuit board, and a preset number for a target power supply type.

6. The method according to claim 1, characterized in that The design data includes a prohibited layout area; Determining the test point position for any routing network according to the test point layout rule and the position of any routing network relative to the target circuit board includes: Determining an allowed layout area for any routing network according to the prohibited layout area; The test point position is determined in the allowed layout area according to a test point layout rule and a position of any routing network relative to the target circuit board.

7. The method according to claim 6, characterized in that The allowed layout area includes at least one of the following: a routing path area and a via area; Determining the position of the test point in the allowed layout area according to the test point layout rule and the position of any routing network relative to the target circuit board includes: In a case where the allowed layout area includes the routing path area, determining the test point position in the routing path area; When the allowed layout area does not include the routing path area, or the routing path area does not meet the test point layout conditions, the test point position is determined in the via area.

8. The method according to claim 7, characterized in that The via region includes at least one via; Determining the position of the test point in the via area includes: Determining test point routing information according to via size information of a target via in the at least one via and test point size information; The test point position is determined according to the test point routing information.

9. The method according to claim 8, characterized in that The test point routing information includes the test point routing length and the test point routing angle, wherein the test point routing angle is the angle between the signal routing connecting the target via and the test point routing; Determining the test point routing information according to the via size information and the test point size information of the target via in the at least one via includes: Determining, based on the via size information and the test point size information, a distance between a center of the target via and a center of the test point when the target via is connected to the test point, and determining the distance as a trace length of the test point; The test point routing angle is determined according to the test point routing length and a preset angle condition, wherein the preset angle condition includes that the angle between the signal routing of the target via and the test point routing is greater than or equal to 90°.

10. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 9.

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