Power supply chip, circuit board assembly and electronic equipment

Abstract

The invention relates to the technical field of circuits, and discloses a power supply chip, a circuit board assembly and electronic equipment, and the power supply chip comprises a synchronization module, an oscillation module and a clock selection module. The oscillation module is connected with a first clock input pin of the synchronization module; the clock selection module is connected with a clock control pin of the synchronization module; the oscillation module is configured to generate a first clock signal and input the first clock signal to the synchronization module through the first clock input pin; the synchronization module is configured to obtain a second clock signal of the external circuit through the second clock input pin; the clock selection module is configured to input a clock control signal to the synchronization module through the clock control pin, and the synchronization module is configured to determine a first clock signal or a second clock signal as a target clock signal according to the clock control signal and operate with the target clock signal; and high-precision synchronization of clock signals between the power supply chip and the external circuit is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a power supply chip, a circuit board assembly and an electronic device. BACKGROUND

[0002] The multi-chip synchronization scheme of the power supply chip is a high-efficiency, reliable and flexible design strategy, which is widely used in various power supply systems requiring high power, high efficiency and high reliability.

[0003] The existing multi-chip synchronization scheme of the power supply chip generally has limited synchronization accuracy and strict requirements for the quality of the main clock signal, which may cause frequency deviation, phase offset, reduced reliability, and decreased system efficiency, and cannot meet the requirements of the current high-precision clock synchronization and low-energy consumption application scenarios. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a power supply chip, a circuit board assembly and an electronic device, so as to realize high-precision synchronization of clock signals between the power supply chip and the external circuit.

[0005] To solve the above technical problems, the embodiments of the present application provide a power supply chip, comprising: a synchronization module, an oscillation module and a clock selection module; the oscillation module is connected to a first clock input pin of the synchronization module; the clock selection module is connected to a clock control pin of the synchronization module; the oscillation module is configured to generate a first clock signal and input the first clock signal to the synchronization module through the first clock input pin; the synchronization module is configured to obtain a second clock signal of an external circuit through a second clock input pin; the clock selection module is configured to input a clock control signal to the synchronization module through the clock control pin, and the synchronization module is configured to determine the first clock signal or the second clock signal as a target clock signal according to the clock control signal, and run with the target clock signal.

[0006] The embodiments of the present application also provide a circuit board assembly, comprising: the above-mentioned power supply chip.

[0007] The embodiments of the present application also provide an electronic device, comprising: the above-mentioned circuit board assembly.

[0008] In some embodiments, the oscillation module comprises: a first comparator, a first resistor, a second resistor, a third resistor, a first switch, a direct current source, a second switch; a first end of the first resistor is connected to a power supply, a second end of the first resistor is connected to a first end of the second resistor, a second end of the second resistor is grounded, the second end of the first resistor is also connected to a first end of the third resistor, a second end of the third resistor is connected to a first end of the first switch, a second end of the first switch is grounded; a positive input end of the first comparator is connected to an input pin of the oscillation module, a negative input end of the first comparator is connected to the second end of the first resistor, an output end of the first comparator is connected to the first clock input pin; the input pin of the oscillation module is also connected to a first end of the direct current source, a second end of the direct current source is connected to a first end of the second switch, a second end of the second switch is grounded; the synchronization module further comprises a switch control pin, which is connected to a control end of the first switch and a control end of the second switch respectively.

[0009] In some embodiments, the first switch and the second switch are both NMOS tubes.

[0010] In some embodiments, the clock selection module comprises a second comparator, a third comparator, a fourth resistor, a fifth resistor, a sixth resistor; the synchronization module comprises two clock control pins, one of which is a first clock control pin and the other of which is a second clock control pin; a first end of the fourth resistor is connected to a power supply, a second end of the fourth resistor is connected to a first end of the fifth resistor, a second end of the fifth resistor is connected to a first end of the sixth resistor, a second end of the sixth resistor is grounded; a positive input end of the second comparator is connected to an input pin of the oscillation module, a negative input end of the second comparator is connected to the second end of the fourth resistor, an output end of the second comparator is connected to one of the clock control pins; the synchronization module is configured to switch back to the first clock signal as the target clock signal when the first clock control pin is enabled and there is no second clock signal input; a negative input end of the third comparator is connected to the input pin of the oscillation module, a positive input end of the third comparator is connected to the second end of the fifth resistor, an output end of the second comparator is connected to the other clock control pin; the synchronization module is configured to select the second clock signal as the target clock signal when the second clock control pin is enabled and the second clock signal is earlier than the first clock signal.

[0011] In some embodiments, the clock interaction module comprises: a seventh resistor, an eighth resistor, a third switch; a first end of the seventh resistor is connected to the second clock input pin, a second end of the seventh resistor is connected to the external circuit; the first end of the seventh resistor is also connected to a first end of the third switch, a second end of the third switch is connected to the clock output pin; a first end of the eighth resistor is connected to the first end of the seventh resistor, a second end of the eighth resistor is grounded.

[0012] In some embodiments, the third switch is a PMOS tube.

[0013] In some embodiments, the clock interaction module is connected to a plurality of external circuits; the clock interaction module is configured to obtain a plurality of second clock signals of the plurality of external circuits, and input the plurality of second clock signals to the synchronization module through the second clock input pin; the synchronization module is configured to select a second clock signal with the earliest time among the plurality of second clock signals as a third clock signal, and select the first clock signal as the target clock signal in the case that the first clock control pin is enabled and the first clock signal is earlier than the third clock signal; select the third clock signal as the target clock signal in the case that the second clock control pin is enabled and the third clock signal is earlier than the first clock signal.

[0014] In some embodiments, the power supply chip further comprises a clock interaction module; the clock interaction module is connected to a clock output pin of the synchronization module and the second clock input pin; the clock interaction module is configured to obtain the first clock signal through the clock output pin and output the first clock signal to the external circuit; the clock interaction module is also configured to obtain the second clock signal of the external circuit and input the second clock signal to the synchronization module through the second clock input pin.

[0015] The technical scheme provided by the embodiments has at least the following advantages:

[0016] The power supply chip generates the first clock signal through the internal oscillation module, obtains the second clock signal of the external circuit through the second clock input pin, obtains the clock control signal through the clock selection module, and determines the first clock signal or the second clock signal as the target clock signal according to the clock control signal, and runs with the target clock signal, so as to realize high-precision synchronization of the clock signal between the power supply chip and the external circuit in the case that the power supply chip is connected to the external circuit. BRIEF DESCRIPTION OF DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate similar elements, and as such, continue to refer to a like reference numeral, and no attempt is made to show all of the routine, optional or alternate elements to facilitate the discussion. The drawings are not intended to be limiting in any way.

[0018] Figure 1 is a circuit structure schematic diagram of a power chip according to an embodiment of the present application;

[0019] Figure 2 is another circuit structure schematic diagram of a power chip according to an embodiment of the present application;

[0020] Figure 3 is a specific circuit structure schematic diagram of a power chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and the embodiments can be combined and referenced with each other without contradiction.

[0022] An embodiment of the present application relates to a power chip, and a specific circuit structure schematic diagram is as shown in Figure 1 The power chip of the embodiment includes a synchronization module 10, an oscillation module 20 and a clock selection module 30.

[0023] Specifically, the oscillation module 20 is connected to a first clock input pin of the synchronization module 10; the clock selection module 30 is connected to a clock control pin of the synchronization module 10; the oscillation module 20 is configured to generate a first clock signal and input the first clock signal to the synchronization module 10 through the first clock input pin; the synchronization module 10 is configured to obtain a second clock signal of an external circuit 40 through a second clock input pin; the clock selection module 30 is configured to input a clock control signal to the synchronization module 10 through the clock control pin, and the synchronization module 10 is configured to determine the first clock signal or the second clock signal as a target clock signal according to the clock control signal and run with the target clock signal.

[0024] The power supply chip in the embodiment generates the first clock signal through the internal oscillation module 20, and obtains the second clock signal of the external circuit 40 through the second clock input pin, obtains the clock control signal through the clock selection module 30, and the synchronization chip determines the first clock signal or the second clock signal as the target clock signal according to the clock control signal, and operates with the target clock signal, so that the high-precision synchronization of the clock signals between the power supply chip and the external circuit 40 is realized when the power supply chip is connected with the external circuit 40.

[0025] In some embodiments, the external circuit 40 is a signal generator, which can send the second clock signal to multiple power supply chips, so that after receiving the second clock signal, the multiple power supply chips all select the second clock signal as the target clock signal to operate, thereby realizing the high-precision synchronization of the clock signals between the multiple power supply chips.

[0026] In some embodiments, the external circuit 40 is another power supply chip, which generates the second clock signal and inputs the second clock signal to the power supply chip in the embodiment through the second clock input pin of the power supply chip in the embodiment; correspondingly, the power supply chip in the embodiment generates the first clock signal, which can also be output to the other power supply chip, so that the power supply chip in the embodiment and the other power supply chip both obtain the first clock signal and the second clock signal, and operate according to the same logic (such as selecting the earliest clock signal) as the target clock signal. It should be noted that the structure of the power supply chip in the embodiment and the other power supply chip can be the same, from the perspective of the other power supply chip, the power supply chip in the embodiment is its corresponding external circuit 40, the first clock signal generated by the power supply chip in the embodiment is the second clock signal accepted by the other power supply chip, and the second clock signal received by the power supply chip in the embodiment is the first clock signal generated by the other power supply chip.

[0027] It should be noted that the external circuit 40 can be multiple, that is, the power supply chip in the embodiment can be connected with multiple external power supply chips, and the clock signal generated by each power supply chip can be sent to other power supply chips and receive the clock signal generated by other power supply chips.

[0028] In order to realize that the power supply chip in the embodiment has the function of sending the first clock signal generated by itself and receiving the second clock signal generated by other power supply chips, in addition to the synchronization module 10, the oscillation module 20 and the clock selection module 30 described above, the embodiment also includes a clock interaction module, such as Figure 2 As shown in FIG. 5, which is another circuit structure schematic diagram of the power supply chip in the embodiment, the power supply chip in the embodiment further includes a clock interaction module 50, which is connected with the clock output pin and the second clock input pin of the synchronization module 10.

[0029] Specifically, the clock interaction module 50 is configured to obtain a first clock signal through a clock output pin and output the first clock signal to the external circuit 40; the clock interaction module 50 is also configured to obtain a second clock signal from the external circuit 40 and input the second clock signal to the synchronization module 10 through a second clock input pin.

[0030] The power chip of this embodiment sends its own first clock signal to the external circuit 40 (another power chip) through the clock interaction module 50, and receives the second clock signal of the external circuit 40 (another power chip) through the clock interaction module 50, so that the power chip of this embodiment and the external circuit 40 (another power chip) can both operate through the same logic (such as selecting the earliest clock signal) as the target clock signal, thereby improving the accuracy of clock synchronization between multiple power chips.

[0031] like Figure 3 As shown in FIG. 1 , a schematic diagram of a specific circuit structure of the power supply chip of the present embodiment is shown. The oscillation module 20 in the power supply chip of the present embodiment includes: a first comparator COMP1, a first resistor R1, a second resistor R2, a third resistor R3, a first switch ON1, a DC source Is, and a second switch ON2; a first end of the first resistor R1 is connected to a power supply VREF, a second end of the first resistor R1 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is grounded, the second end of the first resistor R1 is further connected to a first end of the third resistor R3, a second end of the third resistor R3 is connected to a first end of the first switch ON1, and a second end of the first switch ON1 is grounded; a positive input end of the first comparator COMP1 is connected to an input pin RTCT of the oscillation module 20, a negative input end of the first comparator COMP1 is connected to a second end of the first resistor R1, and an output end of the first comparator COMP1 is connected to a first clock input pin OSC IN; the input pin RTCT of the oscillation module 20 is further connected to a first end of the DC source Is, a second end of the DC source Is is connected to a first end of the second switch ON2, and a second end of the second switch ON2 is grounded; the synchronization module 10 further includes a switch control pin CLK OUT, a switch control pin CLK OUT is connected to the control end of the first switch ON1 and the control end of the second switch ON2 respectively.

[0032] The synchronization module 10 of this embodiment can be a bidirectional synchronization chip, so as to realize the function of obtaining the first clock signal and the second clock signal. In addition, the bidirectional synchronization chip can also obtain a clock control signal, and select the first clock signal or the second clock signal as the target clock signal according to the clock control signal, and operate with the target clock signal.

[0033] In some embodiments, the first switch ON1 and the second switch ON2 are both NMOS tubes. In other embodiments, the first switch ON1 and the second switch ON2 can also be switching devices such as triodes, relays, contactors, etc.

[0034] Specifically, the oscillation module 20 generates a triangular wave in the continuous charging and discharging process, which is input to the positive input terminal of the first comparator COMP1. The input pin RTCT of the oscillation module 20 is used to control the swing frequency of the triangular wave generated by the oscillation module 20. The swing frequency is determined according to the capacitance and resistance at the input pin RTCT. In this embodiment, the resistance and capacitance at the input pin RTCT are replaced, so that the oscillation frequency of the charging and discharging of the oscillation circuit serves as a settable control frequency, so as to achieve the control effect of the synchronization frequency when using internal synchronization mode.

[0035] Specifically, the power supply VREF gives different reference voltages at the rising edge and the falling edge of the oscillation module 20, for example, the reference voltage at the rising edge is 3V, and the reference voltage at the falling edge is 1.5V. The triangular wave generated by the oscillation module 20 is oscillating by itself. After comparison by the first comparator COMP1, the first comparator COMP1 generates a square wave, i.e. the first clock signal, which enters the first clock input pin OSC IN of the synchronization module 10. The first clock signal can determine the frequency of the power supply chip.

[0036] For ease of understanding, the voltage of the power supply VREF is set to 5V, the resistance value of the first resistor R1 is 20KΩ, the resistance value of the second resistor R2 is 30KΩ, and the resistance value of the third resistor R3 is 12KΩ.

[0037] Specifically, the synchronization module 10 first controls the first switch ON1 and the second switch ON2 to be off through the switch control pin CLK OUT. Since the first switch ON1 is off, the first resistor R1 and the second resistor R2 divide the power supply voltage (5V) after voltage division, and the reference voltage at the negative input terminal of the first comparator COMP1 is 3V. Since the second switch ON2 is off, the DC source Is charges the input pin RTCT of the oscillation module 20, and the oscillation module 20 is in a charging state, and the triangular wave is in a rising edge state. When the triangular wave gradually exceeds 3V, the first comparator COMP1 compares the voltages at the positive input terminal and the negative input terminal, and outputs a high level 1. The first clock input pin OSC IN of the synchronization module 10 receives the high level first clock signal.

[0038] After the first clock input pin OSC IN of the synchronization module 10 receives the first clock signal of the high level, the synchronization module 10 controls the first switch ON1 and the second switch ON2 to be turned on by the switch control pin CLK OUT at this time. Since the first switch ON1 is turned on, the first resistor R1, the second resistor R2 and the third resistor R3 divide the power voltage (5V) to obtain a reference voltage of 1.5V at the negative input end of the first comparator COMP1. Since the second switch ON2 is turned on to be grounded, the direct current source Is discharges the input pin RTCT of the oscillation module 20, and the oscillation module 20 is in a discharging state. When the triangular wave gradually decreases to below 1.5V, the first comparator COMP1 compares the voltage at the positive input end with the voltage at the negative input end, and the first comparator COMP1 outputs the low level 0. The first clock input pin OSC IN of the synchronization module 10 receives the first clock signal of the low level.

[0039] After the first clock input pin OSC IN of the synchronization module 10 receives the first clock signal of the low level, the synchronization module 10 controls the first switch ON1 and the second switch ON2 to be turned off by the switch control pin CLK OUT at this time. The above steps are repeated to generate the square wave, i.e. the first clock signal.

[0040] With reference to the above description, the synchronization module 10 can generate the first clock signal of the square wave by the above steps. The first clock signal is output to the first clock output pin OSC OUT of the synchronization module 10. Figure 3The clock selection module 30 in the power supply chip of the embodiment includes a second comparator COMP2, a third comparator COMP3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The synchronization module 10 includes two clock control pins, one of which is a first clock control pin NO EXT SYNC, and the other of which is a second clock control pin EXT SYNC. The first end of the fourth resistor R4 is connected to a power supply, the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is grounded. The positive input end of the second comparator COMP2 is connected to the input pin RTCT of the oscillation module 20, the negative input end of the second comparator COMP2 is connected to the second end of the fourth resistor R4, and the output end of the second comparator COMP2 is connected to one of the clock control pins. The synchronization module 10 is configured to switch back to the first clock signal as the target clock signal in the case that the first clock control pin NO EXT SYNC is enabled and no second clock signal is input. The negative input end of the third comparator COMP3 is connected to the input pin RTCT of the oscillation module 20, the positive input end of the third comparator COMP3 is connected to the second end of the fifth resistor R5, and the output end of the second comparator COMP2 is connected to the other clock control pin. The synchronization module 10 is configured to select the second clock signal as the target clock signal in the case that the second clock control pin EXT SYNC is enabled and the second clock signal is earlier than the first clock signal.

[0041] Specifically, the first clock control pin NO EXT SYNC is used to inform the synchronization module 10 that it can use its own first clock signal as the target clock signal, and the second clock control pin EXT SYNC is used to inform the synchronization module 10 that it can use an external second clock signal as the target clock signal, but the specific selection of which clock signal as the target clock signal also needs to meet specific requirements, i.e., the target clock signal is the earliest clock signal.

[0042] For ease of illustration, the power supply voltage is set to 5V, the resistance of the fourth resistor R4 is set to 10KΩ, the resistance of the fifth resistor R5 is set to 20KΩ, and the resistance of the sixth resistor R6 is set to 20KΩ. Therefore, after the voltage division of the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6, the voltage at the negative input end of the second comparator COMP2 is 4V, and the voltage at the positive input end of the third comparator COMP3 is 2V.

[0043] From the above, the triangle wave generated by the oscillation module 20 fluctuates between 1.5V and 3V in the normal operation process. Since the positive input terminal of the second comparator COMP2 is connected to the input pin RTCT of the oscillation module 20, and the negative input terminal of the third comparator COMP3 is connected to the input pin RTCT of the oscillation module 20, in the normal operation stage, the triangle wave fluctuates between 1.5V and 3V, when the triangle wave is lower than 2V, the output terminal of the second comparator COMP2 outputs low level, the output terminal of the third comparator COMP3 outputs high level, the second clock control pin EXT SYNC is enabled, informing the synchronization module 10 that it can synchronize the external second clock signal, when the triangle wave is between 2V and 3V, the output terminal of the second comparator COMP2 outputs low level, the output terminal of the third comparator COMP3 outputs low level, at this time the second clock control pin EXT SYNC is not enabled, the synchronization module 10 cannot synchronize the external second clock signal.

[0044] That is, even if the synchronization module 10 receives the second clock signal and determines that the second clock signal is earlier than the first clock signal, it is still necessary to switch the first clock signal to the second clock signal at a specific time, that is, the time period when the triangle wave is lower than 2V, to improve the adaptability and stability of the power supply chip.

[0045] When the synchronization module 10 selects to switch to the second clock signal for clock synchronization, the synchronization module 10 switches to the external synchronization mode and stops the oscillation period of the oscillation module 20, that is, the synchronization module 10 stops controlling the first switch ON1 and the second switch ON2 to be continuously turned on and turned off through the switch control pin CLK OUT, at this time the synchronization module 10 directly controls the first switch ON1 and the second switch ON2 to be turned off through the switch control pin CLK OUT, at this time the input pin RTCT of the oscillation module 20 is gradually charged through the direct current source Is. When the input pin RTCT of the oscillation module 20 is charged to 4V or more, the output terminal of the second comparator COMP2 outputs high level, the output terminal of the third comparator COMP3 outputs low level, the first clock control pin NOEXT SYNC is enabled, and at the same time detects and confirms that there is no external second control signal input to the synchronization module 10, informs the synchronization module 10 that it can switch to the internal synchronization mode, that is, switch back to the internal first clock signal control.

[0046] When the first clock control pin NO EXT SYNC of the synchronization module 10 is enabled and there is no second clock signal, it is necessary to switch back to the internal first clock signal control, at this time, the oscillation period of the oscillation module 20 is started, that is, the synchronization module 10 controls the first switch ON1 and the second switch ON2 to be continuously turned on and turned off again through the above-mentioned switch control pin CLK OUT, so as to generate a square wave, that is, the first clock signal, and input the first clock signal to the synchronization module 10 through the first clock input pin OSC IN of the synchronization module 10.

[0047] It should be noted that the synchronization module 10 of the embodiment is internally provided with an intelligent frequency matching algorithm. After the second clock signal of the external circuit 40 is obtained, it is judged whether the second clock signal of the external circuit 40 meets the preset condition, for example, the preset condition is that the second clock signal of the external circuit 40 is at least 65% of the free oscillation frequency of the first clock signal of the power supply chip of the embodiment, and the pulse width of the second clock signal is greater than 20ns. The second clock signal that meets the preset condition has the qualification of being synchronized by the power supply chip of the embodiment. Of course, the second clock signal being synchronized by the voltage chip of the embodiment must also meet the above-mentioned other requirements, such as: the time of the second clock signal is earlier than that of the first clock signal, and the second clock control pin EXT SYNC of the synchronization module 10 is enabled. By taking the preset condition as the basis to judge whether the second clock signal can be synchronized, the accuracy of synchronization can be ensured while automatically adjusting the working frequency of the chip.

[0048] With reference to Figure 3 The clock interaction module 50 of the power supply chip of the embodiment comprises: a seventh resistor R7, an eighth resistor R8, and a third switch ON3. The first end of the seventh resistor R7 is connected to the second clock input pin SYNC IN, and the second end of the seventh resistor R7 is connected to the external circuit 40. The first end of the seventh resistor R7 is also connected to the first end of the third switch ON3, and the second end of the third switch ON3 is connected to the clock output pin SYNC OUT. The first end of the eighth resistor R8 is connected to the first end of the seventh resistor R7, and the second end of the eighth resistor R8 is grounded.

[0049] In some embodiments, the third switch ON3 is a PMOS tube. In other embodiments, the third switch ON3 can also be a switching device such as a triode, a relay, a contactor, etc.

[0050] In the embodiment, the external circuit 40 is connected to the clock interaction module 50 through the SYNC pin, the clock interaction module 50 can transmit the first clock signal generated by itself to the external circuit 40 through the SYNC pin, and the second clock signal of the external circuit 40 can be transmitted to the synchronization module 10 through the SYNC pin, so that the synchronization module 10 determines to run according to the first clock signal or the second clock signal. The synchronization module 10 can also be connected to the control end of the third switch ON3, and the synchronization module 10 can determine whether to send the first clock signal of itself to the external circuit 40 through the third switch ON3. For example, in the case of the external circuit 40 being a signal generator, the power supply chip can be synchronized according to the second clock signal of the signal generator, and it is not necessary to send the first clock signal to the signal generator, at this time the synchronization module 10 can control the third switch ON3 to be turned off; in the case of the external circuit 40 being another power supply chip, clock synchronization is needed between multiple power supply chips, at this time the synchronization module 10 can control the third switch ON3 to be turned on, so that the first clock signal of each power supply chip can be sent to other power supply chips, and the synchronization accuracy between multiple power supply chips is improved.

[0051] In some embodiments, the clock interaction module 50 is connected to multiple external circuits 40, that is, the external circuits 40 are all another power supply chip, and the SYNC pins of each power supply chip are connected together; the clock interaction module 50 is configured to obtain the second clock signals of the multiple external circuits 40, and input the multiple second clock signals to the synchronization module 10 through the second clock input pin SYNC IN;

[0052] The synchronization module 10 is configured to switch back to the first clock signal as the target clock signal in the case that the first clock control pin NO EXT SYNC is enabled and no second clock signal is input; the synchronization module 10 is configured to select the second clock signal as the target clock signal in the case that the second clock control pin EXT SYNC is enabled and the second clock signal is earlier than the first clock signal, specifically:

[0053] The synchronization module 10 is configured to select the second clock signal that is the earliest in time among the multiple second clock signals as the third clock signal, and switch back to the first clock signal as the target clock signal in the case that the first clock control pin NO EXT SYNC is enabled and no second clock signal is input; select the third clock signal as the target clock signal in the case that the second clock control pin EXT SYNC is enabled and the third clock signal is earlier than the first clock signal.

[0054] The power supply chip in the embodiment generates a first clock signal through the internal oscillation module 20, acquires a second clock signal of the external circuit 40 through the second clock input pin SYNC IN, acquires a clock control signal through the clock selection module 30, and determines the first clock signal or the second clock signal as a target clock signal according to the clock control signal, and operates with the target clock signal, so as to realize high-precision synchronization of the clock signals between the power supply chip and the external circuit 40 in the case that the power supply chip is connected with the external circuit 40.

[0055] The embodiment improves the circuit structure of the power supply chip, improves the synchronization performance between multiple power supply chips, and significantly improves the synchronization precision and reliability of the multi-chip system compared with the traditional internal clock type synchronization clock scheme, the precision is improved by about 30%, and the overall power consumption is reduced due to the increased synchronization precision, which is suitable for a wide range of power management applications, and improves the market competitiveness and application value of the product.

[0056] The embodiment of the application further provides a circuit board assembly, which comprises the power supply chip according to any one of the above embodiments.

[0057] It can be found that the embodiment is a circuit board assembly corresponding to the circuit embodiment, and the embodiment can be implemented in cooperation with the circuit embodiment. The related technical details mentioned in the circuit embodiment are still valid in the embodiment, and in order to reduce repetition, they will not be described here. Accordingly, the related technical details mentioned in the embodiment can also be applied to the circuit embodiment.

[0058] In addition, in order to highlight the innovative part of the application, some units that are not closely related to solving the technical problems proposed in the application are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment.

[0059] The embodiment of the application further provides an electronic device, which comprises the circuit board assembly according to the above embodiment.

[0060] The division of the above various components is only for the purpose of clear description, and when implemented, it can be combined into one component or some components can be split and decomposed into multiple components, as long as the same logical relationship is included, it is within the protection scope of the application.

[0061] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the application.

Claims

1. A power chip, characterized in that: include: Synchronization module, oscillation module, clock selection module; The oscillation module is connected to the first clock input pin of the synchronization module; the clock selection module is connected to the clock control pin of the synchronization module; The oscillation module is configured to generate a first clock signal and input the first clock signal to the synchronization module through the first clock input pin; The synchronization module is configured to obtain a second clock signal of the external circuit through a second clock input pin; The clock selection module is configured to input a clock control signal to the synchronization module through the clock control pin, and the synchronization module is configured to determine the first clock signal or the second clock signal as a target clock signal according to the clock control signal and operate with the target clock signal.

2. The power chip according to claim 1, characterized in that: The oscillation module includes: a first comparator, a first resistor, a second resistor, a third resistor, a first switch, a DC source, and a second switch; A first end of the first resistor is connected to a power supply, a second end of the first resistor is connected to a first end of the second resistor, a second end of the second resistor is grounded, the second end of the first resistor is further connected to a first end of the third resistor, a second end of the third resistor is connected to a first end of the first switch, and a second end of the first switch is grounded; The positive input terminal of the first comparator is connected to the input pin of the oscillation module, the negative input terminal of the first comparator is connected to the second end of the first resistor, and the output terminal of the first comparator is connected to the first clock input pin; The input pin of the oscillation module is further connected to the first end of the DC source, the second end of the DC source is connected to the first end of the second switch, and the second end of the second switch is grounded; The synchronization module further includes switch control pins, and the switch control pins are respectively connected to the control end of the first switch and the control end of the second switch.

3. The power chip according to claim 2, characterized in that: The first switch and the second switch are both NMOS transistors.

4. The power chip according to claim 2, characterized in that: The clock selection module includes a second comparator, a third comparator, a fourth resistor, a fifth resistor, and a sixth resistor; the synchronization module includes two clock control pins, one of which is a first clock control pin and the other is a second clock control pin; A first end of the fourth resistor is connected to a power supply, a second end of the fourth resistor is connected to a first end of the fifth resistor, a second end of the fifth resistor is connected to a first end of the sixth resistor, and a second end of the sixth resistor is grounded; The positive input terminal of the second comparator is connected to the input pin of the oscillation module, the negative input terminal of the second comparator is connected to the second end of the fourth resistor, and the output terminal of the second comparator is connected to one of the clock control pins; the synchronization module is configured to switch back to the first clock signal as the target clock signal when the first clock control pin is enabled and the second clock signal is not input; The negative input of the third comparator is connected to the input pin of the oscillation module, the positive input of the third comparator is connected to the second end of the fifth resistor, and the output of the second comparator is connected to another clock control pin; the synchronization module is configured to select the second clock signal as the target clock signal when the second clock control pin is enabled and the second clock signal is earlier than the first clock signal.

5. The power chip according to claim 1, characterized in that: The clock interaction module includes: a seventh resistor, an eighth resistor, and a third switch; A first end of the seventh resistor is connected to the second clock input pin, and a second end of the seventh resistor is connected to the external circuit; the first end of the seventh resistor is also connected to the first end of the third switch, and a second end of the third switch is connected to the clock output pin; A first end of the eighth resistor is connected to the first end of the seventh resistor, and a second end of the eighth resistor is grounded.

6. The power chip according to claim 5, characterized in that: The third switch is a PMOS tube.

7. The power chip according to claim 4, characterized in that: The clock interaction module is connected to the plurality of external circuits; the clock interaction module is configured to obtain the second clock signals of the plurality of external circuits and input the plurality of second clock signals into the synchronization module through the second clock input pins; The synchronization module is configured to select the earliest second clock signal among the plurality of second clock signals as the third clock signal, and select the first clock signal as the target clock signal when the first clock control pin is enabled and the first clock signal is earlier than the third clock signal; In a case where the second clock control pin is enabled and the third clock signal is earlier than the first clock signal, the third clock signal is selected as the target clock signal.

8. The power chip according to claim 1, characterized in that: The power chip further includes a clock interaction module; the clock interaction module is connected to the clock output pin of the synchronization module and the second clock input pin; The clock interaction module is configured to obtain the first clock signal through the clock output pin and output the first clock signal to the external circuit; The clock interaction module is further configured to obtain the second clock signal of the external circuit and input the second clock signal to the synchronization module through the second clock input pin.

9. A circuit board assembly, characterized in that: include: The power chip according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The circuit board assembly of claim 9.

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