Semiconductor switch

Abstract

Provided is a semiconductor switch capable of driving a load with high precision using a weak current. The semiconductor switch includes an electromotive force generation circuit that generates an electromotive force based on light reception, and a first switching transistor that is connected between a first output terminal and a reference voltage node and drives a load when the electromotive force is generated. A second switching transistor that is connected between a second output terminal and the reference voltage node and drives a load when the electromotive force is generated; and a protection circuit that uses the electromotive force as a power supply voltage and protects the first switching transistor and the second switching transistor from overcurrent and overheating.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-063628 (filing date: April 10, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor switch. Background Art

[0004] Photorelays have several operating modes, one of which is a solar cell mode. In solar cell mode, a switching transistor is turned on using a small amount of electromotive force generated by light emission from an LED within the photorelay, thereby driving a load.

[0005] Controlling the on / off switching of the switching transistor requires a timer to determine the timing of on / off switching. This timer can be implemented as a digital or analog circuit. However, in the aforementioned solar cell mode, the current flowing through the light-receiving side of the photorelay is very small, making it difficult to operate the timer using this weak current. Summary of the Invention

[0006] According to an embodiment of the present invention, a semiconductor switch capable of driving a load with high precision using a weak current is provided.

[0007] A semiconductor switch according to one embodiment of the present invention includes:

[0008] an electromotive force generating circuit for generating an electromotive force based on received light;

[0009] a first switching transistor connected between the first output terminal and a reference voltage node, and driving a load when generating the electromotive force;

[0010] a second switching transistor connected between the second output terminal and the reference voltage node, driving a load when generating the electromotive force; and

[0011] The protection circuit utilizes the electromotive force as a power supply voltage to protect the first switching transistor and the second switching transistor from overcurrent and overheat. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram showing the overall configuration of a semiconductor switch according to one embodiment.

[0013] Figure 2 This is a detailed circuit diagram of an electromotive force generating circuit.

[0014] Figure 3 yes Figure 2Equivalent circuit diagram of the current generating circuit.

[0015] Figure 4 Yes Figure 1 A circuit diagram showing an example of a specific circuit configuration of a protection circuit.

[0016] Figure 5A Yes Figure 4 A circuit diagram showing an example of a specific circuit configuration of a micro current source.

[0017] Figure 5B It is a continuation Figure 5A Circuit diagram.

[0018] Figure 6 Yes Figure 4 A circuit diagram showing an example of a specific circuit configuration of an overcurrent and overheat detection circuit.

[0019] Figure 7 Yes Figure 4 A circuit diagram showing an example of a specific circuit configuration of RS-F / F within a protection control circuit.

[0020] Figure 8 It is a diagram showing the truth table of RS-F / F. DETAILED DESCRIPTION

[0021] The following describes embodiments of a semiconductor switch with reference to the accompanying drawings. The following description focuses on the main components of the semiconductor switch. However, the semiconductor switch may contain components or functions not shown or described. The following description does not exclude components or functions not shown or described.

[0022] Figure 1 FIG. 1 is a block diagram showing the overall structure of a semiconductor switch 1 according to an embodiment of the present invention. Figure 1 As shown, a semiconductor switch 1 according to one embodiment includes an electromotive force generating circuit 2 , a first switching transistor Q1 , a second switching transistor Q2 , and a protection circuit 3 .

[0023] The electromotive force generating circuit 2 includes a light-emitting element and a light-receiving element. The light-receiving element receives light emitted by the light-emitting element and generates an electromotive force based on the received light. The light-emitting element is, for example, an LED (Light Emitting Diode). The light-receiving element is, for example, a photodiode. The following describes an example of using a photodiode as a light-receiving element. A photodiode has multiple operating modes, one of which is called a solar cell mode. In solar cell mode, the photodiode generates an electromotive force when receiving light. The electromotive force generating circuit 2 of this embodiment operates the photodiode in solar cell mode, for example.

[0024] The current source CS1 is connected to the electromotive force generating circuit 2 to cause current to flow through the light emitting element. The electromotive force generating circuit 2 outputs the electromotive force VCC and a GATE1 signal that sets the voltage of the GATE line connected to the gates of the first and second switching transistors Ql and Q2.

[0025] The first switching transistor Ql is connected between the VSENl terminal and a reference voltage node (e.g., a ground node), and drives a load not shown based on the electromotive force generated in the electromotive force generating circuit 2.

[0026] The second switching transistor Q2 is connected between the VSEN2 terminal and a reference voltage node (e.g., a ground node), and drives a load not shown based on the electromotive force generated in the electromotive force generating circuit 2.

[0027] The first and second switching transistors Ql and Q2 are, for example, NMOS transistors. A first resistor Rl is connected between the body of the first switching transistor Ql and a reference voltage node (e.g., a ground node GND_S). A Zener diode Dl is connected between the gate and the drain of the first switching transistor Ql. The anode of the Zener diode Dl is connected to the gate of the first switching transistor Ql, and the cathode of the Zener diode Dl is connected to the drain of the first switching transistor Ql. A first overcurrent detection signal VSENl is output from the VSENl terminal connected to the body of the first switching transistor Ql.

[0028] A second resistor R2 is connected between the body of the second switching transistor Q2 and a reference voltage node (e.g., a ground node GND_S). A Zener diode D2 is connected between the gate and the drain of the second switching transistor Q2. The anode of the Zener diode D2 is connected to the gate of the second switching transistor Q2, and the cathode of the Zener diode D2 is connected to the drain of the second switching transistor Q2. A second overcurrent detection signal VSEN2 is output from the VSEN2 terminal connected to the body of the second switching transistor Q2.

[0029] The first and second overcurrent detection signals VSENl and VSEN2 described above are signals that become high during overcurrent detection.

[0030] The protection circuit 3 utilizes the electromotive force VCC generated in the electromotive force generating circuit 2 as a power supply voltage, and protects the first switching transistor Ql and the second switching transistor Q2 from overcurrent and overheat. The protection circuit 3 generates a first reference voltage SC_REF, a second reference voltage TSD_REF, a third reference voltage REF_285, and a fourth reference voltage VCT using the electromotive force VCC generated in the electromotive force generating circuit 2. The first reference voltage SC_REF is used for detecting overcurrent. The second reference voltage TSD_REF is used for detecting overheat. The fourth reference voltage VCT is a low voltage signal generated from the third reference voltage REF_285.

[0031] The protection circuit 3 outputs an overcurrent monitoring signal indicating whether or not overcurrent is judged, and an overheat monitoring signal indicating whether or not overheat is judged. The overcurrent monitoring signal is, for example, a signal which becomes low in the case where overcurrent is judged. The overheat monitoring signal is, for example, a signal which becomes low in the case where overheat is judged.

[0032] Figure 2 is a detailed circuit diagram of the electromotive force generating circuit 2. As shown in Figure 2 , the electromotive force generating circuit 2 has a current generating circuit 4, a first photodiode column 5, a second photodiode column 6, a third photodiode column 7, a disconnection control circuit 8, resistors R3, R4.

[0033] A gate electrode of the first switching transistor Ql and a gate electrode of the second switching transistor Q2 are connected to a GATE line. A GATEl line connected to the GATE line via an analog switch described later is branched into a GATE2 line and a GATE3 line via the resistors R3, R4.

[0034] An anode of a diode D3 is connected to an fGND node. In the present specification, a cathode of the diode D3 is referred to as an fGNDl node.

[0035] The current generating circuit 4 generates a current upon receiving the light emitted from the light emitting element 2a as described later. The generated current flows to the first photodiode column 5, the second photodiode column 6, and the third photodiode column 7.

[0036] The first photodiode column 5, the second photodiode column 6, and the third photodiode column 7 each have a configuration in which a plurality of photodiodes PD are connected in series. The plurality of photodiodes PD connected in series in the first photodiode column and the second photodiode column are oriented in the same direction, and in contrast, the third photodiode column has a plurality of photodiodes PD connected in series in the opposite direction to the first photodiode column and the second photodiode column.

[0037] More specifically, the first photodiode column includes a plurality of photodiodes PD connected in series between the VCC node and the fGND1 node. The anode of each photodiode PD is arranged on the VCC node side, and the cathode is arranged on the fGND1 node side.

[0038] The second photodiode column includes a plurality of photodiodes PD connected in series between the GATE2 wiring and the fGND1 node. The anode of each photodiode PD is arranged on the GATE2 wiring side, and the cathode is arranged on the fGND1 node side.

[0039] The third photodiode array includes a plurality of photodiodes PD connected in series between the input node of the off control circuit 8 and the fGND1 node. The anode of each photodiode PD is arranged on the fGND1 node side, and the cathode is arranged on the input node side of the off control circuit 8.

[0040] The OFF control circuit 8 includes an NMOS transistor Q3 , an NPN transistor Q4 , a diode D3 , Zener diodes D4 and D5 , and resistors R3 and R4 .

[0041] NMOS transistor Q3 is a depletion-type transistor. Even when the gate voltage is below 0V, current flows between the drain and source of NMOS transistor Q3, and the voltage level of the GATE1 wiring reaches ground voltage. The gate of NMOS transistor Q3 is connected in parallel to a third photodiode array and resistor R6 via resistor R5. The drain of NMOS transistor Q3 is connected to the GATE3 wiring. The source of NMOS transistor Q3 is connected to the base of NPN transistor Q4 and the fGND1 node. The emitter of NPN transistor Q4 is connected to the ground node, and the collector is connected to the GATE3 wiring.

[0042] Between the GATE2 wiring and the ground node f_GND, two Zener diodes D4 and D5 are connected in series in opposite directions to each other.

[0043] Next, the operation of the electromotive force generating circuit 2 will be described. When the light emitting element 2a is non-emitting, since the NMOS transistor Q3 in the off control circuit 8 is a depletion type, current flows between the drain and source of the NMOS transistor Q3, and the GATE1 wiring and the GATE wiring become a voltage level close to the ground voltage. Therefore, Figure 1 The first switch transistor Q1 and the second switch transistor Q2 are both turned off.

[0044] If the light emitting element 2a emits light, electromotive forces are generated at both ends of the first photodiode column 5, and the electromotive forces are output from the VCC line. In addition, if the light emitting element 2a emits light, electromotive forces are generated at both ends of the second photodiode column 6, and the voltage level of the GATE 1 line rises. Further, if the light emitting element 2a emits light, electromotive forces are generated at both ends of the third photodiode column 7, the gate voltage of the NMOS transistor Q3 in the off control circuit 8 becomes a negative voltage, the NMOS transistor Q3 is cut off, and no current flows between the drain and the source any more. Therefore, the voltage level of the GATE 1 line rises, and the first switch transistor Ql and the second switch transistor Q2 are turned on. Thus, the first switch transistor Ql and the second switch transistor Q2 can drive the load.

[0045] Figure 3 is Figure 2 an equivalent circuit diagram of the current generating circuit 4. The current generating circuit 4 has a light emitting circuit 4a and a light receiving circuit 4b. The light emitting circuit 4a has the light emitting element 2a and a current source CS 1. As shown in Figure 3 , the current source CS 1 can be equivalently represented by two resistors R7, R8 and a voltage source VS.

[0046] The light receiving circuit 4b has a first current generating portion 4c connected to one end of the first photodiode column 5, a second current generating portion 4d connected to one end of the second photodiode column 6, and a third current generating portion 4e connected to one end of the third photodiode column 7.

[0047] The first current generating portion 4c has a first current source CS2 and a second current source CS3, resistors R9, R10, Rl l, and a capacitor Cl. The first current source CS2 is connected in series to the resistor R9, the second current source CS3, the resistor RlO and the capacitor Cl are connected in parallel, and the resistor Rl l is connected in series to the parallel circuit.

[0048] The second current generating portion 4d has a third current source CS4 and a fourth current source CS5, resistors R12, R13, R14, and a capacitor C2. The third current generating portion 4e has a fifth current source CS6 and a sixth current source CS7, resistors R15, R16, R17, and a capacitor C3. The circuit configuration of the second current generating portion 4d and the third current generating portion 4e is the same as that of the first current generating portion 4c.

[0049] The current generated by the electromotive force generated in the first photodiode array 5 flows to the first current generating section 4c. The current generated by the electromotive force generated in the second photodiode array 6 flows to the second current generating section 4d. The current generated by the electromotive force generated in the third photodiode array 7 flows to the third current generating section 4e. The first current source CS2 and the second current source CS3 within the first current generating section 4c equivalently represent the current generated by the electromotive force generated in the first photodiode array 5. The third current source CS4 and the fourth current source CS5 within the second current generating section 4d equivalently represent the current generated by the electromotive force generated in the second photodiode array 6. The fifth current source CS6 and the sixth current source CS7 within the third current generating section 4e equivalently represent the current generated by the electromotive force generated in the third photodiode array 7.

[0050] Figure 4 Yes Figure 1 A circuit diagram showing an example of a specific circuit configuration of the protection circuit 3. Figure 4 As shown, the protection circuit 3 includes an overcurrent and overheat detection circuit 11 , a small current source 12 , a protection control circuit 13 , an analog switch 14 , a low voltage holding circuit 15 , and an internal power supply voltage holding circuit 16 .

[0051] The overcurrent and overheat detection circuit 11 includes a comparator 31 for detecting overcurrent, a comparator 32 for detecting overheat, and a diode D6 for generating a reference voltage for overheat detection. Comparator 31 outputs a low-level overcurrent detection signal O_SC when detecting overcurrent. Comparator 32 outputs a low-level overheat detection signal O_TSD when detecting overheat. The detailed structure of the overcurrent and overheat detection circuit 11 will be described later.

[0052] The micro-current source 12 uses the electromotive force VCC generated by the first photodiode array 5 within the electromotive force generating circuit 2 as a power supply voltage to generate a micro-current and supply it to the overcurrent and overheat detection circuit 11. The micro-current generated by the micro-current source 12 is, for example, on the order of tens of nanoamperes (nA). The detailed structure of the micro-current source 12 will be described later.

[0053] The protection control circuit 13 forcibly turns off the first switching transistor Q1 and the second switching transistor Q2 when at least one of overcurrent and overheating is detected by the protection circuit 3. The protection control circuit 13 includes an AND gate G1, a resistor R21, a capacitor C4, an OR gate G2, an RS flip-flop (hereinafter referred to as RS-F / F) 17, a resistor R22, an NMOS transistor Q5, a PMOS transistor Q6, an NMOS transistor Q7, a resistor R23, a capacitor C5, inverters IV1 to IV5, and an NMOS transistor Q8.

[0054] The AND gate G1 outputs a logical product of the overcurrent detection signal O_SC and the overheat detection signal O_TSD. If at least one of the overcurrent and the overheat is detected, the output of the AND gate G1 becomes a low level.

[0055] The output signal of the AND gate G1 is input to one input terminal of the OR gate G2. One end of a resistor R21 and one end of a capacitor C4 are connected to the other input terminal of the OR gate G2. The other end of the resistor R21 is connected to the output node of the AND gate G1, and the other end of the capacitor C4 is connected to the ground node GND_S. Thus, the output of the OR gate G2 becomes a low level after the output signal of the AND gate G1 changes from a high level to a low level, and after a time corresponding to the time constant of the resistor value of the resistor R21 and the capacitance of the capacitor C4. Thus, the OR gate G2, the resistor R21, and the capacitor C4 function as a timer that counts a time corresponding to the time constant of the resistor value of the resistor R21 and the capacitance of the capacitor C4.

[0056] The output signal of the OR gate G2 is input to the set (S) terminal of the RS-F / F 17. The reset (RST) terminal of the RS-F / F 17 is input with a reset signal RST described later.

[0057] If the S terminal becomes a low level, the RS-F / F 17 becomes a set state, and the Q terminal becomes a high level. Thus, the NMOS transistor Q5 is turned on, and the drain of the NMOS transistor Q5 becomes a ground level. Therefore, the PMOS transistor Q6 is turned on, and the drain of the PMOS transistor Q6 becomes a high level voltage.

[0058] One end of a resistor R23 is connected to the drain of the PMOS transistor Q6, and a capacitor C5 is connected between the other end of the resistor R23 and the ground node. If the voltage level of the drain of the transistor Q6 changes, the signal logic of each of the output nodes of the inverters IV1, IV2, and IV4 changes after a time corresponding to the time constant determined by the resistor value of the resistor R23 and the capacitance of the capacitor C5.

[0059] For example, if the drain of the transistor Q6 becomes a high level voltage, the signal logic of the output nodes of the inverters IV4 and IV5 changes slightly delayed, and the gate signal Gshunt of the NMOS transistor Q8 becomes a high level voltage. Thus, the NMOS transistor Q8 is turned on, and the voltage level of the GATE wire is lowered. Therefore, the first switching transistor Q1 and the second switching transistor Q2 are forcibly turned off.

[0060] At this time, since the output of the inverter IV3 becomes high and the output of the inverter IV1 becomes low, both the NMOS transistor Q9 and the PMOS transistor Q10 constituting the analog switch 14 are turned off. If the analog switch 14 is turned off, even if the GATE1 signal output from the electromotive force generation circuit 2 is high, the GATE line connected to the gates of the first and second switching transistors Q1 and Q2 no longer becomes high, and the first and second switching transistors Q1 and Q2 can be reliably turned off.

[0061] Instead of the analog switch 14, a diode D7 can be connected. The anode of the diode D7 is connected to the GATE line, and the cathode of the diode D7 is connected to the GATE1 line. The diode D7 functions as a blocking diode, and prevents the voltage of the GATE1 line from being supplied to the gates of the first and second switching transistors Q1 and Q2. In this way, the analog switch 14 or the diode D7 functions as a voltage cutoff circuit that cuts off the GATE line (first line) connected to the output node of the protection circuit 3 and the gates of the first and second switching transistors Q1 and Q2 from the GATE1 line (second line) from which the electromotive force is supplied, when the protection circuit 3 forcibly turns off the first and second switching transistors Q1 and Q2.

[0062] The low voltage holding circuit 15 has a PNP transistor Q11 and three capacitors C6, C7, and C8 connected in parallel between the emitter-collector of the PNP transistor Q11. The fourth reference voltage VCT generated in the minute current source 12 described later is supplied to the emitter of the PNP transistor Q11.

[0063] The third reference voltage REF_285 of a prescribed voltage level is input to the base of the PNP transistor Q11. The PNP transistor Q11 holds the fourth reference voltage VCT of a voltage level lower than the voltage level of the third reference voltage REF_285 between the emitter-collector based on the third reference voltage REF_285 input to the base.

[0064] The internal power supply voltage holding circuit 16 has a capacitor C21 that holds the internal power supply voltage VCC_int generated in the minute current source 12.

[0065] Figure 5A and Figure 5B is a circuit diagram showing one example of the specific circuit configuration of the minute current source 12 of Figure 4 Figure 5A and Figure 5B the circuits of Figure 5A and Figure 5B ​As shown, the minute current source 12 has an internal power supply voltage generating circuit 21, a first reference voltage generating circuit 22, a second reference voltage generating circuit 23, a third reference voltage generating circuit 24, and a minute current generating circuit 25.

[0066] The internal power supply voltage generating circuit 21 has a resistor R31, Zener diodes D8, D9, D10, a diode-connected depletion-mode PMOS transistor Q21, an NPN transistor Q22, a resistor R32, an NPN transistor Q23, resistors R33, R34, and Zener diodes D11, D12.

[0067] A VCC line is connected to one end of the resistor R31. Three Zener diodes D8, D9, D10 are connected in series between the other end of the resistor R31 and a ground node. The cathodes of these Zener diodes D8, D9, D10 are connected to the other end of the resistor R31, and the anodes are connected to the ground node GND.

[0068] The diode-connected PMOS transistor Q21 functions as a blocking diode D13. This blocking diode D13 is provided for separating the electromotive force VCC from the internal power supply voltage VCC_int, and the anode of the blocking diode D13 is disposed on the line side of the electromotive force VCC, and the cathode is disposed on the line side of the internal power supply voltage VCC_int.

[0069] The collector of the NPN transistor Q22 is connected to the cathode of the blocking diode D13. A resistor R32 is connected between the base and the collector of the NPN transistor Q22. The base of the NPN transistor Q22 is connected to the collector of the NPN transistor Q23. A resistor R33 is connected between the collector and the base of the NPN transistor Q23, and a resistor R34 is connected between the base and the emitter of the NPN transistor Q23. Two Zener diodes D11, D12 are connected in series with each other toward opposite directions between the emitter of the NPN transistor Q23 and the ground node GND.

[0070] The first reference voltage generating circuit 22 has capacitors C11, C12, PNP transistors Q24 to Q27, resistors R35 to R39, and an NMOS transistor Q28. The emitter of the PNP transistor Q24 is connected to the VCC_int node. The collector of the PNP transistor Q24 is connected to the emitter of the PNP transistor Q25. The collector and the base of the PNP transistor Q25 are short-circuited, and a capacitor C12 is connected between this short-circuit node and the VCC_int node. Four resistors R35 to R38 are connected in series between the collector of the PNP transistor Q25 and the ground node.

[0071] A resistor R39 is connected between the emitter of a PNP transistor Q26 and a VCC int node. The collector of the PNP transistor Q26 is connected to the emitter of a PNP transistor Q27, and the base of a PNP transistor Q24 is connected to a node at this connection. The base of the PNP transistor Q26, the collector of the PNP transistor Q24, and the emitter of a PNP transistor Q25 are commonly connected. The collector of the PNP transistor Q27 is connected to the drain of an NMOS transistor Q28. The source of the NMOS transistor Q28 is connected to a ground node GND.

[0072] A third reference voltage REF_285 is output between a resistor R35 and a resistor R36. A capacitor Cll is connected between a node at which the third reference voltage REF_285 is output and the ground node GND. A first reference voltage SC_REF is output between the resistor R36 and a resistor R37.

[0073] The second reference voltage generating circuit 23 has an NMOS transistor Q31, two PMOS transistors Q32, Q33, a resistor R41, an NMOS transistor Q34, two PMOS transistors Q35, Q36, two NMOS transistors Q37, Q38, two PMOS transistors Q39, Q40, an NMOS transistor Q41, resistors R41 to R47, and capacitors C13 to C15.

[0074] The gate and the drain of the NMOS transistor Q28 are short-circuited, and the gate of the NMOS transistor Q28 is connected to the gate of the NMOS transistor Q31. Thus, the NMOS transistor Q31 and the NMOS transistor Q28 constitute a current mirror circuit.

[0075] The drain of the NMOS transistor Q31 is connected to the drain and the gate of a PMOS transistor Q32. The source of the PMOS transistor Q32 is connected to the VCC int node. The gate of the PMOS transistor Q32 is connected to the gate of a PMOS transistor Q33, and the PMOS transistor Q32 and the PMOS transistor Q33 constitute a current mirror circuit. The source of the PMOS transistor Q33 is connected to the VCC int node. A resistor R41 is connected between the drain of the PMOS transistor Q33 and the ground node.

[0076] The drain of the NMOS transistor Q34 is connected to the VCC int node, and the source and the gate of the NMOS transistor Q34 are short-circuited.

[0077] The source of the PMOS transistor Q35 is connected to the VCC int node, and the gate is connected to the gate and the drain of a PMOS transistor Q36. Thus, the PMOS transistor Q35 and the PMOS transistor Q36 constitute a current mirror circuit.

[0078] The drain of the PMOS transistor Q35 is connected to the drain of the NMOS transistor Q37. The drain of the PMOS transistor Q36 is connected to the drain of the NMOS transistor Q38. The sources of these NMOS transistors Q37, Q38 are connected to each other. In addition, between the drains of these NMOS transistors Q37, Q38, the resistor R42 and the capacitor C13 are connected in series.

[0079] The source of the PMOS transistor Q39 is connected to the VCC int node. The gate of the PMOS transistor Q39 is connected to the drains of the transistors Q35, Q37. The drain of the PMOS transistor Q39 is connected to the drain of the NMOS transistor Q41. The gate and the source of the NMOS transistor Q41 are shorted.

[0080] The source of the NMOS transistor Q37, the source of the NMOS transistor Q38, and the gate and the source of the NMOS transistor Q41 are commonly connected, and between this connection node and the ground node, the two resistors R43, R44 are connected in series. The resistor R45 is connected between the drain of the NMOS transistor Q41 and the ground node GND.

[0081] The source of the PMOS transistor Q40 is connected to the VCC int node. The gate of the PMOS transistor Q40 is connected to the gate of the PMOS transistor Q39 and to the drains of the transistors Q35, Q37.

[0082] Between the drain of the PMOS transistor Q40 and the ground node GND, the two resistors R46, R47 are connected in series. The capacitor C15 is connected in parallel to the resistor R47. Between the drain of the PMOS transistor Q40 and the connection node of the resistor R46 and the ground node GND, the capacitor C14 is connected.

[0083] The first reference voltage SC_REF is output from the drain of the PMOS transistor Q40 and the connection node of the resistor R46. The second reference voltage TSD_REF is output from the connection node of the resistor R46 and the resistor R47.

[0084] Figure 5B The illustrated third reference voltage generating circuit 24 has six PMOS transistors Q51 to Q56, an NMOS transistor Q57, and a PNP transistor Q58.

[0085] The gate and the drain of the PMOS transistor Q53 are shorted, and at this shorted node, the gates of the six PMOS transistors Q51 to Q56 are connected. Therefore, the six PMOS transistors Q51 to Q56 constitute a current mirror circuit.

[0086] The source of the PMOS transistor Q51 is connected to the VCC int node, and the drain of the PMOS transistor Q51 is connected to the source of the PMOS transistor Q52. The drain of the PMOS transistor Q52 is connected to the source of the PMOS transistor Q53.

[0087] The source of the PMOS transistor Q54 is connected to the VCC int node, and the drain of the PMOS transistor Q54 is connected to the source of the PMOS transistor Q55. The drain of the PMOS transistor Q55 is connected to the source of the PMOS transistor Q56.

[0088] The gate and the drain of the PMOS transistor Q53 are connected to the drain of the NMOS transistor Q57. The source of the NMOS transistor Q57 is connected to the ground node.

[0089] The drain of the PMOS transistor Q56 is connected to the emitter and the base of the PNP transistor Q58. The collector of the PNP transistor Q58 is connected to the ground node. The fourth reference voltage VCT is output from the drain of the PMOS transistor Q56.

[0090] The minute current generating circuit 25 has a total of fourteen PMOS transistors Q61 to Q74 and the NMOS transistor Q75 which constitute a current mirror circuit.

[0091] The source of the PMOS transistor Q61 is connected to the VCC int node, and the gate and the drain are shorted, and the drain of the shorted node is connected to the drain of the NMOS transistor Q75. The source of the NMOS transistor Q75 is connected to the ground node GND. The gate of the NMOS transistor Q75 is connected to the gate of the NMOS transistor Q57.

[0092] The sources of the thirteen PMOS transistors Q62 to Q74 are connected to the VCC int node, and the gates are commonly connected to each other, and the gate of the PMOS transistor Q61 is also connected to the connection node.

[0093] The minute currents are output from the drains of the thirteen PMOS transistors Q62 to Q74. Twelve of the thirteen minute currents are supplied to the overcurrent and overheating detection circuit 11, and the remaining one is supplied to the protection circuit 3.

[0094] Figure 6 is a circuit diagram showing an example of the detailed circuit configuration of the overcurrent and overheating detection circuit 11 of Figure 4 Figure 6 ​As shown, the overcurrent and overheat detection circuit 11 has a first comparator 31a and a second comparator 31b that constitute a comparator 31 for overcurrent detection, and a third comparator 32 for overheat detection. The first comparator 31a compares the voltage level of the first overcurrent detection signal VSEN1 with the voltage level of a first reference voltage SC_REF, and outputs an error signal indicating the comparison result. The first comparator 31a outputs a low-level error signal when the voltage level of the first overcurrent detection signal VSEN1 is higher than the voltage level of the first reference voltage.

[0095] The second comparator 31b compares the voltage level of the second overcurrent detection signal VSEN2 with the voltage level of the first reference voltage, and outputs an error signal indicating the comparison result. The second comparator 31b outputs a low-level error signal when the voltage level of the second overcurrent detection signal VSEN2 is higher than the voltage level of the first reference voltage.

[0096] A first wiring that transmits the error signal output from the first comparator 31a and a second wiring that transmits the error signal output from the second comparator 31b are wired ORed, generating an overcurrent monitoring signal O-SC.

[0097] A general diode decreases the forward voltage as the temperature becomes higher, and thus it is possible to determine whether or not it is overheated by comparing the forward voltage of the diode with a prescribed reference voltage. Therefore, the third comparator 32 compares the forward voltage of the diode D6 with a fifth reference voltage, and outputs an error signal indicating the comparison result. If the forward voltage of the diode becomes lower than the fifth reference voltage due to overheating, the third comparator 32 outputs a low-level overheat detection signal O-TSD.

[0098] The first comparator 31a has resistors R51, R52, a Zener diode D21, four PNP transistors Q81 to Q84, two NPN transistors Q85, Q86, a capacitor C21, an NPN transistor Q87, a capacitor C21, and a resistor R53.

[0099] The first overcurrent detection signal VSEN1 is input to the base of the PNP transistor Q81 via the resistor R51. The resistor R52 and the Zener diode D21 are connected in parallel between the base of the PNP transistor Q81 and a ground node.

[0100] A minute current from the minute current source 12 is supplied to the emitter of the PNP transistor Q81. The emitter of the PNP transistor Q81 is connected to the base of the PNP transistor Q82. A minute current from the minute current source 12 is supplied to the emitter of the PNP transistor Q82 and the emitter of the PNP transistor Q83.

[0101] The collector of the PNP transistor Q82 is connected to the collector and the base of the NPN transistor Q85. The collector of the PNP transistor Q83 is connected to the collector of the NPN transistor Q86. The bases of the NPN transistors Q85 and Q86 are connected to each other, constituting a current mirror circuit.

[0102] A minute current from the minute current source 12 is supplied to the base of the PNP transistor Q83 and the emitter of the PNP transistor Q84. The collector of the PNP transistor Q84 is connected to the ground node. The base of the PNP transistor Q84 is supplied with the first reference voltage SC_REF via the resistor R53.

[0103] The collector of the PNP transistor Q83 and the collector of the NPN transistor Q86 are connected to the base of the NPN transistor Q87. The overcurrent monitoring signal is output from the collector of the NPN transistor Q86.

[0104] The second comparator 31b has the resistors R54, R55, the Zener diode D22, four PNP transistors Q88 to Q91, two NPN transistors Q92, Q93, the capacitor C22, the NPN transistor Q94, and the resistor R56.

[0105] The second overcurrent detection signal VSEN2 is input to the base of the PNP transistor Q88 via the resistor R54. The resistor R55 and the Zener diode D22 are connected in parallel between the base of the PNP transistor Q88 and the ground node.

[0106] A minute current from the minute current source 12 is supplied to the emitter of the PNP transistor Q88. The emitter of the PNP transistor Q88 is connected to the base of the PNP transistor Q89. A minute current from the minute current source 12 is supplied to the emitter of the PNP transistor Q89 and the emitter of the PNP transistor Q90.

[0107] The collector of the PNP transistor Q89 is connected to the collector and the base of the NPN transistor Q92. The collector of the PNP transistor Q90 is connected to the collector of the NPN transistor Q93. The bases of the NPN transistors Q92 and Q93 are connected to each other, constituting a current mirror circuit.

[0108] A minute current from the minute current source 12 is supplied to the base of the PNP transistor Q90 and the emitter of the PNP transistor Q91. The collector of the PNP transistor Q91 is connected to the ground node. The base of the PNP transistor Q91 is supplied with the first reference voltage SC_REF via the resistor R56.

[0109] The base of the NPN transistor Q94 is connected to the collector of the PNP transistor Q90 and the collector of the NPN transistor Q93 . The collector of the NPN transistor Q94 outputs an overcurrent monitoring signal O_SC.

[0110] The third comparator 32 includes a diode-connected NPN transistor Q95 , four PNP transistors Q96 to Q99 , two NPN transistors Q100 and Q101 , a capacitor C23 , a resistor R58 , and an NPN transistor Q102 .

[0111] A small current from a small current source 12 is supplied to the base and collector of a diode-connected NPN transistor Q95 (the anode of a diode D6). The emitter of the NPN transistor Q95 is connected to the ground node. The forward voltage of the diode D6 formed by the NPN transistor Q95 is input to the base of a PNP transistor Q96 via a resistor R57. A second reference voltage TSD_REF is input to the base of a PNP transistor Q99 via a resistor R58. The emitter of the PNP transistor Q96 is connected to the base of a PNP transistor Q97, and the emitter of the PNP transistor Q99 is connected to the base of a PNP transistor Q98. The emitters of these PNP transistors Q97 and Q98 are connected to each other, and the small current is supplied from the small current source 12.

[0112] The collector of the PNP transistor Q97 is connected to the collector of the NPN transistor Q100, and the collector of the PNP transistor Q98 is connected to the collector and base of the NPN transistor Q101. These NPN transistors Q100 and Q101 constitute a current mirror circuit.

[0113] Capacitor C23 is connected between the base of PNP transistor Q99 and the ground node. The base of NPN transistor Q102 is connected to the collector of PNP transistor Q97 and the collector of NPN transistor Q100. A small current is supplied to the collector of NPN transistor Q102 from small current source 12. The emitter of NPN transistor Q102 is connected to the ground node. An overheat monitoring signal O_TSD is output from the collector of NPN transistor Q102.

[0114] Figure 7 Yes Figure 4 A circuit diagram showing an example of a specific circuit configuration of the RS-F / F 17 within the protection control circuit 13. Figure 7As shown, the RS-F / F 17 has a 3-input NAND gate G3, a 2-input NAND gate G4, and an inverter IV 10. The 3-input NAND gate G3 is input with VDD, a set signal S, and an output signal of the 2-input NAND gate G4, and outputs a NAND signal of these signals. An output signal of the 3-input NAND gate G3 is output from a Q terminal, and a signal inverted in the inverter IV 10 is output from a / Q terminal.

[0115] The 2-input NAND gate G4 is input with the output signal of the 3-input NAND gate G3 and a reset signal R, and outputs a NAND signal of these signals. An output signal of the 2-input NAND gate G4 is input to the 3-input NAND gate G3.

[0116] Figure 8 is a table showing a truth table of the RS-F / F 17. If the set signal S becomes a low level, the Q terminal becomes a high level, and if the reset signal R becomes a low level, the / Q terminal becomes a high level.

[0117] Thus, in the present embodiment, the protection circuit 3 is caused to operate by using the electromotive force generated by the light reception, and thus the first switching transistor Ql and the second switching transistor Q2 can be protected from the overcurrent and the overheat. According to the present embodiment, since the power supply circuit is not needed to cause the protection circuit 3 to operate, the semiconductor switch 1 can be miniaturized, and the application range of the semiconductor switch 1 of the present embodiment can be expanded.

[0118] Further, in the present embodiment, the overcurrent is detected based on the slight current flowing through the main body in correspondence with the current flowing between the drain and the source of the first switching transistor Ql and the second switching transistor Q2, and the overheat is detected from the change in the forward voltage of the diode, and thus the detection of the overcurrent and the overheat can be performed with low power consumption and high accuracy.

[0119] Further, from the time when at least one of the overcurrent and the overheat is detected, until the period corresponding to the time constant of the resistance value of the resistance R21 and the capacitance of the capacitor C4, the first switching transistor Ql and the second switching transistor Q2 are caused to be turned off. Thus, the timer composed of the analog circuit can be driven using the weak power, and the first switching transistor Ql and the second switching transistor Q2 can be protected by the circuit composed of low power consumption and small scale.

[0120] [Supplementary note]

[0121] [Item 1]

[0122] A semiconductor switch comprising:

[0123] an electromotive force generation circuit that generates an electromotive force based on light reception;

[0124] a first switching transistor connected between the first output terminal and a reference voltage node, which drives the load when the electromotive force is generated;

[0125] a second switching transistor connected between the second output terminal and the reference voltage node, which drives the load when the electromotive force is generated; and

[0126] a protection circuit which utilizes the electromotive force as a power supply voltage, and protects the first switching transistor and the second switching transistor from overcurrent and overheat.

[0127] [Item 2]

[0128] The semiconductor switch according to Item 1, comprising:

[0129] a first overcurrent detection circuit which outputs a first overcurrent detection signal corresponding to a current flowing between a drain and a source of the first switching transistor; and

[0130] a second overcurrent detection circuit which outputs a second overcurrent detection signal corresponding to a current flowing between a drain and a source of the second switching transistor,

[0131] the protection circuit determines whether to turn off the first switching transistor and the second switching transistor based on signal levels of the first overcurrent detection signal and the second overcurrent detection signal.

[0132] [Item 3]

[0133] The semiconductor switch according to Item 2, the first overcurrent detection circuit has a first resistor connected between a body and a source of the first switching transistor, and outputs the first overcurrent detection signal having a signal level corresponding to a voltage across the first resistor,

[0134] the second overcurrent detection circuit has a second resistor connected between a body and a source of the second switching transistor, and outputs the second overcurrent detection signal having a signal level corresponding to a voltage across the second resistor.

[0135] [Item 4]

[0136] The semiconductor switch according to Item 2 or 3, the protection circuit has an overcurrent determination circuit,

[0137] the overcurrent determination circuit has:

[0138] a first comparator which compares a signal level of the first overcurrent detection signal with a prescribed first reference voltage; and

[0139] a second comparator that compares a signal level of the second overcurrent detection signal with the first reference voltage.

[0140] [Item 5]

[0141] The semiconductor switch according to Item 4, wherein the protection circuit has:

[0142] a first wiring connected to an output node of the first comparator; and

[0143] a second wiring connected to an output node of the second comparator,

[0144] a connection node of the first wiring and the second wiring generates an overcurrent detection signal obtained by operating the output signal of the first comparator and the output signal of the second comparator.

[0145] [Item 6]

[0146] The semiconductor switch according to Item 4, wherein the protection circuit has an overheat detection circuit,

[0147] the overheat detection circuit has:

[0148] a diode for overheat detection; and

[0149] a third comparator that compares a forward voltage of the diode with a second reference voltage.

[0150] [Item 7]

[0151] The semiconductor switch according to Item 6, wherein the protection circuit has a micro-current source that generates a micro-current using the electromotive force as a power supply voltage,

[0152] the micro-current is supplied to the first comparator, the second comparator, and the third comparator from the micro-current source.

[0153] [Item 8]

[0154] The semiconductor switch according to Item 6 or 7, wherein the protection circuit has a protection control circuit that forcibly turns off the first switching transistor and the second switching transistor when at least one of overcurrent and overheat is detected by the first comparator, the second comparator, and the third comparator.

[0155] [Item 9]

[0156] The semiconductor switch according to Item 8, wherein the protection circuit has a timer that stands by for a prescribed period from when at least one of overcurrent and overheat is detected by the first comparator, the second comparator, and the third comparator.

[0157] The protection control circuit forcibly turns off the first switching transistor and the second switching transistor after the timer has been on for the prescribed period.

[0158] [Item 10]

[0159] The semiconductor switch according to any one of items 1 to 9,

[0160] The timer has a resistor, a capacitor, and a logic gate circuit,

[0161] The logic gate circuit performs a logical operation between a detection signal that becomes a prescribed signal logic when at least one of an overcurrent or an overheat is detected and a delay signal that delays the timing at which the detection signal becomes the prescribed signal logic,

[0162] The protection circuit forcibly turns off the first switching transistor and the second switching transistor when the signal logic of the output signal of the logic gate circuit changes.

[0163] [Item 11]

[0164] The semiconductor switch according to item 10, the prescribed period is adjusted by a time constant determined by the resistance value of the resistor and the capacitance of the capacitor.

[0165] [Item 12]

[0166] The semiconductor switch according to any one of items 1 to 11, the protection circuit has a voltage cutoff circuit that cuts off a first wiring that connects an output node of the protection circuit and gates of the first switching transistor and the second switching transistor from a second wiring that supplies the electromotive force when the first switching transistor and the second switching transistor are forcibly turned off.

[0167] [Item 13]

[0168] The semiconductor switch according to item 12, the voltage cutoff circuit has a diode that has an anode connected to the gates of the first switching transistor and the second switching transistor and a cathode connected to the output node of the electromotive force generation circuit.

[0169] [Item 14]

[0170] The semiconductor switch according to item 12, the voltage cutoff circuit has an analog switch that switches between connecting and cutting off the gates of the first switching transistor and the second switching transistor from the output node of the electromotive force generation circuit.

[0171] [Item 15]

[0172] The semiconductor switch as claimed in claim 1 to 14, wherein the electromotive force generating circuit comprises:

[0173] a light emitting element;

[0174] a first photodiode string having two or more photodiodes connected in series to generate an electromotive force by receiving light emitted from the light emitting element;

[0175] a second photodiode string having two or more photodiodes connected in series to generate an electromotive force by receiving light emitted from the light emitting element;

[0176] a third photodiode string having two or more photodiodes connected in series to generate an electromotive force by receiving light emitted from the light emitting element; and

[0177] a voltage control circuit that controls a voltage of a wiring connected to a gate of the first switching transistor and a gate of the second switching transistor, based on the electromotive force generated by the light reception of the second photodiode string and the electromotive force generated by the light reception of the third photodiode string,

[0178] the electromotive force of the first photodiode string is used as a power voltage of the protection circuit.

[0179] [Item 16]

[0180] The semiconductor switch as claimed in item 15, wherein the direction of connection of the two or more photodiodes in the first photodiode string and the second photodiode string is opposite to the direction of connection of the two or more photodiodes in the third photodiode string.

[0181] [Item 17]

[0182] The semiconductor switch as claimed in item 16, wherein the voltage control circuit turns on both the first switching transistor and the second switching transistor when the electromotive force generated by the light reception of the second photodiode string exceeds a first threshold voltage, and turns off both the first switching transistor and the second switching transistor when the electromotive force generated by the light reception of the third photodiode string becomes equal to or less than a second threshold voltage.

[0183] [Item 18]

[0184] A semiconductor switch as claimed in any one of items 1 to 17, comprising a semiconductor chip in which the electromotive force generating circuit and the protection circuit are built-in.

[0185] The application is not limited to the above-described embodiments, and various modifications can be made by those skilled in the art. The effects of the application are not limited to the above-described effects. That is, various additions, changes, and partial deletions can be made within the scope of the conceptual ideas and the spirit of the application according to the claims and equivalents thereof.

[0186] BRIEF DESCRIPTION OF DRAWINGS

[0187] 1 semiconductor switch, 2 electromotive force generating circuit, 2a light emitting element, 3 protection circuit, 4 current generating circuit, 4a light emitting circuit, 4b light receiving circuit, 4c first current generating section, 4d second current generating section, 4e third current generating section, 5 first photodiode row, 6 second photodiode row, 7 third photodiode row, 8 off control circuit, 11 overcurrent and overheat detection circuit, 12 minute current source, 13 protection control circuit, 14 analog switch, 15 low voltage holding circuit, 16 internal power supply voltage holding circuit, 17 RS-F / F, 21 internal power supply voltage generating circuit, 22 first reference voltage generating circuit, 23 second reference voltage generating circuit, 24 third reference voltage generating circuit, 25 minute current generating circuit, 31 comparator, 31a first comparator, 31b second comparator, 32 third comparator.

Claims

1. A semiconductor switch comprising: an electromotive force generating circuit for generating an electromotive force based on received light; a first switching transistor connected between the first output terminal and a reference voltage node, and driving a load when generating the electromotive force; a second switching transistor connected between the second output terminal and the reference voltage node, and driving a load when generating the electromotive force; as well as The protection circuit utilizes the electromotive force as a power supply voltage to protect the first switching transistor and the second switching transistor from overcurrent and overheat.

2. The semiconductor switch according to claim 1, comprising: a first overcurrent detection circuit, outputting a first overcurrent detection signal corresponding to the current flowing between the drain and the source of the first switching transistor; and The second overcurrent detection circuit outputs a second overcurrent detection signal corresponding to the current flowing between the drain and source of the second switching transistor. The protection circuit determines whether to turn off the first switching transistor and the second switching transistor based on signal levels of the first overcurrent detection signal and the second overcurrent detection signal.

3. The semiconductor switch according to claim 2, wherein The first overcurrent detection circuit includes a first resistor connected between the body and the source of the first switching transistor, and outputs the first overcurrent detection signal having a signal level corresponding to the voltage across both ends of the first resistor. The second overcurrent detection circuit includes a second resistor connected between the body and the source of the second switching transistor, and outputs the second overcurrent detection signal having a signal level corresponding to a voltage across the second resistor.

4. The semiconductor switch according to claim 2, wherein The protection circuit has an overcurrent determination circuit, The overcurrent determination circuit has: a first comparator, for comparing a signal level of the first overcurrent detection signal with a prescribed first reference voltage; as well as The second comparator compares the signal level of the second overcurrent detection signal with the first reference voltage.

5. The semiconductor switch according to claim 4, comprising: a first wiring connected to an output node of the first comparator; and a second wiring connected to an output node of the second comparator, A connection node between the first wiring and the second wiring generates an overcurrent detection signal obtained by wired-ORing an output signal of the first comparator and an output signal of the second comparator.

6. The semiconductor switch according to claim 4, wherein The protection circuit has an overheat detection circuit, The overheat detection circuit has: Overheat detection diodes; and The third comparator compares the forward voltage of the diode with a second reference voltage.

7. The semiconductor switch according to claim 6, wherein The protection circuit includes a minute current source that generates a minute current by using the electromotive force as a power supply voltage. The first comparator, the second comparator, and the third comparator are each supplied with a minute current from the minute current source.

8. The semiconductor switch according to claim 6, wherein The protection circuit includes a protection control circuit that forcibly turns off the first switching transistor and the second switching transistor when at least one of overcurrent and overheat is detected by the first comparator, the second comparator, and the third comparator.

9. The semiconductor switch according to claim 8, wherein The protection circuit includes a timer that stands by for a predetermined period of time after at least one of overcurrent and overheat is detected by the first comparator, the second comparator, and the third comparator. The protection control circuit forcibly turns off the first switching transistor and the second switching transistor after the timer waits for the predetermined period.

10. The semiconductor switch according to claims 1 to 9, The electromotive force generating circuit comprises: Light-emitting element; A first photodiode array includes two or more photodiodes connected in series and generating an electromotive force by receiving light emitted by the light emitting element; A second photodiode array includes two or more photodiodes connected in series and generating an electromotive force by receiving light emitted by the light emitting element; A third photodiode array includes two or more photodiodes connected in series and generating an electromotive force by receiving light emitted by the light emitting element; as well as a voltage control circuit that controls the voltage of wiring connected to the gate of the first switching transistor and the gate of the second switching transistor based on the electromotive force generated by the second photodiode column and the electromotive force generated by the third photodiode column; The electromotive force of the first photodiode column is used as a power supply voltage of the protection circuit.

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