Planar gate IGBT device and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a planar gate IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof, and the device comprises a substrate, doped regions, a gate region and P-type floating regions arranged in one-to-one correspondence with the doped regions, the gate region is located on the substrate; the doped regions are located on the substrate, located below the gate region and located at the two ends of the gate region; the doped region comprises an N + source region and a P-type body region, the N + source region is located in the P-type body region, and the surface of the N + source region, the surface of the P-type body region and the surface of the substrate are located on the same horizontal plane; the P-type floating regions are located in the substrate, located below the gate regions, located between the doped regions and located in designated regions on the sides of the corresponding P-type body regions, and the P-type floating regions are close to the P-type body regions and are not in contact with the P-type body regions. Through the structural arrangement of the device, the conduction voltage drop of the planar gate IGBT device is reduced, and the reliability and practicability of the planar gate IGBT device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a planar gate IGBT device and a manufacturing method thereof. BACKGROUND

[0002] In power system applications, planar gate IGBT (Insulated Gate Bipolar Transistor) devices are widely used in low-frequency power electronic devices such as frequency converters, motor drives, industrial controls, etc. due to their high withstand voltage and large current carrying capacity. In planar gate IGBT, the JFET resistance similar to MOSFET devices hinders the further optimization of the on-state voltage drop of the IGBT device, resulting in a problem of high on-state voltage drop of the planar gate IGBT. Then, the trench gate IGBT eliminates the JFET resistance, which significantly reduces the on-state voltage drop of the trench gate IGBT, making the trench gate IGBT a mainstream design.

[0003] However, in high-voltage IGBT applications above 3300V, the reliability risk of the trench gate IGBT is greater than that of the planar gate IGBT. This is because the bottom of the trench of the trench gate IGBT concentrates the electric field, which is more susceptible to high-voltage impact, thereby damaging the gate oxide layer and causing device damage and circuit failure. Therefore, in high-voltage planar gate IGBT applications, the high on-state voltage drop of the planar gate IGBT is an urgent problem to be solved. SUMMARY

[0004] The embodiments of the present application provide a planar gate IGBT device and a manufacturing method thereof, which solve the technical problem of high on-state voltage drop of the planar gate IGBT in high-voltage planar gate IGBT applications in the prior art, achieve the technical effects of reducing the on-state voltage drop of the planar gate IGBT device, optimizing the trade-off between the on-state voltage drop and the blocking voltage of the high-voltage planar gate IGBT, and improving the reliability and practicality of the planar gate IBGT device.

[0005] In a first aspect, the embodiments of the present application provide a planar gate IGBT device, comprising: a substrate, a doped region and a gate region, and a P-type floating region corresponding to the doped region one by one. The gate region is located above the substrate. The doped region is located on the substrate and below the gate region and at both ends of the gate region; the doped region comprises: an N+ source region and a P-type body region, the N+ source region is located in the P-type body region, the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located on the same horizontal plane. The P-type floating region is located in the substrate, under the gate region, between the doped regions, and in the designated area beside the corresponding P-type body region, and is close to the P-type body region and not in contact with the P-type body region, so as to realize low on-state voltage drop of the planar gate IGBT device.

[0006] Optionally, the gate region comprises a gate oxide layer, a thick oxide layer, and a gate polysilicon layer. The gate oxide layer and the thick oxide layer are located on the surface of the substrate, and the gate oxide layer is located on both sides of the thick oxide layer. The gate polysilicon layer is located on the gate oxide layer and the thick oxide layer. The gate polysilicon layer is in a curved shape with a groove, and the groove of the gate polysilicon layer covers the thick oxide layer.

[0007] Optionally, the horizontal area of the designated area is the area between the adjacent side of the P-type body region and the designated side of the thick oxide layer, wherein the adjacent side of the P-type body region is one side of the P-type body region adjacent to another doped region, and the designated side of the thick oxide layer is the side closest to the P-type body region.

[0008] Optionally, the vertical area of the designated area is the area between the surface of the P-type body region and the bottom of the P-type body region to 15 um below.

[0009] Optionally, the doping concentration of the P-type floating region is less than the doping concentration of the P-type body region.

[0010] Optionally, further comprising an N-type carrier storage layer. The N-type carrier storage layer corresponds to the doped region one by one, the doped region is located in the N-type carrier storage layer, and the surface of the N-type carrier storage layer is located in the same horizontal plane as the surface of the substrate. In the presence of the N-type carrier storage layer, the P-type floating region is not in contact with the N-type carrier storage layer.

[0011] Optionally, further comprising an emitter metal layer, the emitter metal layer is located on the substrate and the gate region, and covers the gate region and the doped region.

[0012] Optionally, further comprising a dielectric layer, the dielectric layer is located on the gate region and under the emitter metal layer, and covers the gate region to isolate the gate region and the emitter metal layer.

[0013] Optionally, further comprising an N-type field termination layer, a P-type collector layer, and a collector metal layer. The N-type field termination layer is located below the substrate; The P-type collector layer is located below the N-type field termination layer; The collector metal layer is located below the P-type collector layer.

[0014] Based on the same inventive concept, in a second aspect, the present application also provides a manufacturing method of a planar gate IGBT device, which is used to manufacture the planar gate IGBT device as described in the first aspect, and the method comprises: forming a gate region above a substrate; forming the doped regions on the substrate and below the gate region, the doped regions being located at both ends of the gate region; the doped regions comprise: an N+ source region and a P-type body region, the N+ source region being located within the P-type body region, the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate being located at the same level; forming the P-type floating region in the substrate and below the gate region, the P-type floating region also being located between the doped regions and in a specified area beside the corresponding P-type body region, the P-type floating region being close to the P-type body region and not in contact with the P-type body region, so as to achieve a low on-state voltage drop of the planar gate IGBT device.

[0015] The one or more technical solutions in the embodiments of the present application have at least the following technical effects or advantages: In the planar gate IGBT device structure of the embodiments of the present application, the P-type floating region is arranged in a specified area beside the P-type body region of each doped region located on the substrate and below the gate region. In this way, the junction curvature of the P-type body region and the electric field intensity below the gate oxide layer of the silicon surface of the substrate (especially at the step where the thick oxide layer and the gate oxide layer meet) are significantly reduced, the front carrier concentration of the planar gate IGBT device is greatly improved, the on-state voltage drop of the planar gate IGBT device is reduced, and the blocking voltage is not sacrificed at the same time. Through the arrangement of the P-type floating region, the trade-off ability between the on-state voltage drop and the blocking voltage of the high-voltage planar gate IGBT is also optimized, and the reliability and practicability of the planar gate IGBT device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The detailed description is made with reference to the accompanying drawings. Figure 1 The structure schematic diagram of the planar gate IGBT device in the embodiments of the present application is shown; Figure 2A curve diagram showing the cell width and saturation voltage of the comparative device in the embodiment of the present application is shown; Figure 3 A curve diagram showing the structure depth and front carrier concentration of the planar gate IGBT device in the embodiment of the present application is shown; Figure 4 A curve diagram showing the voltage and current between the collector and the emitter of the planar gate IGBT device in the embodiment of the present application is shown; Figure 5 A structure diagram showing the implantation of the P-type floating region on the substrate in the embodiment of the present application is shown; Figure 6 A structure diagram showing the formation of the P-type floating region on the substrate in the embodiment of the present application is shown; Figure 7 A structure diagram showing the formation of the thick oxide layer and the implantation of the N-type carrier storage layer in the embodiment of the present application is shown; Figure 8 A structure diagram showing the thermal growth of the gate oxide layer after the thick oxide layer and the formation of the gate polysilicon in the embodiment of the present application is shown; Figure 9 A structure diagram showing the formation of the P-type body region, the N+ source region and the emitter metal layer in the embodiment of the present application is shown; Figure 10 A step flow diagram showing the manufacturing method of the planar gate IGBT device in the embodiment of the present application is shown; In the drawings, 110, substrate; 120, doped region; 130, gate region; 140, N-type carrier storage layer; 150, P-type floating region; 160, emitter metal layer; 170, N-type field termination layer; 180, P-type collector layer; 190, collector metal layer; 111, dielectric layer; 121, N+ source region; 122, P-type body region; 131, gate oxide layer; 132, gate polysilicon; 133, thick oxide layer. DETAILED DESCRIPTION

[0017] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0018] Embodiment One The first embodiment of the present application provides a planar gate IGBT device, as shown in FIG. 1, which comprises a substrate 110, a doped region 120, a gate region 130, an N-type carrier storage layer 140, a P-type floating region 150, an emitter metal layer 160, an N-type field termination layer 170, a P-type collector layer 180, a collector metal layer 190 and a dielectric layer 111. Figure 1As shown, the planar gate IGBT device includes: a substrate 110, a doped region 120 and a gate region 130, and a P-type floating region 150 arranged one-to-one corresponding to the doped region 120. The gate region 130 is located above the substrate 110. The doped region 120 is located on the substrate 110 and below the gate region 130, and at both ends of the gate region 130. The doped region 120 includes: an N+ source region 121 and a P-type body region 122. The N+ source region 121 is located within the P-type body region 122, and the surface of the N+ source region 121, the surface of the P-type body region 122 and the surface of the substrate 110 are located at the same level.

[0019] The P-type floating region 150 is located within the substrate 110, below the gate region 130, between the doped regions 120, and in a designated area corresponding to the side of the P-type body region 122. The P-type floating region 150 is close to the P-type body region 122 and is not in contact with the P-type body region 122, so as to realize low on-state voltage drop of the planar gate IGBT device.

[0020] It should be noted that the planar gate IGBT device of the present embodiment is particularly suitable for high-voltage applications, i.e. high-voltage IGBT applications above 3300V, and can also be used in low-voltage applications. The planar gate IGBT device of the present embodiment uses N-type single crystal silicon material as the material of the substrate 110, which serves as the drift region of the IGBT device. The substrate 110 is an N-type lightly doped substrate. The N+ source region 121 is an N-type heavily doped source region. The shape of the P-type floating region 150 is not limited and can be set according to actual needs. For example, the P-type floating region 150 can be point-shaped or square-shaped.

[0021] In the planar gate IGBT device structure of the present embodiment, the P-type floating region 150 is arranged in a designated area corresponding to the side of the P-type body region 122 of each doped region 120 located on the substrate 110 and below the gate region 130. This significantly reduces the junction curvature of the P-type body region 122 and the electric field intensity below the gate oxide layer on the surface of the silicon substrate 110, greatly increases the front surface carrier concentration of the planar gate IGBT device, reduces the on-state voltage drop of the planar gate IGBT device, and does not sacrifice the blocking voltage. By arranging the P-type floating region 150, the trade-off between the on-state voltage drop and the blocking voltage of the high-voltage planar gate IGBT is also optimized, and the reliability and practicability of the planar gate IGBT device are improved.

[0022] Next, the structure of the planar gate IGBT device of the present embodiment will be described in detail. Figure 1 The structure of the planar gate IGBT device of the present embodiment will be described in detail. The gate region 130 includes a gate oxide layer 131, gate polysilicon 132, and a thick oxide layer 133. The gate oxide layer 131 and the thick oxide layer 133 are located on the surface of the substrate, with the gate oxide layer 131 located on both sides of the thick oxide layer 133. The gate polysilicon 132 is located above the gate oxide layer 131 and the thick oxide layer 133. The gate polysilicon 132 is curved with a groove, and the groove of the gate polysilicon 132 covers the thick oxide layer 133.

[0023] Specifically, the gate oxide layer 131 and the thick oxide layer 133 are both layers formed of oxides, and the thick oxide layer 133 includes a field oxide layer and a gate oxide layer. The gate oxide layer 131 is a single-pass gate oxide layer. The arrangement of the gate oxide layer 131 and the thick oxide layer 133 forms a thin-thick oxide layer.

[0024] The doping regions 120 are located at both ends of the gate region 130. Figure 1 As shown, the doped region 120 on the left is located at the left end of the gate region 130, and the doped region 120 on the right is located at the right end of the gate region 130. Each end of the gate region 130 (i.e., each end of the gate oxide layer 131 and the gate polysilicon 132 of the gate region 130) covers a portion of the N+ source region 121 and the P-type body region 122 of the corresponding doped region 120. For example, the left end of the gate region 130 covers a portion of the N+ source region 121 and the P-type body region 122 of the doped region 120 on the left. Similarly, the right end of the gate region 130 covers a portion of the N+ source region 121 and the P-type body region 122 of the doped region 120 on the right.

[0025] The gate polysilicon 132 is made of polysilicon, and the gate oxide layer 131 and the thick oxygen layer 133 are made of silicon dioxide. The gate polysilicon 132 is shaped like a "hat" in the gate oxide layer 131, that is, it is curved with a groove. Especially in high-voltage applications, this shape of the gate polysilicon 132 has the effect of reducing the Miller capacitance, thereby reducing switching losses. The thick oxygen layer can withstand higher electric fields, ensuring the life of the gate oxide layer 131 under high-voltage conditions, making the device more reliable and having voltage resistance and other effects. The groove formed by the gate polysilicon 132 covers the thick oxygen layer 133.

[0026] A P-type floating region 150 is provided for each doped region 120. The P-type floating region 150 is located between the doped regions 120 and in a designated area lateral to the corresponding P-type body region 122. The P-type floating region 150 is adjacent to the P-type body region 122 but does not contact the P-type body region 122. A designated area of ​​the P-type floating region 150 is provided for the P-type body region 122 of each doped region 120. The horizontal area of ​​the designated area of ​​the P-type body region 122 (i.e., the designated area of ​​the P-type floating region 150 corresponding to the P-type body region 122) is the area between the adjacent side of the P-type body region 122 and the designated side of the thick oxide layer 133. The adjacent side of the P-type body region 122 is the side of the P-type body region 122 adjacent to the P-type body region 122 of another doped region 120. The designated side of the thick oxide layer 133 is the side of the thick oxide layer 133 closest to the P-type body region 122. The vertical region of the designated area is the region between the surface of the P-type body region 122 and the bottom of the P-type body region 122 to 15 μm below.

[0027] Specifically, in Figure 1 In the figure, for the P-type body region 122 of the left doped region 120, the designated area of ​​the P-type body region 122 (i.e., the designated area of ​​the P-type floating region 150 corresponding to the left P-type body region 122) is the horizontal area between the adjacent side of the left P-type body region 122 and the designated side of the thick oxide layer 133. The adjacent side of the left P-type body region 122 is the side of the left P-type body region 122 adjacent to the P-type body region 122 of the right doped region 120, i.e., the right side of the left P-type body region 122. The designated side of the thick oxide layer 133 is the side of the thick oxide layer 133 closest to the left P-type body region 122, i.e., the left side of the thick oxide layer 133. Similarly, for the P-type body region 122 of the right doped region 120, the designated area of ​​the P-type body region 122 (i.e., the designated area of ​​the right P-type body region 122 corresponding to the P-type floating region 150) is the horizontal area between the adjacent side of the right P-type body region 122 and the designated side of the thick oxide layer 133. The adjacent side of the right P-type body region 122 is the side of the right P-type body region 122 adjacent to the P-type body region 122 of the left doped region 120, i.e., the left side of the right P-type body region 122. The designated side of the thick oxide layer 133 is the side of the thick oxide layer 133 closest to the right P-type body region 122, i.e., the right side of the thick oxide layer 133.

[0028] The vertical area of ​​the designated area of ​​the P-type body region 122 of the doped region 120 on the left is the area between the surface of the P-type body region 122 on the left and the bottom of the P-type body region 122 on the left to 15um or 10um below. The boundary between the bottom of the P-type body region 122 on the left and 15um or 10um below is the boundary of the bottom of the P-type body region 122 on the left, which is 15um or 10um apart in the vertical direction toward the substrate 110. Similarly, the vertical area of ​​the designated area of ​​the P-type body region 122 of the doped region 120 on the right is the area between the surface of the P-type body region 122 on the right and the bottom of the P-type body region 122 on the right, which is 15um or 10um apart in the vertical direction toward the substrate 110.

[0029] By limiting the position of the P-type floating region 150 corresponding to the P-type body region 122 of each doped region 120, the P-type floating region 150 is positioned as close as possible to the corresponding P-type body region 122 without contacting the P-type body region 122. The P-type floating region 150 reduces the junction curvature of the P-type body region 122 and the electric field strength below the gate oxide layer on the surface of the silicon substrate 110 (particularly at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), thereby increasing the front-side carrier concentration of the planar gate IGBT device and reducing the on-state voltage drop of the planar gate IGBT device.

[0030] In addition, the doping concentration of the P-type floating region 150 is lower than the doping concentration of the P-type body region 122 to achieve a low on-state voltage drop of the device. The doping concentration of the P-type floating region 150 cannot be greater than the doping concentration of the P-type body region 122. Although increasing the doping concentration of the P-type floating region 150 will better reduce the electric field, that is, the blocking voltage will be higher; it will introduce the problem of a rapid increase in the on-state voltage drop. The increase in the on-state voltage drop is because the doping concentration of the P-type floating region 150 increases, which narrows the electron current path. Therefore, the doping concentration of the P-type floating region 150 should not be set too high.

[0031] The planar gate IGBT device of this embodiment further includes an N-type carrier storage layer 140. The N-type carrier storage layer 140 corresponds one-to-one with the doped region 120. The doped region 120 is located within the N-type carrier storage layer 140. The surface of the N-type carrier storage layer 140 is coplanar with the surface of the substrate 110. In the presence of the N-type carrier storage layer 140, the P-type floating region 150 is not in contact with the N-type carrier storage layer 140.

[0032] Specifically, if Figure 1As shown, the left doped region 120 is located in the left N-type carrier storage layer 140, and the right doped region 120 is located in the right N-type carrier storage layer 140. The surface of the N-type carrier storage layer 140 is at the same level as the surface of the substrate 110. In the presence of the N-type carrier storage layer 140, in the specified region of the P-type body region 122 of each doped region 120, the P-type floating region 150 does not contact the N-type carrier storage layer 140, i.e. the P-type floating region 150 does not locate in the N-type carrier storage layer 140, to avoid the P-type floating region 150 and the N-type carrier storage layer 140 forming a PN junction, and thus avoid introducing a PNP parasitic tube on the electron and hole paths, i.e. avoid the P-type floating region 150 + N-type carrier storage layer 140 + P-type body region 122 forming a PNP parasitic tube. In this way, by setting the P-type floating region 150, the peak electric field at the junction curvature of the P-type body region 122 and the gate oxide layer below the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet) is reduced, the impact of the N-type carrier storage layer 140 on the withstand voltage is reduced, the margin of the doping concentration of the N-type carrier storage layer 140 is improved, and the on-state voltage drop of the planar gate IGBT device is significantly reduced. Moreover, the combination of the P-type floating region 150 and the N-type carrier storage layer 140 makes the planar gate IGBT device more suitable for high-voltage IGBT applications, improves the reliability and practicability of the planar gate IGBT device in high-voltage applications, and also improves the margin of the doping concentration of the N-type carrier storage layer 140. The increase of the margin of the doping concentration of the N-type carrier storage layer 140 can reduce the on-state voltage drop without increasing the off-state loss.

[0033] The planar gate IGBT device of the embodiment further comprises an emitter metal layer 160. The emitter metal layer 160 is located above the substrate 110 and the gate region 130, and the emitter metal layer 160 covers the gate region 130 and the doped region 120. The material of the emitter metal layer 160 includes but is not limited to aluminum, copper, gold.

[0034] The planar gate IGBT device of the embodiment further comprises a dielectric layer 111. The dielectric layer 111 is located on the gate region 130 and below the emitter metal layer 160, and the dielectric layer 111 covers the gate region 130, i.e. the dielectric layer 111 covers the gate oxide layer 131 and the gate polysilicon 132 of the gate region 130, to isolate the gate region 130 and the emitter metal layer 160. The material of the dielectric layer 111 is a boron-doped, phosphorus-doped oxide layer. The dielectric layer 111 is an ILD (InterLayer Dielectric) dielectric layer, which plays an electrical isolation role, and also improves signal transmission speed and reduces power consumption, and provides physical support for the emitter metal layer 160 to ensure structural stability.

[0035] The planar gate IGBT device of the embodiment further comprises an N-type field termination layer 170, a P-type collector layer 180, and a collector metal layer 190. The N-type field termination layer 170 is located below the substrate 110, the P-type collector layer 180 is located below the N-type field termination layer 170, and the collector metal layer 190 is located below the P-type collector layer 180. The P-type collector layer 180 is a P-type heavily doped collector layer. The material of the collector metal layer 190 includes but is not limited to aluminum, titanium, nickel, and silver.

[0036] The structural principle of the planar gate IGBT device of the embodiment is as follows: The P-type floating region 150 is arranged in a designated area of each P-type body region 122, i.e. the P-type floating region 150 is arranged in a lateral direction of the curvature of the PN junction formed by each P-type body region 122, and the doping concentration of the P-type floating region 150 is smaller than that of the P-type body region 122. The P-type floating region 150 is not in contact with the N-type carrier storage layer 140, and the P-type floating region 150 is capacitively coupled with the substrate 110 around to generate an adaptive potential. The potential center will attract a part of the potential lines at the PN junction curvature of the P-type body region 122 and below the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), thereby reducing the peak electric field at the PN junction curvature of the P-type body region 122 and below the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), and reducing the impact of the N-type carrier storage layer 140 on the withstand voltage. This effectively moderates the electric field intensity at the PN junction curvature of the P-type body region 122 and below the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), improves the margin of the doping concentration of the N-type carrier storage layer 140 of the planar gate IGBT device, thereby increasing the front carrier concentration of the planar gate IGBT device, achieving the effect of reducing the on-state voltage drop, and enhancing the reliability and practicability of the planar gate IGBT device, and being compatible with the existing process.

[0037] In addition, the P-type floating region 150 is floating and located in a lateral direction of the P-type body region 122, and does not introduce a PNP parasitic tube below the emitter metal layer 160. The existence of the PNP parasitic tube will hinder the removal of holes when the IGBT device is turned off. Therefore, the structure of the planar gate IGBT device of the embodiment does not affect the turn-off capability.

[0038] The P-type floating region 150 is floating and located near the curvature of the PN junction of the P-type body region 122. This prevents the introduction of a PNP parasitic transistor formed by the P-type floating region 150, the N-type carrier storage layer 140, and the P-type body region 122 on the surface of the silicon substrate 110. This PNP parasitic transistor would enhance the JFET effect of the device and significantly increase the on-state voltage drop. Therefore, the P-type floating region 150 in the planar gate IGBT device structure of this embodiment has essentially no effect on the increase in the on-state voltage drop.

[0039] The following compares and analyzes the planar gate IGBT device of this embodiment (i.e., a planar gate IGBT device with a P-type floating region 150 + an N-type carrier storage layer 140) with a comparative planar gate IGBT device. The comparative device is a planar gate IGBT device with an N-type carrier storage layer 140 but without a P-type floating region 150. The remaining structure of the comparative device is identical to that of the planar gate IGBT device of this embodiment.

[0040] In power system applications, the operating frequency of planar gate IGBT devices is only a few hundred hertz, requiring the planar gate IGBT device chip to have a lower on-state voltage drop. In power systems, the inevitable parasitic inductance causes the planar gate IGBT device to have a large voltage overshoot during large current shutdown, which requires the planar gate IGBT device chip to have a high blocking voltage capability, and it is necessary to use a high resistivity substrate 110 to prepare the IGBT device. In order to pursue a lower on-state voltage drop, the planar gate IGBT device in high-voltage applications will use a larger IGBT device cell width with a carrier storage layer design compared to the device. Although the larger cell width can reduce the JFET resistance, it can reduce the device's on-state voltage drop to a certain extent. However, if Figure 2 The relationship between the cell width and saturation voltage of the comparative device is shown in the graph. When the cell width Pitch exceeds 70μm, the device's effect of reducing the on-state voltage drop tends to saturate, that is, the saturation voltage Vcesat of the device shown on the vertical axis approaches saturation. And the larger the cell width, the larger the chip area required. However, the concentration of the carrier storage layer exceeds 1e16cm -3 When the gate oxide layer is etched, the junction curvature of the P-type body region 122 and the local electric field concentration below the gate oxide layer on the surface of the silicon substrate 110 will be caused, thereby reducing the blocking voltage of the IGBT device.

[0041] like Figure 3 As shown, the solid line represents the planar gate IGBT device of this embodiment, and the dotted line represents the comparative device. Figure 3 The horizontal axis represents the structural depth of the substrate 110 of the device, and the vertical axis represents the front carrier concentration of the device. At the same structural depth of the device, it can be seen that the front carrier concentration of the device of this embodiment is greater than the front carrier concentration of the comparative device. Figure 3 In FIG. 1 , the inflection point of the curve similar to a trough represents the PN junction formed by the P-type body region 122.Figure 4 As shown, the solid line represents the planar gate IGBT device of this embodiment, and the dotted line represents the comparative device. Figure 4 The horizontal axis represents the voltage Vce‌ between the collector and emitter of the device, and the vertical axis represents the current Ic of the device at the corresponding voltage. At the same current, the voltage of the device of this embodiment is smaller than that of the comparative device.

[0042] These explanations demonstrate that, through the device structure of this embodiment, by introducing a P-type floating region 150 with a lower doping concentration than the P-type body region 122 at the lateral position of the junction bend of the P-type body region 122, the junction curvature of the P-type body region 122 and the electric field strength beneath the gate oxide layer on the surface of the silicon substrate 110 are effectively reduced. This allows the use of an N-type carrier storage layer 140 with a higher doping concentration, further increasing the front-side carrier concentration of the planar gate IGBT device and thereby reducing the on-state voltage drop. Furthermore, under the same cell size, the device structure of this embodiment can significantly increase the N-type carrier concentration of the N-type carrier storage layer 140 and reduce the drop in the blocking voltage of the IGBT device, thereby optimizing the trade-off between the on-state voltage drop and the blocking voltage of the planar gate IGBT device in high-voltage applications and achieving a low on-state voltage drop.

[0043] Next, combine Figure 1 The following describes the manufacturing process of the planar gate IGBT device of this embodiment: like Figure 5 As shown, the implantation of the P-type floating region 150 is completed on the substrate 110. The material of the P-type floating region 150 is boron B or boron fluoride BF2 or a combination of B and BF2. The implantation energy range of the P-type floating region 150 material is 20~2000KeV, and the implantation dose range is 1e12~1e13cm -2 .

[0044] like Figure 6 As shown, the substrate 110 is epitaxially grown by a thermal process, and the epitaxial layer ( Figure 6 The doping concentration of region A) is consistent with the doping concentration of substrate 110. The doping concentration of epitaxial layer A can also be inconsistent with the doping concentration of substrate 110 or set according to actual needs. The thickness of the epitaxial layer grown on substrate 110 ranges from 3 to 15 μm. Simultaneously, P-type floating region 150 is pushed into a dot-like shape during the thermal process, thereby forming P-type floating region 150.

[0045] like Figure 7As shown, a thick oxide layer is grown on the substrate 110 and in the middle of the cell, forming a thick oxide layer 133. The thickness of the thick oxide layer 133 ranges from 1.2 to 3 μm. Next, the N-type carrier storage layer 140 is implanted. Phosphorus ion implantation can be used to form the N-type carrier storage layer 140, with an implantation energy range of 20 to 2500 KeV and an implantation dose range of 1e12 to 2e13 cm -2 .like Figure 8 As shown, a gate oxide layer 131 is thermally grown with a thickness ranging from 80 nm to 120 nm. An N-type high doping concentration ranging from 1e19 to 1e21 cm -3 The polysilicon is etched to form a gate polysilicon 132 having a groove shape.

[0046] like Figure 9 As shown, in the N-type carrier storage layer 140, the P-type body region 122 and the N+ source region 121 are implanted and the well is pushed. Then, the dielectric layer 111 is deposited, and after the contact hole etching is completed, the metal is deposited to form the emitter metal layer 160 to obtain the emitter. Finally, the conventional substrate 110 bottom surface thinning, implantation, annealing and metal deposition process are completed, that is, the N-type field stop layer 170 is formed under the substrate 110, the P-type collector layer 180 is formed under the N-type field stop layer 170, and the collector metal layer 190 is formed under the P-type collector layer 180 to achieve the following. Figure 1 The complete structure shown.

[0047] While maintaining compatibility with existing processes, the introduction of a P-type floating region 150 with a lower doping concentration than the P-type body region 122, lateral to the junction bend of the P-type body region 122, effectively mitigates the junction curvature of the P-type body region 122 and the electric field strength beneath the gate oxide layer on the surface of the silicon substrate 110. This also increases the margin of the planar-gate IGBT device with respect to the carrier concentration of the N-type carrier storage layer 140, thereby increasing the front-side carrier concentration of the planar-gate IGBT device and reducing the on-state voltage drop. The structure of the planar-gate IGBT device of this embodiment can be achieved without complex manufacturing processes, thereby achieving the goal of reducing costs and increasing efficiency.

[0048] Example 2 Based on the same inventive concept, the second embodiment of the present invention further provides a method for manufacturing a planar gate IGBT device, which is used to manufacture the planar gate IGBT device shown in the first embodiment. Figure 10 As shown, the production method includes: S201, forming a gate region on a substrate; S202, forming the doped region on the substrate and under the gate region, the doped region is located at both ends of the gate region; the doped region comprises: N+ source region and P-type body region, the N+ source region is located in the P-type body region, the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located in the same horizontal plane; S203, forming the P-type floating region in the substrate and under the gate region, the P-type floating region is also located between the doped regions and in the specified area corresponding to the side of the P-type body region, the P-type floating region is close to the P-type body region and is not in contact with the P-type body region, so as to realize the low on-state voltage drop of the planar gate IGBT device.

[0049] Since the manufacturing method of the planar gate IGBT device introduced in the embodiment is the manufacturing method adopted for the planar gate IGBT device in Embodiment One of the present application, the specific implementation of the manufacturing method of the planar gate IGBT device of the present embodiment and its various forms can be understood by those skilled in the art based on the planar gate IGBT device introduced in Embodiment One of the present application, so the manufacturing method of the planar gate IGBT device will not be introduced in detail here. As long as those skilled in the art implement the manufacturing method adopted for the planar gate IGBT device in Embodiment One of the present application, it belongs to the scope of the present application.

[0050] Those skilled in the art will appreciate that although preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0051] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. A planar gate IGBT device, characterized in that: include: A substrate, a doped region and a gate region, and a P-type floating region arranged in one-to-one correspondence with the doped region; The gate region is located on the substrate; The doping region is located on the substrate, below the gate region, and at both ends of the gate region; The doped region includes: an N+ source region and a P-type body region, the N+ source region is located within the P-type body region, and the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located in the same horizontal plane; The P-type floating region is located in the substrate, below the gate region, between the doped regions, and in a designated area on the side of the corresponding P-type body region. The P-type floating region is close to the P-type body region and is non-contacting with the P-type body region to achieve a low on-state voltage drop of the planar gate IGBT device.

2. The planar gate IGBT device according to claim 1, wherein: The gate region includes: a gate oxide layer, a thick oxygen layer and gate polysilicon; The gate oxide layer and the thick oxide layer are located on the surface of the substrate, and the gate oxide layer is located on both sides of the thick oxide layer; The gate polysilicon is located on the gate oxide layer and the thick oxygen layer; The gate polysilicon is in a curved shape with a groove, and the groove of the gate polysilicon covers the thick oxygen layer.

3. The planar gate IGBT device according to claim 2, wherein: The horizontal area of ​​the designated area is the area between the adjacent side of the P-type body region and the designated side of the thick oxide layer, wherein the adjacent side of the P-type body region is the side of the P-type body region adjacent to another doped region of the P-type body region, and the designated side of the thick oxide layer is the side of the thick oxide layer closest to the P-type body region.

4. The planar gate IGBT device according to claim 3, wherein: The vertical region of the designated area is the region between the surface of the P-type body region and the bottom of the P-type body region to 15 um below.

5. The planar gate IGBT device according to claim 1, wherein: The doping concentration of the P-type floating region is lower than the doping concentration of the P-type body region.

6. The planar gate IGBT device according to any one of claims 1 to 5, characterized in that: Also includes: N-type carrier storage layer; The N-type carrier storage layer corresponds to the doped region in a one-to-one manner, the doped region is located in the N-type carrier storage layer, and the surface of the N-type carrier storage layer and the surface of the substrate are located at the same horizontal plane; Wherein, in the case where the N-type carrier storage layer exists, the P-type floating region is not in contact with the N-type carrier storage layer.

7. The planar gate IGBT device according to claim 1, wherein: Also includes: Emitter metal layer; the emitter metal layer is located on the substrate and the gate region, and the emitter metal layer covers the gate region and the doped region.

8. The planar gate IGBT device according to claim 7, wherein: Also includes: A dielectric layer is located on the gate region and below the emitter metal layer. The dielectric layer covers the gate region to isolate the gate region from the emitter metal layer.

9. The planar gate IGBT device according to claim 1, wherein: Also includes: N-type field stop layer, P-type collector layer and collector metal layer; The N-type field stop layer is located below the substrate; The P-type collector layer is located below the N-type field stop layer; The collector metal layer is located below the P-type collector layer.

10. A method for manufacturing a planar gate IGBT device, characterized in that: A method for manufacturing a planar gate IGBT device according to any one of claims 1 to 9, comprising: forming a gate region on the substrate; forming the doped region on the substrate and below the gate region, the doped region being located at both ends of the gate region; the doped region comprising: an N+ source region and a P-type body region, the N+ source region being located within the P-type body region, and the surface of the N+ source region, the surface of the P-type body region, and the surface of the substrate being located at the same horizontal plane; The P-type floating region is formed in the substrate and below the gate region. The P-type floating region is also located between the doped regions and in a designated area on the side of the corresponding P-type body region. The P-type floating region is close to the P-type body region and is non-contacting with the P-type body region to achieve a low on-state voltage drop of the planar gate IGBT device.

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