High-K low-K composite dielectric shield gate power device and preparation method thereof

Abstract

The invention relates to the technical field of power semiconductors, and provides a high-K and low-K composite dielectric shield gate power device and a preparation method thereof, the voltage endurance capability of the device and the compatibility of switching frequency are remarkably improved through the partition optimization design of a dielectric layer, the interface state density of a dielectric system is effectively reduced through the innovative design of a discontinuous interface layer, and the performance of the device is improved. And due to the unique low-K dielectric distribution scheme, the stray capacitance of the grid electrode-shielding electrode is reduced by more than 40%, and the high-frequency switching loss is remarkably reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and particularly relates to a high-K / low-K composite dielectric shielded gate power device and a preparation method thereof. BACKGROUND

[0002] In a power semiconductor device, a shielded gate trench structure significantly improves the electric field distribution and switching characteristics of a traditional MOSFET by introducing a grounded shield electrode. With the development of power electronic systems towards high voltage and high frequency, the traditional single dielectric scheme faces fundamental limitations: high dielectric constant (high-K) dielectric can enhance the electric field regulation but leads to an increase in parasitic capacitance, while low dielectric constant (low-K) dielectric reduces the capacitance but weakens the withstand voltage capability. This contradiction is particularly prominent in advanced devices such as super-junction structures and wide-bandgap semiconductors.

[0003] The introduction of high-K dielectric (such as HfO2, Al2O3) in the SGT structure can effectively improve the electric field regulation capability, but it is accompanied by three major problems: the significant increase in gate capacitance leads to an increase in switching loss; the high-temperature deposition process is not compatible with the back-end process; and the high-K / semiconductor interface defects cause reliability risks. Existing solutions such as interface passivation layers partially improve reliability, but sacrifice the dielectric performance advantage.

[0004] To meet the high-frequency application requirements of 5G base stations, electric vehicles, and other applications, low-K dielectric (such as fluorine-doped SiO2, porous organosilicate) has become a key path to reduce parasitic capacitance. However, due to insufficient mechanical strength, it is prone to deformation or cracking under high voltage, leading to electric field concentration and carrier multiplication, ultimately causing dielectric breakdown. Poor thermal stability limits the process window, and the use of low-K dielectric alone can cause the device's withstand voltage performance to deteriorate sharply.

[0005] The integration of high-K and low-K dielectric faces three challenges: interface band mismatch leading to charge accumulation; thermal expansion coefficient difference causing film stress; and process temperature window mutual restriction. Existing patent technologies either adopt a simple stacked structure leading to performance compromise, or achieve limited improvement through complex processes, and none of them can fundamentally solve the problem of synergistic optimization of the dielectric system. SUMMARY

[0006] The application provides a high-K / low-K composite dielectric shielded gate power device and a preparation method thereof to solve or partially solve the problems raised in the background art.

[0007] The application provides a high-K low-K composite dielectric shield gate power device, which comprises an N-type drain region, an N-type epitaxial layer above the N-type drain region, and further comprises: a groove which penetrates through a P-type well region layer and extends to the inside of the N-type epitaxial layer; a high-K dielectric layer which is in contact with the lower part and the bottom end of the inner side of the groove, the dielectric constant of the high-K dielectric layer is greater than or equal to 10, and the thickness is 10-20 nm; a nitrided interface layer which covers the top end of the high-K dielectric layer, the thickness is 1-2 nm, and the coverage is less than or equal to 60 %; a low-K dielectric layer which is in contact with the upper part of the inner side of the groove and the nitrided interface layer, the dielectric constant of the low-K dielectric layer is less than or equal to 3.0, and the thickness is 50-200 nm; a shield gate electrode which is filled in the lower part of the groove and is composed of doped polysilicon and is in direct contact with the high-K low-K composite dielectric layer; an HDP isolation layer which covers the top end of the shield gate electrode and is in contact with the side of the low-K dielectric layer, and the thickness is 500±50 nm; a gate oxide layer which covers the upper surface of the HDP isolation layer and the upper edge of the low-K dielectric layer and extends to the top of the inner sidewall of the groove, and the thickness is 5-15 nm; a gate electrode which is above the shield gate electrode and is composed of polysilicon, is insulated from the shield gate electrode through the HDP isolation layer and the gate oxide layer, and is insulated from the low-K dielectric layer through the gate oxide layer; a P-type well region layer which is above the N-type epitaxial layer and surrounds the upper part of the groove; an N+ source region layer which is above the P-type well region layer and is adjacent to the top of the groove; an interlayer dielectric layer which covers the N+ source region layer and the top of the groove, and a contact hole is formed in the interlayer dielectric layer; and a metal interconnection layer which connects the source region and the gate electrode through the contact hole.

[0008] Preferably, the coverage area of the high-K dielectric layer accounts for 30 %-50 % of the inner surface area of the groove, and the thickness at the bottom of the groove is 1.5-3 times of the sidewall thickness.

[0009] Preferably, the porosity of the low-K dielectric layer is 30 %-50 %, and the ratio of the dielectric constants of the low-K dielectric layer and the high-K dielectric layer is less than or equal to 0.3.

[0010] Preferably, the nitrided interface layer is discontinuously distributed in island shape, the size of a single nitrided region is 3-5 nm, and the interval is 2-3 nm.

[0011] Preferably, the HDP isolation layer is formed by three deposition-etching cycles, the thickness of each deposition is 200 nm, and 50 nm is removed by etching.

[0012] Preferably, the gate oxide layer is aluminum oxide, the thickness is 5-10 nm, and the dielectric constant is greater than or equal to 9.

[0013] Preferably, the P-type well region is not in contact with the high-K dielectric layer, and the electric field coupling is realized through lateral expansion of the depletion region.

[0014] The application also provides a preparation method of the high-K / low-K composite dielectric shield gate power device.

[0015] S1. Etching a trench with a depth-width ratio of ≥2:1 on an N-type epitaxial layer;

[0016] S2. Selectively depositing a high-K dielectric layer at the lower part of the trench by means of inclined mask ALD;

[0017] S3. Forming a discontinuous nitridation interface layer by means of pulse plasma treatment;

[0018] S4. Depositing a fluorine-doped low-K dielectric layer by means of low-temperature PECVD;

[0019] S5. Sequentially filling a shield gate electrode, an HDP isolation layer and a gate electrode.

[0020] Preferably, in step S2, the number of cycles of ALD deposition is 200±5 at the bottom and 100±5 at the sidewall, and the thickness control accuracy is ±0.5 nm.

[0021] Preferably, in step S4, the gas ratio of SiH4 / CF4 / N2O is 50 / 150 / 20 sccm, and the deposition temperature is ≤250°C.

[0022] Compared with the prior art, the application has the following beneficial effects:

[0023] (1) The application provides a high-K / low-K composite dielectric shield gate power device structure, which significantly improves the compatibility of the withstand voltage capability and the switching frequency of the device through the partition optimization design of the dielectric layer.

[0024] (2) The application provides a high-K / low-K composite dielectric shield gate power device structure, which effectively reduces the interface state density of the dielectric system through the innovative discontinuous interface layer design, and greatly improves the device reliability.

[0025] (3) The application provides a high-K / low-K composite dielectric shield gate power device structure, which reduces the gate-shield parasitic capacitance by more than 40% through the unique low-K dielectric distribution scheme, and significantly reduces the high-frequency switching loss.

[0026] (4) The application provides a preparation process of the high-K / low-K composite dielectric shield gate power device, which adopts full low-temperature process, is compatible with the traditional SGT process, and only needs to adjust part of the dielectric deposition parameters and mask design to realize without adding additional photolithography steps.

[0027] (5) The present application provides a preparation process for a high-K / low-K composite dielectric shielded gate power device, which achieves precise regional distribution control of the dielectric layer through selective atomic layer deposition technology, with good process repeatability and high yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present application is further described below with reference to the accompanying drawings and examples.

[0029] Figure 1 This is a schematic diagram of the power device structure of this application.

[0030] Figure 2 This is a structural diagram of the hard mask deposition stage of the preparation method of this application.

[0031] Figure 3 This is a schematic diagram of the structure of the trench etching stage of the preparation method of this application.

[0032] Figure 4 This is a structural diagram of the hard mask stripping stage of the preparation method of this application.

[0033] Figure 5 This is a structural diagram of the high-K dielectric layer deposition stage of the preparation method of this application.

[0034] Figure 6 This is a structural diagram of the interface nitriding treatment stage of the preparation method of this application.

[0035] Figure 7 This is a structural diagram of the low-K dielectric layer deposition stage of the preparation method of this application.

[0036] Figure 8 This is a structural diagram of the shielding gate electrode formation stage of the preparation method of this application.

[0037] Figure 9 This is a structural diagram of the HDP medium deposition stage of the preparation method of this application.

[0038] Figure 10 This is a structural diagram of the trench oxide layer etching stage of the preparation method of this application.

[0039] Figure 11 This is a schematic structural diagram of the gate oxide layer formation stage of the preparation method of this application.

[0040] Figure 12 This is a schematic diagram of the structure of the gate formation stage of the preparation method of this application.

[0041] Figure 13 This is a schematic diagram of the structure of the P-well injection stage of the preparation method of this application.

[0042] Figure 14 This is a structural diagram of the low-temperature laser annealing stage of the preparation method of this application.

[0043] Figure 15 A schematic diagram of the phase structure of the source injection stage of the preparation method of the present application,

[0044] Figure 16 A schematic diagram of the phase structure of the insulating dielectric layer stage of the preparation method of the present application,

[0045] Figure 17 A schematic diagram of the phase structure of the contact hole etching stage of the preparation method of the present application,

[0046] Figure 18 A schematic diagram of the phase structure of the metallization stage of the preparation method of the present application.

[0047] In the drawings:

[0048] 1, N-type drain region, 2, N-type epitaxial layer, 3, trench, 4, high-K dielectric layer, 5, nitride interface layer, 6, low-K dielectric layer, 7, shield gate electrode, 8, HDP isolation layer, 9, gate oxide layer, 10, gate electrode, 11, P-type well region layer, 12, N+ source region layer, 13, interlayer dielectric layer, 14, contact hole, 15, metal interconnection layer. DETAILED DESCRIPTION

[0049] As used in the specification and claims, certain terminology is used to describe parts that will be apparent to those skilled in the art. It is not intended to limit the claimed application to any particular terminology. The specification and claims should not be construed as indicating a preference or limitation to any specific component name. As used in the specification and claims, the term "comprising" is to be construed as meaning "including, but not limited to." The term "substantially" means within acceptable manufacturing tolerances, which will vary from one component to another, and from one manufacturer to another.

[0050] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "horizontal", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0051] In this application, unless specifically defined otherwise, the terms "mounting", "connected", "connection", "fixed", and the like should be construed broadly and, for example, can be a fixed connection, or a detachable connection, or an integral connection; can be a mechanical connection, or an electrical connection; can be a direct connection, or an indirect connection via an intermediate medium, or a communication between the internal elements of two components. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0052] Embodiment 1

[0053] As Figure 1 shown, the present application provides 1, a high-K low-K composite dielectric shield gate power device, characterized in that, comprising an N-type drain region 1, an N-type epitaxial layer 2 located above the N-type drain region 1, further comprising:

[0054] a trench 3 which passes through the P-type well region layer 11 and extends to the inside of the N-type epitaxial layer 2;

[0055] a high-K dielectric layer 4 which is in contact with the lower part and the bottom end of the inner side of the trench 3, the dielectric constant ε of the high-K dielectric layer 4 is ≥10, the thickness is 10-20nm, and the coverage area accounts for about 50% of the inner surface area of the trench;

[0056] a nitrided interface layer 5 which covers the top end of the high-K dielectric layer 4, the thickness is 1-2nm, the distribution is discontinuous and the coverage is ≤60%, and the overlapping area ratio with the top part of the high-K dielectric layer 4 is 40%-60%;

[0057] a low-K dielectric layer 6 which is in contact with the upper part of the inner side of the trench 3 and the nitrided interface layer 5, the dielectric constant ε of the low-K dielectric layer 6 is ≤3.0, and the thickness is 50-200nm;

[0058] a shield gate electrode 7 which is filled in the lower part of the trench 3 and is composed of doped polysilicon, and is in direct contact with the composite dielectric layer composed of the high-K dielectric layer 4 and the low-K dielectric layer 6;

[0059] an HDP isolation layer 8 which covers the top end of the shield gate electrode 7 and is in contact with the side of the low-K dielectric layer 6, and the thickness is 500±50nm;

[0060] a gate oxide layer 9 which covers the upper surface of the HDP isolation layer 8 and the upper edge of the low-K dielectric layer 6, and extends to the top of the inner sidewall of the trench 3, and the thickness is 5-15nm;

[0061] a gate electrode 10 which is located above the shield gate electrode 7 and is composed of polysilicon, and is insulated from the shield gate electrode 7 through the HDP isolation layer 8 and the gate oxide layer 9, and is insulated from the low-K dielectric layer 6 through the gate oxide layer 9;

[0062] P-type well region layer 11, on top of the N-type epitaxial layer 2, and surrounding the upper part of the trench 3;

[0063] N+ source region layer 12, on top of the P-type well region layer 11, and adjacent to the top of the trench 3;

[0064] Interlayer dielectric layer 13, covering the N+ source region layer 12 and the top of the trench 3, and a contact hole 14 is formed in the interlayer dielectric layer 13;

[0065] Metal interconnection layer 15, connecting the source region and the gate electrode 10 through the contact hole.

[0066] Specifically, the coverage area of the high-K dielectric layer 4 accounts for 30%-50% of the inner surface area of the trench 3, and the thickness at the bottom of the trench 3 is 1.5-3 times the thickness of the sidewall.

[0067] Specifically, the porosity of the low-K dielectric layer 6 is 30%-50%, and the ratio of its dielectric constant to that of the high-K dielectric layer 4 is ≤0.3.

[0068] Specifically, the nitrided interface layer 5 is discontinuously distributed in island shape, with a single nitrided region having a size of 3-5 nm and a spacing of 2-3 nm.

[0069] Specifically, the HDP isolation layer 8 is formed by three deposition-etching cycles, with a deposition thickness of 200 nm each time and an etching removal of 50 nm.

[0070] Specifically, the gate oxide layer 9 is aluminum oxide (Al2O3), with a thickness of 5-10 nm and a dielectric constant ε≥9.

[0071] Specifically, the P-type well region is not in contact with the high-K dielectric layer 4, and the electric field coupling is achieved through lateral expansion of the depletion region.

[0072] Embodiment 2

[0073] Based on Embodiment 1, the present embodiment provides a preparation method of a high-K low-K composite dielectric shielded gate power device, for preparing the high-K low-K composite dielectric shielded gate power device as described in Embodiment 1, comprising the following steps:

[0074] S1. Etching a trench 3 with a depth-to-width ratio ≥2:1 on the N-type epitaxial layer 2;

[0075] S2. Selectively depositing a high-K dielectric layer 4 at the lower part of the trench 3 by inclined mask ALD;

[0076] S3. Forming a discontinuous nitrided interface layer 5 by pulse plasma treatment;

[0077] S4. Depositing a fluorine-doped low-K dielectric layer 6 by low-temperature PECVD;

[0078] S5. Fill the shield gate electrode 7, the HDP isolation layer 8 and the gate electrode 10 in sequence.

[0079] Specifically, in step S1, the specific method of etching the trench 3 with a depth-to-width ratio of ≥2:1 on the N-type epitaxial layer 2 is as follows:

[0080] like Figure 2 As shown, the hard mask is deposited: the LPCVD-Si3N4 / SiO2 composite mask is deposited. The process steps include: ① placing the silicon substrate in the LPCVD reaction chamber; ② SiH2Cl2 / NH3 = 200 / 800 sccm; ③ reaction pressure 300 mTorr; ④ temperature 780±5°C; ⑤ deposition time 12 minutes and 30 seconds; ⑥ subsequent dry oxygen oxidation at 900°C to generate 50nm SiO2;

[0081] like Figure 3 As shown, trench etching: ICP etching forms a 3μm deep trench, and the process steps include: ① main etching: SF6 / O2=80 / 20sccm, 800W ICP / 150W bias; ② over etching: CF4 / O2=60 / 20sccm, 50W bias; ③ sidewall angle control 88°±0.5°; ④ endpoint detection: OES monitoring SiF*440nm signal.

[0082] Specifically, in step S2, the specific method of selectively depositing the high-K dielectric layer 4 at the bottom of the trench 3 by tilted mask ALD is as follows:

[0083] like Figure 4 As shown, hard mask stripping: wet etching to remove the mask, the process steps include: ① 85% H3PO4 solution, 85±2°C, 16 minutes and 7 seconds; ② 5:1 BHF, 23±1°C, 45±2 seconds; ③ SC1 cleaning (NH4OH:H2O2:H2O=1:1:5);

[0084] like Figure 5 As shown, high-K dielectric layer deposition: tilted mask ALD deposition of HfO2, the process steps include: ① TDMAHf / H2O precursor, 250±1℃; ② 200 cycles (20nm) on the bottom and 100 cycles (10nm) on the sidewall; ③ the mask is tilted 45°±1°, blocking 1.2 times the width of the trench opening.

[0085] Specifically, in step S3, the specific method for forming the discontinuous nitrided interface layer 5 is as follows:

[0086] like Figure 6As shown, the selective nitridation process uses photolithography or a self-aligned process to expose only the top region of the high-K dielectric layer, followed by pulsed plasma nitridation. The process steps include: ① NH3 / N2 = 50 / 50 sccm; ② RF power 200±5W; ③ Pulse cycle: 5 seconds on / 3 seconds off, total time 20±0.5 seconds; ④ Temperature 200±2°C.

[0087] Specifically, in step S4, the specific method of depositing the fluorine-doped low-K dielectric layer 6 by low-temperature PECVD is as follows:

[0088] like Figure 7 As shown, PECVD deposited fluorine-doped SiO 2， The process steps include: ① SiH4 / CF4 / N2O = 50 / 150 / 20 sccm; ② Power 300±10W; ③ Temperature 200±2°C; ④ Deposition pressure: 2.5±0.1 Torr; ⑤ Deposition time 3 minutes and 20 seconds; ⑥ UV curing: 254nm, 300mJ / cm 2 .

[0089] Specifically, if Figure 8 As shown, the method of forming the shield gate electrode 7 is as follows:

[0090] LPCVD polysilicon deposition and etching process steps include: ① SiH4 / PH3 = 200 / 2sccm, deposition temperature: 620±3℃; deposition pressure: 200±5mTorr; ② Etching: Cl2 / HBr / O2 = 50 / 20 / 5sccm; ICP power: 400±10W; bias power: 100±5W; etching time: real-time monitoring based on OCD.

[0091] Specifically, if Figure 9 As shown, the filling method of the HDP isolation layer 8 is as follows:

[0092] The gap-filling isolation layer is formed, and the process steps include: ① SiH4 / O2 / Ar = 60 / 250 / 600sccm; ② ICP 2000W / bias power 300W; ③ deposition temperature: 350±5℃; ④ deposition pressure: 4±0.2mTorr; ⑤ 3 deposition-etching cycles (200nm+50nm); ⑥ 400℃ N2 annealing for 30 minutes.

[0093] Specifically, the gate electrode 10 is formed as follows:

[0094] like Figure 10 As shown, etching of the oxide layer in the trench: etching the oxide layer in the trench, the process steps include: ① Etching gas: CHF3 50sccm + Ar 50sccm; ② RF power: 300±10W; ③ Etching temperature: ≤100℃; ④ Etching time: according to endpoint detection;

[0095] like Figure 11 As shown, gate oxide layer formation: ALD-Al2O3 deposition, the process steps include: ① TMA / H2O precursor, 150±1℃; ② 100 cycles (10nm); ③ O2 plasma treatment (300W, 30 seconds);

[0096] like Figure 12 As shown, gate formation: polysilicon deposition and patterning, the process steps include: ① deposition: SiH4 / PH3=200 / 2sccm, deposition temperature: 620±3℃; deposition pressure: 200±5mTorr; ② etching: HBr / Cl2 / O2=50 / 20 / 5sccm.

[0097] Specifically, the preparation method further includes P-well implantation, low-temperature laser annealing, source electrode implantation, insulating dielectric layer formation, contact hole etching, and metallization.

[0098] Specifically, if Figure 13 As shown, P well injection: BF2 + Ion implantation, the process steps include: ① beam current density: ≤1μA / cm 2 ;②Energy 80keV±5keV;③Dose 5×10 13 ±5%cm -2 ; ④ Angle 7°±0.5°; ⑤ Wafer temperature 50℃.

[0099] Specifically, if Figure 14 As shown, low-temperature laser annealing: impurity activation, the process steps include: ① excimer laser (wavelength 308nm), beam uniformity: ±3%, pulse width: 20ns; ② energy density: 0.8-1.2J / cm 2 ; ③ Number of pulses: 3-5 times (overlap rate 90%); ④ Substrate temperature: 300℃ (thermal assistance to enhance activation rate).

[0100] Specifically, if Figure 15 As shown, source injection: P + Ion implantation, the process steps include: ① energy 50±1keV; ② dose 5×10 15 ±5%cm -2 ; ③ Room temperature operation.

[0101] Specifically, if Figure 16 As shown, the insulating dielectric layer: PECVD SiO2 deposition, the process steps include: ① SiH4 / N2O = 100 / 300 sccm; ② temperature 400±5°C; ③ deposition pressure: 1.5±0.1 Torr; ④ thickness 500±20nm.

[0102] Specifically, ifFigure 17 As shown, contact hole etching: RIE etching, the process steps include: ① CF4 / CHF3 / Ar = 50 / 50 / 50 sccm; ② ICP 500W / bias power 150W; ③ temperature 150±5°C.

[0103] Specifically, if Figure 18 As shown, metallization: TiN / Al stack deposition, the process steps include: ①TiN: reactive sputtering, target: Ti; reaction gas: N2 / Ar=20 / 50sccm, deposition temperature: 250±5℃; sputtering power: 5±0.1kW; film thickness: 10±1nm; ②Al: magnetron sputtering, target: Al (99.999%); deposition temperature: 250±5℃; sputtering power: 8±0.2kW; film thickness: 1.0±0.05μm; ③ total thickness 1.01±0.05μm.

[0104] Preferably, in step S2, the number of ALD deposition cycles is 200±5 for the bottom and 100±5 for the sidewall, and the thickness control accuracy is ±0.5 nm.

[0105] The above describes the implementation methods of the present application in detail in conjunction with the accompanying drawings, but the present application is not limited to the above implementation methods. Various changes can be made within the scope of knowledge possessed by ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A high-K low-K composite dielectric shielded gate power device, characterized in that: The invention comprises an N-type drain region (1), an N-type epitaxial layer (2) located above the N-type drain region (1), and further comprises: A trench (3) passes through the P-type well region layer (11) and extends to the interior of the N-type epitaxial layer (2); a high-K dielectric layer (4), which contacts the lower portion and bottom end of the inner side surface of the trench (3), wherein the dielectric constant ε of the high-K dielectric layer (4) is ≥10 and the thickness is 10-20 nm; a nitride interface layer (5), which covers the top of the high-K dielectric layer (4), has a thickness of 1-2 nm, and a coverage of ≤60%; A low-K dielectric layer (6) is in contact with the upper portion of the inner side surface of the trench (3) and the nitride interface layer (5), wherein the low-K dielectric layer (6) has a dielectric constant ε≤3.0 and a thickness of 50-200 nm; a shielding gate electrode (7), filled in the lower portion of the trench (3), made of doped polysilicon, and in direct contact with a composite dielectric layer composed of a high-K dielectric layer (4) and a low-K dielectric layer (6); An HDP isolation layer (8), covering the top of the shielding gate electrode (7) and contacting the side of the low-K dielectric layer (6), with a thickness of 500±50 nm; a gate oxide layer (9), covering the upper surface of the HDP isolation layer (8) and the upper edge of the low-K dielectric layer (6), extending to the top of the inner sidewall of the trench (3), and having a thickness of 5-15 nm; a gate electrode (10), located above the shielding gate electrode (7), formed of polysilicon, insulated from the shielding gate electrode (7) by the HDP isolation layer (8) and the gate oxide layer (9), and insulated from the low-K dielectric layer (6) by the gate oxide layer (9); A P-type well region layer (11), which is located on the upper portion of the N-type epitaxial layer (2) and surrounds the upper portion of the trench (3); An N+ source region layer (12), which is located on the upper portion of the P-type well region layer (11) and is adjacent to the top of the trench (3); an interlayer dielectric layer (13) covering the N+ source region layer (12) and the top of the trench (3), and forming a contact hole (14) in the interlayer dielectric layer (13); A metal interconnection layer (15) connects the source region and the gate electrode (10) through the contact hole.

2. The high-K low-K composite dielectric shielded gate power device according to claim 1, characterized in that: The coverage area of ​​the high-K dielectric layer (4) accounts for 30%-50% of the inner surface area of ​​the trench (3), and the thickness at the bottom of the trench (3) is 1.5-3 times the thickness of the side wall.

3. The high-K low-K composite dielectric shielded gate power device according to claim 1, characterized in that: The porosity of the low-K dielectric layer (6) is 30%-50%, and the dielectric constant ratio between the low-K dielectric layer (6) and the high-K dielectric layer (4) is ≤0.

3.

4. The high-K low-K composite dielectric shielded gate power device according to claim 1, characterized in that: The nitrided interface layer (5) is distributed in a discontinuous island shape, with a size of a single nitrided area of ​​3-5 nm and a spacing of 2-3 nm.

5. The high-K low-K composite dielectric shielded gate power device according to claim 1, characterized in that: The HDP isolation layer (8) is formed by three deposition-etching cycles, with each deposition thickness of 200 nm and each etching removal of 50 nm.

6. The high-K low-K composite dielectric shielded gate power device according to claim 1, characterized in that: The gate oxide layer (9) is aluminum oxide, has a thickness of 5-10 nm, and a dielectric constant ε≥9.

7. The high-K low-K composite dielectric shielded gate power device according to claim 4, characterized in that: The P-type well region is not in contact with the high-K dielectric layer (4), and electric field coupling is achieved through lateral expansion of the depletion region.

8. A method for preparing a high-K low-K composite dielectric shielded gate power device, for preparing the high-K low-K composite dielectric shielded gate power device according to any one of claims 1 to 7, characterized in that: The steps include: S1. Etching a trench (3) having a depth-to-width ratio ≥ 2:1 on the N-type epitaxial layer (2); S2. selectively depositing a high-K dielectric layer (4) in the lower portion of the trench (3) by tilted mask ALD; S3. A pulsed plasma treatment is used to form a discontinuous nitrided interface layer (5); S4. Low temperature PECVD deposition of fluorine-doped low-K dielectric layer (6); S5. Fill the shielding gate electrode (7), HDP isolation layer (8) and gate electrode (10) in sequence.

9. The method for preparing a high-K low-K composite dielectric shielded gate power device according to claim 8, characterized in that: In step S2, the number of ALD deposition cycles is 200±5 for the bottom and 100±5 for the sidewall, and the thickness control accuracy is ±0.5 nm.

10. The method for preparing a high-K low-K composite dielectric shielded gate power device according to claim 8, characterized in that: In step S4, a gas ratio of SiH4 / CF4 / N2O=50 / 150 / 20 sccm is used, and the deposition temperature is ≤250°C.

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