A voltage-resistant MOSFET device with embedded oxide buried layer and a method for manufacturing the same

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a voltage-resistant MOSFET device with embedded oxide buried layers and a preparation method thereof, which comprises a plurality of parallel MOS cells, a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source and a gate, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, an upper oxide buried layer is arranged between two adjacent P well layers and directly below the gate, and the upper oxide buried layer is composed of a plurality of oxide particles which do not contact each other. The upper and lower discrete oxide buried layer structures, i.e. the particle group of the upper oxide buried layer and the rectangular particles of the lower oxide buried layer, can block the peak value of the transverse electric field and optimize the vertical electric field distribution at the same time, the problem of parasitic capacitance caused by the continuous medium layer can be effectively avoided, the breakdown voltage performance of the device can be significantly improved, and the energy loss in the switching process can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a voltage-resistant MOSFET device with embedded oxide buried layer and a preparation method thereof. BACKGROUND

[0002] In current high-voltage MOSFET devices, the traditional continuous medium buried layer structure is prone to introduce parasitic capacitance, leading to increased switching loss and limiting the increase of breakdown voltage; and the voltage-resistant technology such as super-junction often relies on complex epitaxy or multiple implantation processes, facing problems such as high manufacturing cost and uneven electric field distribution. Especially in the key area below the gate, a single dielectric layer is difficult to optimize both the lateral and vertical electric fields, which restricts the application performance of the device in high-frequency and high-power scenarios. The existing solutions have significant bottlenecks in balancing the on-resistance, voltage resistance and process feasibility.

[0003] An existing patent discloses a semi-super junction MOSFET with auxiliary oxide buried layer (publication number CN107425070B). The bottom auxiliary layer electric field of the semi-super junction MOSFET in the existing patent is in a triangular / gradient distribution, which limits its contribution to the overall voltage resistance. Moreover, the avalanche breakdown point of the existing patent is located at the edge of the P-body region, and the breakdown current flowing through the parasitic BJT base region resistance is prone to cause device failure. SUMMARY

[0004] The present application provides a voltage-resistant MOSFET device with embedded oxide buried layer and a preparation method thereof to solve the existing technical problems, solving the problem of parasitic capacitance caused by continuous dielectric layer.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a voltage-resistant MOSFET device with embedded oxide buried layer, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain, a semiconductor epitaxial layer, a source and a gate, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, an upper oxide buried layer is provided between two adjacent P well layers and directly below the gate, the upper oxide buried layer is composed of a plurality of non-contact oxide particles;

[0006] A lower oxide buried layer is provided inside the N substrate layer and directly below the gate, the lower oxide buried layer is composed of three non-contact oxide rectangular particles, wherein the bottom end of the oxide rectangular particle is in direct contact with the drain.

[0007] Further, the material of the upper oxide buried layer and the lower oxide buried layer is one of silicon dioxide and a silicon nitride composite material.

[0008] Further, the cross-sectional profile of the N substrate layer near the lower oxide buried layer is in a convex shape.

[0009] Further, the inside of the N drift layer and directly below the P+ layer is formed with a side P- layer by ion implantation, the top end of the side P- layer directly contacts the P+ layer, and the bottom end of the side P- layer directly contacts the N substrate layer.

[0010] Further, the inside of the N drift layer and above the raised area of the N substrate layer is provided with a covering N- layer.

[0011] Further, the cross-sectional profile of the covering N- layer is arc-shaped, and the covering N- layer only covers the raised area of the N substrate layer.

[0012] Further, the covering N- layer further includes a full-covering N- layer covering the entire N substrate layer.

[0013] Further, the inside of the N substrate layer and between two adjacent rectangular oxide particles is formed with a doped P- layer by ion implantation, the height of the cross-sectional profile of the doped P- layer is lower than the height of the cross-sectional profile of the rectangular oxide particles.

[0014] A preparation method of an embedded oxide buried layer voltage-resistant MOSFET device, specifically comprising:

[0015] S1, forming a raised area on the surface of the N substrate layer by photolithography and selective etching process, and predefining the pattern position of the lower oxide buried layer in the raised area;

[0016] S2, locally oxidizing or depositing a dielectric in the raised area of the N substrate layer to form a lower oxide buried layer composed of three mutually non-contacting rectangular oxide particles, ensuring that the bottom end of the rectangular oxide particles directly contacts the drain formed subsequently, and that a semiconductor trench is reserved between the particles;

[0017] S3, in the trench between the rectangular oxide particles of the lower oxide buried layer, boron ions are implanted by mask control to form a doped P- layer with a height lower than that of the oxide particles;

[0018] S4, epitaxially growing an N drift layer on the N substrate layer, and synchronously controlling the epitaxial parameters to make the raised topography of the N substrate layer extend upward;

[0019] S5, etching a trench between adjacent P well layers, depositing silicon dioxide or composite dielectric and etching back to form a discrete particle-shaped upper oxide buried layer; sequentially forming an N well layer, a P well layer and a P+ layer by multiple photolithography and ion implantation;

[0020] S6, depositing polysilicon and patterning to form a gate electrode covering directly above the upper oxide buried layer;

[0021] S7, depositing a metal layer on the front surface of the device and forming source and gate contacts by photolithography, and preparing a drain metal layer after thinning the back surface of the substrate.

[0022] The application provides a voltage-resistant MOSFET device with embedded oxide buried layers and a preparation method thereof.

[0023] 1. The application optimizes the vertical electric field distribution while blocking the peak value of the lateral electric field by the upper and lower discrete oxide buried layer structures, i.e. the particle group of the upper oxide buried layer and the rectangular particle of the lower oxide buried layer, effectively avoids the parasitic capacitance problem caused by the continuous medium layer, significantly improves the breakdown voltage performance of the device and reduces the energy loss in the switching process.

[0024] 2. The application forms a local super-junction charge compensation mechanism in the drift region by the longitudinal deep implantation design of the side P-layer, suppresses the abnormal increase of the on-resistance under high voltage, thereby improving the dynamic resistance characteristics and enhancing the resistance of the device under the avalanche breakdown condition.

[0025] 3. The application offsets the electric field concentration effect by the concentration gradient modulation of the arc-shaped N-layer covering the substrate protruding area, significantly improves the breakdown voltage under the premise of maintaining low on-resistance, and is especially suitable for the dual requirements of efficiency and withstand voltage in high-frequency application scenarios.

[0026] 4. The application simplifies the complex process required by the traditional voltage-resistant layer structure by introducing the full-coverage N-layer, reduces the number of photolithography and implantation by full-area uniform doping, significantly improves the production yield and reduces the manufacturing cost while maintaining the core voltage-resistant capability.

[0027] 5. The application widens the depletion region range by the implantation of the low-position doped P-layer between the particles of the lower oxide buried layer, effectively suppresses the electric field peak at the edge of the oxide medium, significantly reduces the leakage current under high-temperature environment and improves the stability of the breakdown voltage. DETAILED DESCRIPTION

[0028] Figure 1 is a schematic diagram of example one in the application;

[0029] Figure 2 is a schematic diagram of example two in the application;

[0030] Figure 3 is a schematic diagram of example three in the application;

[0031] Figure 4 is a schematic diagram of example four in the application;

[0032] Figure 5 is a schematic diagram of example five in the application.

[0033] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N-substrate layer; 5. N-drift layer; 6. N-well layer; 7. P-well layer; 8. P+ layer; 9. Upper buried oxide layer; 10. Lower buried oxide layer; 11. Side P- layer; 12. Covering N- layer; 13. Doped P- layer; 1201. Fully covered N- layer. Detailed Implementation

[0034] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 5 As shown, a method for fabricating a MOSFET device with an embedded buried oxide layer specifically includes:

[0036] Step 1: A raised region is formed on the surface of the N substrate layer 4 using photolithography and selective etching processes, and the pattern position of the buried oxide layer 10 is predefined in the raised region. The raised region and the position of the buried oxide layer are precisely defined by photolithography and selective etching to ensure that the subsequent structure is strictly aligned with the gate projection area, providing a geometric basis for electric field optimization, while avoiding additional mask layers to simplify the process.

[0037] Step 2: Perform localized oxidation or dielectric deposition on the raised area of ​​the N substrate layer 4 to form three non-contact rectangular oxide particles constituting the lower buried oxide layer 10. This ensures that the bottom of the rectangular oxide particles is in direct contact with the drain 1 formed subsequently, and that semiconductor trenches are retained between the particles. The localized oxidation or dielectric deposition forms a discrete rectangular particle structure, which realizes vertical electric field modulation of the direct contact between the lower buried oxide layer and the drain, significantly reducing the on-resistance. The semiconductor trenches retained between the particles create space for P-type implantation.

[0038] Step 3: In the rectangular oxide particle trenches of the lower buried oxide layer 10, boron ions are implanted through mask control to form a doped P-layer 13 with a height lower than that of the oxide particles. Low-position boron implantation is performed in the oxide particle trenches to form a doped P-layer, which effectively widens the depletion region and suppresses the concentration of electric field at the edge of the dielectric, improves high-temperature stability, and avoids affecting the carrier mobility of the substrate.

[0039] Step 4: Epitaxially grow an N-drift layer 5 on the N-substrate layer 4, and simultaneously control the epitaxial parameters to extend the protrusion morphology of the N-substrate layer 4 upward; the epitaxial growth synchronously replicates the substrate protrusion morphology to the drift layer, maintains the continuity of the longitudinal electric field distribution, provides a forming basis for the arc-shaped N-layer, and ensures the coordinated optimization of breakdown voltage and on-resistance.

[0040] Step 5: Etch trenches between adjacent P-well layers 7, deposit silicon dioxide or composite dielectric, and etch back to form discrete granular buried oxide layers 9; N-well layer 6, P-well layer 7, and P+ layer 8 are formed sequentially through multiple photolithography and ion implantation processes; the trench etch-back process realizes the discrete granular structure of the buried oxide layers, blocking the transverse peak electric field between P-wells; the composite dielectric selection enhances the withstand voltage reliability, and synchronous well region implantation ensures the superjunction charge compensation effect.

[0041] Step 6: Deposit polysilicon and pattern it to form gate 3, which is directly above the upper buried oxide layer 9. The gate polysilicon directly covers the discrete upper buried oxide layer, and the gate-source capacitance and gate-drain capacitance are reduced by utilizing the dielectric segmentation effect, which significantly improves the switching speed and reduces drive loss.

[0042] Step 7: Deposit a metal layer on the front side of the device and form the source 2 and gate 3 contacts using photolithography. After thinning the back side of the substrate, fabricate the drain 1 metal layer. The front metallization and back thinning integration process optimizes the current path, reduces the source-drain series resistance, and at the same time, the substrate thinning enhances heat dissipation, ensuring the reliability of the device under high power density.

[0043] Example 1

[0044] like Figure 1 As shown, according to one aspect of the present invention, a voltage-resistant MOSFET device with an embedded buried oxide layer is provided, comprising a plurality of parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-drift layer 5, an N-well layer 6, a P-well layer 7, and a P+ layer 8. An upper buried oxide layer 9 is provided between two adjacent P-well layers 7 and directly below the gate 3. The upper buried oxide layer 9 is composed of a plurality of non-contact oxide particles. A lower buried oxide layer 10 is provided inside the N-substrate layer 4 and directly below the gate 3. The lower buried oxide layer 10 is composed of three non-contact rectangular oxide particles, wherein the bottom end of the rectangular oxide particles is in direct contact with the drain 1. Both the upper buried oxide layer 9 and the lower buried oxide layer 10 are made of silicon dioxide or a composite material of silicon dioxide and silicon nitride. The cross-sectional profile of the N-substrate layer 4 near the lower buried oxide layer 10 is convex.

[0045] The upper buried oxide layer 9 forms discrete particles between adjacent P-wells 7, blocking the lateral electric field peak; the bottom of the rectangular particles in the lower buried oxide layer 10 is connected to the drain 1, optimizing the vertical electric field distribution. Furthermore, the discrete structure avoids parasitic capacitance in the continuous dielectric layer, and the dual electric field modulation significantly improves the breakdown voltage while reducing switching losses.

[0046] Example 2

[0047] like Figure 2As shown, a side P-layer 11 is formed inside the N drift layer 5 and directly below the P+ layer 8 by ion implantation. The top end of the side P-layer 11 is in direct contact with the P+ layer 8, and the bottom end of the side P-layer 11 is in direct contact with the N substrate layer 4.

[0048] The deep-implanted P-layer 11 from the P+ layer 8 to the N substrate layer 4 forms a local superjunction structure with the N drift layer 5, achieving longitudinal charge compensation upon depletion. Furthermore, it suppresses the phenomenon of drift region on-resistance increasing with voltage, thereby reducing dynamic resistance and improving avalanche tolerance.

[0049] Example 3

[0050] like Figure 3 As shown, a covering N-layer 12 is provided inside the N drift layer 5 and above the protruding area of ​​the N substrate layer 4. The cross-sectional profile of the covering N-layer 12 is arc-shaped, and the covering N-layer 12 only covers the protruding area of ​​the N substrate layer 4.

[0051] An arc-shaped N-layer 12 is implanted only above the bump region of the N-substrate 4, and the electric field concentration effect at the bump is counteracted by the concentration gradient. The breakdown voltage is significantly improved compared with the conventional structure, while maintaining low on-resistance, making it suitable for high-frequency applications.

[0052] Example 4

[0053] like Figure 4 As shown, a covering N-layer 12 is provided inside the N drift layer 5 and above the protruding area of ​​the N substrate layer 4. The covering N-layer 12 also includes a full-coverage N-layer 1201, which covers the entire N substrate layer 4.

[0054] The N-layer 1201 uniformly covers the entire N-substrate 4, reducing process complexity through global doping. While maintaining 90% breakdown voltage, the number of photolithography steps is reduced, resulting in significantly improved mass production yield and lower costs.

[0055] Example 5

[0056] like Figure 5 As shown, a doped P-layer 13 is formed inside the N substrate layer 4 and between two adjacent rectangular oxide particles by ion implantation. The height of the cross-sectional profile of the doped P-layer 13 is lower than the height of the cross-sectional profile of the rectangular oxide particles.

[0057] A low-level P-layer 13 is injected between the oxide buried layer 10 particles to broaden the electric field distribution by utilizing the depletion region of the PN junction and suppressing the electric field spikes at the edges of the oxide particles. The leakage current is reduced by an order of magnitude, and the breakdown voltage stability at high temperature (175℃) is significantly improved.

[0058] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A voltage-resistant MOSFET device with embedded oxide buried layer, comprising a plurality of mutually juxtaposed MOS cells, a single MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), the semiconductor epitaxial layer comprising an N substrate layer (4), an N drift layer (5), an N well layer (6), a P well layer (7) and a P+ layer (8), characterized in that: An upper oxide buried layer (9) is arranged between two adjacent P well layers (7) and directly below the gate (3), and the upper oxide buried layer (9) is composed of a plurality of oxide particles not in contact with each other; A lower oxide buried layer (10) is arranged inside the N substrate layer (4) and directly below the gate (3), and the lower oxide buried layer (10) is composed of three oxide rectangular particles not in contact with each other, wherein the bottom end of the oxide rectangular particles is in direct contact with the drain (1); A doped P layer (13) is formed by ion implantation inside the N substrate layer (4) and between two adjacent oxide rectangular particles, and the height of the cross-sectional profile of the doped P layer (13) is lower than that of the oxide rectangular particles.

2. The voltage-resistant MOSFET device with embedded oxide burying layer according to claim 1, characterized in that: The material of the upper oxide buried layer (9) and the lower oxide buried layer (10) is one of silicon dioxide and a composite material of silicon dioxide and silicon nitride.

3. The voltage withstanding MOSFET device with embedded oxide buried layer according to claim 1, wherein: The cross-sectional profile of the N substrate layer (4) near the lower oxide buried layer (10) is in a convex shape.

4. The voltage withstanding MOSFET device with embedded oxide buried layer according to claim 1, wherein: A side P layer (11) is formed by ion implantation inside the N drift layer (5) and directly below the P+ layer (8), the top end of the side P layer (11) is in direct contact with the P+ layer (8), and the bottom end of the side P layer (11) is in direct contact with the N substrate layer (4).

5. The voltage withstanding MOSFET device with embedded oxide buried layer according to claim 3, wherein: An overlying N layer (12) is arranged inside the N drift layer (5) and above the convex shape region of the N substrate layer (4).

6. The voltage withstanding MOSFET device with embedded oxide buried layer according to claim 5, wherein: The cross-sectional profile of the overlying N layer (12) is in an arc shape, and the overlying N layer (12) only covers the convex region of the N substrate layer (4).

7. The voltage withstanding MOSFET device with embedded oxide buried layer according to claim 5, wherein: The overlying N layer (12) further includes a full overlying N layer (1201) covering the entire N substrate layer (4).

8. A method of fabricating an embedded oxide buried layer voltage- withstanding MOSFET device, characterized by, The preparation method of the voltage-resistant MOSFET device with embedded oxide buried layers in claim 1, specifically includes: S1, forming a convex region on the surface of the N substrate layer (4) by photolithography and selective etching process, and defining the pattern position of the lower oxide buried layer (10) in the convex region; S2, performing local oxidation or dielectric deposition in the convex region of the N substrate layer (4) to form a lower oxide buried layer (10) composed of three rectangular oxide particles not in contact with each other, ensuring that the bottom end of the rectangular oxide particles is in direct contact with the subsequently formed drain (1), and that a semiconductor trench is reserved between the particles; S3, performing boron ion implantation in the trench between the rectangular oxide particles of the lower oxide buried layer (10) by mask control to form a doped P layer (13) with a height lower than that of the oxide particles; S4, epitaxially growing an N drift layer (5) on the N substrate layer (4) and synchronously controlling the epitaxial parameters to extend the convex topography of the N substrate layer (4) upward; S5, etching a trench between adjacent P well layers (7), depositing silicon dioxide or composite dielectric and etching back to form a discrete particle-shaped upper oxide buried layer (9); sequentially forming an N well layer (6), a P well layer (7) and a P+ layer (8) by multiple photolithography and ion implantation; S6, depositing polysilicon and patterning to form a gate (3) covering directly above the upper oxide buried layer (9). S7, depositing a metal layer on the front surface of the device and forming source (2) and gate (3) contacts by photolithography, and preparing a metal layer for the drain (1) after thinning the back surface of the substrate.

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