Solid state circuit breaker

Abstract

The solid-state circuit breaker provided by the present disclosure comprises a first surface and a second surface arranged oppositely; an anode located on the side of the first surface; an nJFET located on the side of the second surface, wherein the nJFET comprises an n-channel layer, a first source and a first drain, the first source and the first drain are arranged along a first direction, and the first drain is a cathode of the solid-state circuit breaker; and a pJFET located on the side of the second surface and arranged alternately with the nJFET in a second direction perpendicular to the first direction, wherein the pJFET comprises a p-channel layer, a second source and a second drain, the second source is shared with the first source, and the second drain is shared with the first drain.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a solid-state circuit breaker. BACKGROUND

[0002] The solid-state circuit breaker in the direct current power grid is an important application of silicon carbide power electronics, which can be used in new energy vehicles, photovoltaic energy storage and other scenarios. The solid-state circuit breaker is normally open under normal working conditions, and the current passes through the solid-state circuit breaker to reach the power switch and the power load. The solid-state circuit breaker can detect an excessively high current load in the direct current bus under an extreme scenario, such as a short circuit of the direct current power grid load, and actively shut off the current in the direct current bus through the overcurrent. However, the related solid-state circuit breaker has an excessively large specific on-resistance, which increases power loss and other effects. SUMMARY

[0003] Embodiments of the present disclosure provide a solid-state circuit breaker, which can reduce the specific on-resistance of the solid-state circuit breaker.

[0004] In some embodiments, the solid-state circuit breaker provided by the embodiments of the present disclosure comprises:

[0005] a first surface and a second surface arranged oppositely;

[0006] an anode located on the side where the first surface is located;

[0007] an nJFET located on the side where the second surface is located, the nJFET comprising an n-channel layer, a first source and a first drain, wherein the first source and the first drain are arranged in a first direction, and the first drain is a cathode of the solid-state circuit breaker;

[0008] a pJFET located on the side where the second surface is located and arranged alternately with the nJFET in a second direction perpendicular to the first direction, the pJFET comprising a p-channel layer, a second source and a second drain, wherein the second source is shared with the first source, and the second drain is shared with the first drain.

[0009] In some embodiments, in the above-mentioned solid-state circuit breaker provided by the embodiments of the present disclosure, the nJFET further comprises an n+ substrate, an n-drift layer, an n-current diffusion layer, a p-type well layer, a first p+ connection structure, a first n+ contact layer and a p+ top gate layer in a third direction perpendicular to the first direction and the second direction; wherein

[0010] the n-current diffusion layer and the p-type well layer are embedded in the n-drift layer on the side of the n-drift layer away from the n+ substrate, and the depth of the n-current diffusion layer is greater than the depth of the p-type well layer;

[0011] The first n+ contact layer and the p+ top gate layer are embedded in the n- channel layer away from a side of the n+ substrate, and the first n+ contact layer and the p+ top gate layer are arranged apart by the n- channel layer in the first direction;

[0012] The first n+ contact layer is in contact with a surface of the first source facing the n+ substrate, and the p+ top gate layer is in contact with a surface of the first drain facing the n+ substrate;

[0013] The first p+ connection structure extends through the n- channel layer and into the p-type well layer, the first p+ connection structure is in contact with the p+ top gate layer in the first direction, and the first p+ connection structure is in contact with a surface of the first drain facing the n+ substrate.

[0014] In some embodiments, in the above-mentioned solid-state circuit breaker provided by the embodiments of the present disclosure, the p-type well layer comprises first p-type well structures and second p-type well structures arranged alternately in the first direction; wherein,

[0015] The first p-type well structure is in the first drain in the n+ substrate, and the first p-type well structure is in the n- current diffusion layer in the n+ substrate, and the first p-type well structure is in the n+ substrate and the first p+ connection structure in the n+ substrate.

[0016] The first source is in the second p-type well structure in the n+ substrate, and the second p-type well structure is in the n- current diffusion layer in the n+ substrate.

[0017] In some embodiments, in the above-mentioned solid-state circuit breaker provided by the embodiments of the present disclosure, the pJFET further comprises the n+ substrate, the n- drift layer, the first p-type well structure and the second p-type well structure, the p- channel layer is embedded in the n- drift layer away from a side of the n+ substrate, the p- channel layer is located between the first p-type well structure and the second p-type well structure, and the p- channel layer is in the n+ substrate and the n- current diffusion layer in the n+ substrate.

[0018] In some embodiments, in the solid-state circuit breaker provided by the embodiments of the present disclosure, the pJFET further comprises a second p+ connection structure, the second p+ connection structure is arranged alternately with the first p+ connection structure in the same layer and in the first direction, the second p+ connection structure is arranged discontinuously in the region where the nJFET is located, and the orthogonal projection of the second p+ connection structure on the n+ substrate is located within the orthogonal projection of the second p-type well structure on the n+ substrate, and the surface of the second p+ connection structure away from the n+ substrate is in contact with the surface of the second source electrode facing the n+ substrate.

[0019] In some embodiments, in the solid-state circuit breaker provided by the embodiments of the present disclosure, the pJFET further comprises the n- channel layer, the p+ top gate layer and the first p+ connection structure, and the p+ top gate layer is arranged spaced apart from the second p+ connection structure through the n- channel layer.

[0020] In some embodiments, in the solid-state circuit breaker provided by the embodiments of the present disclosure, the pJFET further comprises a third p+ connection structure, the third p+ connection structure is arranged alternately with the first p+ connection structure in different layers and in the second direction, the third p+ connection structure is embedded in the first p-type well structure on the side of the first p-type well structure away from the n+ substrate, and the surface of the third p+ connection structure away from the n+ substrate is in contact with the surface of the second drain electrode facing the n+ substrate.

[0021] In some embodiments, in the solid-state circuit breaker provided by the embodiments of the present disclosure, the pJFET further comprises a second n+ contact layer, a gate dielectric layer and a gate; wherein,

[0022] The second n+ contact layer is embedded in the first p-type well structure on the side of the first p-type well structure away from the n+ substrate, the surface of the second n+ contact layer away from the n+ substrate is in contact with the surface of the second drain electrode facing the n+ substrate, and the third p+ connection structure is arranged between the second n+ contact layers;

[0023] The surface of the gate dielectric layer facing the n+ substrate is in contact with the surface of the p- channel layer and the surface of the second n+ contact layer away from the n+ substrate, and the gate is arranged spaced apart from the second drain electrode on the side of the gate dielectric layer away from the n+ substrate.

[0024] In some embodiments, in the solid-state circuit breaker provided by the embodiments of the present disclosure, the pJFET further comprises a third n+ contact layer, the third n+ contact layer is embedded in the second p-type well structure on at least the side of the second p-type well structure away from the n+ substrate, and the third n+ contact layer is arranged in contact with the p- channel layer.

[0025] In some embodiments, in the solid state circuit breaker provided by the embodiments of the present disclosure, the third n+ contact layer is further embedded in the second p+ connection structure on the side of the second p+ connection structure close to the second drain, and the third n+ contact layer is in contact with the second source.

[0026] The present disclosure has the following advantages:

[0027] The solid state circuit breaker provided by the embodiments of the present disclosure comprises: a first surface and a second surface arranged oppositely; an anode located on the side of the first surface; an nJFET located on the side of the second surface, the nJFET comprising an n-channel layer, a first source and a first drain, wherein the first source and the first drain are arranged along a first direction, and the first drain is a cathode of the solid state circuit breaker; and a pJFET located on the side of the second surface and arranged alternately with the nJFET along a second direction perpendicular to the first direction, the pJFET comprising a p-channel layer, a second source and a second drain, wherein the second source is shared with the first source, and the second drain is shared with the first drain. The proportion of the parallel number of the nJFET and the pJFET can be freely allocated in a monolithic integrated device, so that the specific on-resistance of the solid state circuit breaker can be better reduced. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A top view of the solid state circuit breaker provided by the embodiments of the present disclosure;

[0029] Figure 2 Another top view of the solid state circuit breaker provided by the embodiments of the present disclosure;

[0030] Figure 3 A cross-sectional view of the nJFET along the I-I' direction in the solid state circuit breaker shown in Figure 1 and Figure 2

[0031] Figure 4 A cross-sectional view of the pJFET along the II-II' direction in the solid state circuit breaker shown in Figure 1 and Figure 2

[0032] Figure 5 Various working regions of the solid state circuit breaker shown in Figures 1-4

[0033] Figure 6 A top view of the solid state circuit breaker shown in Figures 1-4

[0034] A cross-sectional view of the solid state circuit breaker shown in Figure 7 Figures 1-4

[0035] Figure 8 A cross-sectional view of the solid state circuit breaker shown in​​​​​Figures 1-4 A cross-sectional view of an nJFET of the solid state circuit breaker during fabrication;

[0036] Figure 9 For Figures 1-4 A cross-sectional view of a pJFET of the solid state circuit breaker during fabrication;

[0037] Figure 10 For Figures 1-4 Another cross-sectional view of an nJFET of the solid state circuit breaker during fabrication;

[0038] Figure 11 For Figures 1-4 Another cross-sectional view of a pJFET of the solid state circuit breaker during fabrication;

[0039] Figure 12 For Figures 1-4 Another cross-sectional view of an nJFET of the solid state circuit breaker during fabrication;

[0040] Figure 13 For Figures 1-4 Another cross-sectional view of a pJFET of the solid state circuit breaker during fabrication;

[0041] Figure 14 For Figures 1-4 Another cross-sectional view of an nJFET of the solid state circuit breaker during fabrication;

[0042] Figure 15 For Figures 1-4 Another cross-sectional view of a pJFET of the solid state circuit breaker during fabrication;

[0043] Figure 16 For Figures 1-4 Another cross-sectional view of an nJFET of the solid state circuit breaker during fabrication;

[0044] Figure 17 For Figures 1-4 Another cross-sectional view of a pJFET of the solid state circuit breaker during fabrication;

[0045] Figure 18 Another cross-sectional view of a pJFET of the solid state circuit breaker during fabrication according to an embodiment of the present disclosure;

[0046] Figure 19 Another cross-sectional view of a pJFET of the solid state circuit breaker during fabrication according to an embodiment of the present disclosure;

[0047] Figure 20 For Figure 18 And Figure 19 A cross-sectional view of a completed pJFET;

[0048] Figure 21 for Figure 20 a cross-sectional view of a gate electrode of a pJFET of a solid state circuit breaker according to an embodiment of the present disclosure;

[0049] Figure 22 a cross-sectional view of a pJFET of a solid state circuit breaker according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] For the purpose of making the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that, in the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for clarity. In the present disclosure, example embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated in the drawings but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features; an illustrated sharp angle can be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and do not reflect true scales or proportions. Furthermore, the same or similar reference numerals are used to denote the same or similar elements or elements having the same or similar function throughout the figures. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components.

[0051] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The use of the terms "first", "second", and the like, does not imply any order, quantity, or importance, but merely distinguishes different components. The terms "include", "comprise", and the like, mean to encompass the elements listed thereafter, not to exclude other elements. The terms "connected", "coupled", and the like, do not necessarily mean to be directly and physically connected or coupled, but can include wireless connection or coupling. The terms "inner", "outer", "upper", "lower", and the like, are used only to indicate relative positions, and can change when the absolute positions of the described objects change.

[0052] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, or be directly connected to the other element or layer, or intervening elements or intervening layers can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, or be directly connected to the other element or layer, or intervening elements or intervening layers can be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or intervening layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Figure 1 and Figure 2 are respectively top views of a solid-state circuit breaker provided by embodiments of the present disclosure, Figure 3 and Figure 4 are respectively longitudinal sectional views of a solid-state circuit breaker provided by embodiments of the present disclosure, wherein Figure 1 corresponds to Figure 3 and Figure 4 is a III-III' transverse sectional view in Figure 2 corresponds to Figure 3 and Figure 4 is a IV-IV' transverse sectional view in Figure 1 and Figure 2 are respectively marked I-I' and II-II' two longitudinal sections, which respectively correspond to Figure 3 and Figure 4 are respectively two longitudinal sectional views, wherein Figure 3 corresponds to an nJFET in a solid-state circuit breaker, Figure 4 corresponds to a pJFET in a solid-state circuit breaker. As Figures 1-4As shown, the solid-state circuit breaker provided by the embodiments of the present disclosure can include oppositely arranged first and second surfaces, an anode A, an nJFET, and a pJFET, wherein the nJFET and the pJFET are located on the same side of the n+ substrate 101 (for example, the side on which the second surface is located), the anode A is located on the side of the n+ substrate 101 away from the nJFET and the pJFET (for example, the side on which the first surface is located), the nJFET includes an n-channel layer 102, a first source S1, and a first drain D1, wherein the first source S1 and the first drain D1 are arranged along a first direction X, and the conduction direction of the n-channel layer 102 is the first direction X, the first source S1 is a floating electrode S, and the first drain D1 is a cathode K of the solid-state circuit breaker; the pJFET and the nJFET are alternately arranged in a second direction Y perpendicular to the first direction X, the pJFET includes a p-channel layer 103, a second source S2, and a second drain D2, wherein the conduction direction of the p-channel layer 103 is the first direction X, the second source S2 is shared with the first source S1 (that is, the second source S2 and the first source S1 of the present disclosure are one source, and for distinction, the part of the source in the nJFET region is referred to as the first source S1, and the part of the source in the pJFET region is referred to as the second source S2), and the second drain D2 is shared with the first drain D1 (that is, the second drain D2 and the first drain D1 of the present disclosure are one drain, and for distinction, the part of the drain in the nJFET region is referred to as the first drain D1, and the part of the drain in the pJFET region is referred to as the second drain D2).

[0054] In the solid-state circuit breaker provided by the embodiments of the present disclosure, the nJFET and the pJFET are included, and the nJFET and the pJFET are respectively based on the n-channel layer 102 and the p-channel layer 103, the mobilities of the two are different, the mobility of the n-channel layer 102 is much greater than that of the p-channel layer 103, and the distribution ratio of the n-channel layer 102 and the p-channel layer 103 needs to be optimized. In the case that the channel conduction direction of the nJFET and the pJFET is parallel to the alternate distribution direction of the nJFET and the pJFET, the current of the final solid-state circuit breaker is limited by the pJFET, thereby causing the specific on-resistance of the design scheme to be too large and unable to achieve the optimal specific on-resistance. By setting the channel conduction direction of the nJFET and the pJFET to be perpendicular to the alternate distribution direction of the nJFET and the pJFET, the proportion of the number of parallel cells of the nJFET and the p-JFET can be freely distributed in the monolithic integrated solid-state circuit breaker, so that the specific on-resistance of the solid-state circuit breaker can be better reduced.

[0055] In some embodiments, in the solid-state circuit breaker provided by the embodiments of the present disclosure, as Figures 1-4As shown, in a third direction Z perpendicular to the first direction X and the second direction Y, the nJFET of the present disclosure can further include an n+ substrate 101, an n- drift layer 104, an n- current diffusion layer 105, a p-type well layer 106 (including first and second p-type well structures pw1 and pw2 arranged alternately in the first direction X), a first p+ connection structure 107, a first n+ contact layer 108, and a p+ top gate layer 109; wherein the n- current diffusion layer 105 and the p-type well layer 106 are embedded in the n- drift layer 104 on a side of the n- drift layer 104 away from the n+ substrate 101, the n- current diffusion layer 105 has a depth greater than that of the p-type well layer 106; the first n+ contact layer 108 and the p+ top gate layer 109 are embedded in the n- channel layer 102 on a side of the n- channel layer 102 away from the n+ substrate 101, the first n+ contact layer 108 and the p+ top gate layer 109 are spaced apart by the n- channel layer 102 in the first direction X; a surface of the first n+ contact layer 108 away from the n+ substrate 101 is in contact with a surface of the first source electrode S1 facing the n+ substrate 101, and a surface of the p+ top gate layer 109 away from the n+ substrate 101 is in contact with a surface of the first drain electrode D1 facing the n+ substrate 101; the first p+ connection structure 107 extends through the n- channel layer 102 and into the first p-type well structure pw1, the first p+ connection structure 107 is in contact with the p+ top gate layer 109 in the first direction X, and the first p+ connection structure 107 is in contact with a surface of the first drain electrode D1 facing the n+ substrate 101; a footprint of the first p-type well structure pw1 on the n+ substrate 101 is located within a footprint of the first drain electrode D1 on the n+ substrate 101 and partially overlaps with a footprint of the n- current diffusion layer 105 on the n+ substrate 101, and the footprint of the first p-type well structure pw1 on the n+ substrate 101 and a footprint of the first p+ connection structure 107 on the n+ substrate 101 overlap each other (e.g., coincide); a footprint of the first source electrode S1 on the n+ substrate 101 is located within a footprint of the second p-type well structure pw2 on the n+ substrate 101, and a footprint of the second p-type well structure pw2 on the n+ substrate 101 partially overlaps with a footprint of the n- current diffusion layer 105 on the n+ substrate 101.

[0056] Continuing to refer to Figures 1-4It can be known that, in the above solid-state circuit breaker provided by the embodiment of the present disclosure, the pJFET can further include an n+ substrate 101, an n- channel layer 102, an n- drift layer 104, a first p-type well structure pw1, a second p-type well structure pw2, a first p+ connection structure 107, a p+ top gate layer 109, and a second p+ connection structure 110, wherein a projection of the first p-type well structure pw1 on the n+ substrate 101 is located within a projection of the second drain D2 on the n+ substrate 101 and overlaps (for example, coincides) with a projection of the first p+ connection structure 107 on the n+ substrate 101, a projection of the second source S2 on the n+ substrate 101 is located within a projection of the second p-type well structure pw2 on the n+ substrate 101, the p+ top gate layer 109 contacts a surface of the n+ substrate 101 away from the second drain D2 facing a surface of the n+ substrate 101, the first p+ connection structure 107 penetrates through the n- channel layer 102 and extends into the first p-type well structure pw1, the first p+ connection structure 107 contacts the p+ top gate layer 109 in the first direction X, and the first p+ connection structure 107 contacts the surface of the n+ substrate 101 away from the second drain D2; the p- channel layer 103 is embedded in the n- drift layer 104 on a side of the n- drift layer 104 away from the n+ substrate 101, the p- channel layer 103 is located between the first p-type well structure pw1 and the second p-type well structure pw2, and projections of the p- channel layer 103 on the n+ substrate 101 and the n- current diffusion layer 105 on the n+ substrate 101 are alternately arranged along the second direction Y; the second p+ connection structure 110 is in the same layer as the first p+ connection structure 107 and is alternately arranged along the first direction X, the second p+ connection structure 110 is arranged to be disconnected in the region where the nJFET is located, a projection of the second p+ connection structure 110 on the n+ substrate 101 is located within a projection of the second p-type well structure pw2 on the n+ substrate 101, and the second p+ connection structure 110 contacts a surface of the n+ substrate 101 away from the second source S2 facing a surface of the n+ substrate 101; and the p+ top gate layer 109 and the second p+ connection structure 110 are spaced apart by the n- channel layer 102.

[0057] In the conduction process of the solid-state circuit breaker of the present disclosure, electrons flow from the n- current diffusion layer 105 of the nJFET through the n- channel layer 102 to the first n+ contact layer 108, and enter the first source S1; then the current flows from the first source S1 to the second source S2 of the pJFET, and then the current flows through the second p-type well structure pw2 and the p- channel layer 103 to enter the first p-type well structure pw1 and the first p+ connection structure 107, and enters the cathode K of the solid-state circuit breaker. As the positive voltage VAK of the bottom anode A increases, the n- channel layer 102 of the nJFET enters a saturation state first, at which time the current is the rated trigger current (I trig); as the positive voltage VAK of the bottom anode A is further increased, the p-channel layer 103 of the pJFET is further pinched off, and finally enters a blocking state.

[0058] Figure 5 The various working regions of the solid-state circuit breaker provided by the embodiments of the present disclosure are specifically shown, such as Figure 5 As shown, the normal conduction process of the solid-state circuit breaker of the present disclosure is located in a (I) linear working region. As the voltage of the anode A gradually increases, the voltage of the floating electrode S rises, which is equivalent to the voltage of the cathode K relative to the floating electrode S being negative, and the nJFET is gradually pinched off in the linear conduction process. The solid-state circuit breaker enters a (II) current transit process, and the voltage of the floating electrode S relative to the cathode K is much lower than that of the anode A relative to the floating electrode S. Then, as the solid-state circuit breaker starts the self-triggered turn-off process, the voltage of the anode A continues to increase, the pJFET is further pinched off, the overall current of the solid-state circuit breaker decreases, until the voltage of the anode A of the solid-state circuit breaker reaches the voltage of the DC bus, and the solid-state circuit breaker enters a (III) blocking state. If, after the solid-state circuit breaker is completely turned off, the voltage of the anode A is further increased, when the p-channel layer 103 in the pJFET part (II-II' cross section) reaches through (i.e., the depletion region in the p-channel layer 103 reaches the top boundary of the p-channel layer 103), the solid-state circuit breaker will reach through, that is, the (IV) reach-through working region of the above Figure 4 .

[0059] In some embodiments, Figures 1-4 The solid-state circuit breaker shown in

[0060] Step 1: As shown in Figure 6 and Figure 7 , prepare the n+ silicon carbide substrate 101, and epitaxially grow the n- drift layer 104 thereon, wherein the n+ substrate 101 includes alternating p-type conductive regions and n-type conductive regions.

[0061] Step 2: First, deposit a hard mask (not shown in the figure) on the n- drift layer 104 of silicon carbide, by spin-coating photoresist, exposing, curing, developing, etching the hard mask (Hard Mask), and obtaining an opening on the hard mask (Hard Mask), and then performing ion implantation at the opening. As shown in Figure 8As shown, the above steps are repeated sequentially in the n-type conductive region to form a first p-type well structure pw1 and a second p-type well structure pw2 with moderate p-type doping. The target doping concentration is preferably 2e⁻¹. 18 / cm 3 ~5e 18 / cm 3 And an n-type lightly doped n-current diffusion layer, with a target doping concentration of 5e 16 / cm 3 ~1e 17 / cm 3 Correspondingly, such as Figure 9 As shown, in the p-type conductive region, the above steps are repeated to inject... Figure 9 The first p-type well structure pw1 and the second p-type well structure pw2 shown are moderately doped with p-type doping, and the target doping concentration is preferably 2e⁻¹. 18 / cm 3 ~5e 18 / cm 3 The above steps are repeated between the first p-type well structure pw1 and the second p-type well structure pw2 to form a lightly doped p-channel layer 103 by ion implantation, with a target doping concentration of 5e. 16 / cm 3 ~1e 17 / cm 3 .

[0062] Step 3: As Figure 10 and Figure 11 As shown, an n-channel layer 102 is grown through a secondary epitaxial process, with a target doping concentration of 5e⁻¹. 16 / cm 3 ~2e 17 / cm 3 .

[0063] Step 4: Deposit a hard mask on the n-channel layer 102. Then, using a spin-coating photoresist process, expose, cure, and develop the hard mask to create openings. Ion implantation is then performed at these openings. Figure 12 As shown, the above steps are repeated sequentially in the n-type conductive region to form a p-type heavily doped first p+ connection structure 107, with a preferred target doping concentration of 2e. 18 / cm 3 ~1e 19 / cm 3 The p-type heavily doped p+ top gate layer 109 has a target doping concentration of 2e⁻¹. 18 / cm 3 ~5e 18 / cm 3And an n-type heavily doped first n+ contact layer 108, with a target doping concentration of 1e. 18 / cm 3 ~1e 20 / cm 3 Correspondingly, such as Figure 13 As shown, in the p-type conductive region, repeat the above steps, injecting as... Figure 13 The p-type heavily doped first p+ linker structure 107 and second p+ linker structure 110 shown have a target doping concentration preferably of 2e⁻¹. 18 / cm 3 ~1e 19 / cm 3 And a p-type heavily doped p+ top gate layer 109, with a target doping concentration of 2e 18 / cm 3 ~5e 18 / cm 3 .

[0064] Step 5: As Figure 14 and Figure 15 As shown, the silicon carbide wafer after ion implantation is annealed to activate the doped atoms in the ion-implanted silicon carbide semiconductor. An oxide layer is deposited for device passivation. The passivation layer 111 is etched by spin-coating photoresist, exposure, curing, and development processes to obtain an opening on the passivation layer 111.

[0065] Step 6: Deposit metallic Ni on the surface of the silicon carbide device, and then perform high-temperature annealing at an ambient temperature of 1000℃. Next, remove the metallic Ni from the passivation layer 111 surface using a wet process. During annealing, Ni reacts with SiC to form a NiSi compound. Finally, as shown... Figure 16 and Figure 17 The black area represents the NiSi compound formed after annealing, used to achieve ohmic contact between the metal and the silicon carbide semiconductor. In this step, the design dimensions and fabrication process of the n-type conductive region (I-I') and the p-type conductive region (II-II') are consistent.

[0066] Step 7: Fabricate the cathode K and floating electrode S of the solid-state circuit breaker on the front side of the device. The cathode K and floating electrode S are isolated by a passivation layer 111. Subsequently, complete the metal deposition of the anode A on the back side and the ohmic contact process, thus completing the final step. Figures 1-4 The solid-state circuit breaker shown is integrated on the same chip. Figure 3 and Figure 4 The NiSi compound was omitted. In this step, the design dimensions and process of the n-type conductive region (I-I') and the p-type conductive region (II-II') are consistent.

[0067] In some embodiments, this disclosure may maintain the nJFET structure of the n-type conductive region unchanged and further improve the structure of the pJFET of the p-type conductive region. Specifically, corresponding to the fourth step described above... Figure 13 The process steps differ; specifically, ion implantation can be performed by repeating the above steps in the p-type conductive region to form... Figure 19 The second p+ connection structure 110 shown has a preferred target doping concentration of 2e. 18 / cm 3 ~1e 19 / cm 3 Then in the corresponding Figure 13 The n-channel layer 102 is removed by etching in the region of the top p+ gate layer 109 and the first p+ connection structure 107. The etching opening can be greater than or equal to Figure 13 In the region where the top gate layer 109 of the middle p+ and the first p+ connection structure 107 are located, the etched opening boundary can contact the second p+ connection structure 110, or be located inside the region where the second p+ connection structure 110 is located. However, it is necessary to ensure that the remaining size of the mesa region of the second p+ connection structure 110 is, for example, greater than 1 μm, so that the second source S2 formed subsequently can achieve effective ohmic contact with the second p+ connection structure 110.

[0068] Furthermore, a hard mask can be deposited within the etched p-type conductive region. Through spin-coating photoresist, exposure, curing, and development processes, the hard mask is etched to obtain an opening. Ion implantation is then performed at the opening, including vertical implantation and angled implantation of the second p+ connection structure 110 sidewalls, such as... Figure 18 The arrows shown point to form a shape like... Figure 18 The distribution morphology of the n+ type doped region and the third p+ connection structure 112 are shown. The n+ type doped region may include a second n+ contact layer 113 and a third n+ contact layer 114; wherein, the second n+ contact layer 113 is embedded in the first p-type well structure pw1 on the side away from the n+ substrate 101, the surface of the second n+ contact layer 113 away from the n+ substrate 101 is in contact with the surface of the subsequently fabricated second drain D2 facing the n+ substrate 101, a third p+ connection structure 112 is provided between the second n+ contact layers 113, the third n+ contact layer 114 is embedded in the first p-type well structure pw1 on the side away from the n+ substrate 101, and the second p+ connection structure 110 is embedded in the second p+ connection structure 110 on the side close to the subsequently fabricated second drain D2, and the third n+ contact layer 114 is in contact with the p-channel layer 103 and the subsequently fabricated second source S2.

[0069] Further, the gate dielectric layer 115 and the gate 116 can be deposited in the p-type conductive region and etched Figure 19 outside the regions shown. Figure 19 The dashed box of the n-type channel region of the equivalent parallel n-MOSFET realizes the parallel connection of the pJFET of the solid-state circuit breaker. A positive VGS gate voltage can be applied to the gate 116 on the n-type channel region of the n-MOSFET to open the n-type inversion channel inside the p-channel layer 103.

[0070] After that, the above-mentioned sixth step and seventh step are repeated to finally realize the second source S2 and the second drain D2 in the p-type conductive region, and the anode A on the back surface, which are respectively electrically connected to the corresponding electrodes in the n-type conductive region, and realize the direct ohmic contact between the second source S2 and the third n+ contact layer 114 on the sidewall of the second p+ connection structure 110. Figure 20

[0071] Therefore, the disclosure designs an additional MOS gate control structure on the p-channel layer 103 of the pJFET. In the disclosure Figures 1-4 The rated trigger current (I trig ) of the solid-state circuit breaker shown is a fixed value, and the maximum output current value of the solid-state circuit breaker cannot be automatically regulated by external electrical control (voltage or current control). However, in some application scenarios, such as capacitive load scenarios, it is necessary to charge the capacitor with a current higher than the rated trigger current (I trig ), and the current higher than the rated trigger current (I trig ) is adjustable, and the solid-state circuit breaker will start to spontaneously turn off after reaching the rated trigger current (I trig ), and only has a pulse of charging current, which cannot realize continuous and effective charging of the capacitive load.

[0072] Therefore, we need to actively control the solid-state circuit breaker, and introduce an equivalent parallel n-type MOSFET in the pJFET device region, so that Figure 20 The solid-state circuit breaker shown is actively controlled by adding a first gate drive GD1 (Gate Driver-1) and a second gate drive GD2 (Gate Driver-2). At this time, by applying different levels of gate drive voltage (greater than the threshold voltage of the equivalent parallel n-type MOSFET) such as +5V to +20V through the first gate drive GD1 and the second gate drive GD2, the voltage of the gate 116 relative to the cathode K is positive, and the equivalent n-type MOSFET is partially or fully open, which is equivalent to a variable resistor. At this time, the current flowing through the solid-state circuit breaker will be Figure 21 ​p-channel layer 103 induces a partial inversion layer electron channel, thereby realizing parallel connection of the n-channel layer 102 to the p-channel layer 103, and realizing active current increase of the solid-state circuit breaker by the gate drive voltage of the first gate drive GD1 and the second gate drive GD2, at which time the conduction current is higher than the rated trigger current (I trig ), and successful charging of the capacitive load can be realized. Different gate drive voltages of the first gate drive GD1 and the second gate drive GD2 make the n-type MOSFET equivalent to resistors of different resistances, corresponding to the charging current of each selectable solid-state circuit breaker for the capacitive load from high to low. Meanwhile, under the condition of the capacitive load, increasing the equivalent n-type MOSFET structure can significantly reduce the inrush current at startup. Further, when the solid-state circuit breaker shown in Figure 20 is in the (III) blocking state, the first gate drive GD1 and the second gate drive GD2 apply a forward opening voltage, and the reset of the solid-state circuit breaker can be realized, so that the solid-state circuit breaker is re-conducted from the off state.

[0073] Figure 22 Another structure diagram of the pJFET region in the solid-state circuit breaker provided by the embodiment of the present disclosure is shown in Figure 22 , in which the nJFET structure of the n-type conductive region is consistent with the nJFET structure shown in Figure 3 . Figure 22 The main difference from Figure 21 is that the distribution morphology of the third n+ contact layer 114 on both sides of the n-type channel region of the equivalent parallel n-type MOSFET is different, and the third n+ contact layer 114 does not extend to the second source S2, but is only distributed inside the second p-type well structure pw2. The actively controlled solid-state circuit breaker designed in this way can also work normally. Since the source is in a floating state during the operation of the solid-state circuit breaker (working in the (I) region), it has a forward bias with respect to the cathode K (ground, voltage 0V), so that there is a forward voltage drop between the second p-type well structure pw2 and the third n+ contact layer 114 adjacent thereto, the PN junction is turned on, and when the first gate drive GD1 and the second gate drive GD2 apply, for example, a forward drive voltage of +20V (the voltage of the gate 116 with respect to the cathode K is +20V), the p-channel layer 103 shown in Figure 22 induces an inversion layer electron channel and is turned on, thereby realizing the current adjustable function of the solid-state circuit breaker, and the effect is the same as that of the solid-state circuit breaker shown in Figure 21 .

[0074] In summary, the present disclosure Figures 1-4The embodiment shown designs a new distribution structure of nJFET and pJFET as a solid-state circuit breaker, wherein the channel conduction direction of the nJFET and the pJFET is perpendicular to the alternating distribution direction of the nJFET and the pJFET, and the proportion of the parallel number of the nJFET and the pJFET cells can be freely allocated in the monolithic integrated solid-state circuit breaker, so as to better reduce the specific on-resistance of the solid-state circuit breaker. And referring to Figure 21 and Figure 22 The present disclosure is based on Figures 1-4 The solid-state circuit breaker shown in the embodiment designs an additional MOS gate control structure above the p-channel layer 103 of the pJFET, which can realize the dynamic regulation of the output current of the solid-state circuit breaker. The solid-state circuit breaker provided by the embodiment of the present disclosure is used as a direct current circuit breaker in new energy automobile direct current power distribution system, energy storage, medium voltage direct hanging, flexible direct current transmission and other scenes.

[0075] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0076] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A solid state circuit breaker, characterized by Comprise: n+ substrate, the n+ substrate comprising oppositely arranged first surface and second surface; anode, located on the side of the first surface; nJFET, located on the side of the second surface, the nJFET comprising n- channel layer, first source and first drain, wherein the first source and the first drain are arranged along a first direction, the first drain is the cathode of the solid-state circuit breaker; pJFET, located on the side of the second surface and alternately arranged with the nJFET in a second direction perpendicular to the first direction, the pJFET comprising p- channel layer, second source and second drain, wherein the second source is shared with the first source, and the second drain is shared with the first drain; The nJFET further comprises n-drift layer, n-current diffusion layer, p-type well layer, first p+ connection structure, first n+ contact layer, p+ top gate layer along a third direction perpendicular to the first direction and the second direction; wherein, The n-current diffusion layer and the p-type well layer are embedded in the n-drift layer on the side of the n-drift layer away from the n+ substrate, and the depth of the n-current diffusion layer is greater than the depth of the p-type well layer; The first n+ contact layer and the p+ top gate layer are embedded in the n-channel layer on the side of the n-channel layer away from the n+ substrate, and the first n+ contact layer and the p+ top gate layer are spaced apart by the n-channel layer in the first direction; The surface of the first n+ contact layer away from the n+ substrate is in contact with the surface of the first source towards the n+ substrate, and the surface of the p+ top gate layer away from the n+ substrate is in contact with the surface of the first drain towards the n+ substrate; The first p+ connection structure penetrates through the n-channel layer and extends into the p-type well layer, the first p+ connection structure is in contact with the p+ top gate layer in the first direction, and the first p+ connection structure is in contact with the surface of the first drain towards the n+ substrate; The pJFET further comprises the n-drift layer, the first p-type well structure and the second p-type well structure, the p-channel layer is embedded in the n-drift layer on the side of the n-drift layer away from the n+ substrate, the p-channel layer is located between the first p-type well structure and the second p-type well structure, and the projection of the p-channel layer on the n+ substrate and the projection of the n-current diffusion layer on the n+ substrate are alternately arranged in the second direction.

2. The solid state circuit breaker of claim 1, wherein, The p-type well layer comprises the first p-type well structure and the second p-type well structure alternately arranged in the first direction; wherein, The projection of the first p-type well structure on the n+ substrate is located within the projection of the first drain on the n+ substrate, and partially overlaps with the projection of the n-current diffusion layer on the n+ substrate, and the projection of the first p-type well structure on the n+ substrate and the projection of the first p+ connection structure on the n+ substrate overlap each other. The first source is located in the orthographic projection of the second p-type well structure on the n+ substrate, and the orthographic projection of the second p-type well structure on the n+ substrate partially overlaps with the orthographic projection of the n- current diffusion layer on the n+ substrate.

3. The solid state circuit breaker of claim 1 or 2, wherein The pJFET further comprises a second p+ connection structure, which is in the same layer as the first p+ connection structure and is arranged alternately in the first direction, and the second p+ connection structure is arranged discontinuously in the region where the nJFET is located, and the orthographic projection of the second p+ connection structure on the n+ substrate is located in the orthographic projection of the second p-type well structure on the n+ substrate, and the surface of the second p+ connection structure away from the n+ substrate is in contact with the surface of the second source electrode facing the n+ substrate.

4. The solid state circuit breaker of claim 3, wherein, The pJFET further comprises the n- channel layer, the p+ top gate layer and the first p+ connection structure, and the p+ top gate layer is spaced apart from the second p+ connection structure by the n- channel layer.

5. The solid state circuit breaker of claim 3, wherein, The pJFET further comprises a third p+ connection structure, which is in a different layer from the first p+ connection structure and is arranged alternately in the second direction, and the third p+ connection structure is embedded in the first p-type well structure on the side away from the n+ substrate, and the surface of the third p+ connection structure away from the n+ substrate is in contact with the surface of the second drain electrode facing the n+ substrate.

6. The solid state circuit breaker of claim 5, wherein, The pJFET further comprises a second n+ contact layer, a gate dielectric layer and a gate; wherein, The second n+ contact layer is embedded in the first p-type well structure on the side away from the n+ substrate, and the surface of the second n+ contact layer away from the n+ substrate is in contact with the surface of the second drain electrode facing the n+ substrate, and the third p+ connection structure is arranged between the second n+ contact layers; The surface of the gate dielectric layer facing the n+ substrate is in contact with the surface of the p- channel layer and the second n+ contact layer away from the n+ substrate, and the gate is arranged on the side of the gate dielectric layer away from the n+ substrate and is spaced apart from the second drain electrode.

7. The solid state circuit breaker of claim 6, wherein, The pJFET further comprises a third n+ contact layer, which is embedded in the second p-type well structure at least on the side away from the n+ substrate, and the third n+ contact layer is in contact with the p- channel layer.

8. The solid state circuit breaker of claim 7, wherein, The third n+ contact layer is also embedded in the second p+ connection structure on the side close to the second drain electrode, and the third n+ contact layer is in contact with the second source electrode.

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