A light emitting diode chip and a method of manufacturing the same

Abstract

The application discloses a light-emitting diode chip and a preparation method thereof. In the preparation method of the light-emitting diode chip, the thickness of an Nth quantum well layer is greater than that of a first quantum well layer, the Nth quantum well layer is subjected to a patterning treatment to form a plurality of first grooves, inorganic scattering particles are filled in the plurality of first grooves, a P-type semiconductor layer is subjected to a patterning treatment to form a plurality of second grooves, and organic scattering particles are filled in the plurality of second grooves. The first grooves and the second grooves are arranged in cooperation, and then the inorganic scattering particles and the organic scattering particles are filled respectively. The light emitted by the quantum well light-emitting layer is scattered by the inorganic scattering particles and the organic scattering particles, so that the light-emitting diode chip has high light-emitting efficiency, and the light-emitting angle of the light-emitting diode chip is widened.

Description

Technical Field

[0001] This invention relates to the field of semiconductor light-emitting technology, specifically to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Gallium nitride (GaN)-based light-emitting diode (LED) wafers are core materials in modern semiconductor lighting and display technologies, becoming the mainstream choice in these fields due to their high efficiency, long lifespan, and environmental friendliness. Traditional LED wafers mainly consist of a growth substrate, on which a buffer layer, a silicon-doped n-type GaN layer, an alternating InGaN / GaN multi-quantum-well active layer, a magnesium-doped p-type GaN layer, and a transparent conductive layer are sequentially grown. In the LED chip fabrication process, the LED wafer undergoes photolithography and etching to define the device structure of each individual LED chip. Then, metal electrodes and passivation layers are deposited via electron beam evaporation or sputtering to prevent electrode oxidation and leakage. Finally, the LED wafer is laser-cut or diamond-bladed, and qualified LED chips are sorted. Improving the LED chip fabrication process and optimizing its structure to enhance its light extraction efficiency has attracted widespread attention. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this application provides a light-emitting diode chip and a method for fabricating the same.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] An embodiment of this application provides a method for fabricating a light-emitting diode (LED) chip, the method comprising the following steps:

[0006] Provide substrate.

[0007] A buffer layer, an undoped semiconductor layer, an N-type semiconductor layer, and a quantum well light-emitting layer are sequentially grown on the substrate. The quantum well light-emitting layer includes an N-layer quantum well layer and an N-1-layer quantum barrier layer, wherein the first quantum well layer contacts the N-type semiconductor layer, the Nth quantum well layer covers the N-1-layer quantum barrier layer, and the thickness of the Nth quantum well layer is greater than the thickness of the first quantum well layer, where N is an integer not less than 3.

[0008] The Nth quantum well layer is patterned to form a plurality of first grooves.

[0009] Inorganic scattering particles are filled into multiple of the first grooves.

[0010] Next, the Nth quantum well layer is planarized.

[0011] Next, a P-type semiconductor layer is grown on the Nth quantum well layer.

[0012] The P-type semiconductor layer is patterned to form a plurality of second grooves.

[0013] Organic scattering particles are filled into a plurality of the second grooves.

[0014] Next, a transparent conductive layer is formed on the P-type semiconductor layer.

[0015] In a preferred embodiment, before patterning the Nth quantum well layer, the ratio of the thickness of the Nth quantum well layer to the thickness of the first quantum well layer is 2-8.

[0016] In a preferred embodiment, during the patterning process of the Nth quantum well layer to form a plurality of first grooves, the plurality of first grooves are randomly arranged, and the ratio of the depth of the first groove to the thickness of the Nth quantum well layer is 0.3-0.5, and the ratio of the total area of ​​the plurality of first grooves to the area of ​​the upper surface of the Nth quantum well layer is 0.3-0.6.

[0017] In a preferred embodiment, an inorganic scattering particle layer is formed on the surface of the Nth quantum well layer by a spraying process, thereby allowing some of the inorganic scattering particles to fill the first groove. The inorganic scattering particles are titanium dioxide nanoparticles or silicon dioxide nanoparticles.

[0018] In a preferred embodiment, the Nth quantum well layer is planarized to remove a portion of the Nth quantum well layer, thereby allowing inorganic scattering particles to fill only the first groove.

[0019] In a preferred embodiment, during the patterning process of the P-type semiconductor layer to form a plurality of second grooves, the plurality of second grooves are randomly arranged, and the ratio of the depth of the second groove to the thickness of the P-type semiconductor layer is 0.2-0.6, and the ratio of the total area of ​​the plurality of second grooves to the area of ​​the upper surface of the P-type semiconductor layer is 0.3-0.6.

[0020] In a preferred embodiment, an organic scattering particle layer is formed on the surface of the P-type semiconductor layer by a spraying process, thereby allowing some of the organic scattering particles to fill the second groove. The organic scattering particles are PMMA nano-scattering particles or PS nano-scattering particles.

[0021] In a preferred embodiment, before forming a transparent conductive layer on the P-type semiconductor layer, the P-type semiconductor layer is planarized to remove part of the P-type semiconductor layer, thereby allowing the organic scattering particles to fill only the second groove.

[0022] The present invention also proposes a light-emitting diode chip, wherein the light-emitting diode chip is prepared by the above-described method for preparing a light-emitting diode chip.

[0023] Compared with the prior art, the light-emitting diode chip and its fabrication method of the present invention have the following beneficial effects: In the fabrication method of the light-emitting diode chip of the present invention, by setting the thickness of the Nth quantum well layer to be greater than the thickness of the first quantum well layer, the Nth quantum well layer is patterned to form a plurality of first grooves, and inorganic scattering particles are filled in the plurality of first grooves. Furthermore, by patterning the P-type semiconductor layer, a plurality of second grooves are formed, and organic scattering particles are filled in the plurality of second grooves. The combination of the first grooves and the second grooves, and the filling of inorganic scattering particles and organic scattering particles respectively, allows the light emitted by the quantum well light-emitting layer to be scattered by the inorganic scattering particles and organic scattering particles, which can greatly increase the light extraction efficiency of the light-emitting diode chip and is beneficial to expanding the light extraction angle of the light-emitting diode chip. Furthermore, by optimizing the ratio of the thickness of the Nth quantum well layer to the thickness of the first quantum well layer to 2-8, multiple first grooves are randomly arranged, and the ratio of the depth of the first groove to the thickness of the Nth quantum well layer is 0.3-0.5, the ratio of the total area of ​​the multiple first grooves to the area of ​​the upper surface of the Nth quantum well layer is 0.3-0.6, multiple second grooves are randomly arranged, and the ratio of the depth of the second groove to the thickness of the P-type semiconductor layer is 0.2-0.6, the ratio of the total area of ​​the multiple second grooves to the area of ​​the upper surface of the P-type semiconductor layer is 0.3-0.6. Through the above settings, the lifespan of the light-emitting diode chip can be increased and the stability of the light-emitting diode chip can be improved. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure in this application in which a buffer layer, an undoped semiconductor layer, an N-type semiconductor layer, and a quantum well light-emitting layer are grown sequentially on a substrate.

[0026] Figure 2This is a schematic diagram of the structure in this application where the Nth quantum well layer is patterned to form multiple first grooves.

[0027] Figure 3 This is a schematic diagram of the structure in this application where inorganic scattering particles are filled in multiple first grooves.

[0028] Figure 4 This is a schematic diagram of the structure in this application where a P-type semiconductor layer is grown on the Nth quantum well layer.

[0029] Figure 5 This is a schematic diagram of the structure in this application where a P-type semiconductor layer is patterned to form multiple second groove layers.

[0030] Figure 6 This is a schematic diagram of the structure in this application where multiple second grooves are filled with organic scattering particles.

[0031] Figure 7 This is a schematic diagram of the structure in this application where a transparent conductive layer is formed on a P-type semiconductor layer.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100, Substrate; 200, Buffer layer; 300, Undoped semiconductor layer; 400, N-type semiconductor layer; 501, First quantum well layer; 502, Quantum barrier layer; 503, Nth quantum well layer; 5031, First groove; 600, Inorganic scattering particles; 700, P-type semiconductor layer; 701, Second groove; 800, Organic scattering particles; 900, Transparent conductive layer. Detailed Implementation

[0034] The following detailed description of the embodiments of this application, in conjunction with the accompanying drawings, will provide a thorough understanding of how this application uses technical means to solve technical problems and achieve corresponding technical effects, enabling its implementation. The embodiments of this application and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this application. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that although the terms "first," "second," "third," etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0036] It should be understood that spatial relation terms such as "above," "located above," "below," "located below," etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as "below other elements" will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Embodiments of this application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, fabrication techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shape of the region shown herein, but should include shape deviations due to, for example, fabrication processes.

[0039] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0040] An embodiment of this application provides a method for fabricating a light-emitting diode (LED) chip, the method comprising the following steps:

[0041] like Figure 1 As shown, a substrate 100 is provided, which may be a sapphire substrate, a silicon substrate or a silicon carbide substrate. In a specific embodiment of the present invention, the substrate 100 is a sapphire substrate.

[0042] like Figure 1As shown, a buffer layer 200, an undoped semiconductor layer 300, an N-type semiconductor layer 400, and a quantum well light-emitting layer are sequentially grown on the substrate. The quantum well light-emitting layer includes an N-layer quantum well layer and an N-1-layer quantum barrier layer 502 that are alternately arranged. The first quantum well layer 501 contacts the N-type semiconductor layer 400, the Nth quantum well layer 503 covers the N-1-layer quantum barrier layer 502, and the thickness of the Nth quantum well layer 503 is greater than the thickness of the first quantum well layer 501. Here, N is an integer not less than 3.

[0043] In a specific embodiment, aluminum nitride is formed as a buffer layer 200 by magnetron sputtering. The specific conditions of the magnetron sputtering process are as follows: pure aluminum palladium material is selected, inert argon gas is introduced as the sputtering gas, and nitrogen gas is introduced as the nitrogen source and oxygen source. The magnetron sputtering frequency is adjusted to 1000-2000W, the magnetron sputtering temperature is adjusted to 300-500℃, and the gas pressure in the chamber is 0.1-1Pa during the sputtering process, so as to grow aluminum nitride with a thickness of 50-200 nanometers. In a more specific embodiment, the magnetron sputtering frequency is adjusted to 1000W, 1200W, 1400W, 1600W, 1800W or 2000W, and the magnetron sputtering temperature is adjusted to 300℃, 330℃, 360℃, 390℃, 420℃, 450℃, 480℃, 510℃, 540℃, 570℃ or 600℃. During sputtering, the gas pressure in the chamber is 0.1Pa, 0.2Pa, 0.4Pa, 0.6Pa, 0.8Pa or 1Pa to grow aluminum nitride with a thickness of 50 nm, 70 nm, 90 nm, 120 nm, 150 nm, 180 nm or 200 nm.

[0044] In a specific embodiment, the undoped semiconductor layer 300 may be an undoped gallium nitride layer or an undoped aluminum gallium nitride layer, and the N-type semiconductor layer 400 may be an N-type gallium nitride layer or an N-type aluminum gallium nitride layer. The undoped semiconductor layer 300 and the N-type semiconductor layer 400 are formed by metal-organic chemical vapor deposition.

[0045] In a specific embodiment, the quantum well light-emitting layer includes an N-layer quantum well layer and an N-1-layer quantum barrier layer 502 arranged alternately. The first quantum well layer 501 contacts the N-type semiconductor layer 400, the Nth quantum well layer 503 covers the N-1-layer quantum barrier layer 502, and the thickness of the Nth quantum well layer 503 is greater than the thickness of the first quantum well layer 501. N is an integer not less than 3, specifically N can be 5-20. The quantum well layer can be an InGaN quantum well layer or an AlGaN quantum well layer, and correspondingly, the quantum barrier layer can be a GaN quantum barrier layer or an AlGaN quantum barrier layer. Accordingly, the quantum well light-emitting layer is formed by metal-organic chemical vapor deposition.

[0046] In a specific embodiment, before patterning the Nth quantum well layer 503, the ratio of the thickness of the Nth quantum well layer 503 to the thickness of the first quantum well layer 501 is 2-8. More specifically, the ratio of the thickness of the Nth quantum well layer 503 to the thickness of the first quantum well layer 501 is 2, 3, 5 or 8.

[0047] like Figure 2 As shown, the Nth quantum well layer 503 is patterned to form a plurality of first grooves 5031.

[0048] In a specific embodiment, the Nth quantum well layer 503 is patterned using a wet etching process or a dry etching process. During the patterning process of the Nth quantum well layer 503 to form a plurality of first grooves, the plurality of first grooves are randomly arranged, and the ratio of the depth of the first groove to the thickness of the Nth quantum well layer is 0.3-0.5, and the ratio of the total area of ​​the plurality of first grooves to the area of ​​the upper surface of the Nth quantum well layer is 0.3-0.6. More specifically, the ratio of the total area of ​​the plurality of first grooves to the area of ​​the upper surface of the Nth quantum well layer is 0.3, 0.4, 0.5 or 0.6.

[0049] like Figure 3 As shown, inorganic scattering particles 600 are filled in a plurality of the first grooves 5031.

[0050] In a specific embodiment, an inorganic scattering particle layer is formed on the surface of the Nth quantum well layer 503 by a spraying process, thereby allowing some inorganic scattering particles 600 to fill the first groove 5031. The inorganic scattering particles 600 are titanium dioxide nanoparticles or silicon dioxide nanoparticles.

[0051] Next, the Nth quantum well layer 503 is planarized. In a specific embodiment, the planarization is performed by a chemical mechanical polishing process. By planarizing the Nth quantum well layer 503, a portion of the Nth quantum well layer 503 is removed, thereby ensuring that the inorganic scattering particles 600 fill only the first groove 5031.

[0052] like Figure 4 As shown, a P-type semiconductor layer 700 is then grown on the Nth quantum well layer 503.

[0053] In a specific embodiment, the P-type semiconductor layer 700 may be a P-type gallium nitride layer or a P-type aluminum gallium nitride layer, and the P-type semiconductor layer 700 is formed by metal-organic chemical vapor deposition technology. More specifically, the P-type semiconductor layer 700 is epitaxially grown at 900-950°C.

[0054] like Figure 5 As shown, the P-type semiconductor layer 700 is patterned to form a plurality of second grooves 701.

[0055] In a specific embodiment, during the process of patterning the P-type semiconductor layer 700 to form a plurality of second grooves 701, the plurality of second grooves 701 are randomly arranged, and the ratio of the depth of the second groove 701 to the thickness of the P-type semiconductor layer 700 is 0.2-0.6, and the ratio of the total area of ​​the plurality of second grooves 701 to the area of ​​the upper surface of the P-type semiconductor layer 700 is 0.3-0.6.

[0056] In a specific embodiment, the Nth quantum well layer 503 is patterned using a wet etching process or a dry etching process, such that the ratio of the depth of the second groove 701 to the thickness of the P-type semiconductor layer 700 is 0.2-0.4 or 0.4-0.6, and the ratio of the total area of ​​the plurality of second grooves 701 to the area of ​​the upper surface of the P-type semiconductor layer 700 is 0.3, 0.4, 0.5 or 0.6.

[0057] like Figure 6 As shown, organic scattering particles 800 are filled in a plurality of second grooves 701.

[0058] In a specific embodiment, an organic scattering particle layer is formed on the surface of the P-type semiconductor layer 700 by a spraying process, thereby allowing some of the organic scattering particles to fill the second groove. The organic scattering particles are PMMA nano-scattering particles or PS nano-scattering particles. Furthermore, the P-type semiconductor layer 700 is planarized to remove part of the P-type semiconductor layer 700, thereby allowing the organic scattering particles to fill only the second groove 701.

[0059] like Figure 7 As shown, a transparent conductive layer 900 is then formed on the P-type semiconductor layer 700.

[0060] In a specific embodiment, ITO or AZO is formed as a transparent conductive layer 900 by low-temperature deposition technology. More specifically, it is formed by any suitable process such as magnetron sputtering or electron beam evaporation, and the deposition temperature is not higher than 300°C. After deposition, a low-temperature annealing treatment is performed, and the annealing temperature is also not higher than 300°C.

[0061] like Figure 7 As shown, the present invention also proposes a light-emitting diode chip, which is prepared by the above-described method for preparing a light-emitting diode chip.

[0062] An embodiment of this application provides a method for fabricating a light-emitting diode (LED) chip, the method comprising the following steps:

[0063] Provide substrate.

[0064] A buffer layer, an undoped semiconductor layer, an N-type semiconductor layer, and a quantum well light-emitting layer are sequentially grown on the substrate. The quantum well light-emitting layer includes an N-layer quantum well layer and an N-1-layer quantum barrier layer, wherein the first quantum well layer contacts the N-type semiconductor layer, the Nth quantum well layer covers the N-1-layer quantum barrier layer, and the thickness of the Nth quantum well layer is greater than the thickness of the first quantum well layer, where N is an integer not less than 3.

[0065] The Nth quantum well layer is patterned to form a plurality of first grooves.

[0066] Inorganic scattering particles are filled into multiple of the first grooves.

[0067] Next, the Nth quantum well layer is planarized.

[0068] Next, a P-type semiconductor layer is grown on the Nth quantum well layer.

[0069] The P-type semiconductor layer is patterned to form a plurality of second grooves.

[0070] Organic scattering particles are filled into a plurality of the second grooves.

[0071] Next, a transparent conductive layer is formed on the P-type semiconductor layer.

[0072] Furthermore, before patterning the Nth quantum well layer, the ratio of the thickness of the Nth quantum well layer to the thickness of the first quantum well layer is 2-8.

[0073] Furthermore, during the patterning process of the Nth quantum well layer to form a plurality of first grooves, the plurality of first grooves are randomly arranged, and the ratio of the depth of the first groove to the thickness of the Nth quantum well layer is 0.3-0.5, and the ratio of the total area of ​​the plurality of first grooves to the area of ​​the upper surface of the Nth quantum well layer is 0.3-0.6.

[0074] Furthermore, an inorganic scattering particle layer is formed on the surface of the Nth quantum well layer through a spraying process, thereby allowing some of the inorganic scattering particles to fill the first groove. The inorganic scattering particles are titanium dioxide nanoparticles or silicon dioxide nanoparticles.

[0075] Furthermore, by planarizing the Nth quantum well layer, a portion of the Nth quantum well layer is removed, thereby ensuring that the inorganic scattering particles fill only the first groove.

[0076] Furthermore, during the process of patterning the P-type semiconductor layer to form a plurality of second grooves, the plurality of second grooves are randomly arranged, and the ratio of the depth of the second groove to the thickness of the P-type semiconductor layer is 0.2-0.6, and the ratio of the total area of ​​the plurality of second grooves to the area of ​​the upper surface of the P-type semiconductor layer is 0.3-0.6.

[0077] Furthermore, an organic scattering particle layer is formed on the surface of the P-type semiconductor layer through a spraying process, thereby allowing some of the organic scattering particles to fill the second groove. The organic scattering particles are PMMA nano-scattering particles or PS nano-scattering particles.

[0078] Furthermore, before forming a transparent conductive layer on the P-type semiconductor layer, the P-type semiconductor layer is planarized to remove part of the P-type semiconductor layer, thereby allowing the organic scattering particles to fill only the second groove.

[0079] The present invention also proposes a light-emitting diode chip, wherein the light-emitting diode chip is prepared by the above-described method for preparing a light-emitting diode chip.

[0080] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a light-emitting diode chip, characterized in that: The method for fabricating the light-emitting diode chip includes the following steps: Provide substrate; A buffer layer, an undoped semiconductor layer, an N-type semiconductor layer, and a quantum well light-emitting layer are sequentially grown on the substrate. The quantum well light-emitting layer includes an N-layer quantum well layer and an N-1-layer quantum barrier layer, wherein the first quantum well layer contacts the N-type semiconductor layer, the Nth quantum well layer covers the N-1-layer quantum barrier layer, and the thickness of the Nth quantum well layer is greater than the thickness of the first quantum well layer, where N is an integer not less than 3. The Nth quantum well layer is patterned to form a plurality of first grooves; Inorganic scattering particles are filled into multiple first grooves; Next, the Nth quantum well layer is planarized. Next, a P-type semiconductor layer is grown on the Nth quantum well layer; The P-type semiconductor layer is patterned to form a plurality of second grooves; Organic scattering particles are filled into multiple second grooves; Next, a transparent conductive layer is formed on the P-type semiconductor layer.

2. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that: Before patterning the Nth quantum well layer, the ratio of the thickness of the Nth quantum well layer to the thickness of the first quantum well layer is 2-8.

3. The method for fabricating a light-emitting diode chip according to claim 2, characterized in that: During the patterning process of the Nth quantum well layer to form a plurality of first grooves, the plurality of first grooves are randomly arranged, and the ratio of the depth of the first groove to the thickness of the Nth quantum well layer is 0.3-0.5, and the ratio of the total area of ​​the plurality of first grooves to the area of ​​the upper surface of the Nth quantum well layer is 0.3-0.

6.

4. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that: An inorganic scattering particle layer is formed on the surface of the Nth quantum well layer by a spraying process, thereby allowing some of the inorganic scattering particles to fill the first groove. The inorganic scattering particles are titanium dioxide nanoparticles or silicon dioxide nanoparticles.

5. The method for fabricating a light-emitting diode chip according to claim 4, characterized in that: By planarizing the Nth quantum well layer, a portion of the Nth quantum well layer is removed, thereby allowing inorganic scattering particles to fill only the first groove.

6. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that: During the process of patterning the P-type semiconductor layer to form a plurality of second grooves, the plurality of second grooves are randomly arranged, and the ratio of the depth of the second groove to the thickness of the P-type semiconductor layer is 0.2-0.6, and the ratio of the total area of ​​the plurality of second grooves to the area of ​​the upper surface of the P-type semiconductor layer is 0.3-0.

6.

7. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that: An organic scattering particle layer is formed on the surface of the P-type semiconductor layer by a spraying process, thereby allowing some of the organic scattering particles to fill the second groove. The organic scattering particles are PMMA nano-scattering particles or PS nano-scattering particles.

8. The method for fabricating a light-emitting diode chip according to claim 7, characterized in that: Before forming a transparent conductive layer on the P-type semiconductor layer, the P-type semiconductor layer is planarized to remove part of the P-type semiconductor layer, thereby allowing the organic scattering particles to fill only the second groove.

9. A light-emitting diode chip, characterized in that, The light-emitting diode chip is prepared by the method for preparing a light-emitting diode chip according to any one of claims 1-8.

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