Time-to-digital converter (TDC) employing single stage delay pair and noise shaping to achieve wide input range and reduction of quantization noise in phase locked loop (PLL)

Abstract

A time-to-digital converter (TDC) employing a single stage delay pair to achieve a wide input range and reduce quantization noise in a phase-locked loop (PLL), and related methods of manufacture are disclosed. Aspects disclosed in particular embodiments include a single stage Vernier time-to-digital converter (TDC) that mitigates the effects of device mismatch, thereby avoiding spurious tones that may occur in fractional-N PLL applications. In combination with the delta-sigma noise shaping stage and the rough TDC based on the ring oscillator, good balance among the resolution, the detection range and the PLL locking speed is realized.

Description

TECHNICAL FIELD

[0001] The technology of the present disclosure relates generally to phase-locked loops, and more particularly, to a time-to-digital converter that provides fast locking and low noise. BACKGROUND

[0002] Phase-locked loops (PLLs) are widely used to generate a signal that continues to oscillate at a desired frequency and with as little noise as possible. For example, a PLL can be used to generate a carrier signal for wired or wireless communication or a system clock for clocking digital logic in an integrated circuit. As improvements in integrated circuit (IC) fabrication processes continue to shrink feature sizes, the advantages of using a digital PLL (DPLL) become more apparent. One of the components in a DPLL that can significantly affect the quality of the generated output signal is a time-to-digital converter (TDC) circuit. In a PLL, the TDC circuit receives two signals (e.g., rising edges) that are separated by a time period related to the phase difference between the generated output signal and a reference signal. The TDC circuit converts the time period to an integer that is used to adjust the control of a numerically controlled oscillator that generates the output signal.

[0003] Since the purpose of a DPLL is to keep the phase of the output signal always close to the phase of the reference signal, it is preferable to measure the time difference in fine increments (e.g., with higher resolution) to detect smaller changes. On the other hand, when the DPLL is initially powered on, the phases of the output signal and the reference signal can be far apart. Measuring a large amount of time in very small increments can require a large amount of circuitry, which can take up area on the IC and consume power. If the DPLL cannot determine the phase difference between the output signal and the reference signal, it can take a longer time to synchronize the output signal with the reference signal when powered on. Thus, in this regard, it is preferable to increase the size of the time measurement increments, which can reduce the amount of circuitry.

[0004] A conventional Vernier TDC uses two sets of delay circuits to measure the time difference, but the number of stages required to give a given input range increases with resolution. Furthermore, if the delay of the delay stages is not consistent due to, for example, process variations, noise (e.g., spurs) can be generated on the output signal. Another option to reduce the amount of circuitry and avoid delay inconsistencies is to use a single-stage Vernier TDC, which includes a single delay stage used in a feedback method. However, the delay time of the single-stage delay affects the input range and resolution of the TDC circuit, which are contradictory requirements. Thus, it is desirable to have a TDC circuit that has a wide detection range without sacrificing resolution. SUMMARY

[0005] Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) that achieves a wide input range and reduces quantization noise in a phase-locked loop (PLL). Methods of a fast-locking DPLL with low spurious tone are also disclosed.

[0006] The ability of the TDC circuit to track the reference signal is critical to the PLL. Vernier TDCs are a well-known design that require the use of long strings of delay circuits, which take up area, consume power, and can cause noise in the output signal due to delay inconsistencies. The single-stage TDC employs the concept of a Vernier TDC, but uses a single-stage delay pair in the feedback loop to reduce circuitry and avoid delay inconsistencies. Because the TDC measures a time period in increments with a certain resolution, there is necessarily a residual portion (e.g., a time remainder) that cannot be reflected in the integer generated by the TDC. In an example TDC circuit, a first measurement circuit determines an integer number of time increments in the time period and a remainder, and a second measurement circuit generates a fraction indicator that indicates whether the accumulation of the time remainder and a previous time remainder exceeds an integer number of time increments. In some examples, the fraction indicator can be used in a PLL to increase the resolution of the TDC, providing more frequent and finer adjustments to a digitally controlled oscillator (DCO). In this way, the TDC circuit can have a wider detection range while pushing quantization noise to a higher frequency range that can be filtered out by the PLL.

[0007] In this regard, a time-to-digital converter (TDC) circuit is disclosed. The TDC circuit includes a first measurement circuit configured to: receive a start pulse signal and a stop pulse signal that are separated in time by a time period; determine an integer number of first time increments that are consecutive in the time period; and determine that a time remainder of the time period is less than the first time increment (step size). The TDC circuit also includes a second measurement circuit configured to: add the time remainder to a previous accumulated remainder to generate a current accumulated remainder; and generate a fraction indicator that indicates whether a magnitude (positive or negative) of the current accumulated remainder is greater than half of the first time increment (step size). Further, in response to the fraction indicator indicating that the magnitude of the current accumulated remainder is greater than half of the first time increment, a next accumulated remainder is generated that includes a difference between the first time increment and the current accumulated remainder, and in response to the fraction indicator indicating that the magnitude of the current accumulated remainder is less than half of the first time increment, the next accumulated remainder is generated that includes the current accumulated remainder.

[0008] In another aspect, a method of a TDC circuit is disclosed. The method includes receiving a start pulse signal and a stop pulse signal separated in time by a time period, determining an integer number of first time increments and a time remainder in the time period that is less than the first time increment, adding the time remainder to a previous accumulated remainder to generate a current accumulated remainder, and generating a fractional indicator that indicates whether the current accumulated remainder differs from the first time increment by more than half of the first time increment. The method further includes generating a next accumulated remainder that includes a difference between the first time increment and the current accumulated remainder in response to the fractional indicator indicating that the current accumulated remainder differs from the first time increment by more than half of the first time increment, and generating the next accumulated remainder based on the current accumulated remainder in response to the fractional indicator indicating that the current accumulated remainder differs from the first time increment by less than half of the first time increment.

[0009] In another aspect, a phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a digitally controlled oscillator (DCO), a loop filter circuit, a frequency divider circuit, and a time-to-digital (TDC) system. The TDC system includes a coarse TDC circuit and a fine TDC circuit. The fine TDC circuit includes a first measurement circuit configured to receive a start pulse signal and a stop pulse signal separated in time by a time period, determine an integer number of consecutive first time increments in the time period, and determine that a time remainder of the time period is less than one of the first time increments. The fine TDC circuit further includes a second measurement circuit configured to add the time remainder to a previous accumulated remainder to generate a current accumulated remainder, generate a fractional indicator that indicates whether a magnitude of the current accumulated remainder is greater than half of the first time increment, and generate a next accumulated remainder that includes a difference between the first time increment and the current accumulated remainder in response to the fractional indicator indicating that the magnitude of the current accumulated remainder is greater than half of the first time increment, and generate the next accumulated remainder that includes the current accumulated remainder in response to the fractional indicator indicating that the magnitude of the current accumulated remainder is less than half of the first time increment. The PLL circuit further includes a range determination circuit configured to determine whether a duration of the time period is within a time period range, and generate an integer corresponding to the duration of the time period in the coarse TDC circuit in response to determining that the duration of the time period is greater than a maximum time period within the time period range, and generate an integer corresponding to the time period in the fine TDC in response to determining that the duration of the time period is within the time period range. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1is a block diagram of an exemplary time-to-digital (TDC) system including an exemplary TDC circuit having a first measurement circuit for determining the number of time increments in a time period and a second measurement circuit for accumulating remainders and generating an indicator of a fraction of the time increment to reduce quantization noise in a PLL;

[0011] Figure 2 is a block diagram showing an example of a phase-locked loop (PLL), including Figure 1 An exemplary TDC circuit of the present invention has a first measurement circuit for determining the number of time increments in a time period and a second measurement circuit for accumulating remainders and generating an indicator of a fraction of the time increment to reduce quantization noise in a PLL;

[0012] Figure 3 yes Figure 1 a flowchart of a method of an exemplary TDC circuit in accordance with an embodiment of the present invention, the method determining a number of time increments in a time period, accumulating remainders, and generating an indicator of a fraction of the time increment;

[0013] Figure 4 It shows Figure 1 a logic circuit diagram showing details of a first measurement circuit in a TDC in the embodiment of the present invention, the first measurement circuit being configured to determine the number of time increments in a time period and to provide a time remainder to a second measurement circuit;

[0014] Figure 5 It shows Figure 4 a timing diagram showing the operation of the first measurement circuit in an example of two reference cycles of a reference clock;

[0015] Figure 6A It shows Figure 1 a logic circuit diagram of details of a second measurement circuit in the TDC of the embodiment of the present invention for adding the remainder from the first measurement circuit to the previous accumulated remainder, generating a fractional indicator for higher resolution, and calculating the next accumulated remainder;

[0016] Figure 6B is a logic diagram showing an analog adder circuit for adding a remainder from a first measurement circuit to a previously accumulated remainder;

[0017] Figure 7 is a timing diagram showing the Figure 1 In the TDC circuit, the time margin from the first measurement circuit is added to the previous cumulative margin to generate a current cumulative margin, and if the current cumulative margin exceeds the fractional portion of the time increment, the time increment is subtracted from the current cumulative margin to generate a next cumulative margin.

[0018] Figure 8is a logic circuit diagram of a calibration circuit for calibrating Figure 4 the timing resolution of a first measurement circuit

[0019] Figure 9 is a timing diagram showing the signals of the calibration circuit Figure 8 during the calibration process

[0020] Figure 10 is a block diagram of an exemplary processor-based system that can include a PLL, as shown in Figure 1 , Figure 4 , Figure 6A , and Figure 6B the PLL includes a TDC circuit in a TDC system. DETAILED DESCRIPTION

[0021] Several exemplary aspects of the disclosure are now described, with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] Aspects disclosed in the DETAILED DESCRIPTION include a single-stage Vernier time-to-digital converter (TDC) for achieving a wide input range and reduced quantization noise in a phase-locked loop (PLL). Methods of a fast-locking DPLL with low spurious tones are also disclosed.

[0023] In this regard, Figure 1 is a block diagram of an exemplary time-to-digital (TDC) system 100 in an integrated circuit chip 101, including an exemplary TDC circuit 102 having a first measurement circuit 104 to determine an integer 106 that indicates an integer number of time increments T1 in a time period TP between a start pulse signal START and a stop pulse signal STOP. The time period TP between the start pulse signal START and the stop pulse signal STOP is equal to a time period TP between a reference clock C REF and a feedback clock C FB However, as described below, even if the reference clock C REF can be leading or lagging the feedback clock C FB , the start pulse signal START will be leading the stop pulse signal STOP.

[0024] The first measurement circuit 104 generates a time remainder TR as the remainder of the time period TP, and the time remainder TR is less than the time increment TI. In the example, TP=N(TI)+TR, where N is an integer 106. The time remainder TR is sometimes referred to as the residual time. The TDC circuit 102 also includes a second measurement circuit 108 that generates a fraction indicator 110 based on the sum of the time remainder TR and a previous cumulative remainder PAR (not shown here) to indicate whether the current cumulative remainder CAR (not shown) exceeds the fraction of the time increment TI.

[0025] In further detail Figure 1 Before the TDC system 100 is described, first refer to Figure 2 An example of a phase locked loop (PLL) 200 in which the TDC system 100 may be employed is described. The first measurement circuit 104 and the second measurement circuit 108 of the TDC circuit 102 will be referred to as Figure 4-7 is described in further detail.

[0026] Figure 2 The PLL 200 in FIG. 1 is an example of a TDC system 100 that may be employed including the TDC circuit 102. The PLL 200 includes a digitally controlled oscillator (DCO) 202 that generates a signal at an output frequency F OUT Oscillating output clock signal C OUT . Output clock signal C OUT It can be a carrier signal for wired or wireless communication, or it can be a system clock in a digital logic circuit such as IC chip 101. For such applications, it is desirable to output a clock signal C OUT To improve phase and frequency consistency, PLL 200 receives a reference clock signal C REF , the reference clock signal C REF For example, it can come from a crystal oscillator or other reliable, consistent source to be used with the output clock signal C OUT Output frequency F OUT Can be different from the reference clock signal C REF Reference frequency F REF For example, the output frequency F OUT It can be the reference frequency F REF The PLL 200 includes a frequency divider circuit 204, which outputs a clock signal C OUT The output frequency F OUT Divide by X to produce a feedback frequency F FB The feedback clock signal C FB , for use with the reference clock signal C REF Make a comparison.

[0027] In some examples, the multiple X is non-integer, but the frequency divider circuit 204 is a multiple modulus divider (MMD) that can only divide by integers. The mismatch between X and the nearest integer generates significant noise in the output clock signal C OUT , so a dithering circuit (not shown) can be used to switch the integer divisor of the frequency divider circuit 204 between two or more integer values (e.g., between 10 and 11 for an average of 10.65) to obtain an average of a non-integer multiple. This type of dithering circuit increases the frequency accuracy compared to a PLL without a dithering circuit, but still generates noise in the output clock signal C OUT . PLLs that include the TDC system 100 and the TDC circuit 102 in Figure 1 , with or without a dithering circuit coupled to the frequency divider circuit, can reduce the noise in the output clock signal C OUT by pushing the quantization noise out of the PLL bandwidth, where it can be effectively filtered.

[0028] With further reference to Figure 2 , the PLL 200 can receive the reference clock signal C REF and the feedback clock signal C FB as the start pulse signal START and the stop pulse signal STOP. In some examples, the PLL 200 includes a phase frequency detector (PFD) 206 in addition to the TDC 208. The TDC 208 can be the TDC system 100 including the TDC circuit 102 in Figure 1 . In examples that include the PFD 206, the PFD 206 receives the reference clock signal C REF and the feedback clock signal C FB , compares the phase of the feedback clock signal C FB to the phase of the reference clock signal C REF , and generates the start pulse signal START and the stop pulse signal STOP that indicate a phase difference as a time period TP. As an example, the PFD 206 generates the start pulse signal START as a pulse (e.g., a voltage step) with a rising edge and the stop pulse signal STOP as a pulse with a rising edge such that the two rising edges are separated in time by the time period TP corresponding to the phase difference. The TDC 208 generates an integer 210 that is a quantization of the time period TP. The integer 210 indicates a number of time increments in the time period TP and can be positive or negative. The integer 210 can change in each cycle of the reference clock signal C REF and is filtered by a loop filter 212. The loop filter 212 provides a filtered control signal 214 to the DCO 202 to control the frequency F of the output clock C OUT .OUT Integer 210 is based on the time / phase offset of the feedback clock C FB relative to the reference clock C REF , and is used by the DCO 202 to bring the phases closer together, ultimately achieving a "locked state" in which the phases of the reference clock signal C REF and the feedback clock signal C FB are the same or remain within a small (e.g., undetectable) range of phase difference.

[0029] Returning to Figure 1 , the TDC system 100 includes a range determination circuit 112 that receives the reference clock C REF and the feedback clock C FB separated by a time period TP. The range determination circuit 112 determines the sign of the time period TP in a sign detection circuit 114, and determines whether the duration of the time period TP is within the range of time periods of the TDC circuit 102. The time period TP has a negative sign if the feedback clock C REF is received at the TDC system 100 before the reference clock C FB . The time period TP has a positive sign if the reference clock C REF is received at the TDC system 100 before the feedback clock C REF . The sign detection circuit 114 generates a sign indicator SIGN that indicates the sign or polarity of the time period TP. If the sign indicator SIGN is positive, the start pulse signal START is based on the reference clock C REF and the stop pulse signal STOP is based on the feedback clock C FB . On the other hand, where the sign indicator SIGN is negative, a reordering circuit 116 in the range determination circuit 112 generates the start pulse signal START from the reference clock C REF and the stop pulse signal STOP from the feedback clock C FB . In this way, the start pulse signal START will reach the first measurement circuit 104 before the stop pulse signal STOP, regardless of the sign indicator SIGN.

[0030] The range determination circuit 112 includes a lower limit detector 118 and an upper limit detector 120. The lower limit detector 118 determines whether the time period TP separating the start pulse signal START and the stop pulse signal STOP is less than the time increment resolution of the TDC circuit 102. If so, the lower limit detector 118 generates a signal RST1 to reset the TDC circuit 102, preparing the TDC circuit 102 for the next start pulse signal START. In the example shown, if the time period TP is less than the minimum detectable time or resolution T RES, the lower limit detector 118 sets the flip-flop circuit DFF1 to a low level. Specifically, if the stop pulse signal STOP propagates through the first delay circuit 122 having a first delay period ("first delay") T1 before the start pulse signal START propagates through the second delay circuit 124 having a second delay period ("second delay") T2, the flip-flop circuit DFF1 is set to a low level, thereby generating the signal RST1. Therefore, T RES = T1 - T2. For example, if the time period TP is shorter than the resolution T that occurs in the locked state RES , then the TDC system 100 does not provide Figure 2 For example, if no adjustment is required, the integer 125 output from the TDC system 100 may be "0," which indicates that the output clock C OUT and reference clock C REF There is no positive or negative phase difference between them. It should be noted that this article uses a flip-flop circuit as an edge-triggered storage element, rather than a level-sensitive latch circuit. A flip-flop circuit (also referred to as a "flip-flop" in this article) can also be called a data flip-flop or an arbiter circuit.

[0031] The upper limit detector 120 determines whether the time period TP exceeds the maximum detection time of the TDC circuit 102, which corresponds to the maximum number of time increments TI that the TDC circuit 102 can detect in the time period TP. In this example, if the upper limit detector 120 determines that the time period TP exceeds the maximum detection time, it generates a signal RST2 to activate the coarse TDC circuit 127 and reset the TDC circuit 102, thereby preparing the TDC circuit 102 for the next start pulse signal START. In this case, if the stop pulse signal does not reach the flip-flop circuit DFF2 before the start pulse signal START propagates through the delays 126A and 126B, the flip-flop circuit DFF2 generates the signal RST2. When the output clock C OUT and reference clock C REF Coarse TDC circuit 127 may be initially activated immediately after power-up when the phase shift signals may be significantly out of phase. Coarse TDC circuit 127 is capable of measuring much larger time periods TP than TDC circuit 102, but with a much coarser resolution. TDC circuit 102 may be referred to as fine TDC circuit 102 relative to coarse TDC circuit 127 because it measures time periods at higher resolution time increments TI.

[0032] As an example, the resolution of the coarse TDC circuit 127 can be determined by the loop (e.g., ring oscillator) of the delay circuits 128(1)-128(3), each having a delay T3. Prior to receiving the stop pulse signal STOP, the counter 130 counts the number of times the start pulse signal START propagates through the loop of the delay circuits 128(1)-128(3). The coarse TDC circuit 127 generates an integer 132 that is indicative of the time period TP. The sign correction circuit 134 receives the sign indicator SIGN and converts the integer 132 to a negative number if the sign indicator SIGN is negative. It should be appreciated that the integer 132 generated by the coarse TDC circuit 127 can be identical to the integer 106 generated by the TDC circuit 102. In other words, the resolution difference between the time increment TI of the TDC circuit 102 and the time measured by the loop of the delay circuits 128 is accounted for in the generation of the integers 106 and 132.

[0033] The first measurement circuit 104 provides the time remainder TR as a time difference between a pulse on the first remainder input 135 and a pulse on the second remainder input 136 to the second measurement circuit 108.

[0034] The TDC system 100 includes an adder 138 for adding the integer 106 generated by the first measurement circuit 104 and the fraction indicator 110 generated by the second measurement circuit 108 to generate a high resolution integer 140. A sign flip-flop circuit 142 stores the sign indicator SIGN until the integer 106 is generated by the TDC circuit 102. If the SIGN generated in the sign flip-flop circuit 142 indicates that the time remainder TR is negative, a sign correction circuit 144 corrects the high resolution integer 140. A selector circuit 148 selects one of the high resolution integer 140 from the TDC circuit 102 and the integer 132 from the coarse TDC circuit 127 depending on the circuit employed. The term "flip-flop circuit" is used herein interchangeably with the terms "data flip-flop" or "flip-flop."

[0035] Figure 3 is Figure 1A flowchart of a method of the exemplary TDC circuit of FIG. 1 for determining a number of time increments Tl and a fraction of a time increment in a time period TP, the method including receiving a start pulse signal START and a stop pulse signal STOP separated in time by the time period TP (block 302), and determining an integer number 106 of first time increments Tl and a time remainder TR less than the first time increment Tl within the time period TP (block 304). The method includes adding the time remainder TR to a previous accumulated remainder PAR to generate a current accumulated remainder CAR (block 306), and generating a fraction indicator 110 indicating whether the difference between the current accumulated remainder and the first time increment is greater than a fraction of the first time increment Tl (block 308). The method further includes, in response to the fraction indicator 110 indicating that the difference between the current accumulated remainder CAR and the first time increment Tl is greater than the fraction of the first time increment Tl, generating a next accumulated remainder NAR including the difference between the first time increment Tl and the current accumulated remainder CAR (block 310), and in response to the fraction indicator 110 indicating that the difference between the current accumulated remainder CAR and the first time increment Tl is less than the fraction of the first time increment Tl, generating the next accumulated remainder NAR based on the current accumulated remainder CAR (block 312).

[0036] Figure 4 is a logic circuit diagram showing details of a first measurement circuit 400, which can be the first measurement circuit 104 in the TDC circuit 102 of FIG. 1. Figure 1 The first measurement circuit 400 is for determining a number of time increments Tl in a time period TP, and providing a time remainder TR to the second measurement circuit 108.

[0037] The first measurement circuit 400 employs a method similar to a Vernier TDC circuit (not shown) in which a start pulse signal propagates through a series of delay circuits each having a first delay Tl ("first delay period Tl") and a stop pulse signal propagates through a series of delay circuits each having a second delay T2 ("second delay period T2"). The second delay T2 is shorter than the first delay Tl, so the stop pulse signal eventually catches up with the start pulse signal after X delay circuits. From this, it can be determined that, in this example, the start pulse signal and the stop pulse signal are separated by a period of time that is at least X times (Tl - T2). In such a circuit, a first problem is that the time difference between the start pulse signal and the stop pulse signal can also include a time remainder that is less than Tl - T2, which cannot be measured by a Vernier circuit. The resolution of the time measurement by a Vernier circuit is limited to Tl - T2, so the time remainder can allow for a difference or error in the PLL that is less than Tl - T2. A second problem with a Vernier circuit is that the delay circuits in the first series can not all have exactly the same delay Tl due to, for example, process variations in manufacturing, and for the same reason, the delay circuits in the second series can not all have exactly the same delay T2, which can produce noise in the output clock generated by the PLL. The TDC circuit 102 solves both of these problems. The first problem is solved by the second measurement circuit 108 in Figure 1 will be described in detail with reference to FIG. 6. The second problem will be solved as described below.

[0038] The first measurement circuit 400 includes a first delay feedback circuit 402 that includes a first delay circuit 404 that receives the start pulse signal START at a first delay input 406. The first delay feedback circuit 402 employs the first delay circuit 404 to delay the start pulse signal START and generates a delayed start pulse signal DSTRT on a first delay output 408. The first delay circuit 404 has a delay with a duration of Tl. In this regard, the first delay circuit 404 corresponds to a stage in the first series of delay circuits in a Vernier circuit, but rather than passing the delayed start pulse signal DSTRT to the next delay circuit, the first delay feedback circuit 402 feeds back the delayed start pulse signal DSTRT from the first delay output 408 back to the first delay input 406 and reuses the first delay circuit 404 in an iterative manner.

[0039] In a similar aspect, the first measurement circuit 400 includes a second delay feedback circuit 410 that includes a second delay circuit 412 that receives the stop pulse signal STOP at a second delay input 414. The second delay feedback circuit 410 employs the second delay circuit 412 to delay the stop pulse signal STOP and generate a delayed stop pulse signal DSTP on a second delay output 416. The second delay circuit 412 has a delay of a duration T2 that is shorter than T1. Thus, the time increment TI (also referred to as the resolution T RES ) measured by the first measurement circuit 400 is T1-T2. In this regard, the second delay circuit 412 corresponds to a stage in a second series of delay circuits in a Vernier circuit, but the second delay feedback circuit 410 feeds back the delayed stop pulse signal DSTP from the second delay output 416 back to the second delay input 414 and iteratively reuses the second delay circuit 412. Employing the first delay feedback circuit 402 and the second delay feedback circuit 410 is because the first delay circuit 404 and the second delay circuit 412 are reused, there is no delay mismatch due to different cascaded units as in a conventional Vernier TDC. In this regard, the first measurement circuit 400 avoids spurious tones.

[0040] The first measurement circuit 400 includes a flip-flop circuit 418 having a data output 420 that is set when the delayed start pulse signal DSTRT is first provided to a data input 422 and the delayed stop pulse signal DSTP is first provided to a clock input 424. The data output 420 is reset in subsequent iterations when the delayed stop pulse signal DSTOP is generated on the second delay output 416 before the delayed start pulse signal DSTRT is generated on the first delay output 408. In other words, the flip-flop 418 is reset when the propagation of the delayed stop pulse signal DSTOP through the second delay feedback circuit 410 catches up to the propagation of the delayed start pulse signal DSTRT through the first delay feedback circuit 402.

[0041] The first measurement circuit 400 includes a counter circuit 426 that includes a counter 428 and a count flip-flop 430. A trigger flip-flop 432 in the first measurement circuit 400 is used to detect the transition of the count mode flip-flop 418 and trigger the generation of the time remainder TR, which is the difference between the first time remainder signal TRS1 on a first remainder output 434 and the second time remainder signal TRS2 on a second remainder output 436.

[0042] Further reference Figure 4 is made to the timing diagram 500 in Figure 5 to provide a description of additional features of the first measurement circuit 400 and its operation.Figure 5 is a timing diagram illustrating signals at certain points in the first measurement circuit 400. The signals are represented as binary values (e.g., "0" or low level and "1" or high level), which can represent voltage levels at the identified points in the first measurement circuit 400. The transitions between these binary values are referred to herein as rising and falling edges, e.g., where the passage of time is from left to right.

[0043] Specifically, starting from the top, the timing diagram 500 includes inputs 438 and 440, which receive a start pulse signal START and a stop pulse signal STOP, respectively. Figure 5 Next included are a first delay input 406, a second delay input 414, a first delay output 408, and a second delay output 416. Figure 5 Also included are a data output 420 of the count mode flip-flop 418 and a node 442 for triggering generation of the time remainder TR. Finally, Figure 5 Included are a first remainder output 434 and a second remainder output 436 that generate the time remainder TR.

[0044] As Figure 5 shown, a rising edge LI of the start pulse signal START, i.e., the moment at which the level of the start pulse signal START begins to rise, occurs at time to; at time ti, a rising edge L2 of the stop pulse signal STOP indicates a rise of the stop pulse signal STOP. The time between the rising edge of the start pulse signal START and the rising edge of the stop pulse signal STOP is the time period TP (i.e., TP = ti - to) that is measured by the first measurement circuit 400 in time increments TI. The start pulse signal START and the stop pulse signal STOP are received at a pulse generation circuit 444. The pulse generation circuit 444 respectively produces a wide pulse WP corresponding to the start pulse signal START on the first delay input 406 and a narrow pulse NP corresponding to the stop pulse signal STOP on the second delay input 414. The rise of the narrow pulse NP lags the rise of the wide pulse WP by the time period TP, but the narrow pulse NP and the wide pulse WP fall at the same time.

[0045] The wide pulse WP propagates through a first NOR gate (NOR circuit) Rl and a second NOR gate R2 before propagating through a first delay circuit 404 to a first delay output 408. The first delay output 408 is coupled to an input of an AND gate Al, which is further coupled back to the first NOR gate Rl. In this regard, a feedback loop is formed from the first delay output 408 back to the first delay input 406. The total first feedback loop time Tl_P from the first delay output 408, through the first delay feedback circuit 402, and back to the first delay output 408 includes the propagation delays through the NOR gates Rl and R2, the AND gate Al, and the first delay circuit 404.

[0046] The narrow pulse NP propagates through the third NOR gate R3 and the fourth NOR gate R4 before propagating through the second delay circuit 412 to the second delayed output 416. The second delayed output 416 is coupled to the input of another AND gate A2, which is further coupled back to the third NOR gate R3. At this point, a feedback loop is also formed from the second delayed output 416 back to the second delayed input 414. The total second feedback loop time T2_P through the second feedback delay circuit 410 includes the propagation delay through the NOR gates R3 and R4, the AND gate A2, and the second delay circuit 412.

[0047] The wide pulse WP on the first delay output 408 is also referred to as the delayed start pulse signal DSTART, and the narrow pulse NP on the second delay output 416 is also referred to as the delayed stop pulse signal DSTOP. The first delay output 408 is coupled to the data input 422 of the counting mode flip-flop 418, and the second delay output 416 is coupled to the clock input 424 of the counting mode flip-flop 418. Figure 1 The range determination circuit 112 in the embodiment (which includes a lower limit detector 118) determines the range provided to Figure 1 Time period TP of TDC circuit 102 in FIG4 is equal to or greater than T1-T2. Therefore, when wide pulse WP first propagates through first delay circuit 404 to first delayed output 408 (see time t2), the rising edge of wide pulse WP arrives at data input 422 before the rising edge of narrow pulse NP arrives at clock input 424 (see t3). Consequently, the rising edge of narrow pulse NP triggers count mode flip-flop 418, propagating wide pulse WP from data input 422 to data output 420. Second delayed output 416 is also coupled to counter 428 of counter circuit 426, such that after wide pulse WP has propagated through first delay circuit 404 to first delayed output 408, counter 428 increments each time narrow pulse NP propagates through second delay circuit 412 (see t3 and t4) to second delayed output 416. Counter 428 thus counts iterations of narrow pulse NP through second delayed feedback circuit 410. The number of iterations is provided to count flip-flop 430 at node 446.

[0048] When the wide pulse WP and the narrow pulse NP are iteratively fed back through the first delay feedback circuit 402 and the second delay feedback circuit 410, respectively, the data output 420 remains high. Because the delay T2 of the second delay feedback circuit 410 is shorter than the delay Tl of the first delay feedback circuit 402, the rising edge of the delayed stop pulse signal DSTOP (or narrow pulse NP) will reach the second delay output 416 after some number of iterations before the rising edge of the delayed start pulse signal DSTRT (or wide pulse WP) reaches the first delay output 408 (see t5). When the narrow pulse NP reaches the clock input 424 of the count mode flip-flop 418 before the wide pulse WP reaches the data input 422 of the count mode flip-flop 418, the data input 422 of the count mode flip-flop 418 is still low when the narrow pulse NP clocks the data input 422 to the data output 420, causing the data output 420 to fall to low at t6.

[0049] As described above, the number of iterations of the delayed stop pulse signal DSTOP on the second delay output 416 is provided to the count flip-flop 430 on node 446 by the counter 428. When the data output 420 falls to low, the count flip-flop 430 stores the count on node 446 to generate an integer 448, which can be the integer 106 in Figure 1 In this regard, the first measurement circuit 400 determines the number of time increments TI (equal to Tl - T2) that occur in the time period TP. The time remaining in the time period TP is the time remainder TR, which is the difference between the rising edge on the second delay output 416 and the rising edge on the first delay output 408, or the amount of time that the rising wide pulse WP lags behind the rising narrow pulse NP.

[0050] The data output 420 falling to low also turns on AND gates 450 and 452, which are coupled to the second delay output 416 and the first delay output 408, respectively. Thus, based on the narrow pulse NP, a rising edge first appears on the first remainder output 434. A rising edge corresponding to the wide pulse WP later appears on the second remainder output 436. The time between the rising edge on the first remainder output 434 and the rising edge on the second remainder output 436 is the time remainder TR between the rising edges of the second delay output 416 and the first delay output 408.

[0051] The start pulse signal START and the stop pulse signal STOP occur every period of the reference clock C Figure 2 shown. Thus, once the reference clock C REF is started, the start pulse signal START and the stop pulse signal STOP occur every period of the reference clock C REFIn the first cycle of , the integer 106 is generated, the first measurement circuit 400 needs to be reset to prepare for measuring the time period TP in the next cycle. In this regard, the first measurement circuit 400 includes a reset flip-flop 454 having a clock input 456 coupled to the negative data output 458 of the count mode flip-flop 418. As described above, when the delayed stop pulse signal DSTP catches up with the delayed start pulse signal DSTART and when the data output 420 of the count mode flip-flop 418 falls to a low level, the negative data output 458 rises, triggering the clock input 456. The data input 460 of the reset flip-flop 454 receives the master reset signal RSTB, which is not used in normal operation and can be assumed to be maintained at a high ("1") level. The negative data output 462 of the reset flip-flop 454 causes the pulse generator 464 to reset the counter 428. When the next start pulse signal START and stop pulse signal STOP arrive, the pulse generator 466 resets the reset flip-flop 454. The master reset signal RSTB is provided to other inputs of the first measurement circuit 400, such as Figure 4 As shown.

[0052] Figure 6A is a logic circuit diagram showing details of the second measurement circuit 600. The second measurement circuit 600 may be Figure 1 The second measurement circuit 108 in the TDC circuit 102 in the second measurement circuit 600 is obtained from the first measurement circuit 104 (or Figure 4 The first measurement circuit 400 in FIG. 1 receives the time remainder TR and adds the time remainder TR to the previous cumulative remainder PAR to generate a current cumulative remainder CAR. The second measurement circuit 600 generates a fraction indicator 110 based on the current cumulative remainder CAR, which is added (e.g., by Figure 1 The second measurement circuit 600 also calculates the next cumulative remainder NAR. As described below, the next cumulative remainder NAR generated during one cycle of the start pulse signal START and the stop pulse signal STOP is fed back and becomes the previous cumulative remainder PAR during the next cycle of the start pulse signal START and the stop pulse signal STOP. In this way, all time remainders TR contribute to the accuracy of the TDC.

[0053] The second measurement circuit 600 includes a time adder circuit 602 , an analog-to-digital converter (ADC) circuit 604 , and a digital-to-analog converter (DAC) circuit 606 , which are explained separately. Figure 6B A detailed logic circuit diagram of the time adder circuit 602 is provided in FIG. Figure 6AAs shown, the time adder circuit 602 receives a remainder start signal RSTRT on a first remainder input 608 and a remainder stop signal RSTOP on a second remainder input 610. The first remainder input 608 can be coupled to the first remainder output 434 of the first measurement circuit 400 in Figure 4 , and the second remainder input 610 can be coupled to the second remainder output 435. The remainder stop signal RSTOP rises after the remainder start signal RSTRT at a time interval equal to the time remainder TR of the time period TP. The time adder circuit 602 also receives a previous accumulated remainder PAR on a first PAR input 612 and a second PAR input 614. The time interval between a rising edge on the first PAR input 612 and a rising edge on the second PAR input 614 is equal to the previous accumulated remainder PAR. The time remainder TR and the previous accumulated remainder PAR are added together by the time adder circuit 602 as described with reference to Figure 6B .

[0054] Figure 6B The time adder circuit 602 in the time measurement circuit 600 includes a discharge circuit 616, a first capacitor 618, a second capacitor 620, a first summing flip-flop 622, and a second summing flip-flop 624. Reference is first made to Figure 6B for a detailed description of the time adder circuit 602, and reference is made to the timing diagrams in Figure 6B and Figure 7 for a detailed description of its operation.

[0055] The discharge circuit 616 includes a first discharge control circuit 626 that includes transistors 628A and 628B for discharging the first capacitor 618 in response to an initialization reset signal RST INI. The transistors 628A and 628B are coupled in series between a first node 630P and a ground rail GND. The first discharge control circuit 626 also includes transistors 632A and 632B that are also coupled in series between the first node 630P and the ground rail GND. The control inputs 634A and 634B of the transistors 632A and 632B are respectively coupled to the second PAR input 614 and the first remainder input 608.

[0056] The discharge circuit 616 also includes a second discharge control circuit 636 that includes transistors 638A and 638B for discharging the second capacitor 620 in response to an initialization reset signal RST INI. The transistors 638A and 638B are coupled in series between the second node 630N and the ground rail GND. The second discharge control circuit 636 also includes transistors 639A and 639B that are also coupled in series between the first node 630P and the ground rail GND. The control inputs 640A and 640B of the transistors 639A and 639B are coupled to the first PAR input 612 and the second remainder input 610, respectively. The first node 630P is coupled to the power rail PWR through a first switch (e.g., transistor) 642A, and the second node 630N is coupled to the power rail PWR through a second switch 642B. Both the first switch 642A and the second switch 642B are controlled by the remainder start signal RSTRT. The first node 630P is coupled to the clock input 646A of the first summing flip-flop 622 via a first inverter 648A, and the second node 630N is coupled to the clock input 646B of the second summing flip-flop 624 via a second inverter 648B.

[0057] Prior to providing the time remainder TR, the first remainder input 608 (RSTRT) and the second remainder input 610 (RSTOP) are at a low level. The low level of the remainder start signal RSTRT controls the first switch 642A and the second switch 642B to be open to couple the first node 630P and the second node 630N to the power rail PWR to charge both the first capacitor 618 and the second capacitor 620 to a first voltage VDD, which can be a supply voltage. The first PAR input 612 and the second PAR input 614 are also initially at a low level to turn on the transistor 632A in the first discharge control circuit 626 and to turn on the transistor 638A in the second discharge control circuit 636. The low levels in the first and second remainder inputs 608, 610 keep the transistors 632B and 638B off. Thus, even though the transistors 632A and 638A are on, the first and second capacitors 618, 620 cannot be discharged by the first and second discharge control circuits 626, 636. Figure 7 In the initial state of

[0058] At time t0 of the timing diagram in Figure 7 the rising transition of the first remainder input 608 turns off the first and second switches 642A, 642B. The rising transition of the first remainder input 608 turns on the transistor 632B to allow the first capacitor 618 to start discharging, as shown in Figure 7the first node 630P. Following the rising of the first remainder input 608, at time tl is the rising transition of the second remainder input 610, both having a separation time equal to the time remainder TR. The rising of the second remainder input 610 turns on transistor 638B, allowing the second capacitor 620 to discharge, as shown by the voltage on the second node 630N. Figure 7 The first capacitor 618 discharges for the duration of the time remainder TR, and then both the first capacitor 618 and the second capacitor 620 continue to discharge following the rising of the second remainder input 610.

[0059] Assuming the first capacitor 618 and the second capacitor 620 discharge at the same rate, at time tl the difference between the voltage at the first node 630P and the voltage at the second node 630N corresponds to the time remainder TR. This difference remains constant as both the first capacitor 618 and the second capacitor 620 continue to discharge. At time t2, which is shortly after the rising of the second remainder input 610 at tl, one of the first PAR input 612 and the second PAR input 614 occurs. Figure 7 In the first instance of the above, the first PAR input 612 rises at t2, turning off transistor 638A, which stops the second capacitor 620 (e.g., node 630N) from discharging from the first voltage VDD to the second reduced voltage V2, while the first capacitor 618 continues to discharge. At time t3, which is spaced from time t2 by an amount equal to the previously accumulated remainder PAR, the second PAR input 614 also rises, turning off transistor 632A to stop the first capacitor 618 (e.g., node 630P) from discharging from the first voltage VDD to the first reduced voltage VI. Thus, the discharge duration of the first capacitor 618 differs from the discharge duration of the second capacitor by an amount equal to the sum of the time remainder TR and the previously accumulated remainder PAR. Since this discharge duration difference corresponds to a voltage difference based on the same discharge rate, at time t3 the voltage difference between the first node 630P and the second node 630N is related to the sum of the time remainder TR and the previously accumulated remainder PAR.

[0060] At time t4, a reset signal RST (unrelated to the master reset signal RSTB discussed above) resets the first sum signal SUM+ on the adder output 644A of the first summing flip-flop 622, and resets the second sum signal SUM- on the adder output 644B of the second summing flip-flop 624 to a low level. As Figure 7As shown, although the voltages of the first node 630P and the second node 630N have dropped (due to the rising voltages at the clock inputs 646A and 646B caused by the inverters 648A and 648B), the first summing flip-flop 622 and the second summing flip-flop 624 are not triggered (e.g., clocked). However, at time t5, both the first PAR input 612 and the second PAR input 614 transition to low, causing the transistors 632A and 638A to re-conduct to discharge both the first capacitor 618 and the second capacitor 620 at the same rate. Due to the voltage difference on the first node 630P and the second node 630N, the first node 630P drops to the threshold voltage V THR Below, the clock input 646A of the first summing flip-flop 622 is triggered at the threshold voltage V THR Below, causing the clock input 646B to be activated and setting the second summing signal SUM- of the second summing flip-flop 624 at time t7. In this way, the time difference between the activation of the first summing signal SUM+ and the second summing signal SUM- is also equal to the sum of the time residue TR and the previous accumulated residue PAR, i.e., the current accumulated residue CAR. THR Below, causing the clock input 646B to be activated and setting the second summing signal SUM- of the second summing flip-flop 624 at time t7. In this way, the time difference between the activation of the first summing signal SUM+ and the second summing signal SUM- is also equal to the sum of the time residue TR and the previous accumulated residue PAR, i.e., the current accumulated residue CAR.

[0061] Referring back to Figure 6A , the first and second summing signals SUM+ and SUM- are outputs from the time adder circuit 602 and are coupled to the first input 650A and the second input 650B of the ADC circuit 604, respectively. The function of the ADC circuit 604 is to determine whether the magnitude of the current accumulated residue CAR (which can be positive or negative) is greater than a fraction of the time increment TI. In this example, the fraction is one-half (1 / 2). The ADC circuit 604 includes a first T1 delay circuit 652 and a first TO delay circuit 654, both coupled to the first input 650A. The ADC circuit 604 includes a second TO delay circuit 656 and a second T1 delay circuit 658, both coupled to the second input 650B. The first and second T1 delay circuits 652 and 658 have the same delay of duration T1 as the first delay circuit 404. The first and second TO delay circuits 654 and 656 have the same delay of duration TO.

[0062] For reasons explained below with reference to the DAC circuit 606, the difference between T1 and TO is equal to Figure 4 half the difference between T1 and T2 in the Figure 4the time increment TI used in the first measurement circuit 400 in the time interval between T1 and T0 (which determines Figure 1 the resolution of the TDC circuit 102 in the time interval between T1 and T0, or T1 - T0 = (T1 - T2) / 2. The ADC circuit 604 generates a fractional indicator 660 (which corresponds to Figure 1 the fractional indicator 110 in the time interval between T1 and T0) to indicate whether the current accumulated residue CAR has a magnitude greater than T1 / 2 and whether it is positive or negative.

[0063] The ADC circuit 604 also includes a positive arbitration flip-flop 662 and a negative arbitration flip-flop 664. The first T1 delay circuit 652 is coupled to the data input DIN1 of the positive flip-flop 662, while the second T0 delay circuit 656 is coupled to the clock input CKIN1 of the first positive flip-flop 662. In the example above, in the case where the current accumulated residue CAR is a positive value, the rising edge on the second sum signal SUM- (output 644B) lags behind the rising edge on the first sum signal SUM+ (output 644A) by a time interval equal to the current accumulated residue CAR. In this example, the rising edge on the output 644A propagates through the first T1 delay circuit 652, and the later arriving rising edge on the output 644B propagates through the second T0 delay circuit. If the current accumulated delay CAR is greater than T1 - T0, then the rising edge propagating through the first T1 delay circuit 652 will reach the data input DIN1 of the positive flip-flop 662 before the rising edge propagating through the second T0 delay circuit 656 reaches the clock input CKIN1, and the data output DOUT1 of the positive flip-flop 662 is set to a high level ("1"). On the other hand, if the current accumulated delay CAR is less than T1 - T0, then the rising edge propagating through the second T0 delay circuit 656 reaches the clock input CKIN1 before the rising edge propagating through the first T1 delay circuit 652 reaches the data input DIN1 of the positive flip-flop 662, and the data output DOUT1 of the positive flip-flop 662 is set to a low level ("0").

[0064] A current accumulated residue CAR having a negative value will cause a rising edge to first appear on the output 644B, followed by a rising edge on the output 644A. If the magnitude of the current accumulated residue CAR is greater than T1 - T0, then the rising edges propagating through the first T0 delay circuit 654 and the second T1 delay circuit 658 will cause the data output DOUT2 of the negative flip-flop 664 to be set to "1", otherwise to "0", in the manner described above. The fractional indicator 660 is determined by the positive flip-flop 662 and the negative flip-flop 664. In this example, the fractional indicator 660 can be a two-bit binary value of 01, 00, or 10.

[0065] As noted above, the fractional indicator 660 can be Figure 1fraction indicator 110 in FIG. 1, and Figure 4 The integer 448 in FIG. 4 can be the integer 106. The fraction indicator 110 is used to effectively round up or round down the integer 106 based on the current accumulated remainder CAR. Including the integer 106 and the fraction indicator 110, the TDC circuit 102 improves the accuracy of a TDC circuit having only an integer output, where the remainder is not considered. This adjustment is explained in the following examples.

[0066] If the current accumulated remainder CAR of the first example is +0.75(TI), which is greater than TI / 2, the fraction indicator 660 will cause the integer provided to the DCO 202 to be incremented by 1. It should be understood that this is an over-adjustment in response to the actual time remainder TR in a given period. However, the next accumulated remainder NAR will be -0.25(TI) to compensate for the over-adjustment in the next period (or later).

[0067] In the second example, the current accumulated remainder CAR is any value between ~+0.49(TI) and ~-0.49(TI) (a small margin is provided compared to 0.5, taking into account possible device variations and jitter effects), the fraction indicator will not cause the integer 106 in FIG. 4 to change, and the current accumulated remainder CAR will be the next accumulated remainder NAR used in the next period. Figure 1

[0068] In the third example, the current accumulated remainder CAR is -0.82(TI), so the fraction indicator 660 will cause the integer 106 to be decremented, and +0.18(TI) is provided as the next accumulated remainder NAR.

[0069] Based on the above examples, it can be seen that, on average, the output clock C OUT will have a phase difference from the reference clock C REF that is significantly reduced.

[0070] The purpose of the DAC circuit 606 is to provide the next accumulated remainder NAR from the current period as the previous accumulated remainder PAR in the next period. The DAC circuit 606 can use the output of the ADC circuit 604 to determine whether to add the time increment TI (=T1-T2) to the current accumulated remainder CAR or subtract the time increment TI (=T1-T2) from the current accumulated remainder CAR to generate NAR. Reference is first made to the structure of the DAC circuit 606, and then its operation is described with reference to Figure 6A The DAC circuit 606 is described in structure, and then its operation is described with reference to Figure 7

[0071] ​​The DAC circuit 606 includes a first Tl delay circuit 670 and a first T2 delay circuit 672, both coupled to the output 644A and correspondingly to first and second inputs 674A and 674B of a multiplexer 676. The DAC circuit 606 includes a second Tl delay circuit 680 and a second T2 delay circuit 682, both coupled to the output 644B and correspondingly to first and second inputs 684A and 684B of a multiplexer 686. An output ERR+ of the multiplexer 676 and an output ERR- of the multiplexer 686 are coupled to a delay circuit 690.

[0072] Referring back to Figure 7 , rising edges on the first and second sum signals SUM+ and SUM- are shown at times t5 and t6, respectively, with the first sum signal SUM+ rising first, which occurs when the sign of the current accumulated residue CAR is positive. In the negative case, a rising edge occurs on the second sum signal SUM- prior to the rising edge on the first sum signal SUM+.

[0073] At time t6, the rising edge of the output SUM+ is provided to the first Tl delay circuit 670 and the first T2 delay 672. Based on the fraction indicator 660, the multiplexer 676 selects the first sum signal SUM+ delayed by Tl to provide on the output ERR+. At time t7, the rising edge of the second sum signal SUM- is provided to the second Tl delay circuit 680 and the second T2 delay 682, and the multiplexer 686 selects SUM- delayed by T2 to provide on the output ERR-. In this manner, the time difference between the first and second sum signals SUM+ and SUM- is reduced by the time increment Tl (Tl - T2). That is, the time difference between ERR+ and ERR-, which is the next accumulated residue NAR, is shown as the previous accumulated residue PAR in time t78 of the next cycle. As shown, NAR is equal to the current accumulated residue CAR minus (Tl - T2) in the negative. The delay circuit 690 delays ERR+ and ERR- by the same amount of time and is coupled to the first PAR input 612 and the second PAR input 614, where the next accumulated residue NAR from a cycle of the reference clock C REF is stored and provided as the previous accumulated residue PAR in the next cycle.

[0074] Figure 8 is a logic circuit diagram of a calibration circuit 800, including Figure 4 the first feedback circuit 402 and the second feedback delay circuit 410 of the DAC circuit 400, for calibrating the time resolution T RES , the time resolution T RESis the difference between the first delay period T1 P of the first feedback circuit 402 and the second delay period T2 P of the second feedback delay circuit 410. Details of the first feedback circuit 402 and the second feedback delay circuit 410 are provided above and are not repeated here. If the first number or count CNT1 of the first delay period T1 P is equal to the second number or count CNT2 of the second delay period T2 P, the difference between T1 P and T2 P is known. This can be expressed as the equation:

[0075] CNT1 x T1 P = CNT2 x T2 P.

[0076] In one example, if CNT1 = 4 and CNT2 = 5, then (4) x T1 P = (5) x T2 P.

[0077] Since T RES = T1 P - T2 P, in this example it can be seen that T RES = T1 P / 5.

[0078] As a reminder, Figure 4 The first delay period T1 P in the first feedback circuit 400 is based on the first delay T1 of the first delay circuit 404, NOR gates R1 and R2, and AND gate A1. The second delay period T2 P is based on the second delay T2 of the second delay circuit 412, NOR gates R3 and R4, and AND gate A2. Assuming that NOR gates R1-R4 all have the same delay, and AND gates A1 and A2 also have the same delay, the primary difference between the first delay period T1 P and the second delay period T2 P is based on the difference between the first delay T1 and the second delay T2. The first delay T1 and the second delay T2 can be selected to satisfy the above equation where T1 P = 10 ns and T2 P = 8 ns. However, variations in propagation delay are inevitable in all components, so the calibration circuit 800 is provided to achieve or approximate the above relationship CNT1 x T1 P = CNT2 x T2 P.

[0079] The calibration operation of the calibration circuit 800 can be performed in a calibration mode of the first measurement circuit 400, which counts the number of iterations of CAL IN, determines whether CNT1 x T1 P = CNT2 x T2 P, and adjusts the second delay period T2 P. Alternatively, the calibration circuit 800 can adjust the first delay period T1 P or both the first delay period T1 P and the second delay period T2 P. This operation is described below after the components of the calibration circuit 800 are described.

[0080] The first delay output 802 of the first delay feedback circuit 402 is coupled to a calibration counter 804 and a time delay 806. Both the calibration counter 804 and the time delay 806 are coupled to an AND gate 808. Similarly, the second delay output 810 of the second delay feedback circuit 410 is coupled to an input of a second calibration counter 812 and a time delay 814, where both the second calibration counter 812 and the time delay 814 are further coupled to an AND gate 816.

[0081] The AND gates 808 and 816 have respective outputs 818A and 818B that are coupled to a sequence determination circuit 820. The output 822 of the sequence determination circuit 820 is provided to an adjustment circuit 824, which can generate an adjustment signal ADJ on an output 826. The output 826 is coupled to a variable capacitor 828, which is further coupled to the second delay output 810 of the second delay feedback circuit 410.

[0082] In the calibration mode, the inputs 830A and 830B of the first and second delay circuits 402, 410 are coupled together to simultaneously receive a calibration pulse signal CAL IN, as shown. Figure 9 The calibration counter 804 counts the first number of iterations of the calibration pulse signal CAL IN that propagates through the first delay circuit 402 in the feedback loop, and the calibration counter 812 counts the second number of iterations of the calibration pulse signal CAL IN that propagates through the second delay feedback circuit 410.

[0083] When the calibration counter 804 counts CNT1 reaches a desired value (e.g., 4 in the example described above), the calibration counter 804 generates a first calibration pulse CP1 to the AND gate 808. The time delay 806 delays the CAL IN pulse received from the first delay output 810 to synchronize the first calibration pulse CP1 to the AND gate 808. When the calibration counter 812 counts CNT2 reaches a desired value (e.g., 5), a second calibration pulse CP2 is generated by the calibration counter 812 and provided to the AND gate 816, which are synchronized by the CAL IN pulse propagating through the time delay 814.

[0084] The order determination circuit 820 includes arbiter circuits 832A and 832B. The first calibration pulse CP1 is provided as data to the arbiter circuit 832A through a first offset (delay) circuit 834P and also provided to the arbiter circuit 832B without delay for clocking thereof. Similarly, the second calibration pulse CP2 is provided as data to the flip-flop circuit 832B through a second offset circuit 834N and also provided to the arbiter circuit 832A without offset delay for clocking thereof. As can be seen, due to the offset circuits 834P and 834N, neither of the flip-flop circuits 832P and 832N will be set (e.g., set to “1”) unless the time difference between the first and second calibration pulses CP1 and CP2 is greater than the offset delay. An incrementer 836 generates one of +1, 0, or -1 on an output 826 as an adjustment signal ADJ in accordance with the flip-flop circuits 832P and 832N.

[0085] For example, if the flip-flop circuit 832P is set by the second pulse signal CP2 at the first clock input CK1, then the second calibration pulse CP2 leads the first calibration pulse CP1 by at least the offset delay of the offset circuit 834P. Thus, if the first and second calibration pulses CP1 and CP2 are separated in time by more than the offset delay, then the incrementer 836 will generate the appropriate one of +1 or -1 to cause the adjustment signal ADJ to increase the capacitance of the variable capacitor 828, which increases the capacitance on the second delay output 810 and increases the second delay period T2_P. The variable capacitor 828 can be adjusted by the adjustment signal ADJ to increase or decrease the capacitance. The adjustment signal ADJ can adjust the capacitance of the variable capacitor 828 in increments and the operations described above will be repeated until the first and second calibration pulses CP1 and CP2 are separated by less than the offset delay, which causes the adjustment signal ADJ to be “0”. During normal operation outside of the calibration mode, the variable capacitor 828 remains at the determined capacitance value. With the calibration circuit 800, the time increment TI can be within a range of less than 5% of T1_P. In some examples, the time increment TI can be less than 2% of T1_P.

[0086] In Figure 9One operation of the calibration circuit 800 can be seen in the timing diagram 900. After the calibration pulse signal CAL IN arrives, the count CNT1 of the counter 804 and the count CNT2 of the calibration counter 812 are both incremented in response to the calibration pulse signal CAL IN propagating to the first delay output 802 and the second delay output 810. The count CNT1 is incremented each time the calibration pulse signal CAL IN propagates to the first delay output 802, and the count CNT2 of the calibration counter 812 is incremented each time the calibration pulse signal CAL IN propagates to the second delay output 810. The circuits 838, 840, 842, 844, and 846 are used to reset the calibration circuit 800 in preparation for the next calibration pulse signal CAL IN.

[0087] Figure 10 is a block diagram of an exemplary processor-based system 1000 including a processor 1002 (e.g., a microprocessor) that includes Figure 2 an instruction processing circuit 1004 and a PLL 200, and Figure 1 a TDC system 100. Any of the processor-based system 1000, the processor 1002, and the instruction processing circuit 1004 can be an IC chip 101 in Figure 1 as an example. The processor-based system 1000 can be one or more circuits included in an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and can represent, for example, a server or a computer of a user.

[0088] In this example, the processor 1002 represents one or more general processing circuits such as a microprocessor, a central processing unit, or the like. The processor 1002 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor 1002 includes an instruction cache 1006 for temporary, fast-access memory storage of instructions accessible to the instruction processing circuit 1004. Instructions fetched or prefetched from a memory such as from a cache memory 1012 over a system bus 1010 are stored in the instruction cache 1006. The instruction processing circuit 1004 is configured to process instructions fetched into the instruction cache 1006 and process the instructions for execution.

[0089] The processor 1002 and the cache memory 1012 are coupled to a system bus 1010 and can intercouple other circuitry including input / output (I / O) circuitry 1016, the storage memory 1014, peripheral devices, and various other circuitry as taught herein. Of course, in some embodiments, the processor 1002 and the cache memory 1012 can be integrated into one or more processors as taught herein. In some embodiments, the processor 1002 can communicate directly with other circuitry, such as across a bus bridge 1018. In some embodiments, the processor 1002 can be directly connected to the cache memory 1012, as shown in FIG. 10. Figure 10 Although not shown in FIG. 10, multiple system buses 1010 can be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller 1014 is configured to provide memory access requests to a memory array 1016 in the main memory 1008. The memory array 1016 is comprised of an array of storage bit cells for storing data. By way of non-limiting example, the main memory 1008 can be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as Synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0090] Other devices can be connected to the system bus 1010. As illustrated in Figure 10 FIG. 10, these devices can include, by way of example and not limitation, the main memory 1008, one or more input devices 1018, one or more output devices 1020, a modem 1022, and one or more display controllers 1024. The input device(s) 1018 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) 1020 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 1022 can be any device configured to allow exchange of data to and from a network 1026. The network 1026 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH® network, and the Internet. The modem 1022 can be configured to support any type of communications protocol desired. The processor 1002 can also be configured to access the display controller(s) 1024 over the system bus 1012 to control information sent to one or more displays 1028. The display(s) 1028 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. Any of the input device(s) 1018, the modem 1022, and the output device(s) 1020 can be IC chips 101, or can include the TDC system 100. TM

[0091] Figure 10 ​The processor-based system 1000 in the example embodiment can include a set of instructions 1030 stored in the memory 1008 that are executable by the processor 1002 for carrying out any applications required according to instructions. The instructions 1030 can be stored in the main memory 1008, the processor 1002, and / or the instruction cache 1006 as examples of non-transitory computer-readable media 1032. The instructions 1030 can further reside, completely or at least partially, within the main memory 1008 and / or the processor 1002 during their execution. The instructions 1030 can further be transmitted or received, e.g., over the network 1026 via the modem 1022, such that the network 1026 includes the computer-readable media 1032, while the computer-readable media 1032 is shown as a single medium in the example embodiment, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term “computer- readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a processing device and that cause the processing device to perform any one or more of the methodologies of embodiments disclosed herein. The term “computer-readable medium” should be taken to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0092] Embodiments disclosed herein include various steps. The steps of embodiments disclosed herein can be formed by hardware components or can be embodied in machine-executable instructions, which can be used to program a general-purpose or a special-purpose processor to perform the steps. Alternatively, the steps can be performed by a combination of hardware and software.

[0093] Embodiments disclosed herein can be provided as a computer program product, or software, that can include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory, etc.), a waveguide, and the like.

[0094] Unless specifically stated otherwise, and as can be apparent from the preceding description and disclosed concepts, discussions utilizing terms such as "processing," "computing," "calculating," "determining," "displaying," or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system memories or registers into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0095] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such

[0096] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0097] The aspects disclosed herein can be implemented in hardware and / or in software stored on hardware, which can reside in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, CD-ROM, or any other form of computer readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0098] It is also noted that the operational steps described in any of the example aspects herein are described to provide examples and discussion. The operations described can be performed in numerous different sequences other than the illustrated ones. Furthermore, operations described in a single operational step can actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the example aspects can be combined. It is understood that the operational steps illustrated in the flowchart diagrams can be modified in a variety of different ways, as will be appreciated by persons skilled in the art. Persons of skill in the art will further appreciate that the information and signals described in the above description can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0099] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A time-to-digital converter (TDC) circuit (102), comprising: The first measurement circuit (104) is configured to: Receiving a start pulse signal (START) and a stop pulse signal (STOP) separated in time by a time period (TP); determining an integer number of consecutive first time increments (TI) in said time period (TP); as well as determining a time remainder (TR) of said time period (TP) that is less than one of said first time increments (TI); The second measurement circuit (108) is configured to: adding the temporal remainder (TR) to the previous cumulative remainder (PAR) to generate a current cumulative remainder (CAR); generating a fraction indicator indicating whether a magnitude of the current accumulated remainder is greater than half of the first time increment; generating a next accumulated remainder (NAR) comprising a first difference between the first time increment (TI) and the current accumulated remainder (CAR) in response to the fraction indicator (106) indicating that the magnitude of the current accumulated remainder (CAR) is greater than half the first time increment (TI); and In response to the fraction indicator (106) indicating that the magnitude of the current accumulated remainder (CAR) is less than half the first time increment (TI), the next accumulated remainder (NAR) is generated including the current accumulated remainder (CAR).

2. The TDC circuit according to claim 1 , wherein the first measurement circuit comprises: The first delay feedback circuit includes a first delay circuit, wherein the first delay circuit is configured to: receiving a start pulse signal at a first delay input; delaying the start pulse signal by a first delay period to generate a delayed start pulse signal on a first delayed output; as well as feeding back the delayed start pulse signal from the first delay output to the first delay input; The second delay feedback circuit includes a second delay circuit, wherein the second delay circuit is configured to: receiving a stop pulse signal at a second delay input; delaying the stop pulse signal by a second delay period that is shorter than the first delay period to generate a delayed stop pulse signal on a second delayed output; as well as feeding back the delayed stop pulse signal from the second delay output to the second delay input; as well as A trigger circuit comprising: Data output; a data input coupled to the first delayed output; and a clock input coupled to the second delayed output; in: The time period includes the time from the rising edge of the start pulse signal to the rising edge of the stop pulse signal; The time increment comprises a second difference between the first delay period and the second delay period; and The integer number of the first time increments in the time period comprises: The delayed start pulse signal iteratively propagates through the first delayed feedback circuit and is clocked from the data input of the flip-flop circuit to the data output a number of times in response to the delayed stop pulse signal iteratively propagating through the second delayed feedback circuit to the clock input.

3. The TDC circuit according to claim 2 , further comprising a counter circuit, wherein the counter circuit is configured to: incrementing an iteration number each time the delayed stop pulse signal propagates through the second delay circuit in the second delay feedback circuit; and The integer number is generated based on the number of iterations in response to receiving the delayed stop pulse signal at the clock input of the flip-flop circuit before receiving the delayed start pulse signal at the data input of the flip-flop circuit.

4. The TDC circuit according to claim 3, further comprising: The first remainder output; as well as The second remainder output, in: in response to generating the integer number, generating the time remainder based on a time from receiving the delayed stop pulse signal at the clock input of the flip-flop circuit to receiving the delayed start pulse signal at the data input of the flip-flop circuit; as well as The temporal remainder is the time between a first remainder signal on the first remainder output and a second remainder signal on the second remainder output.

5. The TDC circuit according to any one of claims 2 to 4, further comprising a calibration circuit, wherein the calibration circuit is configured to: receiving a calibration pulse signal; as well as determining whether a first number of iterations of the first delay period differs from a second number of iterations of the second delay period by more than an offset delay; as well as In response to the first number of iterations of the first delay period differing from the second number of iterations of the second delay period by more than the offset delay, the second delay period is adjusted.

6. The TDC circuit according to claim 5 , further comprising: a first calibration counter configured to generate a first calibration pulse in response to counting the first number of iterations of the calibration pulse signal through the first delay circuit; a second calibration counter configured to generate a second calibration pulse in response to counting the second number of iterations of the calibration pulse signal through the second delay circuit; as well as The comparison circuit is configured as follows: receiving the first calibration pulse and the second calibration pulse; as well as In response to the first calibration pulse and the second calibration pulse being separated in time by more than the offset delay, an adjustment signal is generated to adjust the second delay period.

7. The TDC circuit according to any one of claims 1 to 6, wherein the second measurement circuit comprises: First remainder input; Second remainder input; The time adder circuit is configured as: receiving the time remainder from the first measurement circuit as the time between a first remainder signal on the first remainder input and a second remainder signal on the second remainder input; adding the time remainder to the previous accumulated remainder; as well as generating the current cumulative remainder as the time between a first summation signal at an output of the first adder and a second summation signal at an output of the second adder; Analog-to-digital converter (ADC) circuit configured as: coupled to the first adder output and the second adder output; as well as generating the fraction indicator, the fraction indicator indicating whether the magnitude of the current cumulative remainder is greater than the half of the first time increment; and a digital-to-analog converter (DAC) circuit configured to: coupled to the first adder output and the second adder output; in response to the fraction indicator indicating that the magnitude of the current cumulative remainder is greater than half the first time increment, delaying the first summation signal by one of the first delay period and the second delay period, and delaying the second summation signal by the other of the first delay period and the second delay period; as well as In response to the fraction indicator indicating that the magnitude of the current cumulative remainder is less than half the first time increment, the first summation signal and the second summation signal are both delayed by one of the first delay period and the second delay period. 8 . The TDC circuit according to claim 1 , wherein the fraction indicator indicates a polarity of the current accumulated remainder.

9. The TDC circuit according to claim 7 or claim 8, wherein the time adder circuit comprises: a first capacitor, a second capacitor, and a discharge circuit, in: The temporal adder circuit configured to add the temporal remainder to the previous accumulated remainder includes the discharge circuit configured to: discharging the first capacitor for a time equal to the time remainder to reduce a first voltage on the first capacitor from a power supply voltage to a reduced first voltage; in response to the previous cumulative remainder including a positive value, further discharging the first capacitor for a time equal to the previous cumulative remainder to further reduce the reduced first voltage; and in response to the previous cumulative remainder including a negative value, discharging the second capacitor for a time equal to the previous cumulative remainder to reduce a second voltage on the second capacitor from the power supply voltage to a reduced second voltage; and The current accumulated remainder is determined based on a voltage difference between the reduced first voltage and the reduced second voltage.

10. The TDC circuit of claim 9, wherein: The discharge circuit is further configured to discharge the first capacitor from the reduced first voltage and to discharge the second capacitor from the reduced second voltage; activating a first summing flip-flop to generate the first summation signal in response to the first voltage on the first capacitor having a threshold voltage; as well as A second summing flip-flop is activated in response to the second voltage on the second capacitor having the threshold voltage to generate the second summation signal.

11. The TDC circuit according to any one of claims 7 to 10, wherein the ADC circuit comprises: a third delay circuit configured to delay the first sum signal by the first delay period to generate a delayed first sum signal; a fourth delay circuit configured to delay the second summation signal by a third delay period to generate a delayed second summation signal; The second trigger circuit includes: a second data input configured to receive the delayed first summation signal; a second clock input configured to receive the delayed second summation signal; and Second data output, in: The first delay period and the third delay period differ by half of the first time increment; In response to the current cumulative remainder being greater than a difference between the first delay period and the third delay period, the delayed first summation signal is propagated to the second data output; and One bit of the fraction indicator is generated at the second data output of the second flip-flop circuit.

12. The TDC circuit according to any one of claims 7 to 11, wherein the DAC circuit comprises: a fifth delay circuit configured to delay the first sum signal by the first delay period to generate a first delayed first sum signal; a sixth delay circuit configured to delay the first sum signal by the second delay period to generate a second delayed first sum signal; a first multiplexer configured to select, based on the fraction indicator, either the first delayed first summation signal or the second delayed first summation signal for propagation to a first multiplexer output; a seventh delay circuit configured to delay the second sum signal by the first delay period to generate a first delayed second sum signal; an eighth delay circuit configured to delay the second sum signal by the second delay period to generate a second delayed second sum signal; a second multiplexer configured to select either the first delayed second summation signal or the second delayed second summation signal for propagation to a second multiplexer output based on the fraction indicator; as well as The next cumulative remainder is generated based on one of the first delayed first summation signal and the second delayed first summation signal selected at the first multiplexer output, and based on one of the first delayed second summation signal and the second delayed second summation signal selected at the second multiplexer output. 13 . The TDC circuit of claim 1 , wherein the first time increment is less than 5% of the first delay period.

14. The TDC circuit of any one of claims 1 to 13, wherein the integer number is generated as a multi-bit binary value and the fraction indicator is generated as a two-bit binary value.

15. A method of a time-to-digital circuit (TDC) (102), the method comprising: Receiving a start pulse signal (START) and a stop pulse signal (STOP) separated in time by a time period (TP); determining an integer number of first time increments (TI) within the time period (TP) and a time remainder (TR) smaller than the first time increment (TI); adding the temporal remainder (TR) to the previous cumulative remainder (PAR) to generate a current cumulative remainder (CAR); generating a fraction indicator (106) indicating whether the current accumulated remainder (CAR) differs from the first time increment (TI) by more than half the first time increment (TI); generating a next accumulated remainder (NAR) comprising a difference between the first time increment (TI) and the current accumulated remainder (CAR) in response to the fraction indicator (106) indicating that the current accumulated remainder (CAR) differs from the first time increment (TI) by more than half the first time increment (TI); and In response to the fraction indicator (106) indicating that the current accumulated remainder (CAR) differs from the first time increment (TI) by less than half the first time increment (TI), generating the next accumulated remainder (NAR) based on the current accumulated remainder (CAR).

16. The method according to claim 15, further comprising: receiving the start pulse signal at a first delay input of a first delay circuit; delaying the start pulse signal by a first delay period to generate a delayed start pulse signal at a first delayed output of the first delay circuit; as well as feeding back the delayed start pulse signal from the first delay output to the first delay input; receiving the stop pulse signal at a second delay input of a second delay circuit; delaying the stop pulse signal by a second delay period shorter than the first delay period to generate a delayed stop pulse signal at a second delayed output of the second delay circuit; feeding back the delayed stop pulse signal from the second delay output to the second delay input; receiving the delayed start pulse signal at a data input of a flip-flop circuit; as well as receiving the delayed stop pulse signal at a clock input of the flip-flop circuit; in: The time period includes the time from the start of the start pulse to the start of the stop pulse signal; The time increment comprises a difference between the first delay period and the second delay period; as well as The integer number of the first time increments in the time period includes the number of times the delayed start pulse signal iteratively propagates through the first delay circuit and propagates to the data output of the flip-flop circuit in response to the delayed stop pulse signal iteratively propagating through the second delay circuit to the clock input.

17. The method of claim 16, further comprising, in a calibration mode: receiving a calibration pulse signal; determining whether a first number of iterations of the first delay period differs from a second number of iterations of the second delay period by more than an offset delay; as well as In response to the first number of iterations of the first delay period differing from the second number of iterations of the second delay period by more than the offset delay, the second delay period is adjusted.

18. The method according to any one of claims 15 to 17, further comprising: receiving the time remainder as a time from a first remainder signal to a second remainder signal; adding the time remainder to the previous accumulated remainder; generating the current cumulative remainder as the time from the first summation signal to the second summation signal; generating the fraction indicator based on the current cumulative remainder, the fraction indicator indicating whether a magnitude of the current cumulative remainder is greater than the half of the first time increment; in response to the fraction indicator indicating that the magnitude of the current cumulative remainder is greater than half the first time increment, delaying the first summation signal by one of the first delay period and the second delay period, and delaying the second summation signal by the other of the first delay period and the second delay period; as well as In response to the fraction indicator indicating that the magnitude of the current cumulative remainder is less than half the first time increment, the first summation signal and the second summation signal are both delayed by one of the first delay period and the second delay period.

19. The method according to claim 18, further comprising: Adding the temporal remainder to the previous cumulative remainder comprises: discharging the first capacitor for a time equal to the time remainder to reduce a first voltage on the first capacitor from a power supply voltage to a reduced first voltage; in response to the previous cumulative remainder including a positive signal, further discharging the first capacitor for a time equal to the previous cumulative remainder to further reduce the reduced first voltage; in response to the previous cumulative remainder including a negative signal, discharging the second capacitor for a time equal to the previous cumulative remainder to reduce a second voltage on the second capacitor from the power supply voltage to a reduced second voltage; and The current accumulated remainder is determined based on a voltage difference between the reduced first voltage and the reduced second voltage.

20. A phase-locked loop (PLL) circuit (200), comprising: Digitally controlled oscillator (DCO) (202); Loop filter circuit (212); a frequency divider circuit (204); as well as A time-to-digital (TDC) system (208) comprising: coarse TDC circuit (127); A fine TDC circuit (102) comprising: The first measurement circuit (104) is configured to: Receiving a start pulse signal (START) and a stop pulse signal (STOP) separated in time by a time period (TP); determining an integer number of consecutive first time increments (TI) in said time period (TP); and determining a time remainder (TR) of said time period (TP) that is less than one of said first time increments (TI); The second measurement circuit (108) is configured to: adding the temporal remainder (TR) to the previous cumulative remainder (PAR) to generate a current cumulative remainder (CAR); generating a fraction indicator indicating whether a magnitude of the current accumulated remainder (CAR) is greater than half of the first time increment (TI); generating a next accumulated remainder (NAR) comprising a difference between the first time increment (TI) and the current accumulated remainder (CAR) in response to the fraction indicator (106) indicating that the magnitude of the current accumulated remainder (CAR) is greater than half the first time increment (TI); and In response to the fraction indicator (106) indicating that the magnitude of the current accumulated remainder (CAR) is less than half the first time increment (TI), the next accumulated remainder (NAR) is generated including the current accumulated remainder (CAR). The range determination circuit (112) is configured to: determining whether the time period (TP) is within a time period range; generating, in the coarse TDC circuit (127), the integer number (132) corresponding to the time period (TP) in response to determining that the time period (TP) is greater than a maximum time period within the time period range; and In response to determining that the time period (TP) is within the time period range, the integer number (125) corresponding to the time period is generated in the fine TDC (102).

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