Method, device and equipment for repairing invalid storage unit in memory and medium

Abstract

The embodiment of the invention provides a method and device for repairing a failed storage unit in a memory, equipment and a medium, and the method comprises the steps: obtaining a target row address corresponding to an activation operation in response to the received activation operation submitted by a target object; determining a target storage array to which a word line receiving the target row address belongs according to address information of a first address interval in the target row address; and when the target row address is the same as the invalid row address, determining a target redundant word line receiving the target row address according to a target storage array to which the word line receiving the target row address belongs. And the phenomenon that the read-write efficiency of the chip is influenced by increasing the tRCD in the chip due to the fact that the failed memory unit is repaired by using the redundant word line of the memory array where the failed word line is located is avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technology and related technologies, and in particular, to a method, apparatus, device, and medium for repairing a failed storage unit in a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM), also known as main memory, is internal memory that exchanges data directly with the CPU. It offers fast read / write speeds and is typically used as temporary data storage for operating systems and other running programs.

[0003] The DRAM (Dynamic Random Access Memory) memory array is composed of multiple memory cells. During the actual production process, some memory cells may fail. To replace these failed memory cells, the chip design includes redundant circuits. The redundant circuits are used to repair failed memory cells, thereby improving the chip yield.

[0004] In the prior art, repairing a failed memory cell involves first obtaining the address of the failed memory cell through a test process, and then storing the row address of the failed memory cell in a redundant circuit. The row address of the failed cell is automatically loaded during chip power-up. When a row address is input during normal operation, it is compared with the row address stored in the redundant circuit. If the row address does not match, the row address input during normal operation is used. If the row address matches, the redundant word line is used.

[0005] Since access to DRAM memory cells requires activating the row address (through an activation command) first and then accessing the column address (through a write command or a read command), a certain mandatory waiting time (tRCD) is required between these two operations to ensure that the column address can be sent only after the row address signal is stable. However, when the failed word line and the repaired redundant word line are located in the same memory array, the tRCD inside the chip will be reduced, affecting the chip's read and write efficiency. Summary of the Invention

[0006] The embodiments described herein provide a method, apparatus, device, and medium for repairing failed storage cells in a memory, thereby improving chip read and write efficiency.

[0007] In a first aspect, according to the present disclosure, a method for repairing a failed memory cell in a memory is provided, wherein the memory includes a plurality of memory arrays, any one of which includes a plurality of memory cells arranged in an array, and at least two of the plurality of memory arrays include redundant word lines, comprising: In response to receiving an activation operation submitted by a target object, obtaining a target row address corresponding to the activation operation; determining, according to address information of a first address interval in the target row address, a target memory array to which a word line receiving the target row address belongs; When the target row address is the same as the failed row address, a target redundant word line receiving the target row address is determined according to a target memory array to which the word line receiving the target row address belongs.

[0008] In some embodiments of the present disclosure, determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include a redundant word line, selecting a redundant word line from any memory array including redundant word lines as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from memory arrays including redundant word lines other than the target memory array as the target redundant word line receiving the target row address.

[0009] In some embodiments of the present disclosure, the memory array includes a first memory array, a second memory array, a third memory array, and a fourth memory array, the second memory array includes a first redundant word line, and the third memory array includes a second redundant word line; The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs is the first memory array or the fourth memory array, selecting a redundant word line from the second memory array as the target redundant word line receiving the target row address, or selecting a redundant word line from the third memory array as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs is the second memory array, selecting a redundant word line from the third memory array as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs is the third memory array, a redundant word line is selected from the second memory array as the target redundant word line receiving the target row address.

[0010] In some embodiments of the present disclosure, the memory array includes at least a first memory array group and a second memory array group, the first memory array group and the second memory array group include a first memory array, a second memory array, a third memory array, and a fourth memory array, the second memory array includes a first redundant word line, and the third memory array includes a second redundant word line; Before determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address, the method further includes: determining third identification information according to address information of a second address interval in the target row address; The target memory array group to which the word line receiving the target row address belongs is determined according to the correspondence between the third identification information and the fourth identification information of the memory array group.

[0011] In some embodiments of the present disclosure, before determining the target redundant word line receiving the target row address according to the target memory array to which the word line receiving the target row address belongs, the method further includes: obtaining a selection signal, wherein the selection signal is used to select a repair method; The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: A target redundant word line receiving the target row address is determined according to a target memory array to which the word line receiving the target row address belongs and the selection signal.

[0012] In some embodiments of the present disclosure, determining the target redundant word line receiving the target row address according to the target memory array to which the word line receiving the target row address belongs and the selection signal includes: When the target memory array to which the word line receiving the target row address belongs does not include a redundant word line and the selection signal is a first selection signal, selecting a redundant word line from any memory array including redundant word lines as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs includes a redundant word line and the selection signal is a first selection signal, selecting a redundant word line from a memory array including redundant word lines other than the target memory array as the target redundant word line receiving the target row address; When the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as a target redundant word line for receiving the target row address.

[0013] In some embodiments of the present disclosure, determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address includes: determining first identification information according to address information of a first address interval in the target row address; The target memory array to which the word line receiving the target row address belongs is determined according to the correspondence between the first identification information and the second identification information of the memory array.

[0014] In a second aspect, according to the present disclosure, a device for repairing a failed memory cell in a memory is provided, wherein the memory includes a plurality of memory arrays, any one of which includes a plurality of memory cells arranged in an array, and at least two of the plurality of memory arrays include redundant word lines, including: a target row address acquisition module, configured to, in response to receiving an activation operation submitted by a target object, acquire a target row address corresponding to the activation operation; a target storage array determining module, configured to determine, based on address information of a first address interval in the target row address, a target storage array to which a word line receiving the target row address belongs; The target redundant word line determining module is configured to determine a target redundant word line receiving the target row address according to a target storage array to which the word line receiving the target row address belongs when the target row address is the same as the failed row address.

[0015] In a third aspect, according to the present disclosure, a computer device is provided, comprising: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement any method as described in the first aspect.

[0016] In a fourth aspect, according to the content of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, it implements any method as described in the first aspect.

[0017] The method, apparatus, device and medium for repairing a failed storage cell in a memory provided by the embodiments of the present disclosure first obtain the target row address corresponding to the activation operation in response to receiving an activation operation submitted by the target object; then determine the target storage array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address; finally, when the target row address is the same as the failed row address, determine the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs. When the target storage array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any storage array including redundant word lines as the target redundant word line receiving the target row address; when the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array including redundant word lines outside the target storage array as the target redundant word line receiving the target row address. This avoids using the redundant word lines of the storage array where the failed word line is located to repair the failed storage cell, which increases tRCD inside the chip and affects the chip's read and write efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure. Figure 1 This is a flow chart of a method for repairing a failed storage unit in a memory provided by an embodiment of the present disclosure; Figure 2 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure; Figure 3 is a schematic diagram of the structure of another memory provided by an embodiment of the present disclosure; Figure 4 is a timing diagram of a memory provided by an embodiment of the present disclosure; Figure 5A and Figure 5B is a schematic structural diagram of a comparison circuit in a memory provided by an embodiment of the present disclosure; Figure 6 1 is a schematic structural diagram of a device for repairing a failed storage unit in a memory provided by an embodiment of the present disclosure; Figure 7 It is a structural diagram of a computer device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0021] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0022] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0023] In view of the problems existing in the prior art, an embodiment of the present disclosure provides a method for repairing a failed memory cell in a memory, which is applied to the memory. The memory includes multiple memory arrays, any one of which includes multiple memory cells arranged in an array, and at least two of the multiple memory arrays include redundant word lines. Figure 1 FIG. 1 is a flow chart of a method for repairing a failed storage unit in a memory provided by an embodiment of the present disclosure, such as Figure 1 As shown, the method for repairing a failed storage unit in a memory includes: S110 . In response to receiving an activation operation submitted by a target object, obtain a target row address corresponding to the activation operation.

[0024] The memory includes multiple memory arrays, and a memory array includes multiple memory cells arranged in an array.

[0025] During the manufacturing process of memory chips, some word lines may be damaged. At this time, redundant word lines are needed to replace the damaged word lines. The row addresses are transmitted to the memory cells connected to the damaged word lines through the redundant word lines. The process of replacing the damaged word lines with redundant word lines is the process of address remapping, that is, the row address received by the redundant word lines is the row address received by the damaged word lines.

[0026] After receiving the activation operation submitted by the target object, the memory obtains the target row address included in the activation operation, that is, the row address RADT<12:3> carried by the activation command during a normal activation operation.

[0027] It should be noted that the above embodiment exemplifies that the row address includes 10 bits. When the number of storage units in the memory is large, the row address carried by the activation command during the activation operation may also be RADT<13:3> or RADT<14:3>, etc. The embodiment of the present disclosure does not specifically limit this.

[0028] S120 , determining a target memory array to which a word line receiving the target row address belongs based on address information of a first address interval in the target row address.

[0029] The address information of the first address range in the target row address refers to the address information of the eleventh to twelfth address range in the target row address, that is, RADT<12:11>.

[0030] In a specific embodiment, determining the target storage array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address includes: determining first identification information based on the address information of the first address interval in the target row address; and determining the target storage array to which the word line receiving the target row address belongs based on the correspondence between the first identification information and the second identification information of the storage array.

[0031] As an example, Figure 2As shown, the memory includes four memory arrays, namely the first memory array, the second memory array, the third memory array and the fourth memory array. The second identification information corresponding to the first memory array is 00, the second identification information corresponding to the second memory array is 01, the second identification information corresponding to the third memory array is 10, and the second identification information corresponding to the fourth memory array is 11. If the target row address RADT<12:3>=0000000000, the address information RADT<12:11> of the first address interval in the target row address is 00. At this time, the determined first identification information is 00. Through the correspondence between the first identification information and the second identification information of the memory array, it can be determined that the target memory array to which the word line receiving the target row address belongs is the first memory array; if the target row address RADT<12:3>=0100000000, the address information RADT<12:11> of the first address interval in the target row address is 01, at this time, the determined first identification information is 01, through the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the second storage array; if the target row address RADT<12:3>=1000000000, and the address information RADT<12:11> of the first address interval in the target row address is 10, then the determined first identification information is 10, and through the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the third storage array; if the target row address RADT<12:3>=1100000000, and the address information RADT<12:11> of the first address interval in the target row address is 11, then the determined first identification information is 11, and through the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the fourth storage array.

[0032] As another example, Figure 3 As shown, the memory includes eight memory arrays, namely the first memory array, the second memory array, the third memory array, and the fourth memory array of the first memory array group, and the first memory array, the second memory array, the third memory array, and the fourth memory array of the second memory array group. The second identification information corresponding to the first memory array of the first memory array group and the first memory array of the second memory array group is 00, the second identification information corresponding to the second memory array of the first memory array group and the second memory array of the second memory array group is 01, the second identification information corresponding to the third memory array of the first memory array group and the third memory array of the second memory array group is 10, and the second identification information corresponding to the fourth memory array of the first memory array group and the fourth memory array of the second memory array group is 11.

[0033] Since the first storage array in the first storage array group and the first storage array in the second storage array group have the same second identification information, the second storage array in the first storage array group and the second storage array in the second storage array group have the same second identification information, the third storage array in the first storage array group and the third storage array in the second storage array group have the same second identification information, and the fourth storage array in the first storage array group and the fourth storage array in the second storage array group have the same second identification information, in this implementation process, before executing step S120 to determine the target storage array to which the word line receiving the target row address belongs based on the address information in the first address range in the target row address, the method further includes: determining third identification information based on the address information in the second address range in the target row address; and determining the target storage array group to which the word line receiving the target row address belongs based on the correspondence between the third identification information and the fourth identification information of the storage array groups.

[0034] In this case, the number of storage units in the memory is large. In this case, the row address carried by the activation command during normal activation operation can be RADT<13:3>, and the address information of the second address interval in the target row address is the address information of the thirteenth digit in the target row address, that is, RADT <13> .

[0035] At this time, the fourth identification information corresponding to the first storage array group is 0, the fourth identification information corresponding to the second storage array group is 1, the second identification information corresponding to the first storage array is 00, the second identification information corresponding to the second storage array is 01, the second identification information corresponding to the third storage array is 10, and the second identification information corresponding to the fourth storage array is 11. If the target row address RADT<13:3>=00000000000, the address information RADT<13:3> of the second address range in the target row address is 0000000000. <13> =0, the address information RADT<12:11> of the first address interval in the target row address is 00. At this time, the determined third identification information is 0, and the first identification information is 00. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the first storage array of the first storage array group; if the target row address RADT<13:3>=001000000000, the address information RADT<13:3> of the second address interval in the target row address is 00. <13> =0, the address information RADT<12:11> of the first address interval in the target row address is 01. At this time, the determined third identification information is 0, and the first identification information is 01. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the second storage array of the first storage array group; if the target row address RADT<13:3>=01000000000, the address information RADT<13:3> of the second address interval in the target row address is 01. <13> =0, the address information RADT<12:11> of the first address interval in the target row address is 10. At this time, the determined third identification information is 0, and the first identification information is 10. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the third storage array of the first storage array group; if the target row address RADT<13:3>=01100000000, the address information RADT<13:3> of the second address interval in the target row address is 0. <13> =0, address information RADT<12:11> of the first address interval in the target row address=11. At this time, the determined third identification information is 0, and the first identification information is 11. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the fourth storage array of the first storage array group.If the target row address RADT<13:3>=10000000000, the address information of the second address range in the target row address RADT <13> =1, the address information RADT<12:11> of the first address interval in the target row address is 00. At this time, the determined third identification information is 1, and the first identification information is 00. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the first storage array of the second storage array group; if the target row address RADT<13:3>=101000000000, the address information RADT<13:3> of the second address interval in the target row address is 00. <13> =1, the address information RADT<12:11> of the first address interval in the target row address is 01. At this time, the determined third identification information is 1, and the first identification information is 01. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the second storage array of the second storage array group; if the target row address RADT<13:3>=11000000000, the address information RADT<13:3> of the second address interval in the target row address is 01. <13> =1, the address information RADT<12:11> of the first address interval in the target row address is 10. At this time, the determined third identification information is 1, the first identification information is 10, and through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the third storage array of the second storage array group; if the target row address RADT<13:3>=11100000000, the address information RADT<13:3> of the second address interval in the target row address is 11100000000. <13> =1, address information RADT<12:11> of the first address interval in the target row address=11. At this time, the determined third identification information is 1, and the first identification information is 11. Through the correspondence between the third identification information and the fourth identification information of the storage array group, and the correspondence between the first identification information and the second identification information of the storage array, it can be determined that the target storage array to which the word line receiving the target row address belongs is the fourth storage array of the second storage array group.

[0036] It should be noted that Figure 2 and Figure 3 In the example, A<12:11> refers to the second identification information corresponding to each storage array, A <13> Refers to the fourth identification information corresponding to each storage array group, that is, Figure 2 and Figure 3, the second identification information corresponding to the first storage array is 00, the second identification information corresponding to the second storage array is 01, the second identification information corresponding to the third storage array is 10, the second identification information corresponding to the fourth storage array is 11, the fourth identification information corresponding to the first storage array group is 0, and the fourth identification information corresponding to the second storage array group is 1.

[0037] S130 , when the target row address is the same as the failed row address, determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs.

[0038] The failing row address is determined based on a memory testing process.

[0039] By comparing the target row address corresponding to the received activation operation with the failed row address, when the target row address corresponding to the activation operation is the same as the failed row address, the target redundant word line receiving the target row address is determined according to the target storage array to which the word line receiving the target row address belongs.

[0040] Specifically, if the target storage array to which the word line receiving the target row address belongs does not include a redundant word line, a redundant word line is selected from any storage array including redundant word lines as the target redundant word line receiving the target row address; if the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array including redundant word lines other than the target storage array as the target redundant word line receiving the target row address.

[0041] A specific example, see Figure 2 , the memory array includes a first memory array, a second memory array, a third memory array and a fourth memory array, the second memory array includes a first redundant word line, the third memory array includes a second redundant word line ( Figure 2 the redundant word lines included in the second and third memory arrays are not shown); determining a target redundant word line for receiving the target row address according to the target memory array to which the word line receiving the target row address belongs, comprising: when the target memory array to which the word line receiving the target row address belongs is the first memory array or the fourth memory array, selecting a redundant word line from the second memory array as the target redundant word line for receiving the target row address, or selecting a redundant word line from the third memory array as the target redundant word line for receiving the target row address; when the target memory array to which the word line receiving the target row address belongs is the second memory array, selecting a redundant word line from the third memory array as the target redundant word line for receiving the target row address; and when the target memory array to which the word line receiving the target row address belongs is the third memory array, selecting a redundant word line from the second memory array as the target redundant word line for receiving the target row address.

[0042] Another specific exemplary example is Figure 3 As shown, the memory array includes a first memory array group and a second memory array group, the first memory array group and the second memory array group each include a first memory array, a second memory array, a third memory array and a fourth memory array, the second memory array includes a first redundant word line, and the third memory array includes a second redundant word line ( Figure 3 (the redundant word lines included in the second and third memory arrays are not shown). Determining a target redundant word line for receiving the target row address based on a target memory array to which the word line receiving the target row address belongs includes: when the target memory array group to which the word line receiving the target row address belongs is the first memory array group and the target memory array is the first memory array or the fourth memory array, selecting a redundant word line from the second memory array of the first memory array group as the target redundant word line for receiving the target row address, or selecting a redundant word line from the third memory array of the first memory array group as the target redundant word line for receiving the target row address; when the target memory array group to which the word line receiving the target row address belongs is the first memory array group and the target memory array is the second memory array, selecting a redundant word line from the third memory array of the first memory array group as the target redundant word line for receiving the target row address; and when the target memory array group to which the word line receiving the target row address belongs is the first memory array group and the target memory array is the third memory array, selecting a redundant word line from the second memory array of the first memory array group as the target redundant word line for receiving the target row address. When the target memory array group to which the word line receiving the target row address belongs is the second memory array group, and the target memory array is the first memory array or the fourth memory array, a redundant word line is selected from the second memory array of the second memory array group as the target redundant word line receiving the target row address, or a redundant word line is selected from the third memory array of the second memory array group as the target redundant word line receiving the target row address; when the target memory array group to which the word line receiving the target row address belongs is the second memory array group, and the target memory array is the second memory array, a redundant word line is selected from the third memory array of the second memory array group as the target redundant word line receiving the target row address; when the target memory array group to which the word line receiving the target row address belongs is the second memory array group, and the target memory array is the third memory array, a redundant word line is selected from the second memory array of the second memory array group as the target redundant word line receiving the target row address.

[0043] It should be noted that the above embodiment exemplarily indicates that the memory includes two groups of storage array groups. When the memory may also include three groups of storage array groups or multiple groups of storage array groups, the embodiment of the present disclosure does not specifically limit the number of storage array groups. When the storage array groups include multiple groups, the row address carried by the activation command during normal activation operation can be RADT<14:3>, and the address information of the second address range in the target row address is the address information of the thirteenth to fourteenth address range in the target row address, that is, RADT<14:13>.

[0044] Combine Figure 4 When the second memory array and the third memory array include redundant word lines, and according to the address information of the first address interval in the target row address, it is determined that the target memory array to which the word line receiving the target row address belongs is the second memory array, at this time, if the redundant word line in the second memory array is selected, the enabling time of the redundant word line is t1, that is, the redundant word line of the memory array 2 needs to wait until the word line of the target row address fails before it can be enabled. If the redundant word line in the third memory array is selected, since the word line of the target row address in the third memory array is not invalid, the enabling time of the redundant word line in the third memory array is t2. The enabling time of the redundant word line in the third memory array is t1-t2 earlier than the enabling time of the redundant word line in the second memory array, that is, the tRCD improvement time inside the chip is t1-t2, which reduces the tRCD inside the chip and improves the chip read and write efficiency.

[0045] The method for repairing a failed storage cell in a memory provided by an embodiment of the present disclosure first obtains the target row address corresponding to the activation operation in response to receiving an activation operation submitted by a target object; then, based on the address information of the first address interval in the target row address, determines the target storage array to which the word line receiving the target row address belongs; finally, when the target row address is the same as the failed row address, determines the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs. When the target storage array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any storage array including redundant word lines as the target redundant word line receiving the target row address; when the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array including redundant word lines outside the target storage array as the target redundant word line receiving the target row address. This avoids using the redundant word lines of the storage array where the failed word line is located to repair the failed storage cell, which increases the tRCD inside the chip and affects the chip's read and write efficiency.

[0046] Based on the above embodiment, the method for repairing a failed storage unit in a memory provided by the embodiment of the present disclosure further includes: A selection signal is obtained, wherein the selection signal is used to select a repair method.

[0047] at this time, Figure 2 The specific implementation process of step S130 includes: determining the target redundant word line receiving the target row address according to the target memory array to which the word line receiving the target row address belongs and the selection signal.

[0048] Specifically, when the target storage array to which the word line receiving the target row address belongs does not include redundant word lines and the selection signal is a first selection signal, a redundant word line is selected from any one of the storage arrays including redundant word lines as the target redundant word line receiving the target row address; when the target storage array to which the word line receiving the target row address belongs includes redundant word lines and the selection signal is a first selection signal, a redundant word line is selected from a storage array including redundant word lines other than the target storage array as the target redundant word line receiving the target row address; when the selection signal is a second selection signal, a redundant word line is selected from any one of the storage arrays including redundant word lines as the target redundant word line receiving the target row address.

[0049] That is, in this implementation, by adding a selection signal, if the selection signal is a first selection signal, if there are redundant word lines in the target memory array, then a redundant word line is selected from the memory array including the redundant word lines outside the target memory array as the target redundant word line for receiving the target row address; if the selection signal is a second selection signal, if there are redundant word lines in the target memory array, then the redundant word line of the target memory array can be selected as the target redundant word line for receiving the target row address, or a redundant word line can be selected from the memory array including the redundant word lines outside the target memory array as the target redundant word line for receiving the target row address. By adding a row address repair mode, the row address repair mode can be freely selected according to the actual performance of the memory, which can ensure both the efficient use of the redundant circuit and the performance of the chip will not be reduced, thereby improving the yield of the product.

[0050] The following will be explained through a specific example. Different memory arrays in the memory will be provided with corresponding comparison circuits. The comparison circuit compares whether the received target row address is consistent with the failed row address, and outputs a selection signal based on the comparison result. The selection signal determines whether to use the normal word line or the redundant word line. Specifically, during the test process, the memory will store the failed row address in the redundant circuit, such as Figure 5AOr as shown in 5B, RAXAFTL<12:3> is the invalid row address, RAXAFTL <12> Refers to the twelfth invalid row address, ..., RAXAFTL <3> Refers to the third failed row address. The failed row address will be loaded during the memory power-up process. RAF<12:3> is the loaded failed row address. <12> Refers to the twelfth bit of the failed row address loaded, ..., RAF <3> Refers to the third failed row address loaded. The redundant circuit will process the failed row address to obtain the loaded failed row address. RADT<12:3> is the target row address carried by the activation command during normal activation operation. RRFAHIT<12:3> is the comparison signal. RAXAFTL <12> Refers to the comparison signal of the twelfth bit, ...RAXAFTL <3> Refers to the comparison signal of the third bit, and RRHITB is the enable signal of the normal word line or the redundant word line (the redundant word line is selected when RRHITB=0, and the normal word line is selected when RRHITB=1), and SEL is the selection signal used to select the word line repair mode (SEL=0, that is, when the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as the target redundant word line receiving the target row address; SEL=1, that is, when the selection signal is the first selection signal, when the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from the memory array including redundant word lines outside the target memory array as the target redundant word line receiving the target row address).

[0051] Take the second storage array for example, the failed row address A<12:3>=0100000000, that is, the failed row address is located in the second storage array. When storing the failed row address to the redundant circuit, the failed row address that needs to be input is RAXAFTL<12:3>=110000000000, the failed row address RAF<12:3>=0011111111 loaded during power-on, and the row address RADT<12:3>=0100000000 during normal operation. Figure 5A After the comparison circuit of the second memory array shown completes the comparison, the comparison signal RRFAHIT<12:3>=11111111111. If the signal SEL=0 is selected, then the comparison signal is processed by the subsequent logic circuit to obtain the enable signal RRHITB=0. A redundant word line can be selected to repair the failed word line. The redundant word line can be a redundant word line in the second memory array or a redundant word line in the third memory array.

[0052] If the failed row address A<12:3>=0100000000, that is to say, the failed row address is located in the second storage array, if you want to use the redundant word line in the second storage array for repair, then when storing the failed row address to the redundant circuit, the failed row address that needs to be input is RAXAFTL<12:3>=110000000000, the failed row address RAF<12:3>=0011111111 loaded during the power-on process, the row address RADT<12:3>=0100000000 during the normal operation process, the row address RADT<12:3>=0100000000 during the normal operation process, based on Figure 5A After the comparison circuit of the second storage array shown completes the comparison, the comparison signal RRFAHIT<12:3>=11111111111. If SEL=1, then the comparison signal is processed by the subsequent logic circuit to obtain the enable signal RRHITB=1. At this time, if the redundant word line in the second storage array fails to repair the failed word line, the redundant word line in the third storage array may be selected to repair the failed word line in the second storage array.

[0053] The third storage array has the same principle as the second storage array, and is not described in detail in the embodiment of the present disclosure.

[0054] Based on the above embodiments, the present disclosure further provides a device for repairing a failed memory cell in a memory, wherein the memory includes a plurality of memory arrays, any one of which includes a plurality of memory cells arranged in an array, and at least two of the plurality of memory arrays include redundant word lines, such as Figure 6 As shown, the device for repairing a failed storage unit in a memory includes: The target row address acquisition module 410 is configured to, in response to receiving an activation operation submitted by a target object, acquire a target row address corresponding to the activation operation; a target storage array determining module 420, configured to determine a target storage array to which a word line receiving the target row address belongs based on address information of a first address interval in the target row address; The target redundant word line determination module 430 is configured to determine a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs when the target row address is the same as the failed row address.

[0055] The failed storage unit repair device provided in the memory according to the embodiment of the present disclosure first obtains the target row address corresponding to the activation operation in response to receiving the activation operation submitted by the target object; then determines the target storage array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address; finally, when the target row address is the same as the failed row address, determines the target redundant word line receiving the target row address based on the target storage array to which the word line receiving the target row address belongs. When the target storage array to which the word line receiving the target row address belongs does not include redundant word lines, a redundant word line is selected from any storage array including redundant word lines as the target redundant word line receiving the target row address; when the target storage array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from a storage array including redundant word lines outside the target storage array as the target redundant word line receiving the target row address. This avoids using the redundant word lines of the storage array where the failed word line is located to repair the failed storage unit, thereby increasing the tRCD inside the chip and affecting the chip's read and write efficiency.

[0056] In some embodiments of the present disclosure, determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include a redundant word line, selecting a redundant word line from any memory array including redundant word lines as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from memory arrays including redundant word lines other than the target memory array as the target redundant word line receiving the target row address.

[0057] In some embodiments of the present disclosure, the memory array includes a first memory array, a second memory array, a third memory array, and a fourth memory array, the second memory array includes a first redundant word line, and the third memory array includes a second redundant word line; The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs is the first memory array or the fourth memory array, selecting a redundant word line from the second memory array as the target redundant word line receiving the target row address, or selecting a redundant word line from the third memory array as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs is the second memory array, selecting a redundant word line from the third memory array as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs is the third memory array, a redundant word line is selected from the second memory array as the target redundant word line receiving the target row address.

[0058] In some embodiments of the present disclosure, the memory array includes at least a first memory array group and a second memory array group, the first memory array group and the second memory array group include a first memory array, a second memory array, a third memory array, and a fourth memory array, the second memory array includes a first redundant word line, and the third memory array includes a second redundant word line; Before determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address, the method further includes: determining third identification information according to address information of a second address interval in the target row address; The target memory array group to which the word line receiving the target row address belongs is determined according to the correspondence between the third identification information and the fourth identification information of the memory array group.

[0059] In some embodiments of the present disclosure, before determining the target redundant word line receiving the target row address according to the target memory array to which the word line receiving the target row address belongs, the method further includes: obtaining a selection signal, wherein the selection signal is used to select a repair method; The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: A target redundant word line receiving the target row address is determined according to a target memory array to which the word line receiving the target row address belongs and the selection signal.

[0060] In some embodiments of the present disclosure, determining the target redundant word line receiving the target row address according to the target memory array to which the word line receiving the target row address belongs and the selection signal includes: When the target memory array to which the word line receiving the target row address belongs does not include a redundant word line and the selection signal is a first selection signal, selecting a redundant word line from any memory array including redundant word lines as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs includes a redundant word line and the selection signal is a first selection signal, selecting a redundant word line from a memory array including redundant word lines other than the target memory array as the target redundant word line receiving the target row address; When the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as a target redundant word line for receiving the target row address.

[0061] In some embodiments of the present disclosure, determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address includes: determining first identification information according to address information of a first address interval in the target row address; The target memory array to which the word line receiving the target row address belongs is determined according to the correspondence between the first identification information and the second identification information of the memory array.

[0062] Based on the above embodiments, the present application also provides a computer device. Figure 7 , Figure 7 This is a basic structural block diagram of the computer device in this embodiment.

[0063] The computer device includes a memory 510 and a processor 520 that are interconnected and communicate with each other via a system bus. It should be noted that the figure only shows a computer device with components 510-520, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0064] Computer devices can be desktop computers, laptops, PDAs, cloud servers, etc. Computer devices can interact with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0065] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, a hard disk, a multimedia card, card-type memory (such as SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, a magnetic disk, an optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of the computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, or a flash card equipped with the computer device. Of course, the memory 510 may also include both an internal storage unit of the computer device and an external storage device thereof. In this embodiment, the memory 510 is generally used to store an operating system and various application software installed on the computer device, such as the program code of the above-mentioned method. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or are about to be output.

[0066] The processor 520 is generally used to perform the overall operation of the computer device. In this embodiment, the memory 510 is used to store program code or instructions, which include computer operating instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or process data, such as the program code for running the above method.

[0067] In this article, a bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. This bus system can be divided into address buses, data buses, control buses, and so on. For ease of illustration, the diagram uses only a single thick line, but this does not imply that there is only one bus or only one type of bus.

[0068] Another embodiment of the present application further provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads the computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method, and to generate a device that implements the functional actions specified in each block or combination of blocks in the block diagram.

[0069] Computer-readable media include but are not limited to electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any appropriate combination of the foregoing, the memory is used to store program codes or instructions, the program codes include computer operating instructions, and the processor is used to execute the program codes or instructions of the above-mentioned methods stored in the memory.

[0070] For the definitions of memory and processor, please refer to the description of the aforementioned computer device embodiment and will not be repeated here.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0072] Each functional unit or module in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0073] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0074] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0075] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0076] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A method for repairing a failed memory cell in a memory, wherein the memory comprises a plurality of memory arrays, any one of which comprises a plurality of memory cells arranged in an array, and at least two of the plurality of memory arrays comprise redundant word lines, wherein: include: In response to receiving an activation operation submitted by a target object, obtaining a target row address corresponding to the activation operation; determining, according to address information of a first address interval in the target row address, a target memory array to which a word line receiving the target row address belongs; When the target row address is the same as the failed row address, a target redundant word line receiving the target row address is determined according to a target memory array to which the word line receiving the target row address belongs.

2. The method according to claim 1, characterized in that The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs does not include a redundant word line, selecting a redundant word line from any memory array including redundant word lines as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs includes redundant word lines, a redundant word line is selected from memory arrays including redundant word lines other than the target memory array as the target redundant word line receiving the target row address.

3. The method according to claim 1 or 2, characterized in that The memory array includes a first memory array, a second memory array, a third memory array and a fourth memory array, the second memory array includes a first redundant word line, and the third memory array includes a second redundant word line; The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: When the target memory array to which the word line receiving the target row address belongs is the first memory array or the fourth memory array, selecting a redundant word line from the second memory array as the target redundant word line receiving the target row address, or selecting a redundant word line from the third memory array as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs is the second memory array, selecting a redundant word line from the third memory array as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs is the third memory array, a redundant word line is selected from the second memory array as the target redundant word line receiving the target row address.

4. The method according to claim 1 or 2, characterized in that The memory array comprises at least a first memory array group and a second memory array group, the first memory array group and the second memory array group comprise a first memory array, a second memory array, a third memory array and a fourth memory array, the second memory array comprises a first redundant word line, and the third memory array comprises a second redundant word line; Before determining the target memory array to which the word line receiving the target row address belongs based on the address information of the first address interval in the target row address, the method further includes: determining third identification information according to address information of a second address interval in the target row address; The target memory array group to which the word line receiving the target row address belongs is determined according to the correspondence between the third identification information and the fourth identification information of the memory array group.

5. The method according to claim 1, wherein Before determining the target redundant word line receiving the target row address according to the target memory array to which the word line receiving the target row address belongs, the method further comprises: obtaining a selection signal, wherein the selection signal is used to select a repair method; The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs includes: A target redundant word line receiving the target row address is determined according to a target memory array to which the word line receiving the target row address belongs and the selection signal.

6. The method according to claim 5, characterized in that The step of determining a target redundant word line receiving the target row address according to a target memory array to which the word line receiving the target row address belongs and the selection signal comprises: When the target memory array to which the word line receiving the target row address belongs does not include a redundant word line and the selection signal is a first selection signal, selecting a redundant word line from any memory array including redundant word lines as the target redundant word line receiving the target row address; When the target memory array to which the word line receiving the target row address belongs includes a redundant word line and the selection signal is a first selection signal, selecting a redundant word line from a memory array including redundant word lines other than the target memory array as the target redundant word line receiving the target row address; When the selection signal is the second selection signal, a redundant word line is selected from any memory array including redundant word lines as a target redundant word line for receiving the target row address.

7. The method according to claim 1, characterized in that The step of determining, based on address information of a first address interval in the target row address, a target memory array to which a word line receiving the target row address belongs includes: determining first identification information according to address information of a first address interval in the target row address; The target memory array to which the word line receiving the target row address belongs is determined according to the correspondence between the first identification information and the second identification information of the memory array.

8. A device for repairing a failed memory cell in a memory, wherein the memory comprises a plurality of memory arrays, any one of which comprises a plurality of memory cells arranged in an array, and at least two of the plurality of memory arrays comprise redundant word lines, characterized in that: include: a target row address acquisition module, configured to, in response to receiving an activation operation submitted by a target object, acquire a target row address corresponding to the activation operation; a target storage array determining module, configured to determine, based on address information of a first address interval in the target row address, a target storage array to which a word line receiving the target row address belongs; The target redundant word line determining module is configured to determine a target redundant word line receiving the target row address according to a target storage array to which the word line receiving the target row address belongs when the target row address is the same as the failed row address.

9. A computer device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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