Package and method of forming same

Abstract

A method of forming a package includes performing a first plurality of laser grooving processes on a scribe line of a wafer to form a first combined trench, and performing a second plurality of laser grooving processes on the scribe line of the wafer to form a second combined trench. A first sawing process is performed on a scribe line of a substrate. A first sawing process is performed in a portion of the scribe line between the first combined trench and the second combined trench. A second sawing process is performed to saw through the wafer in the scribe line. A second sawing process separates the first device die and the second device die from each other on opposite sides of the scribe line. The embodiment of the invention also provides a package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to packages and methods of forming the same. Background Art

[0002] To achieve more functionality, more device dies are integrated into the same package, and the packages of integrated circuits are becoming increasingly complex. For example, a package can be formed to include multiple device dies, such as a processor and a memory cube, in the same package. A package can include device dies formed using different technologies, and the packages have different functions bonded to the same device die, thus forming a system. This can save manufacturing costs and achieve optimized device performance. The package can be formed as a reconstructed wafer, which is then singulated to form discrete packages. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a method for forming a package, the method comprising: performing a first plurality of laser grooving processes on a scribe line of a substrate to form a first combination groove; performing a second plurality of laser grooving processes on the scribe line of the substrate to form a second combination groove; performing a first sawing process on the scribe line of the substrate, wherein the first sawing process is performed in a portion of the scribe line between the first combination groove and the second combination groove; and performing a second sawing process to saw through the substrate in the scribe line, wherein the second sawing process separates the first device die and the second device die on opposite sides of the scribe line from each other.

[0004] Other embodiments of the present disclosure provide a package comprising: a first device die comprising a semiconductor substrate, wherein the semiconductor substrate comprises: a first edge and a second edge laterally recessed from the first edge, wherein the second edge has at least a portion higher than the first edge; a first top surface laterally located between the first edge and the second edge; and a first residual portion protruding higher than the first top surface, wherein the first residual portion is also laterally located between the first edge and the second edge.

[0005] Another embodiment of the present disclosure provides a package, which includes: a device die, the device die including: multiple dielectric layers; and a semiconductor substrate located below the multiple dielectric layers, wherein the semiconductor substrate includes: a first top surface located below the multiple dielectric layers and in contact with the multiple dielectric layers; and a first extension portion extending laterally beyond the first edges of the multiple dielectric layers, wherein the first extension portion includes: a second top surface lower than the first top surface; and a first section protruding above the second top surface, wherein, in a top view of the package, the first section has a strip shape, and a first length direction of the first section is substantially parallel to the first edges of the multiple dielectric layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 8 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figures 11B to 15 A cross-sectional view of an intermediate stage in the formation and singulation process of a reconstructed wafer is shown in accordance with some embodiments.

[0008] Figure 16A An edge portion of a package is shown in accordance with some embodiments.

[0009] Figure 16B A top view of a package is shown in accordance with some embodiments.

[0010] Figure 17 and Figure 18 A cross-sectional view of an intermediate stage of a laser grooving process using a defocused laser beam is shown, in accordance with some embodiments.

[0011] Figure 19 and Figure 20 An edge portion of a package is shown in accordance with some embodiments.

[0012] Figure 21 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples of different components for implementing the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of clarity and simplicity and does not in itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Packages and methods for forming the same are provided. According to some embodiments of the present disclosure, a reconstructed wafer is formed, and then the reconstructed wafer is singulated into a plurality of packages. The singulation process may include multiple laser grooving processes, wherein the paths of the laser grooving processes may partially overlap. A wide blade sawing (grooving) process may then be performed to saw through structures overlapping the semiconductor substrate of the reconstructed wafer until the semiconductor substrate is exposed. A narrow blade sawing process may then be performed to saw the reconstructed wafer into packages.

[0016] The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of the present disclosure, and those skilled in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the various embodiments. Throughout the various views and illustrative embodiments, like reference numerals are used to represent like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1 to 15 Cross-sectional views illustrating intermediate stages in the formation of a reconstructed wafer and a singulation process of the reconstructed wafer to form packages, according to some embodiments of the present disclosure. Figure 21 The process flow 200 shown schematically also reflects the corresponding process.

[0018] Figure 1 A cross-sectional view of a package assembly 2 according to some embodiments is shown. The package assembly 2 may include multiple device dies 4, wherein edge portions of two adjacent device dies 4 are shown. The device die 4 will be optionally referred to as a chip hereinafter. According to some embodiments, the device die 4 is a memory die, such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die. The device die 4 may also be a logic die, which may be a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input / output (IO) die, a baseband (BB) die, an application processor (AP) die, etc.

[0019] According to some embodiments, wafer 2 includes a semiconductor substrate 20 and components formed on a top surface of semiconductor substrate 20. Semiconductor substrate 20 may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, etc. Through-holes 22 (also referred to as through-silicon vias (TSVs)) may be formed to extend into semiconductor substrate 20, and TSVs 22 are used to electrically couple components on opposite sides of wafer 2 to each other.

[0020] According to some embodiments, package assembly 2 is a device wafer including active devices, such as transistors and / or diodes, and possibly passive devices, such as capacitors, inductors, resistors, etc. According to some embodiments, the active devices are formed on the top surface of semiconductor substrate 20. Exemplary integrated circuit devices may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. According to alternative embodiments, wafer 2 is used to form an interposer without active and passive devices.

[0021] Interconnect structure 24 is formed over semiconductor substrate 20. According to some embodiments, interconnect structure 24 includes a plurality of dielectric layers 26 and conductive features 28 located in dielectric layers 26. Dielectric layers 26 may include an interlayer dielectric (ILD) and a plurality of intermetallic dielectric (IMD) layers located over the ILD. The ILD may be formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. The IMD layer may be formed of a low-k dielectric layer. Dielectric layer 26 may also include a non-low-k dielectric layer located over the IMD layer.

[0022] Conductive features 28 in dielectric layer 26 may include contact plugs, metal lines, vias, metal pads, etc. The formation process may include a single damascene process and a dual damascene process. The material of the conductive features may include tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0023] According to some embodiments, the sealing ring 34 is formed to surround the inner area (active area) of the respective device die 4. The active area is used to form functional integrated circuits (active devices and passive devices) and interconnect structures. The sealing ring 34 can be formed as a complete ring, and there is no interruption in the sealing ring 34 in the top view. Before singulating the wafer 2, the outer edge of the sealing ring 34 can be considered to be the outer boundary of the device die 4. However, it is understood that the singulation process discussed subsequently will leave some parts of the scribe line 6 outside the sealing ring 34 of the discrete device die 4. Accordingly, after the singulation process of sawing the wafer 2 into the discrete device die 4, the discrete device die 4 also includes some parts outside the respective sealing ring 34.

[0024] According to some embodiments, each device die 4 may include a single seal ring. Alternatively, each device die 4 may include multiple seal rings, wherein an outer seal ring surrounds a respective inner seal ring. When more than one seal ring is formed for each device die 4, seal ring 34 is shown as the outermost seal ring closest to scribe line 6.

[0025] According to some embodiments, seal ring 34 includes portions of conductive component 28. For example, seal ring 34 may include metal lines and vias, and may or may not include contact plugs and aluminum pads. Each of the contact plugs and metal lines / vias in seal ring 34 may form a complete ring that is physically combined with the upper and lower rings of the conductive component to form an integrated seal ring.

[0026] refer to Figure 9B , Figure 9B A top view of a portion of a wafer 2 is shown, with a plurality of device dies 4 arranged in an array comprising a plurality of rows and columns, wherein four device dies 4 are shown. A plurality of scribe lines 6 are located in the horizontal direction (X direction) and the vertical direction (Y direction) to separate the rows and columns of device dies 4.

[0027] Return Reference Figure 1 According to some embodiments, dummy conductive features 36 are formed in scribe lines 6 and outside of seal ring 34 of device die 4. According to alternative embodiments, dummy conductive features 36 are not formed in scribe lines 6. According to some embodiments, dummy conductive features 36 include test conductive features that are used to test the functionality of device die 4. Testing can be performed by probing conductive pads, which are top surface features of dummy conductive features 36. Testing is performed prior to the singulation process of wafer 2 discussed later.

[0028] According to some embodiments, after the probing process, a dielectric layer 30 is formed as a top surface layer of the wafer 2. According to an alternative embodiment, the dielectric layer 30 is not formed. The dielectric layer 30 may be deposited using plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), plasma enhanced ALD (PECVD), or the like. The dielectric layer 30 may be formed of or include a silicon-containing dielectric material. According to some embodiments, the material of the dielectric layer 30 may be represented as SiO x N y C z , where x, y, z are relative ratios of O, N, and C. For example, the dielectric layer 30 may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, SiO2, or the like.

[0029] refer to Figure 2 , the front side of the wafer 2 is attached to the carrier 40 via the layer 42. The corresponding process is shown as Figure 21 Process 202 of process flow 200 is shown. According to some embodiments, carrier 40 is a semiconductor carrier, such as a silicon carrier, and layer 42 is a bonding layer. When layer 42 is a bonding layer, layer 42 may be formed from a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or combinations thereof. Accordingly, wafer 2 is bonded to carrier 40, wherein according to some embodiments, bonding layer 42 is bonded to layer 30 by fusion bonding.

[0030] According to an optional embodiment, the carrier 40 includes a transparent substrate, such as a glass substrate, and the layer 42 may be formed of an adhesive, such as a light-to-heat conversion (LTHC) material, which is configured to decompose under the heat of light (such as a laser beam) when the carrier 40 is debonded.

[0031] After the wafer 2 is attached to the carrier 40, a backside grinding process is performed to thin the semiconductor substrate 20. The corresponding process is shown as Figure 21 Process 204 in the illustrated process flow 200 . According to some embodiments, a planarization process is performed until the TSVs 22 are exposed. The semiconductor substrate 20 in the device die 4 may be recessed by an etching process, such that the top portion of the TSVs 22 protrudes above the semiconductor substrate 20 . A dielectric isolation layer (not shown) may then be filled into the recess. The formation of the dielectric isolation layer may include performing a deposition process to deposit a dielectric layer into the recess such that the protruding portion of the TSVs 22 is located in the dielectric layer, followed by a planarization process. The portion of the dielectric layer above the TSVs 22 is removed, and the remaining portion of the dielectric layer forms a dielectric isolation layer, which becomes a portion of the wafer 2 .

[0032] refer to Figure 3 , forming a bonding layer 46 and a bonding pad 48. The corresponding process is shown as Figure 21 The process flow 200 is shown as process 206. A bonding layer 46 is deposited on the wafer 2 and the through-hole 22. The bonding layer 46 may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof.

[0033] Bonding pads 48 are formed in bonding layer 46. According to some embodiments, bonding pads 48 are formed by etching bonding layer 46 to expose through-holes 22, filling the resulting openings with a conductive layer, and performing a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process. Thus, the top surfaces of bonding pads 48 and bonding layer 46 are coplanar with each other. Bonding pads 48 may include a material selected from copper, titanium, titanium nitride, tantalum, tantalum nitride, and the like. For example, each bonding pad 48 may include a titanium nitride barrier layer and a copper region located on the titanium nitride barrier layer.

[0034] refer to Figure 4 , bonding the device die 50 (also referred to as the top die) to the device die 4. The corresponding process is shown as Figure 21 Process 208 in process flow 200 is shown. Bonding may be performed by a face-to-back bonding process, where the front side of device die 50 is bonded to the back side of device die 4. In accordance with some embodiments, each device die 50 may be a logic die, a memory die, an IO die, a separate passive device die, etc.

[0035] Device die 50 may include a semiconductor substrate 52, which may be a silicon substrate. Device die 50 includes an interconnect structure 56 for connecting to active and passive devices in device die 50. Interconnect structure 56 includes metal lines and vias, as shown in the schematic diagram.

[0036] Each device die 50 includes a bonding pad 58 and a bonding layer 60 (also referred to as a bonding film) located at the bottom surface of the device die 50 as shown. The bottom surface of the bonding pad 58 can be coplanar with the bottom surface of the bonding layer 60. According to some embodiments, the bonding layer 60 can be formed of a silicon-containing dielectric material, which can be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. The bonding pad 58 can include copper and can be formed by a damascene process. The bonding layer 60 and the bonding pad 58 are planarized so that their surfaces are coplanar, which may be caused by performing CMP when forming the bonding pad 58.

[0037] The bonding can be achieved by bonding in which bonding pad 58 is bonded to bonding pad 48 by metal-to-metal direct bonding, and bonding layer 60 is bonded to bonding layer 46 by fusion bonding. According to some embodiments, the metal-to-metal direct bonding is a copper-to-copper direct bonding. In addition, bonding layer 60 of device die 50 is bonded to bonding layer 46 of wafer 2 below by fusion bonding, for example, to generate Si-O-Si bonds. The structure above carrier 40 and layer 42 is collectively referred to as reconstructed wafer 100 hereinafter, and more components will be formed in subsequent processes to further expand reconstructed wafer 100.

[0038] refer to Figure 5 , a gap filling process is performed to fill the gaps between adjacent device dies 50 and seal the device dies 50 in a dielectric gap filling region 62 (also referred to as an encapsulant). The corresponding process is shown as Figure 21 Process 210 in process flow 200 is shown. According to some embodiments, gapfill region 62 includes gapfill layer 62, which may further include dielectric liner 62A and dielectric gapfill layer 62B located above dielectric liner 62A. Dielectric liner 62A may be formed of a material having good adhesion to device die 50. According to some embodiments, dielectric liner 62A is formed of or includes silicon nitride. Dielectric liner 62A is formed in a conformal deposition process and is therefore a conformal layer. Dielectric gapfill layer 62B may be formed of an oxide-based dielectric material (such as silicon oxide, silicon oxynitride, silicate glass, etc.). Dielectric gapfill layer 62B may also be formed by a deposition process.

[0039] According to alternative embodiments, the gap-fill layer 62 is formed of or includes a molding compound, a molded underfill, etc. A corresponding process may include dispensing a dielectric material in a flowable form, and curing the dielectric material.

[0040] After gapfill layer 62 is deposited, a planarization process, such as a CMP process or a mechanical polishing process, is performed to make the backside of device die 50 flush with the top surface of gapfill layer 62. The remaining portion of gapfill layer 62 is hereinafter referred to as gapfill region 62.

[0041] In subsequent processes, such as Figure 5 As shown, a bonding layer 64 is formed over the device die 50 and the gap-fill region 62. The bonding layer 64 may also be formed of or include a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. According to an alternative embodiment, the bonding layer 64 is not formed.

[0042] In subsequent processes, such as Figure 6 As shown, the reconstructed wafer 100 is attached to the carrier 68. The corresponding process is shown as Figure 21 Process 212 of process flow 200 is shown. According to some embodiments, carrier 68 remains in the final structure and can serve as a supporting substrate and possibly a heat sink. According to these embodiments, a bonding layer 70 can be formed on carrier 68, and bonding layer 70 is formed of a silicon-containing dielectric material selected from the same group of candidate materials as bonding layer 64. The materials of bonding layers 64 and 70 can be the same or different from each other. Bonding layer 70 is bonded to bonding layer 64 by fusion bonding.

[0043] According to an alternative embodiment, carrier 68 includes a transparent substrate, such as a glass substrate, and layer 70 may be formed of a binder, such as an LTHC material configured to decompose under the heat of light, such as a laser beam.

[0044] The support 40 is then released and the resulting structure is as Figure 7 The corresponding process is shown as Figure 21 Process 214 of process flow 200 is shown. According to some embodiments in which carrier 40 comprises a silicon wafer, carrier 40 can be removed by, for example, injecting hydrogen into carrier 40 to generate a stress concentration layer, and annealing carrier 40 so that carrier 40 can be separated at the stress concentration layer. The remaining portion of carrier 40 can be removed by, for example, etching, a CMP process, or a mechanical grinding process. According to these embodiments, layer 42, which is a bonding layer, can also be removed.

[0045] According to an alternative embodiment in which the carrier 40 is a glass carrier, the reconstructed wafer 100 may be debonded from the carrier 40 by projecting a laser beam onto the layer 42 , which may include an LTHC coating material, thereby causing the LTHC coating material to decompose, thereby releasing the reconstructed wafer 100 from the carrier 40 .

[0046] Next, if Figure 8 As shown, electrical connector 72 is formed. If dielectric layer 30 has not yet been formed, dielectric layer 30 may (or may not) be formed at this time. The corresponding process is shown as Figure 21 Process 216 of process flow 200 is shown. When dielectric layer 30 is formed at this time, dielectric layer 30 can be formed of or include silicon oxide, silicon nitride, silicon oxynitride, etc. Vias 74 are formed to connect electrical connectors 72 to conductive features 28. Electrical connectors 72 can include solder areas, metal pillars, etc.

[0047] In a subsequent process, the reconstructed wafer 100 is singulated in a singulation process to form discrete packages 100'. Discrete packages 100' include device dies 4 and 50 and may or may not include a carrier 68, which may be a supporting substrate. Dashed lines 76 illustrate exemplary locations of surfaces (including the top surface and edges) of package 100' that are generated by the singulation process discussed later.

[0048] The singulation process of the reconstructed wafer 100 is as follows Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B and Figures 12 to 15 shown. Figure 9Aand Figures 9B to 15 The portion of the reconstructed wafer 100 shown is located at Figure 8 The region 78 in FIG. 1 is shown, while other portions of the reconstructed wafer 100 are not shown and may be obtained from Figure 8 Learned from.

[0049] Figure 9A Shown Figure 8 The cross-sectional view of the region 78 is shown. The dummy feature 36 ( Figure 8 , if any) are not shown, although they also exist in the peripheral region P1. Figure 9B A top view of a portion of the wafer 2 is shown, wherein the Figure 9B The cross section 9A-9A in FIG. Figure 9A The cross-sectional view shown.

[0050] like Figure 9A As shown, the scribe line 6 includes a peripheral region P1 located in the middle of the scribe line 6 and a peripheral region P2 located on the opposite side of the peripheral region P1. Each of the peripheral regions P1 and P2 can be a strip-shaped region extending from one side of the wafer 2 (which can have a circular top view shape) to the opposite side (such as Figure 9B ). Peripheral region P1 is the region in which the wide blade sawing process is to be performed. Peripheral region P2 is the region in which the narrower laser grooving process is to be performed. A defocused laser process (as discussed later) may or may not be performed, and if performed, it is also performed in peripheral region P2.

[0051] Reference again Figure 9A , performing the first narrow laser grooving process, each narrow laser grooving process is performed in one peripheral region P2. The corresponding process is shown as Figure 21 The process 218 in the process flow 200 is shown. In each narrow laser slotting process, the laser beam 80 is in the X direction ( Figure 9B ) and also scans in the Y direction, and scans from one end of the wafer to the opposite end in each laser scan.

[0052] Laser beam 80 is shown as having a tapered profile, with the center portion shown extending lower than the edge portions. In practice, laser beam 80 has a uniform width from the exit point of the laser beam generator (not shown) to the location where it lands on wafer 2. On the other hand, the power density of laser beam 80 can have a distribution (such as a Gaussian distribution), with the center portion of laser beam 80 having the highest power and the edge portions having increasingly lower power densities. The illustrated profile 82 shows an exemplary power density distribution profile, where the lower portion of profile 82 represents a higher power density value, and vice versa. Since portions of laser beam 80 with higher power density may result in deeper grooves than portions of laser beam 80 with lower power density, when laser beam 80 with power density profile 82 is projected onto wafer 2, the resulting groove will also have a profile with the center portion being deeper than the edge portions. Therefore, laser beam 80 is drawn as having a tapered shape to reflect the shape of the resulting groove.

[0053] The first narrower laser grooving process can form Figure 10A The trench R1 shown. Throughout the description, the terms "trench" and "recess" are used interchangeably. The trench R1 penetrates the interconnect structure 24 (and the dielectric layer 26) and extends into the semiconductor substrate 20. According to some embodiments, the depth D1 extending into the semiconductor substrate 20 is less than 50% of the thickness T1 of the semiconductor substrate 20. The depth D1 can also be greater than about 1.5 μm to ensure that the upper interconnect structure 24 is removed or substantially removed. For example, the thickness T1 can be in a range between about 3 μm and about 7 μm, and thus the depth D1 can be in a range between about 1.5 μm and about 3 μm. The trench R1 ( Figure 9A ) may have a width W1 in the range between about 2 μm and about 4 μm.

[0054] Next, if Figure 10A and Figure 10B As shown, Figure 10A and Figure 10B , respectively, show a cross-sectional view and a top view, for example, also using the laser beam 80 to perform a second plurality of narrow laser slotting processes in the peripheral region P2. The corresponding process is shown as Figure 21 The process 220 in the process flow 200 is shown. The second plurality of narrow laser grooving processes are performed at a location offset from the location of the first plurality of narrow laser grooving processes. The offset distance S1 is less than the width W1 of the trench R1. The ratio S1 / W1 may be in the range of about 0.2 and about 0.9. Thus, the second plurality of trenches R2 are formed, as shown in FIG. Figure 11A and Figure 11B As shown, the trench R2 partially overlaps with the corresponding nearest trench R1.

[0055] Figure 11A and Figure 11BFurther shown is a third plurality of narrow laser slotting processes performed in the peripheral region P2, for example also using the laser beam 80. The corresponding processes are shown as Figure 21 The third plurality of narrow laser grooving processes are performed at a location further offset from the location of the second plurality of narrow laser grooving processes. The offset distance S2 is also less than the width W1 of the trench R1. The ratio S2 / W1 may be in the range of about 0.2 to about 0.9. Thus, a third plurality of trenches R3 are formed, as shown in FIG. Figure 12 The trench R3 partially overlaps with the corresponding trench R2 and may or may not overlap with the trench R1.

[0056] According to some embodiments, three narrow laser grooving processes are performed in each peripheral region P2. According to alternative embodiments, two narrow laser grooving processes are performed in each peripheral region P2, and thus the third plurality of laser grooving processes are not performed. According to still other alternative embodiments, 4, 5, 6, or more narrow laser grooving processes may be performed in each peripheral region P2, each narrow laser grooving process being partially offset relative to the nearest other grooving processes.

[0057] Trenches R1, R2, and R3 in the same peripheral region P2 are joined together to form a combined trench (recess) RA. Because trenches R1, R2, and R3 are tapered, their upper portions are joined together. Their lower portions may be separated from one another by remnants 84 of wafer 2, which may include portions of semiconductor substrate 20 and may or may not include remnants of dielectric layer 26.

[0058] Since the profiles of the trenches R1, R2, and R3 are tapered, the residual portions 84 are also tapered, with the upper portions of the residual portions 84 being narrower than the respective lower portions. The top surface of the semiconductor substrate 20 between the residual portions 84 (below the trenches R1, R2, and R3) may be flat, rounded, or may have an irregular shape.

[0059] like Figure 11B As shown, in the top view of the wafer 2, the residual portion 84 may also have a strip shape, which may extend from the left edge of the wafer 2 (in the X direction) to the right edge of the wafer 2, and from the top edge of the wafer 2 (in the Y direction of the top view) to the bottom edge of the wafer 2. Figure 12 The resulting cross-sectional view after the third, narrower laser slotting process is shown.

[0060] refer to Figure 13 , a wide blade sawing (grooving) process is performed using a blade 86, which is used to saw the portion of the wafer 2 in the peripheral region P1 (and a possible sub-portion of the peripheral region P2). The corresponding process is shown as Figure 21 The process 224 in the process flow 200 is shown. The blade 86 also extends slightly into the combined groove RA, so that the blade 86 is located opposite the combined groove RA ( Figure 12 ) between the interconnect structure 24 is completely removed. The blade 86 has the ability to remove metal, so that if the pseudo conductive feature 36 ( Figure 8 ), then also remove the pseudo conductive component 36 ( Figure 8 According to an alternative embodiment, the formation of the trench RB is performed by another method such as etching. Figure 14 ) wide slotting process.

[0061] Figure 14 FIG2 shows the wafer 2 after the wide blade sawing process. The blade 86 cuts into the semiconductor substrate 20 but does not cut through the semiconductor substrate 20. Accordingly, the top surface TopS2 of the semiconductor substrate 20 is generated by the wide blade sawing process. Depending on the blade 86, the top surface TopS2 may be flat, or may have other cross-sectional shapes, such as a V-shape, a curved shape, etc. For example, when the top surface TopS2 has a V-shape, the top surface TopS2 may be straight and inclined. On the other hand, the top surface TopS1 ( Figure 16A ) may be irregular or may be curved.

[0062] refer to Figure 15 , a narrow blade sawing process is performed using the blade 88 used for sawing the wafer 2 in the peripheral region P1. Thus, the reconstructed wafer 100 is sawn into the wafers 100 including the device dies 4 and 50 ( Figure 8 The corresponding process is shown as Figure 21 Process 226 of process flow 200 is shown. Blade 88 travels within peripheral region P1 such that blade 88 does not physically contact interconnect structure 24 and dielectric layer 26. It will be appreciated that if blade 88 physically contacts dielectric layer 26 during the narrow blade sawing process, the physical force introduced by blade 88 may tear dielectric layer 26, and delamination may occur between dielectric layer 26 and semiconductor substrate 20.

[0063] If a narrow laser grooving process is performed in each peripheral region P2 to form the trench R1, the width of the trench R1 is small and does not allow for sufficient process margin. A laser grooving process may have to be used to remove the dielectric layer 26 from the peripheral region P1 using a high-energy, wide laser beam. However, it is difficult to control the high-energy, wide laser beam grooving process and to remove all of the dielectric layer in the peripheral region P1 without worrying about overgrooving (and opening) the semiconductor substrate 20.

[0064] According to an embodiment of the present disclosure, by performing a plurality of narrow slotting processes, the combined trench RA is widened and a sufficient process margin is generated, thereby enabling a wide blade sawing process (using blade 86, Figure 13 ) can be performed, and the wide blade sawing process has the ability to accurately and completely remove the dielectric layer 26 without cutting through the semiconductor substrate 20.

[0065] Figure 16A The edge portion of the device die 4 after the narrow blade sawing process is shown, wherein the edge portion is located at Figure 15 The device die 4 includes a combined trench RA generated by a narrow laser grooving process and a trench RB generated by a wide blade sawing process. The residual portion 84 is located in the combined trench RA and may or may not include the dielectric layer 26. The topmost end of the residual portion 84 may be higher than the top surface 20TS of the semiconductor substrate 20, flush with the top surface 20TS of the semiconductor substrate 20, or lower than the top surface 20TS of the semiconductor substrate 20, which also forms an interface with the dielectric layer 26 above. Figure 16A In the embodiment of the present invention, the top surface TopS2 may be lower than the top surface TopS1, flush with the top surface TopS1, or higher than the top surface TopS1. The residual portion 84 is located in the extended portion of the semiconductor substrate 20 extending beyond the edge 100E2.

[0066] Due to the laser grooving process, the edge 100E2 is inclined and may be straight. According to some embodiments, the inclination angle α1 may be in a range between about 80 degrees and about 88 degrees.

[0067] Figure 16B A top view of a package 100 ′ is shown according to some embodiments, wherein Figure 16A The cross-sectional view shown in Figure 16B The cross section 16A-16A in FIG. 1 is obtained. When viewed in a top view, the residual portion 84 may have a length direction parallel to the edge 100E1 of the package 100 '. Each edge portion of the device die 4 has one or more strip-shaped residual portions 84 parallel to the corresponding edge 100E1. The residual portions 84 parallel to different edges 100E1 are physically disconnected from each other. Some residual portions 84 (marked as 84') may also be formed as non-elongated discrete portions. Figure 16B In the embodiment, the portion of the package 100 ′ beyond the edge 100E1 is referred to as an extended portion.

[0068] Figure 17 and Figure 18An intermediate stage of forming a package 100' according to an alternative embodiment is shown. Unless otherwise noted, the materials, structures, and formation processes of the components in these embodiments are substantially the same as those of the components represented by the same reference numerals in the previous embodiments. Throughout the description, details regarding materials, structures, and formation processes provided in each embodiment can be applied to any other embodiment, as applicable.

[0069] The initial process of these embodiments is Figures 1 to 12 Next, as shown in Figure 17 As shown, a defocused laser cleaning process is performed using a defocused laser beam 92 to remove residual portion 84 in peripheral region P2. Defocused laser beam 92 may be defocused from the top surface of wafer 2 and may be defocused from the surface of semiconductor substrate 20 to widen the laser beam and reduce irradiation energy. As a result, residual portion 84 may be removed or reduced without further grooves in semiconductor substrate 20. According to some embodiments, the focal point of laser beam 92 may be located at a position higher than the top surface of wafer 2, for example, with a height difference within a range between approximately 200 μm and approximately 400 μm. Profile 94 illustrates the power density of defocused laser beam 92 according to some embodiments. Figure 18 The resulting structure is shown.

[0070] After the defocused laser cleaning process, perform Figures 13 to 15 The process shown. Figure 19 The resulting package 100' is shown. Figure 19 The residual portion 84 shown has some portions remaining, but the residual portion 84 may also be completely removed. Due to the laser grooving process, the edge 100E2 is inclined and may be straight. According to some embodiments, the inclination angle α1 may be in a range between about 80 degrees and about 88 degrees. The defocused laser cleaning process also causes the edge 100E3 to be formed as an inclined edge, and the edge 100E3 has an inclination angle α2 that is greater than the inclination angle α1. The inclination angle α2 may be in a range between about 75 degrees and about 85 degrees. The difference (α2-α1) may be greater than about 5 degrees and may be in a range between about 5 degrees and about 10 degrees.

[0071] In the embodiments shown above, some processes and components are discussed to form three-dimensional (3D) packages according to some embodiments of the present disclosure. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. For example, the test structure may include test pads formed in a redistribution layer or on a substrate, the test pads allowing testing of 3D packages or 3DICs, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that combine intermediate verification of known good dies to increase yield and reduce costs.

[0072] Embodiments of the present disclosure have several advantageous features. By performing multiple narrow laser grooving processes with partially overlapping laser paths, the width of the resulting combined trench increases. This enables the use of a wide sawing blade without the risk of the blade tearing the dielectric layer. Consequently, the accuracy of the wide sawing / grooving process is improved, allowing the wide sawing / grooving process to stop at the semiconductor substrate without penetrating the semiconductor substrate.

[0073] According to some embodiments of the present disclosure, a method includes: performing a first plurality of laser grooving processes on a scribe line of a substrate to form a first combined groove; performing a second plurality of laser grooving processes on the scribe line of the substrate to form a second combined groove; performing a first sawing process on the scribe line of the substrate, wherein the first sawing process is performed in a portion of the scribe line between the first combined groove and the second combined groove; and performing a second sawing process to saw through the substrate in the scribe line, wherein the second sawing process separates a first device die and a second device die on opposite sides of the scribe line from each other.

[0074] In one embodiment, the first plurality of laser grooving processes includes a first grooving process along a first path in the scribe line, and a second grooving process along a second path in the scribe line, wherein the second path partially overlaps the first path. In one embodiment, the first plurality of laser grooving processes also includes a third grooving process along a third path in the scribe line, wherein the third path partially overlaps the second path. In one embodiment, the first combined trench is wider than a single trench generated by a single grooving process included in the first plurality of laser grooving processes.

[0075] In one embodiment, the first sawing process generates a third trench that joins the first combined trench to the second combined trench. In one embodiment, the first sawing process is stopped after the semiconductor substrate of the substrate is exposed and before the semiconductor substrate is sawed through. In one embodiment, the first sawing process is performed using a blade. In one embodiment, the method further includes performing a defocused laser grooving process on the first combined trench.

[0076] In an embodiment, the first combined trench extends into the semiconductor substrate of the substrate, and at least a remaining portion of the semiconductor substrate is located below the first combined trench and between two trenches generated by two trenching processes in the plurality of trenching processes. In an embodiment, after the second sawing process, the first device die includes a portion of the first combined trench.

[0077] According to some embodiments of the present disclosure, a structure includes a first device die, the first device die including a semiconductor substrate, wherein the semiconductor substrate includes: a first edge and a second edge laterally recessed from the first edge, wherein the second edge has at least a portion higher than the first edge; a first top surface laterally located between the first edge and the second edge; and a first section protruding above the first top surface, wherein the first section is also laterally located between the first edge and the second edge.

[0078] In an embodiment, the first subdivision is tapered and includes a lower portion and an upper portion, and wherein the upper portion is narrower than a corresponding portion of the lower portion. In an embodiment, the first device die further includes a plurality of dielectric layers located above the semiconductor substrate, and wherein the first subdivision further includes subdivisions of the plurality of dielectric layers. In an embodiment, the semiconductor substrate includes a flat top surface that merges with the second edge, and wherein a topmost end of the first subdivision is lower than the flat top surface.

[0079] In an embodiment, a first top surface of the semiconductor substrate is bonded to the first edge, and wherein the semiconductor substrate further comprises a second top surface bonded to the bottom of the first segment, and wherein the first top surface and the second top surface are at different levels. In an embodiment, the first top surface of the semiconductor substrate is bonded to the first edge and is planar, and wherein the second top surface is non-planar. In an embodiment, the structure further comprises a second device die positioned below and electrically connected to the first device die; and a gap-fill region positioned on an opposite side of the second device die, wherein the gap-fill region comprises an additional edge vertically aligned with the first edge of the semiconductor substrate.

[0080] According to some embodiments of the present disclosure, a structure includes: a device die, the device die including: multiple dielectric layers; and a semiconductor substrate located below the multiple dielectric layers, wherein the semiconductor substrate includes: a first top surface located below and in contact with the multiple dielectric layers; and a first extension portion extending laterally beyond a first edge of the multiple dielectric layers, wherein the first extension portion includes: a second top surface lower than the first top surface; and a first section protruding above the second top surface, wherein, in a top view of the structure, the first section has a strip shape, and a first length direction of the first section is parallel to the first edges of the multiple dielectric layers.

[0081] In one embodiment, the semiconductor substrate further includes a second extension portion extending laterally beyond the second edge of the plurality of dielectric layers, wherein the second extension portion includes: a third top surface lower than the first top surface; and a second subdivision protruding above the third top surface, wherein, in a top view of the structure, the second subdivision has a second length direction perpendicular to the first length direction. In one embodiment, the first extension portion further includes: an additional subdivision protruding above the second top surface, wherein, in a top view of the structure, the additional subdivision is parallel to the first subdivision.

[0082] According to one aspect of the present application, a method for forming a package is disclosed, the method comprising: performing a first plurality of laser grooving processes on a scribe line of a substrate to form a first combined trench; performing a second plurality of laser grooving processes on the scribe line of the substrate to form a second combined trench; performing a first sawing process on the scribe line of the substrate, wherein the first sawing process is performed in a portion of the scribe line between the first combined trench and the second combined trench; and performing a second sawing process to saw through the substrate in the scribe line, wherein the second sawing process separates a first device die and a second device die on opposite sides of the scribe line from each other. In some embodiments, the first plurality of laser grooving processes includes: a first grooving process along a first path in the scribe line; and a second grooving process along a second path in the scribe line, wherein the second path partially overlaps the first path. In some embodiments, the first plurality of laser grooving processes further includes: a third grooving process along a third path in the scribe line, wherein the third path partially overlaps the second path. In some embodiments, the first combined trench is wider than a single trench generated by a single grooving process included in the first plurality of laser grooving processes. In some embodiments, the first sawing process generates a third groove that joins the first combined groove to the second combined groove. In some embodiments, the first sawing process is stopped after the semiconductor substrate of the substrate is exposed and before the semiconductor substrate is sawed through. In some embodiments, the first sawing process is performed using a blade. In some embodiments, the method of forming a package further includes performing a defocused laser grooving process on the first combined groove. In some embodiments, the first combined groove extends into the semiconductor substrate of the substrate, and at least a remaining portion of the semiconductor substrate is located below the first combined groove and between two grooves generated by two of the multiple grooving processes. In some embodiments, after the second sawing process, the first device die includes a portion of the first combined groove.

[0083] According to another aspect of the present application, a package is disclosed. The package includes: a first device die comprising a semiconductor substrate, wherein the semiconductor substrate includes a first edge and a second edge laterally recessed from the first edge, wherein the second edge has at least a portion higher than the first edge; a first top surface laterally located between the first edge and the second edge; and a first residual portion protruding above the first top surface, wherein the first residual portion is also laterally located between the first edge and the second edge. In some embodiments, the first residual portion is tapered and includes a lower portion and an upper portion, wherein the upper portion is narrower than a corresponding portion of the lower portion. In some embodiments, the first device die further includes a plurality of dielectric layers located above the semiconductor substrate, and wherein the first residual portion further includes portions of the plurality of dielectric layers. In some embodiments, the semiconductor substrate includes a flat top surface joined to the second edge, and wherein a topmost portion of the first residual portion is lower than the flat top surface. In some embodiments, the first top surface of the semiconductor substrate is joined to the first edge, and wherein the semiconductor substrate further includes a second top surface joined to a bottom portion of the first residual portion, and wherein the first and second top surfaces are at different levels. In some embodiments, the first top surface of the semiconductor substrate is planar in conjunction with the first edge, and wherein the second top surface is non-planar. In some embodiments, the package further comprises: a second device die positioned below and electrically connected to the first device die; and a gap-fill region positioned on an opposite side of the second device die, wherein the gap-fill region comprises an additional edge vertically aligned with the first edge of the semiconductor substrate.

[0084] According to another aspect of the present application, a package is disclosed, comprising: a device die, the device die comprising: a plurality of dielectric layers; and a semiconductor substrate disposed beneath the plurality of dielectric layers, wherein the semiconductor substrate comprises: a first top surface disposed beneath and in contact with the plurality of dielectric layers; and a first extension extending laterally beyond first edges of the plurality of dielectric layers, wherein the first extension comprises: a second top surface lower than the first top surface; and a first subsection protruding above the second top surface, wherein, in a top view of the package, the first subsection has a stripe shape, and a first length direction of the first subsection is substantially parallel to the first edges of the plurality of dielectric layers. In some embodiments, the semiconductor substrate further comprises: a second extension extending laterally beyond second edges of the plurality of dielectric layers, wherein the second extension comprises: a third top surface lower than the first top surface; and a second subsection protruding above the third top surface, wherein, in a top view of the package, the second subsection has a second length direction perpendicular to the first length direction. In some embodiments, the first extending portion further includes an additional portion protruding above the second top surface, wherein the additional portion is parallel to the first portion in a top view of the package.

[0085] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis to design or modify other operations and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a package, comprising: performing a first plurality of laser grooving processes on the scribe lines of the substrate to form first combined trenches; performing a second plurality of laser grooving processes on the scribe lines of the substrate to form second combined trenches; performing a first sawing process on the scribe line of the substrate, wherein the first sawing process is performed in a portion of the scribe line between the first combined trench and the second combined trench; and A second sawing process is performed to saw through the substrate in the scribe line, wherein the second sawing process separates the first device die and the second device die on opposite sides of the scribe line from each other.

2. The method according to claim 1, wherein The first plurality of laser grooving processes include: a first trenching process along a first path in the scribe line; and A second trenching process is performed along a second path in the scribe line, wherein the second path partially overlaps the first path.

3. The method according to claim 2, wherein: The first plurality of laser grooving processes further comprises: A third trenching process is performed along a third path in the scribe line, wherein the third path partially overlaps the second path.

4. The method according to claim 1, wherein The first combined trench is wider than a single trench generated by a single trenching process included in the first plurality of laser trenching processes.

5. The method according to claim 1, wherein The first sawing process creates a third trench that joins the first combined trench to the second combined trench.

6. The method according to claim 1, wherein The first sawing process is stopped after the semiconductor substrate of the substrate is exposed and before sawing through the semiconductor substrate.

7. The method according to claim 1, wherein The first sawing process is performed using a blade. The method of claim 1 , further comprising performing a defocused laser grooving process on the first combined trench.

9. A package comprising: A first device die includes a semiconductor substrate, wherein the semiconductor substrate includes: a first edge and a second edge laterally recessed from the first edge, wherein the second edge has at least a portion that is higher than the first edge; a first top surface laterally located between the first edge and the second edge; and A first residual portion protrudes above the first top surface, wherein the first residual portion is also laterally located between the first edge and the second edge.

10. A package comprising: A device die, the device die comprising: multiple dielectric layers; and a semiconductor substrate located below the plurality of dielectric layers, wherein the semiconductor substrate comprises: a first top surface underlying and contacting the plurality of dielectric layers; and A first extension portion extending laterally beyond first edges of the plurality of dielectric layers, wherein the first extension portion comprises: a second top surface, lower than the first top surface; and The first section protrudes above the second top surface, wherein the first section has a strip shape in a top view of the package, and a first length direction of the first section is substantially parallel to the first edges of the plurality of dielectric layers.

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