Unbiased device under circuit transistor drain and source interconnection

Abstract

The invention relates to an unbiased device under circuit transistor drain and source interconnects. The electronic circuit includes a plurality of field effect transistors (FETs). The plurality of FETs includes a plurality of circuit transistors having drain and source regions connected to a circuit, and a plurality of floating transistors having unconnected and floating drain, source, and gate regions. The plurality of circuit transistors are alternately arranged with the plurality of floating transistors such that the circuit transistors are arranged adjacent to the floating transistors, and at least a portion of a conductive interconnect connected to the circuit transistors is arranged over drain and source regions of the floating transistors.

Description

Technical Field

[0001] This document generally applies to integrated circuit dies or chips, but is not limited thereto. Some embodiments relate to improved layout of integrated circuit elements in an integrated circuit chip. Background Art

[0002] Integrated circuits (ICs) continue to increase in complexity. An IC includes integrated circuit components (e.g., transistors) and conductive interconnects that connect these components. More integrated circuit components are integrated into an IC chip to increase its functionality. Reducing feature size allows more integrated circuit components to be incorporated into an IC chip. However, as more components are included in an IC chip, interconnecting them becomes more difficult. As the feature size of integrated circuit components decreases, the size of the conductive connections does not always decrease, but it is desirable to keep the size of the IC chip small. Therefore, there is a general need for devices, systems, and methods that address the challenges of interconnecting integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views, while numerals having different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example and not limitation, various embodiments discussed in this document.

[0004] Figure 1 An example of circuit transistors of an integrated circuit (IC) chip is shown.

[0005] Figure 2 Another example of a circuit transistor of an IC chip is shown.

[0006] Figure 3 An example of an array of multiple transistors arranged in rows and columns of transistors is shown.

[0007] Figure 4 Another example of a circuit transistor and a floating transistor of an IC chip is shown.

[0008] Figure 5 and Figure 6 A further example of a plurality of transistor arrays is shown.

[0009] Figure 7 is a flowchart of an example of a method of manufacturing an IC. DETAILED DESCRIPTION

[0010] To meet the demand for increasing functional complexity in small electronic devices, manufacturers have increased the density of integrated circuit components in integrated circuit (IC) dies or chips.To increase density, manufacturers have worked to reduce the feature size of semiconductor devices used on IC chips.

[0011] However, scaling transistor functionality to smaller dimensions creates challenges for device layout. Three-dimensional conductive interconnects, such as metal interconnects, are used to connect circuit elements. Tighter geometries create higher three-dimensional parasitic coupling. Metals with lower resistance values ​​are used for interconnects to reduce parasitic resistance. This type of interconnect does not scale as the pitch or feature size of semiconductor integrated devices, such as transistors, decreases. This makes connecting the low-level terminals of transistors challenging.

[0012] Figure 1 An example of a circuit transistor 102 of an IC chip is shown. The transistor is a field effect transistor (FET), such as a metal oxide field effect transistor (MOSFET). In some examples, the FET can include a FinFET. The example shows an oxide diffusion (OD) region 104, gate polysilicon 106, source metal strip 108, drain metal strip 110, and gate metal 112.

[0013] Figure 2 Another example of a circuit transistor 102 is shown. Metal interconnects connect the circuit transistor 102 to other circuits of the IC chip. Figure 2 The spacing ratio in the north-south direction (or y direction) Figure 1 The spacing in the circuit transistor 102 is doubled. In addition, floating transistors 220 are added on the north and south sides of the circuit transistor 102. The floating transistor 220 includes the oxide diffusion region 104 and the gate polysilicon 106, but does not include any metal interconnects that contact the drain or source regions of the floating transistor 220. The interconnects of the circuit transistor 102 are routed in the space created by the floating transistor 220. The floating terminals simplify the interconnections with the circuit transistor 102 in the surrounding area. This simplified routing results in better drain-to-source resistance (Rds) of the circuit transistor. The unbiased device also reduces the total parasitic source capacitance (Cs) and parasitic drain capacitance (Cd).

[0014] Figure 3 An example of an array of multiple FETs arranged in rows and columns is shown. The FETs include circuit transistors 102 and floating transistors 220. Circuit transistors 102 have drain, source, and gate regions that are connected to other circuits or circuit elements of the IC chip. Floating transistors 220 are not connected and have floating drain, source, and gate regions. This example includes only two circuit transistors 102 in a row of circuit transistors to simplify the diagram for explanation purposes. A practical implementation may have hundreds of circuit transistors 102 arranged in a row.

[0015] The rows of circuit transistors 102 and floating transistors 220 are arranged alternately so that the circuit transistors 102 are adjacent to the floating transistors 220 to the north and south of the circuit transistor 102, as shown in FIG. Figure 2 As shown in the example. Figure 2As shown, the pitch in the column direction is greater than the pitch in the row direction. At least a portion of the interconnects to the circuit transistor 102 are routed over the floating drain, source, and gate regions of the floating transistor 220. Figure 3 The example in shows rows of floating transistors 220 alternating with rows of circuit transistors 102. In another exemplary arrangement, columns of floating transistors 220 alternate with columns of circuit transistors 102.

[0016] exist Figure 3 In the example of FIG. 1 , the periphery of the floating transistor 220 surrounds the AC circuit transistor 102 and the floating transistor 220. To simplify the illustration, Figure 3 Not shown in FIG. 2 are the bottom peripheral rows of floating transistors 220. None of the peripheral floating transistors 220 are connected to a voltage plane or a ground plane.

[0017] Figure 4 Another example of a circuit transistor 102 and a floating transistor 220 is shown. Figure 4 The example of FIG. 1 shows the source (s) and drain (d) regions of the circuit transistor 102 and the floating transistor 220 . Figure 4 Also shown are the polysilicon (poly) and field poly-on-Fox of the gate regions of the circuit transistor 102 and the floating transistor 220 . Figure 4 Contacts are shown for the drain and source regions of circuit transistor 102. The drain, source, and gate regions of floating transistor 220 are all floating and do not contact the interconnects routed to circuit transistor 102. Figure 4 As shown, if metal interconnects are connected to the drain, source, and gate regions of floating transistor 220, then floating transistor 220 can be a fully functional transistor.

[0018] Back to Figure 3 , the rows of circuit transistors 102 and floating transistors 220 have continuous oxide diffusion regions between the rows of FETs. Figure 5 Another example of an array of multiple FETs arranged in rows and columns is shown. Figure 5 In the example of , the transistor layout is modular, with rows of circuit transistors 102 and floating transistors 220 having spaces 522 in the oxide diffusion regions between the FET rows.

[0019] Figure 6 Another example of an array of circuit transistors 102 and floating transistors 220 arranged in rows and columns is shown. Figure 3 As in the example of FIG, the periphery of the floating transistor 220 surrounds the AC circuit transistor 102 and the floating transistor 220. Figure 6In the example shown, guard ring region 624 surrounds AC circuit transistor 102 and floating transistor 220, as well as peripheral floating transistor 220. To simplify the illustration, guard ring region 624 is shown only on one side of the FET array. Guard ring region 624 includes devices of a different type than AC circuit transistor 102 and floating transistor 220. AC circuit transistor 102 and floating transistor 220 can be n-type FETs, with guard ring region 624 including p-type floating devices. Alternatively, AC circuit transistor 102 and floating transistor 220 can be p-type FETs, with guard ring region 624 including n-type floating devices.

[0020] The guard ring region 624 includes region 626. The devices 628 in region 626 are floating structures. These structures can be transistors except for the lack of metal interconnects contacting the drain, source, and gate regions. However, these devices may not be functional transistors because they have the same diffusion as the substrate. Region 630 of the guard ring outer region 626 includes devices where structural regions (such as the drain-source regions) can serve as substrate connections and can be connected to circuit ground or voltage planes depending on whether the device is n-type or p-type. The polysilicon regions of the devices in region 630 can be floating.

[0021] Figure 7 7 is a flow chart of an example method 700 for manufacturing an IC. At block 705, active regions of a plurality of FETs are formed on a semiconductor substrate of the IC. The FETs may be FinFETs. Forming the active regions may include forming rows of oxide diffusions for the active regions. In some examples, the rows are continuous, while in some examples, the rows of oxide diffusions are separated and modularized.

[0022] At block 710, a plurality of FETs are created by forming drain and source regions in an active region and forming gate regions of the FETs on the active region. The FETs may be formed as an array of rows and columns of FETS.

[0023] At block 715, an alternating arrangement of circuit transistors and floating transistors is created. Circuit transistors are formed by connecting drain, source, and gate regions to conductive interconnects. A floating transistor is a transistor whose drain, source, and gate regions are unconnected. In some examples, the circuit transistors are formed by connecting alternating rows of transistors to form a circuit transistor row, with the drain, source, and gate regions of transistors in rows on either side of the circuit transistor being unconnected to form the floating transistor region.

[0024] In some examples, forming the alternating arrangement of circuit transistors and floating transistors includes forming rows of transistors with a spacing greater than a spacing between transistors within a row. The circuit transistors can be formed by connecting alternating columns of transistors to form columns of circuit transistors, with drain, source, and gate regions of transistors in columns on either side of the circuit transistor being unconnected and floating.

[0025] At block 720, at least a portion of the conductive interconnects connected to the circuit transistors are arranged or routed over the drain, source, and gate regions of the floating transistors. A periphery of the floating transistors can be formed around rows and columns of alternating or interleaved circuit transistors and floating transistors. In some examples, a guard ring is formed around the periphery of the floating transistors.

[0026] Systems and methods for interconnecting semiconductor devices, such as transistors, within an integrated circuit chip having dense geometries have been described. The additional area provided by floating transistors near the circuit transistors allows for wiring pathways to connect the circuit transistors.

[0027] Additional Notes and Examples

[0028] A first example (Example 1) includes a subject matter (e.g., an electronic device) including a plurality of field effect transistors (FETs). The FETs include a plurality of circuit transistors having drain and source regions connected to a circuit, and a plurality of floating transistors having unconnected and floating drain, source, and gate regions. The plurality of circuit transistors are arranged alternately with the plurality of floating transistors such that the circuit transistors are arranged adjacent to the floating transistors, and at least a portion of a conductive interconnect connected to the circuit transistors is arranged above the drain and source regions of the floating transistors.

[0029] In Example 2, the subject matter of Example 1 optionally includes the FETs arranged in a transistor array having columns and rows of transistors, and the rows of circuit transistors alternate with rows of floating transistors in the transistor array.

[0030] In Example 3, the subject matter of Example 2 can optionally include a FET comprising an oxide diffusion region, and wherein the transistor array comprises spaces in the oxide diffusion region between the transistors.

[0031] In Example 4, the subject matter of Example 2 optionally includes a FET comprising an oxide diffusion region, and wherein the transistor array comprises spaces in the oxide diffusion region between the transistors.

[0032] In Example 5, the subject matter of Example 1 optionally includes the FETs arranged in a transistor array having columns and rows of transistors, and the columns of circuit transistors alternate with columns of floating transistors in the transistor array.

[0033] In Example 6, the subject matter of one or any combination of Examples 1-5 optionally includes the FETs arranged in a transistor array having columns and rows of transistors, and the peripheral rows and columns of transistors include all floating transistors not connected to a voltage or ground plane.

[0034] In Example 7, the subject matter of one or any combination of Examples 1-6 can optionally include a spacing between FETs in a column direction being greater than a spacing between FETs in a row direction.

[0035] In Example 8, the subject matter of one or any combination of Examples 1-7 can optionally include drain and source regions of the floating transistor not being electrically connected to a voltage plane or a ground plane.

[0036] In Example 9, the subject matter of one or any combination of Examples 1-8 can optionally include the plurality of FETs comprising FinFets.

[0037] In Example 10, the subject matter of one or any combination of Examples 1-9 optionally includes the conductive interconnect comprising metal, wherein none of the metal contacts a drain, source, or gate region of the floating transistor.

[0038] Example 11 includes subject matter (e.g., a method of fabricating an integrated circuit), or may optionally include such subject matter by combination with one or more combinations of Examples 1-10, including forming active regions of a plurality of field effect transistors (FETs) on a semiconductor substrate of the integrated circuit, forming the plurality of FETs by forming drain and source regions in the active regions and forming gate regions, forming an alternating arrangement of circuit transistors and floating transistors by connecting the drain, source, and gate regions of alternating transistors to conductive interconnects as circuit transistors and having unconnected drain, source, and gate regions as floating transistors, and disposing at least a portion of the conductive interconnect connected to the circuit transistors over the drain and source regions of the floating transistors.

[0039] In Example 12, the subject matter of Example 11 optionally includes forming an array of columns and rows of a plurality of FETs, connecting drain, source, and gate regions of the FETs in a row of FETs to form a row of circuit transistors with a row of floating transistors on either side of the row of circuit transistors, and routing at least a portion of the conductive interconnects over the floating transistors in the row of floating transistors.

[0040] In Example 13, the subject matter of one or both of Examples 11 and 12 can optionally include forming a continuous row of oxide diffusions for the active area, and forming an array of columns and rows of active areas for the plurality of FETs in the row of oxide diffusions.

[0041] In Example 14, the subject matter of one or both of Examples 11 and 12 optionally includes forming rows of separate regions of oxide diffusion for the active regions, and forming an array of columns and rows of active regions for the plurality of FETs, wherein the active regions in a row are formed in separate regions of oxide diffusion.

[0042] In Example 15, the subject matter of one or any combination of Examples 11-14 optionally includes forming an array of columns and rows of a plurality of FETs, connecting drain, source, and gate regions of the FETs into the columns of FETs to form columns of circuit transistors with a column of floating transistors on either side of the columns of circuit transistors, and routing at least a portion of the conductive interconnects over the floating transistors of the columns of floating transistors.

[0043] In Example 16, the subject matter of one or any combination of Examples 11-15 optionally includes forming an array of columns and rows of a plurality of FETs and not connecting any FETs in peripheral columns and rows of FETs to a conductive interconnect such that the peripheral columns and rows include all floating transistors.

[0044] In Example 17, the subject matter of one or any combination of Examples 11-16 optionally includes forming the FETs in an array comprising FET columns and FET rows such that a FET spacing between FET rows is greater than a FET pitch between FET columns.

[0045] In Example 18, the subject matter of one or any combination of Examples 11-17 can optionally include forming a plurality of FinFETs included in the FET.

[0046] In Example 19, the subject matter of one or any combination of Examples 11-18 can optionally include forming n-type FETs, forming alternating n-type circuit FETs and n-type floating FETs, and forming a p-type floating device guard ring around the n-type circuit FETs and n-type floating FETs.

[0047] In Example 20, the subject matter of one or any combination of Examples 11-18 optionally includes forming p-type FETs, forming alternating p-type circuit FETs and p-type floating FETs, and forming a guard ring of n-type floating devices around the p-type circuit FETs and the p-type floating FETs.

[0048] These non-limiting examples may be combined in any permutation or combination. The foregoing detailed description includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." All publications, patents, and patent documents cited herein are incorporated herein by reference in their entirety, as if individually incorporated herein by reference. If there is a discrepancy between the usage of this document and a document incorporated by reference, the usage in the incorporated reference should be considered supplementary to the usage of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0049] In this document, the terms "a" or "an" are common in patent documents and are used to include one or more, independent of any other instance or usage of "at least one" or "one or more." In this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise noted. In the appended claims, the terms "including" and "in which" are used as synonyms for the respective terms "comprising" and "wherein." Furthermore, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements other than the elements listed after such terms in a claim are considered to fall within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects. The method examples described herein may be at least partially machine or computer implemented.

Claims

1. An electronic device comprising: multiple field-effect transistors (FETs); wherein the plurality of FETs include a plurality of circuit transistors having drain and source regions connected to the circuit, and a plurality of floating transistors having drain, source, and gate regions that are unconnected and floating; wherein a plurality of circuit transistors and a plurality of floating transistors are alternately arranged such that the circuit transistors are arranged adjacent to the floating transistors; and Wherein at least a portion of a conductive interconnect connected to the circuit transistor is disposed over drain and source regions of the floating transistor.

2. The electronic device according to claim 1, wherein the plurality of FETs are arranged in a transistor array having transistor columns and transistor rows; and The transistor array comprises rows of circuit transistors alternating with rows of floating transistors.

3. The electronic device according to claim 2, Wherein the plurality of FETs include oxide diffusion regions, and wherein the transistor array includes spaces in the oxide diffusion regions between transistors.

4. The electronic device according to claim 2, Wherein the plurality of FETs include oxide diffusion regions, and wherein the oxide diffusion regions are continuous between rows of transistors in the transistor array.

5. The electronic device according to claim 1, wherein the plurality of FETs are arranged in a transistor array having transistor columns and transistor rows; and The transistor array comprises columns of circuit transistors alternating with columns of floating transistors.

6. The electronic device according to claim 1, wherein the plurality of FETs are arranged in a transistor array having transistor columns and transistor rows; and The peripheral rows and columns of transistors include all floating transistors that are not connected to a voltage or ground plane. 7 . The electronic device of claim 1 , wherein a spacing between the FETs in a column direction is greater than a pitch between the FETs in a row direction. 8 . The electronic device of claim 1 , wherein the drain and source regions of the floating transistor are not electrically connected to a voltage plane or a ground plane.

9. The electronic device of claim 1, wherein the FET comprises a FinFET.

10. The electronic device defined in claim 1 wherein the conductive interconnect comprises metal, and wherein no metal contacts the drain, source, or gate regions of the floating transistor.

11. A method of manufacturing an integrated circuit, the method comprising: forming active regions of a plurality of field effect transistors (FETs) on a semiconductor substrate of the integrated circuit; forming a plurality of FETs by forming drain and source regions in the active region and forming a gate region; forming an alternating arrangement of circuit transistors and floating transistors by connecting drain, source, and gate regions of alternating transistors to a conductive interconnect as circuit transistors and having unconnected drain, source, and gate regions as floating transistors; and At least a portion of a conductive interconnect connected to the circuit transistor is disposed over drain and source regions of the floating transistor.

12. The method according to claim 11, wherein forming the plurality of FETs comprises forming an array of columns and rows of the plurality of FETs; and Wherein forming the circuit transistors and the floating transistors in an alternating arrangement comprises: connecting drain, source, and gate regions of the FETs to the FET row to form a circuit transistor row, wherein the circuit transistor row is flanked by floating transistor rows on either side; and At least a portion of the conductive interconnect is routed over the floating transistors of the floating transistor row.

13. The method of claim 11 , wherein forming the active region comprises: forming a continuous row of oxide diffusions for the active area; and An array of columns and rows of active areas are formed in the rows of oxide diffusions for a plurality of FETs.

14. The method of claim 11 , wherein forming the active region comprises: forming rows of separate regions of oxide diffusion for said active area; and An array of columns and rows of active areas for a plurality of FETs is formed, wherein the active areas in a row are formed in separate oxide diffusion regions.

15. The method according to claim 11, wherein forming the plurality of FETs comprises forming an array of columns and rows of the plurality of FETs; and Wherein forming the circuit transistors and the floating transistors in an alternating arrangement comprises: connecting drain, source, and gate regions of the FETs into a column of FETs to form a column of circuit transistors, wherein the column of circuit transistors is flanked by columns of floating transistors; and At least a portion of the conductive interconnect is routed over the floating transistors of the column of floating transistors.

16. The method according to claim 11, wherein forming the plurality of FETs comprises forming an array of columns and rows of the plurality of FETs; and None of the FETs of the peripheral columns and rows of FETs are connected to the conductive interconnects such that the peripheral columns and rows include all floating transistors.

17. The method according to claim 11, Wherein forming the plurality of FETs comprises forming the FETs in an array comprising FET columns and FET rows such that a FET spacing between the FET rows is greater than a FET pitch between the FET columns. The method of claim 11 , wherein forming the plurality of FETs comprises forming a plurality of FinFETs.

19. The method of claim 11 , wherein forming the plurality of FETs comprises: Forming an n-type FET; forming n-type circuit FETs and n-type floating FETs arranged alternately; and A guard ring of the p-type floating device is formed around the n-type circuit FET and the n-type floating FET.

20. The method of claim 11, wherein forming the plurality of FETs comprises: Forming a p-type FET; forming p-type circuit FETs and p-type floating FETs arranged alternately; and A guard ring for the n-type floating device is formed around the p-type circuit FET and the p-type floating FET.

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