Capacitor and manufacturing method thereof, storage array, memory and electronic equipment

Abstract

The invention provides a capacitor and a manufacturing method thereof, a storage array, a memory and electronic equipment. The capacitor comprises a first electrode, a second electrode and a ferroelectric layer located between the first electrode and the second electrode, and the ferroelectric layer comprises a non-doped layer and a doped layer. The anti-breakdown electric field capability can be improved, so that the durability and the service life of the capacitor are improved.

Description

Technical Field

[0001] The present application relates to the field of information storage technology, and in particular to a capacitor and a manufacturing method thereof, a storage array, a memory and an electronic device. Background Art

[0002] Most electronic devices today are equipped with memory. Memory can be used to perform write and / or read operations to store and / or retrieve information. Capacitors are typically included in memory to filter out power supply noise in the memory.

[0003] The capacitor comprises a first electrode, a ferroelectric layer, and a second electrode. The ferroelectric layer is made of a ferroelectric material. During use, the ferroelectric layer undergoes multiple ferroelectric polarization reversals. These repeated ferroelectric polarization reversals increase the concentration of oxygen vacancies in the ferroelectric layer, leading to capacitor breakdown. Consequently, the durability and service life of capacitors in related art are relatively low. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides a capacitor and its manufacturing method, a storage array, a memory and an electronic device, which can improve the ability to resist the breakdown electric field, thereby improving the durability and service life of the capacitor.

[0005] In a first aspect of the present application, a capacitor is provided, comprising: a first electrode, a second electrode, and a ferroelectric layer located between the first electrode and the second electrode, wherein the ferroelectric layer comprises a doped layer and an undoped layer, and both the doped layer and the undoped layer comprise ferroelectric grains. In other words, the doping elements of the doped layer are integrated into the ferroelectric grains. Moreover, the doping elements can occupy the sites of the ferroelectric grains and form bonds with oxygen, thereby effectively suppressing the generation of charged oxygen vacancies, thereby facilitating the stabilization of the ferroelectric domains and thereby improving the stability of the ferroelectric grains. Furthermore, the doping layer elements do not cut off the integrity of the ferroelectric grains.

[0006] Furthermore, because the doping elements pin the oxygen vacancies in the ferroelectric layer, the migration of oxygen vacancies under the action of the electric field is effectively controlled during the ferroelectric domain reversal process, preventing them from moving arbitrarily. This increases the breakdown electric field and, in turn, the ability to withstand the electric field, thereby improving the durability of the ferroelectric material at the same operating voltage. Furthermore, it can reduce fatigue during continuous reversal, further improving durability. Furthermore, when the ability to withstand the electric field is improved, the service life of the capacitor can also be increased.

[0007] In some embodiments of the present application, the ferroelectric layer includes at least two undoped layers and at least one doped layer, with each doped layer positioned between two adjacent undoped layers. That is, there is at least one undoped layer between each doped layer and the first electrode, and at least one undoped layer between each doped layer and the second electrode. This prevents direct contact between the doped layer and the first or second electrode, potentially affecting the normal operation of the capacitor.

[0008] Regarding the capacitor structure, in one possible embodiment, a first electrode and a second electrode are stacked, and at least two undoped layers and at least one doped layer are stacked between the first and second electrodes. In one example, the first electrode, the ferroelectric layer, and the second electrode are stacked in a direction along the thickness of the memory. In another example, the first electrode, the ferroelectric layer, and the second electrode are stacked in a direction along the length or width of the memory.

[0009] Regarding the capacitor structure, in another possible embodiment, the second electrode is disposed around the first electrode, and at least two undoped layers and at least one doped layer are disposed around the first and second electrodes. In one example, the first electrode, the ferroelectric layer, and the second electrode can each have a ring-shaped quadrilateral structure. In another example, the first electrode, the ferroelectric layer, and the second electrode can each have a circular ring shape.

[0010] In some embodiments of the present application, the capacitor is symmetrical about the center plane, and the distance between the center plane and the surface of the first electrode away from the second electrode is the same as the distance between the center plane and the surface of the second electrode away from the first electrode. In this way, the absolute values ​​of the positive coercive field strength and the negative coercive field strength are the same, that is, the positive coercive field strength and the negative coercive field strength are symmetrical, so that the situation of flipping imbalance will not occur, thereby alleviating the situation that the storage state on one side cannot be maintained due to flipping imbalance. The larger imprinting effect will cause the ferroelectric polarization curve to shift at high temperature, thereby bringing about problems such as a decrease in the storage window, loss of storage information and difficulty in rewriting. Therefore, when the imprinting effect of the present application is alleviated, the offset of the ferroelectric polarization curve at high temperature can be reduced, thereby not causing the storage window to decrease, improving storage retention and reducing difficulty in rewriting.

[0011] Furthermore, the ferroelectric layer includes a first doped layer and a second doped layer, respectively, located on either side of the central plane. The distance between the first doped layer and the central plane is the same as the distance between the second doped layer and the central plane. That is, the first doped layer and the second doped layer are symmetrical about the central plane. The thickness of the undoped layer between the first doped layer and the second doped layer ranges from 3 nm to 5 nm, for example, 3 nm, 4 nm, or 5 nm. When the thickness of the undoped layer is less than 3 nm, the closer the first doped layer and the second doped layer are to the central plane, the greater the current density and the smaller the imprinting effect. Therefore, the closer the first doped layer and the second doped layer are to the central plane, the more effective the imprinting effect. However, this will result in poor domain continuity in the undoped layer, increased crystallization difficulty, and a significant reduction in remanent polarization. Furthermore, the control of oxygen vacancies near the interface between the first electrode and the undoped layer is lost, resulting in an increased depolarization field and a detrimental effect on the retention of the memory state. When the thickness is greater than 5 nm, the doped layer is further away from the central plane, which is beneficial for the retention of the memory state, but the mitigation of the imprinting effect is less effective. Therefore, when the thickness ranges from 3nm to 5nm, both the storage state maintenance and the mitigation of the imprinting effect can be taken into account.

[0012] In other possible embodiments, the first doped layer and the second doped layer are asymmetrically structured about the central plane. For example, the first doped layer and the second doped layer are located on the same side of the central plane; or the first doped layer and the second doped layer are located on opposite sides of the central plane, and the distance between the first doped layer and the central plane is greater than the distance between the second doped layer and the central plane.

[0013] In some embodiments of the present application, a projection of the doped layer on the first electrode is the same as a projection of the undoped layer on the first electrode.

[0014] In some embodiments of the present application, the material of the undoped layer includes hafnium oxide or hafnium zirconium oxide, and the doping element of the doped layer includes titanium, tantalum, or niobium. Since titanium, tantalum, or niobium are elements in the same group or adjacent subgroup as hafnium, their ionic radii are similar to those of hafnium and zirconium, and therefore, they can better occupy the lattice sites, lattice gaps, and grain boundary defects of hafnium oxide or hafnium zirconium oxide.

[0015] In some embodiments of the present application, the capacitor further includes a first conductive layer and a second conductive layer, the first conductive layer is located between the first electrode and the ferroelectric layer, and the second conductive layer is located between the second electrode and the ferroelectric layer.

[0016] In a second aspect of the present application, a memory array is provided, comprising a switch tube and a capacitor according to any one of the above embodiments, wherein the switch tube is electrically connected to the capacitor. The memory array can achieve all the effects of the capacitor.

[0017] In a third aspect of the present application, a memory is provided, comprising a controller and the aforementioned memory array, wherein the controller is electrically connected to the memory array. The memory can achieve all the effects of the memory array.

[0018] In a fourth aspect of the present application, an electronic device is provided, comprising a circuit board and the aforementioned memory, wherein the circuit board is electrically connected to the memory. The electronic device can achieve all the effects of the memory.

[0019] The fifth aspect of the present application provides a method for manufacturing a capacitor, which comprises: manufacturing a first electrode; manufacturing an initial ferroelectric layer on the first electrode, the initial ferroelectric layer comprising an initial non-doped layer and an initial doped layer stacked, the initial non-doped layer comprising ferroelectric grains, and the initial doped layer comprising doping elements; manufacturing a second electrode on the initial ferroelectric layer; performing a crystallization treatment on the initial ferroelectric layer to obtain a ferroelectric layer, the ferroelectric layer comprising a non-doped layer and a doped layer, both the non-doped layer and the doped layer comprising ferroelectric grains, and the doped layer comprising doping elements. In other words, the doping elements of the doping layer are integrated into the ferroelectric grains, and can occupy the sites of the ferroelectric grains and form bonds with oxygen, thereby effectively suppressing the generation of charged oxygen vacancies, thereby facilitating the stability of the ferroelectric domains and thereby improving the stability of the ferroelectric grains. Moreover, the doping layer elements do not cut off the integrity of the ferroelectric grains.

[0020] Furthermore, because the doping elements pin the oxygen vacancies in the ferroelectric layer, the migration of oxygen vacancies under the action of the electric field is effectively controlled during the ferroelectric domain reversal process, preventing them from moving arbitrarily. This increases the breakdown electric field and thus the ability to withstand the electric field, thereby improving the durability of the ferroelectric material at the same operating voltage. Furthermore, it can also reduce fatigue caused by continuous reversal, further improving durability. Furthermore, when the ability to withstand the electric field is improved, the service life of the capacitor can also be increased.

[0021] In some embodiments of the present application, the spacing between the initial doped layer closest to the first electrode and the first electrode is in the range of 0.1nm-10nm. If the spacing between the two is less than 0.1nm, the spacing between the two is too small, thereby causing the doping elements in the initial doped layer to diffuse to the first electrode during subsequent crystallization processing, thereby affecting the normal use of the capacitor. If the spacing between the two is greater than 10nm, the spacing between the two is too large, resulting in the thickness of the capacitor being too large, thereby increasing the volume of the capacitor and reducing the power density of the capacitor. Therefore, when the spacing between the two is in the range of 0.1nm-10nm, the normal use of the capacitor can be guaranteed, and the power density of the capacitor can be increased.

[0022] Moreover, the distance between the initial doping layer closest to the second electrode and the second electrode is in the range of 0.1 nm to 10 nm. Similarly, when the distance between the two is in the range of 0.1 nm to 10 nm, the normal use of the capacitor can be guaranteed and the power density of the capacitor can be improved.

[0023] In some embodiments of the present application, the initial ferroelectric layer includes at least two stacked and spaced initial non-doped layers, and the spacing between the two adjacent initial non-doped layers ranges from 0.1 nm to 20 nm. If the spacing between the two is less than 0.1 nm, the spacing between the two is too small, resulting in the thickness of the initial doped layer between the two adjacent initial non-doped layers being too small, and unable to provide effective control for the migration of oxygen vacancies. If the spacing between the two is greater than 20 nm, the spacing between the two is too large, resulting in the thickness of the capacitor being too large, thereby increasing the volume of the capacitor and reducing the power density of the capacitor. Therefore, when the spacing between the two is in the range of 0.1 nm to 20 nm, it is possible to provide effective control for the migration of oxygen vacancies and improve the power density of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 Schematic diagram of the three-dimensional structure of a capacitor in the related art;

[0026] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the capacitor shown;

[0027] Figure 3 for Figure 1 The endurance cycle curve of the capacitor shown;

[0028] Figure 4 for Figure 1 The ferroelectric polarization curve of the capacitor shown;

[0029] Figure 5 for Figure 1 The ferroelectric polarization curves of the capacitor shown at different temperatures;

[0030] Figure 6 for Figure 1 The schematic diagram of the capacitor producing the imprinting effect is shown;

[0031] Figure 7 for Figure 1The capacitor shown is a durability curve at different temperatures;

[0032] Figure 8 for Figure 1 Another durability curve of the capacitor shown at 450°C;

[0033] Figure 9 for Figure 1 Another durability curve of the capacitor shown at 500°C;

[0034] Figure 10 This is a schematic diagram of the three-dimensional structure of a capacitor in the first embodiment of the present application;

[0035] Figure 11 for Figure 1 Schematic diagram of the cross-sectional structure of the capacitor shown;

[0036] Figure 12 for Figure 10 The durability curve of the capacitor shown is at an operating voltage of 2V;

[0037] Figure 13 for Figure 10 The endurance curve of the capacitor shown is at an operating voltage of 1.6V;

[0038] Figure 14 for Figure 1 The related technologies and Figure 10 The rewritten difficulty curve of the illustrated embodiment;

[0039] Figure 15 for Figure 1 The related technologies and Figure 10 Memory retention curve of the embodiment shown;

[0040] Figure 16 for Figure 1 The related technologies and Figure 10 The ferroelectric polarization curve of the embodiment shown under one condition;

[0041] Figure 17 for Figure 1 The related technologies and Figure 10 The ferroelectric polarization curve of the embodiment shown under another condition;

[0042] Figure 18 for Figure 1 The related art shown shows a comparison of ferroelectric polarization curves before and after heating at 400°C for 3 hours;

[0043] Figure 19 for Figure 10 Comparison of ferroelectric polarization curves of the shown examples before and after heating at 400°C for 3 hours;

[0044] Figure 20 Comparison of ferroelectric polarization curves of asymmetric capacitors and symmetric capacitors;

[0045] Figure 21 Comparison of the current density curves of the capacitor when the doping layer is at three different positions;

[0046] Figure 22 Comparison of the capacitor's durability curves when the doping layer is at three different positions;

[0047] Figure 23 This is a schematic cross-sectional view of a capacitor in the second embodiment of the present application;

[0048] Figure 24 This is a schematic diagram of the three-dimensional structure of a capacitor in the third embodiment of the present application;

[0049] Figure 25 is a schematic cross-sectional view of a capacitor in a fourth embodiment of the present application;

[0050] Figure 26 is a schematic cross-sectional view of a capacitor according to a fifth embodiment of the present application;

[0051] Figure 27 is a schematic cross-sectional view of a capacitor according to a sixth embodiment of the present application;

[0052] Figure 28 This is a schematic diagram of the three-dimensional structure of a capacitor in the seventh embodiment of the present application;

[0053] Figure 29 for Figure 10 Schematic diagram of the production process of the capacitor shown;

[0054] Figure 30 for Figure 29 Schematic diagram of the specific process of the production method shown.

[0055] Icon: 1-capacitor; 101-center plane; 10-first electrode; 11-surface; 20-ferroelectric layer; 201-initial ferroelectric layer; 21-doped layer; 210-initial doped layer; 22-undoped layer; 220-initial undoped layer; 30-second electrode; 31-surface; 40-first conductive layer; 50-second conductive layer. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0058] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0059] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used with respect to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change in the orientation of the components in the drawings.

[0060] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0061] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0062] The massive growth of data is placing new demands on memory, such as non-volatility, low power consumption, high reliability, and high density. Embedded non-volatile memory (eNVM), a core and indispensable system-on-chip (SoC) technology, is required in microcontroller units (MCUs), automotive chips, and 5G-related chips. These higher-capacity eNVMs are needed to meet the explosive growth in the Internet of Things (IoT), intelligent driving, and other fields.

[0063] The current eNVM technology solution based on traditional embedded flash memory (eFlash) requires high voltage for reading and writing, making it difficult to achieve miniaturization and unable to support continued evolution to process nodes below 28nm.

[0064] The memory can be applied to electronic devices, which also include a circuit board, and the memory can be electrically connected to the circuit board. The electronic devices can be, for example, servers, consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc., and the embodiments of the present application are not limited to this. For example, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (for example, smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Vehicle-mounted electronic products can be car navigation systems, car displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service transactions, etc. Communication electronic products can be servers, memory, radars, base stations, and other communication equipment.

[0065] The memory may include a controller and a memory array, which may include capacitors and switches. The capacitor is used to read information, and the switch is used to select the capacitor. Ferroelectric random access memory (FeRAM) is a type of memory. Its core is a metal-insulator-metal (MIM) capacitor composed of metal-ferroelectric-metal (MFM). Figure 1 and Figure 2 As shown, the capacitor 1 includes a first electrode 10, a ferroelectric layer 20 and a second electrode 30 which are stacked in sequence. The material of the ferroelectric layer 20 is a ferroelectric material.

[0066] Capacitor 1 utilizes the physical phenomenon that the orientation of the electric polarization of ferroelectric materials can be altered by an external electric field. Within the ferroelectric material, the centers of positive and negative charges are asymmetrical, leading to the appearance of electric dipoles and the spontaneous polarization of the ferroelectric material. Under the action of an external electric field, this polarization direction is rewritten to either upward or downward. A detection amplifier can detect the state of the stored information, "0" or "1." Because FeRAM maintains its polarization state after the external electric field is removed, it exhibits non-volatility. Furthermore, ferroelectric polarization reversal primarily originates from electric dipole reversal. Due to its fast reversal speed and minimal Joule heating, it also offers the advantages of fast read / write speeds and low power consumption.

[0067] In one related technology, the ferroelectric material is a perovskite structure material such as lead zirconium titanate (Pb(Zr, Ti)O3, PZT). Since it can only exhibit stable ferroelectricity above a critical thickness, it is not compatible with advanced process size reduction. To solve this problem, in another related technology, the ferroelectric material is a hafnium oxide (HfO2)-based material doped with other elements, such as zirconium (Zr) element doped into hafnium oxide to obtain hafnium zirconium oxide (HZO). Since this material has good compatibility with complementary metal oxide semiconductor (CMOS) processes, the ferroelectric layer 20 can be made by thin film deposition using atomic layer deposition (ALD), so that the ferroelectric layer 20 has a lower crystallization temperature, and can achieve the miniaturization capability limit of the memory size to below 5nm, and achieve non-volatility, low power consumption, high reliability and high density.

[0068] Ferroelectric materials will have an imprint effect, that is, the storage state of the ferroelectric layer 20 will have an imprint effect after experiencing high temperature. Figure 3 As shown, charges accumulate at the interface between the ferroelectric layer 20 and the second electrode 30 .

[0069] Storage retention is a reliability indicator of capacitors under high-temperature working conditions. When capacitor 1 is working in a high-temperature environment, the imprinting effect will cause the polarization-voltage (PV) curve to shift at high temperatures, resulting in a decrease in the storage window and reduced storage retention. The reduced storage retention is specifically manifested as loss of stored information and difficulty in rewriting. Figure 4 As shown, Figure 4 The ferroelectric polarization curve of the capacitor under the influence of high temperature imprinting effect is shown. Figure 4 It can be seen that the ferroelectric polarization curve shifts to the right along the direction of the arrow.

[0070] Figure 2 The ferroelectric layer 20 of the capacitor 1 shown is undoped, the first electrode 10 is in contact with the ferroelectric layer 20, and the second electrode 30 is in contact with the ferroelectric layer 20. When manufacturing the capacitor 1, the first electrode 10, the ferroelectric layer 20, and the second electrode 30 stacked in sequence can be subjected to a rapid thermal annealing (RTA) process, also known as a crystallization process. The effective stress exerted by the first electrode 10 or the second electrode 30 on the ferroelectric layer 20 causes the ferroelectric layer 20 to produce an O phase. The ferroelectric polarization curve of the capacitor 1 after the crystallization process is shown in FIG. Figure 5 As shown. Coercive field strength E C As an indicator of the difficulty of ferroelectric polarization reversal, which indicates the reverse electric field strength required for the polarization strength of the ferroelectric layer 20 to return to zero, the coercive field strength should be appropriately reduced to reduce the operating voltage. Figure 5 As shown, the current coercive field strength is about 1.6 MV / cm, which will limit the further reduction of the operating voltage of the capacitor 1. Moreover, since the continuous ferroelectric polarization reversal will lead to an increase in the concentration of oxygen vacancies in the ferroelectric layer 20, these charged defects will cause the capacitor 1 to break down after being connected.

[0071] Endurance is a performance of the capacitor 1, which determines the service life of the capacitor 1. Figure 6 As shown, the durability cycle of capacitor 1 generally goes through a pristine state, a wake-up effect, and a fatigue period until breakdown or fatigue. When capacitor 1 breaks down prematurely, it indicates that the durability of capacitor 1 is lower.

[0072] In most cases, oxygen vacancies will gradually accumulate at the interface between the first electrode 10 and the ferroelectric layer 20 and at the interface between the second electrode 30 and the ferroelectric layer 20. If oxygen vacancies accumulate too much, the ferroelectric polarization reversal will be fatigued, resulting in reduced polarization and a decrease in the memory window, such as Figure 7 As shown. Capacitor 1 first goes through the wake-up phase, and then 6 After the life stack point, fatigue occurs and the storage window begins to decrease. It is understandable that the storage window can be Figure 7 The two curves at the same temperature are 10 6 The difference between the residual polarization intensities at the two locations is calculated.

[0073] like Figure 8 and Figure 9 As shown, the imprinting effect of ferroelectric materials can also cause a shift in the normalized polarization curve, making it difficult to rewrite the stored state and reducing the memory window. After capacitor 1 experiences high temperatures, the imprinting effect becomes more pronounced due to insufficient crystallization, making it difficult for capacitor 1 to maintain a constant memory window after temperatures of 85°C and 105°C.

[0074] Based on this, Figure 10 As shown, the embodiment of the present application provides a capacitor 1. The capacitor 1 includes a first electrode 10, a second electrode 30 and a ferroelectric layer 20 stacked in sequence, and the stacking direction is the Z direction, that is, the thickness direction of the capacitor 1.

[0075] Figure 10 The materials of the first electrode 10 and the second electrode 30 shown can both be conductive materials, such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). Moreover, the material of the first electrode 10 can be the same as that of the second electrode 30, or the material of the first electrode 10 can be different from that of the second electrode 30. That is, in this embodiment, the capacitor 1 can be an MFM structure. In other embodiments, the capacitor 1 can be a metal-ferroelectric-semiconductor (MFS) structure.

[0076] like Figure 10 As shown, the first electrode 10 and the second electrode 30 may have the same size. For example, the first electrode 10 and the second electrode 30 have the same size along the X direction, the first electrode 10 and the second electrode 30 have the same size along the Y direction, and the first electrode 10 and the second electrode 30 have the same size along the Z direction. For example, the size of the first electrode 10 and the second electrode 30 along the Z direction may both be in the range of 5 nm to 100 nm.

[0077] like Figure 10 As shown, the ferroelectric layer 20 includes a doped layer 21 and an undoped layer 22. Moreover, the ferroelectric layer 20 includes at least two undoped layers 22 and at least one doped layer 21, and each doped layer 21 is located between two adjacent undoped layers 22. For example, Figure 10 As shown, in this embodiment, the ferroelectric layer 20 includes three undoped layers 22 and two doped layers 21, and each doped layer 21 is located between two adjacent undoped layers 22. In other words, there is a spacing between the doped layer 21 closest to the first electrode 10 and the first electrode 10, and the spacing range may be, for example, 0.1nm-10nm; there is also a spacing between the doped layer 21 closest to the second electrode 30 and the second electrode 30, and the spacing range may be, for example, 0.1nm-10nm; and there is a spacing between two adjacent doped layers 21, and the spacing range may be, for example, 0.1nm-20nm.

[0078] like Figure 10 As shown, the projection of the doped layer 21 on the first electrode 10 is the same as the projection of the undoped layer 22 on the first electrode 10. Exemplarily, the size of the doped layer 21 along the X direction is the same as the size of the undoped layer 22 along the X direction, and the size of the doped layer 21 along the Y direction is the same as the size of the undoped layer 22 along the Y direction.

[0079] The size of each doped layer 21 along the Z direction may be the same. For example, the size of each doped layer 21 along the Z direction may range from 0.1 to 5 nm, and the size of the ferroelectric layer 20 along the Z direction may range from 3 nm to 20 nm.

[0080] The doped layer 21 and the undoped layer 22 both include ferroelectric grains. The ferroelectric grains are made of a ferroelectric material. Specifically, in this embodiment, the ferroelectric material may be hafnium oxide (HfO 2 ) or hafnium zirconium oxide (HfZrO).

[0081] Doping layer 21 includes a doping element. The doping element of doping layer 21 may include titanium (Ti), tantalum (Ta), or niobium (Nb) from the same group or adjacent subgroup as hafnium. Furthermore, the doping element may exist as a multivalent metallic element. Since the ionic radius of these doping elements is similar to that of hafnium and zirconium, they can occupy lattice sites, lattice gaps, and grain boundary defects of hafnium oxide or hafnium zirconium oxide. Alternatively, the doping element may exist in the form of an oxide, such as titanium oxide (TiO), tantalum oxide (Ta2O5), niobium monoxide, niobium dioxide, niobium trioxide, or niobium pentoxide.

[0082] The doping concentration of the doping layer 21 may be in the range of 0.1%-30%, for example, 0.1%, 10%, 20% or 30%.

[0083] Since both the doped layer 21 and the undoped layer 22 include ferroelectric grains, and the doped layer 21 includes a doping element, the doping element can be incorporated into the ferroelectric grains and can occupy ferroelectric grain sites and form bonds with oxygen, thereby effectively suppressing the generation of charged oxygen vacancies and stabilizing oxygen vacancies, thereby facilitating the stability of the ferroelectric domains, ferroelectric polarization, and promoting the generation of the O phase, thereby improving the ferroelectric crystal quality and the stability of the ferroelectric grains. Furthermore, the doping element does not disrupt the integrity of the ferroelectric grains.

[0084] The relevant performance parameters of the capacitor 1 in the related art and the present embodiment are calculated to obtain a performance parameter comparison table shown in Table 1.

[0085] Table 1

[0086]

[0087] Since the doping elements have a pinning effect on the oxygen vacancies in the ferroelectric layer 20, the migration of the oxygen vacancies under the action of the electric field is effectively controlled and cannot move arbitrarily during the ferroelectric domain flipping process, thereby increasing the breakdown electric field E BD For example, as shown in Table 1, compared with the related technical solutions, the breakdown electric field E of this embodiment is BD The increase from 3.6 MV / cm to 6.27 MV / cm can improve the ability to withstand electric field breakdown, thereby improving the durability of the ferroelectric material at the same operating voltage. Moreover, when the ability to withstand electric field breakdown is improved, the service life of the capacitor 1 can also be increased.

[0088] In addition, it can be seen from Table 1 that compared with the related art, the coercive field strength E of this embodiment is C From 1.6MV / cm to 0.9MV / cm, the coercive field strength E C It is positively correlated with the operating voltage and device loss of capacitor 1, thereby significantly reducing the operating voltage and device power consumption.

[0089] In addition, the breakdown probability of capacitor 1 is related to E C / E BD There is a positive correlation, when the coercive field strength E C Reduce and break down the electric field E BD After the improvement, the breakdown electric field E can be appropriately reduced BD , the breakdown probability is also reduced. For example, as shown in Table 1, compared with the related art, the breakdown probability of this embodiment is reduced from 44% to 25%. As a result, higher durability can be achieved. For example, as shown in Table 1, compared with the related art, the durability of this embodiment is reduced from 10 9 Increased to 10 penetrations 11 It was not penetrated.

[0090] In addition, since the migration of oxygen vacancies under the action of the electric field is effectively controlled and cannot move arbitrarily, fatigue during continuous flipping can be reduced, thereby further improving durability. The durability of the capacitor 1 of the related technical solution and this embodiment was tested, and the results were obtained. Figure 12 and Figure 13 The durability curve shown in Figure 2. Figure 12 The operating voltage for the durability curve shown is 2V, Figure 13 The operating voltage for the durability curve shown is 1.6V. Figure 12 and Figure 13 It can be seen that the capacitor 1 of the related art is 10 9 Fatigue occurs when the capacitor 1 of this embodiment is 10 10 No fatigue has occurred yet.

[0091] In addition, this embodiment can also effectively improve the storage retention of ferroelectric materials and suppress the imprinting effect. Figure 1 The storage performance of the capacitor 1 of the related technology and the present embodiment is tested and the results are obtained. Figure 14 、 Figure 15 、 Figure 16 and Figure 17 Storage performance comparison chart. Figure 14 The rewriting difficulty curves of the capacitor 1 of the related art and the present embodiment at 105°C are shown. Among them, OS represents rewriting from 0 to 1, and the earlier the OS+ curve and the OS- curve cross, the more difficult the rewriting is. Figure 14 As can be seen from the figure, the OS+ and OS- curves of the related art cross earlier, indicating that the rewriting of capacitor 1 of the related art is more difficult. Moreover, the related art cannot withstand 10 years at 105°C, while the residual polarization of SS+ of this embodiment after 10 years is 10.42uC / cm 2 , SS- after ten years the remnant polarization is -9.62uC / cm 2 , after ten years, the residual polarization is still 10.42-(-9.62)≈20uC / cm 2 .

[0092] Figure 15 The storage retention curves of the capacitor 1 of the related art and the present embodiment at 105° C. are shown. Figure 15 In the figure, SS indicates that the initial storage is 0 and it is still 0 after ten years. And the residual polarization of the related technology SS+ after ten years is 10.25uC / cm 2 , SS- after ten years the remnant polarization is -11.74uC / cm 2 , the storage window is 10.25-(-11.74)=21.99uC / cm 2The residual polarization of SS+ in this embodiment after ten years is 20.99uC / cm 2 , SS- after ten years the remnant polarization is -19.38uC / cm 2 , the storage window is 20.99-(-19.38)=40.37uC / cm 2 As can be seen, the residual polarization of both SS+ and SS- in this embodiment after ten years is greater than that of the related art, indicating that this embodiment has higher storage retention. Furthermore, the storage window of this embodiment is greater than that of the related art 1, as can also be seen in Table 1.

[0093] Figure 16 The ferroelectric polarization curves of the related art and this embodiment are shown. Figure 16 (a) is the ferroelectric polarization curve of the related art. Figure 16 (b) is the ferroelectric polarization curve of this embodiment. Figure 16 As can be seen from (a), the coercive field strength E of the related technology C The offset is -0.69MV / cm, from Figure 16 As can be seen from (b), the coercive field strength E of this embodiment is C The offset is -0.31 MV / cm.

[0094] Figure 17 The ferroelectric polarization curves of the related art and this embodiment are shown. Figure 17 (a) is the ferroelectric polarization curve of the related art. Figure 17 (b) is the ferroelectric polarization curve of this embodiment. Figure 17 As can be seen from (a), the coercive field strength E of the related technology C The offset is -0.31MV / cm, from Figure 17 As can be seen from (b), the coercive field strength E of this embodiment is C The offset is -0.19MV / cm. Figure 17 The ferroelectric polarization curve and Figure 16 The ferroelectric polarization curves were measured at different initial storage states, all at a temperature of 105°C. Figure 16 is the coercive field strength E generated after storing “0” C offset, Figure 17 is the coercive field strength E generated after storing “1” C Offset.

[0095] from Figure 16 and Figure 17 It can be seen from the figure that the coercive field strength E CSmaller offsets mean less ferroelectric polarization loss and a larger effective storage window. Furthermore, this demonstrates that capacitor 1 has greater high-temperature resistance, with better storage retention and stability at high temperatures (industrial and automotive grades, 85°C / 125°C).

[0096] In the making Figure 10 In the process of manufacturing the capacitor 1 shown, the first electrode 10, the initial ferroelectric layer 201 and the second electrode 30 are sequentially manufactured, and then the initial ferroelectric layer 201 is crystallized to obtain the ferroelectric layer 20. The crystallization process specifically involves placing the first electrode 10, the initial ferroelectric layer 201 and the second electrode 30 in a high temperature environment for a certain period of time, and then rapidly annealing them. During the crystallization process, the poor thermal stability of the capacitor 1 may result in a decrease in the storage window and the coercive field strength E. C Therefore, the thermal stability test of the capacitor 1 of the related art can be carried out to obtain Figure 18 The ferroelectric polarization curve is shown. Figure 18 (a) is the initial ferroelectric polarization curve of the capacitor 1 of the related art, Figure 18 (b) is the ferroelectric polarization curve of the capacitor 1 of the related art after being heated at 400°C for 3 hours. The thermal stability test of the capacitor 1 of this embodiment is carried out to obtain Figure 19 The ferroelectric polarization curve is shown. Figure 19 (a) is the initial ferroelectric polarization curve of the capacitor 1 of this embodiment, Figure 19 (b) is the ferroelectric polarization curve of the capacitor 1 of this embodiment after being heated at 400° C. for 3 hours.

[0097] from Figure 18 and Figure 19 The ferroelectric polarization curve can be obtained from the results in Table 2.

[0098] Table 2

[0099] Furnace tube experiment Related technologies This embodiment Storage window 2Pr remnant polarization <![CDATA[15.26uC / cm 2 ]]> <![CDATA[47.13uC / cm 2 ]]> Storage window loss ratio 58％ 3％ <![CDATA[Change in coercive field strength Δ2E C > 0.13MV / cm -0.03MV / cm

[0100] As can be seen from Table 2, after three hours at 400°C, the memory window 2Pr of this embodiment has a larger residual polarization, a smaller memory window loss ratio, and the effective memory window can be maintained. Moreover, the change in coercive field strength is also small and can be ignored. In other words, the coercive field strength E C remains unchanged, therefore, the thermal stability of the capacitor 1 in this embodiment is better.

[0101] like Figure 11As shown, the capacitor 1 has a symmetrical structure about a central plane 101. The distance between the central plane 101 and a surface 11 of the first electrode 10 facing away from the second electrode 30 is the same as the distance between the central plane 101 and a surface 31 of the second electrode 30 facing away from the first electrode 10. Furthermore, two doped layers 21 (a first doped layer and a second doped layer) are located on either side of the central plane 101.

[0102] Figure 20 (a) shows the ferroelectric polarization curve of the capacitor 1 with an asymmetric structure. Figure 20 As can be seen in (a), +Ec is 1.33 MV / cm and -Ec is -0.61 MV / cm. The absolute values ​​of +Ec and -Ec differ, indicating asymmetry between them. Furthermore, the difference between the absolute values ​​of +Ec and -Ec is 0.72 MV / cm. This indicates that if capacitor 1 has an asymmetric structure about center plane 101, +Ec and -Ec will often be asymmetric. Consequently, when positive and negative operating voltages of the same absolute value are applied to capacitor 1, uneven flipping occurs, potentially leading to a situation where the stored state on one side is easily retained while the stored state on the other side is not.

[0103] Figure 20 (b) shows Figure 11 The ferroelectric polarization curve of the capacitor 1 with a symmetrical structure is shown. Figure 20 As can be seen in (b), +Ec is 0.96 MV / cm, -Ec is -0.96 MV / cm, and the absolute values ​​of +Ec and -Ec are the same, that is, +Ec and -Ec are symmetrical. This means that this embodiment can achieve symmetry between +Ec and -Ec, thereby alleviating the problem of the storage state on one side being unable to be maintained due to flipping imbalance.

[0104] It can be understood that in actual design, the doping concentration of the doping layer 21 can be adjusted according to the position of the ferroelectric polarization curve. For example, when the ferroelectric polarization curve is biased to the right, the doping concentration of the doping layer 21 close to the first electrode 10 can be increased; when the ferroelectric polarization curve is biased to the left, the doping concentration of the doping layer 21 close to the second electrode 30 can be increased, thereby effectively improving the asymmetry of +Ec and -Ec.

[0105] The position of each doping layer 21 in the capacitor 1 affects the storage retention and current density (leakage) of the capacitor 1. The storage retention and current density of the capacitor 1 with three different doping layer 21 positions were tested, and the results were as follows: Figure 21 The current density curve shown and Figure 22 The storage retention curve is shown.

[0106] like Figure 11As shown, it is assumed that the thickness of the non-doped layer 22 closest to the first electrode 10 is d1, the thickness of the non-doped layer 22 in the middle is d2, and the thickness of the non-doped layer 22 closest to the second electrode 30 is d3. Figure 21 (a) and Figure 22 In (a), d1 and d3 are both 1 nm, and d2 is 6 nm. Figure 21 (b) and Figure 22 In (b), d1 and d3 are both 2 nm, and d2 is 4 nm. Figure 23 (c) and Figure 23 In (c), d1 and d3 are both 3nm, and d2 is 2nm. Figure 21 In (a), the doped layer 21 of the capacitor 1 is farthest from the center plane 101. Figure 21 In the capacitor 1 corresponding to (c), the doped layer 21 is closest to the central plane 101 .

[0107] from Figure 21 As can be seen in (a), when d1 and d3 are both 1nm and d2 is 6nm, the current density is 1.05A / m 2 , after ten years at 105°C, the remaining storage window is 78%. Figure 21 As can be seen in (b), when d1 and d3 are both 2nm and d2 is 4nm, the current density is 143.06A / m 2 , after ten years at 105°C, the remaining storage window is 84%. Figure 21 As can be seen in (c), when d1 and d3 are both 3nm and d2 is 2nm, the current density is 1297.44A / m 2 , after ten years at 105℃, the remaining storage window is 71%. Figure 21 As shown in (c), when the doping layer 21 is closer to the center plane 101, the current density is greater and the imprinting effect is smaller. It can be seen that the closer the doping layer 21 is to the center plane 101, the more the imprinting effect can be alleviated. Figure 21 As shown in (a), the farther the doping layer 21 is from the central plane 101 , the less effective it is in alleviating the imprinting effect.

[0108] from Figure 22 As can be seen in (a), the remnant polarization after SS+ for ten years is 18.68uC / cm 2 , SS- after ten years the remnant polarization is -20.04uC / cm 2 .from Figure 22 As can be seen in (a), the remnant polarization after SS+ for ten years is 11.34uC / cm 2 , SS- after ten years the remnant polarization is -14.97uC / cm 2 .from Figure 22As can be seen in (c), the residual polarization after SS+ for ten years is 5.99uC / cm 2 , SS- after ten years the remnant polarization is -9.86uC / cm 2 . It can be seen that Figure 22 As shown in (c), as the doped layer 21 gets closer to the center plane 101, the domain continuity of the undoped layer 22 deteriorates, the difficulty of crystallization increases, and the residual polarization is greatly reduced. Moreover, the control of oxygen vacancies near the interface between the first electrode 10 and the undoped layer 22 is lost, the depolarization field increases, and it is not conducive to maintaining the storage state. Figure 22 As shown in (a), the further away the doping layer 21 is from the central plane 101, the more conducive it is to maintaining the storage state.

[0109] Therefore, when the thickness of the non-doped layer 22 between the two doped layers 21 is moderate, for example, 3 nm to 5 nm, specifically 4 nm, both the storage state maintenance and the mitigation of the imprinting effect can be taken into account.

[0110] In other embodiments of the present application, Figure 23 As shown, Figure 10 The difference between the embodiments shown is that the capacitor 1 of this embodiment has an asymmetric structure with respect to the center plane 101. Specifically, Figure 23 As shown, in this embodiment, the distance between the doped layer 21 closest to the first electrode 10 and the surface 11 is greater than the distance between the doped layer 21 closest to the second electrode 30 and the surface 31. In other embodiments, the two doped layers 21 may be located on the same side of the center plane 101.

[0111] In other embodiments of the present application, Figure 24 As shown, Figure 10 The difference between the illustrated embodiments is that the number of doped layers 21 and undoped layers 22 in the ferroelectric layer 20 is different. Specifically, in this embodiment, the ferroelectric layer 20 includes two undoped layers 22 and one doped layer 21, and the doped layer 21 is located between the two undoped layers 22.

[0112] In other embodiments of the present application, Figure 25 As shown, Figure 10 The difference between the embodiments shown is that the stacking directions of the first electrode 10, the ferroelectric layer 20 and the second electrode 30 are different in this embodiment. Specifically, in this embodiment, Figure 26 As shown, the first electrode 10, the ferroelectric layer 20 and the second electrode 30 are stacked along the X direction, that is, along the length or width direction of the memory.

[0113] In other embodiments of the present application, Figure 26 As shown, Figure 10The difference between the embodiments shown is that the structures of the embodiments are different. Specifically, in the embodiment, Figure 26 As shown, the second electrode 30 surrounds the first electrode 10, and three undoped layers 22 and two doped layers 21 are disposed between the first electrode 10 and the second electrode 30. Furthermore, the first electrode 10, the ferroelectric layer 20, and the second electrode 30 all form a ring-shaped quadrilateral.

[0114] In other embodiments of the present application, Figure 27 As shown, Figure 28 The difference between the embodiments shown is that the shapes of the embodiments are different. Figure 27 As shown, the first electrode 10, the ferroelectric layer 20 and the second electrode 30 are all in the form of a ring.

[0115] In other embodiments of the present application, Figure 28 As shown, Figure 10 The difference between the embodiments shown is that the present embodiment Figure 10 Based on the illustrated embodiment, a first conductive layer 40 and a second conductive layer 50 are added. The first conductive layer 40 is located between the first electrode 10 and the ferroelectric layer 20, and the second conductive layer 50 is located between the second electrode 30 and the ferroelectric layer 20. Furthermore, the first conductive layer 40 and the second conductive layer 50 may have the same thickness, and the materials of both the first conductive layer 40 and the second conductive layer 50 may be Nb2O5, Ta2O5, or V2O5, for example.

[0116] The present application also provides a method for manufacturing a capacitor 1, which can be applied to Figure 10 As shown in the capacitor 1. Figure 29 As shown, the production method may include:

[0117] S61, manufacturing a first electrode.

[0118] Thin film deposition methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) can be used to deposit films such as Figure 30 The first electrode 10 is shown in (a).

[0119] S62, forming an initial ferroelectric layer on the first electrode.

[0120] like Figure 30As shown in (b), the initial ferroelectric layer 201 includes two initial doped layers 210 and three initial undoped layers 220. The initial undoped layers 220 include ferroelectric grains, and the material of the ferroelectric grains is a ferroelectric material. Specifically, in this embodiment, the ferroelectric material can be hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO).

[0121] The initial doping layer 210 includes a doping element. The doping element of the doping layer 21 may include titanium (Ti), tantalum (Ta), or niobium (Nb) in the same group or adjacent subgroup as hafnium.

[0122] The spacing between the initial doping layer 210 closest to the first electrode 10 and the first electrode 10 is in the range of 0.1nm-10nm. If the spacing between the two is less than 0.1nm, the spacing between the two is too small, which causes the doping elements in the initial doping layer 210 to diffuse into the first electrode 10 during the subsequent crystallization process, thereby affecting the normal use of the capacitor 1. If the spacing between the two is greater than 10nm, the spacing between the two is too large, resulting in an excessive thickness of the capacitor 1, thereby increasing the volume of the capacitor 1 and reducing the power density of the capacitor 1. Therefore, when the spacing between the two is in the range of 0.1nm-10nm, the normal use of the capacitor 1 can be guaranteed, and the power density of the capacitor 1 can be improved.

[0123] The spacing between two adjacent initial undoped layers 220 ranges from 0.1 nm to 20 nm. If the spacing between the two is less than 0.1 nm, the spacing between the two is too small, resulting in the thickness of the initial doped layer 210 between the two adjacent initial undoped layers 220 being too small, and unable to provide effective control for the migration of oxygen vacancies. If the spacing between the two is greater than 20 nm, the spacing between the two is too large, resulting in the thickness of the capacitor 1 being too large, thereby increasing the volume of the capacitor 1 and reducing the power density of the capacitor 1. Therefore, when the spacing between the two is in the range of 0.1 nm to 20 nm, it is possible to provide effective control for the migration of oxygen vacancies and improve the power density of the capacitor 1.

[0124] S63, forming a second electrode on the initial ferroelectric layer.

[0125] like Figure 30As shown in (c), the second electrode 30 is formed on the initial non-doped layer 220 of the initial ferroelectric layer 201, which is farthest from the first electrode 10. The spacing between the initial doped layer 210 closest to the second electrode 30 and the second electrode 30 is in the range of 0.1nm-10nm. If the spacing between the two is less than 0.1nm, the spacing between the two is too small, which causes the doping elements in the initial doped layer 210 to diffuse into the first electrode 10 during the subsequent crystallization process, thereby affecting the normal use of the capacitor 1. If the spacing between the two is greater than 10nm, the spacing between the two is too large, resulting in an excessive thickness of the capacitor 1, thereby increasing the volume of the capacitor 1 and reducing the power density of the capacitor 1. Therefore, when the spacing between the two is in the range of 0.1nm-10nm, the normal use of the capacitor 1 can be guaranteed and the power density of the capacitor 1 can be improved.

[0126] S64, performing crystallization processing on the initial ferroelectric layer to obtain a ferroelectric layer.

[0127] like Figure 30 As shown in (d), after the initial ferroelectric layer 201 is crystallized, the initial doped layer ( Figure 30 The doping elements in the doped area (shown in the doped area in (d)) will diffuse into the initial undoped layer 220. In other words, the thickness of the doped layer 21 obtained after the crystallization of the initial doped layer is greater than the thickness of the initial doped layer 210. The ferroelectric grains in the initial undoped layer will also diffuse into the initial doped layer after the crystallization process, thereby spreading throughout the entire ferroelectric layer 20.

[0128] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A capacitor, characterized in that: include: a first electrode, a second electrode, and a ferroelectric layer located between the first electrode and the second electrode, wherein the ferroelectric layer includes a doped layer and an undoped layer, and both the doped layer and the undoped layer include ferroelectric grains.

2. The capacitor according to claim 1, wherein The ferroelectric layer includes at least two non-doped layers and at least one doped layer, and each doped layer is located between two adjacent non-doped layers.

3. The capacitor according to claim 2, wherein: The first electrode and the second electrode are stacked, and at least two non-doped layers and at least one doped layer are stacked between the first electrode and the second electrode.

4. The capacitor according to claim 2, wherein The second electrode is disposed around the first electrode, and at least two non-doped layers and at least one doped layer are disposed around the first electrode and the second electrode.

5. The capacitor according to any one of claims 2 to 4, characterized in that: The capacitor has a symmetrical structure about a central plane, and a distance between the central plane and a surface of the first electrode facing away from the second electrode is the same as a distance between the central plane and a surface of the second electrode facing away from the first electrode.

6. The capacitor according to claim 5, characterized in that The ferroelectric layer includes a first doping layer and a second doping layer respectively located on both sides of the central plane, and the thickness of the non-doping layer between the first doping layer and the second doping layer is in the range of 3 nm to 5 nm.

7. The capacitor according to any one of claims 2 to 4, characterized in that: The ferroelectric layer includes a first doping layer and a second doping layer, and the first doping layer and the second doping layer are in an asymmetric structure with respect to a central plane.

8. The capacitor according to any one of claims 1 to 7, characterized in that: The projection of the doped layer on the first electrode is the same as the projection of the undoped layer on the first electrode.

9. The capacitor according to any one of claims 1 to 8, characterized in that: The material of the non-doped layer includes hafnium oxide or hafnium zirconium oxide, and the doping element of the doped layer includes titanium, tantalum or niobium.

10. The capacitor according to any one of claims 1 to 9, characterized in that: The capacitor further includes a first conductive layer and a second conductive layer, the first conductive layer being located between the first electrode and the ferroelectric layer, and the second conductive layer being located between the second electrode and the ferroelectric layer.

11. A storage array, characterized in that: The device comprises a switching tube and the capacitor according to any one of claims 1 to 10, wherein the switching tube is electrically connected to the capacitor.

12. A memory, characterized in that: The device comprises a controller and the memory array according to claim 11, wherein the controller is electrically connected to the memory array.

13. An electronic device, characterized in that: The device comprises a circuit board and the memory according to claim 12, wherein the circuit board is electrically connected to the memory.

14. A method for manufacturing a capacitor, characterized in that: The production method comprises: fabricating a first electrode; forming an initial ferroelectric layer on the first electrode, the initial ferroelectric layer comprising an initial non-doped layer and an initial doped layer stacked together, the initial non-doped layer comprising ferroelectric grains, and the initial doped layer comprising doping elements; forming a second electrode on the initial ferroelectric layer; The initial ferroelectric layer is crystallized to obtain a ferroelectric layer, wherein the ferroelectric layer includes a non-doped layer and a doped layer, both the non-doped layer and the doped layer include ferroelectric grains, and the doped layer includes a doping element.

15. The manufacturing method according to claim 14, characterized in that: The distance between the initial doping layer closest to the first electrode and the first electrode is in the range of 0.1 nm-10 nm, and the distance between the initial doping layer closest to the second electrode and the second electrode is in the range of 0.1 nm-10 nm.

16. The production method according to claim 14 or 15, characterized in that: The initial ferroelectric layer includes at least two stacked and spaced initial non-doped layers, and the distance between two adjacent initial non-doped layers is in the range of 0.1 nm to 20 nm.

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