Electrostatic discharge protection circuit using gallium nitride element

Abstract

An electrostatic discharge protection circuit using a gallium nitride element has a first sub-circuit and a second sub-circuit, the first sub-circuit including a flip-flop coupled to a gate of a power HEMT, a 2DEG resistor coupled to the other end of the flip-flop, a low-voltage HEMT coupled to the gate of the power HEMT, and a second sub-circuit coupled to the gate of the power HEMT. And a gate coupled to the other end of the flip-flop and one end of the two-dimensional electron gas resistor, a source coupled to the gate of the power HEMT and one end of the flip-flop, and a lateral FER coupled to the gate of the low-voltage HEMT, the other end of the flip-flop, and one end of the 2DEG resistor. The second sub-circuit is provided with elements which are completely symmetrical to the first sub-circuit, and the corresponding parts of the second sub-circuit and the first sub-circuit are coupled with each other.

Description

Technical Field

[0001] The present invention generally relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit using a gallium nitride device. Background Art

[0002] Currently, the vast majority of semiconductor devices worldwide are silicon-based semiconductors, using silicon as the base material and channel. However, in high-voltage or high-power applications, silicon-based devices suffer from high on-resistance, which can lead to significant power loss. Furthermore, in high-frequency operating environments, the switching frequency of silicon-based devices is relatively low, resulting in performance far inferior to wide-bandgap compound semiconductor materials such as gallium nitride (GaN) or silicon carbide (SiC). Wide-bandgap compound semiconductor materials like GaN have a wider bandgap and lower on-resistance than traditional silicon-based materials, resulting in greater resistance to high temperatures, high voltages, high frequencies, and high currents, and thus higher energy conversion efficiency. Therefore, GaN devices combine four advantageous properties: excellent heat dissipation, compact size, low energy consumption, and high power, making them suitable for power semiconductor applications. In recent years, driven by the growing demand from high-end industries such as 5G wireless communications and electric vehicles, GaN has emerged as a rising star in third-generation semiconductor materials.

[0003] However, GaN devices typically have a low gate-to-source breakdown voltage (e.g., less than 10V). This makes the gate of GaN devices susceptible to damage from gate voltage overshoots. Electrostatic discharge (ESD), a type of voltage overshoot, is caused by the sudden release of static charge, generating high-intensity electric fields and currents within integrated circuits, potentially damaging GaN devices within the circuit, particularly power GaN devices. Therefore, those skilled in the art need to design and develop circuits and structures that can protect GaN devices, specifically addressing their vulnerability to low gate-to-source breakdown voltage, in order to better utilize GaN devices. Summary of the Invention

[0004] In view of the aforementioned vulnerability of GaN devices to voltage overshoot and damage, the present invention proposes a novel ESD protection circuit. Its unique feature is that all components in the ESD protection circuit can be GaN-based devices, including resistors, capacitors, diodes, or high electron mobility transistors (HEMTs). These components can be fabricated on the same GaN substrate and integrated using the same manufacturing process.

[0005] The present invention aims to provide an electrostatic discharge protection circuit using a gallium nitride device, the structure of which includes: a power high electron mobility transistor having a gate, a source, and a drain, the source and the drain being coupled to a first reference voltage and a second reference voltage, respectively; an electrostatic discharge protection circuit block including a first subcircuit and a second subcircuit; the first subcircuit including: a first trigger having one end coupled to the gate; a first two-dimensional electron gas resistor having one end coupled to the other end of the first trigger; a first low-voltage high electron mobility transistor having a first gate, a first source, and a first drain, the first gate being coupled to the other end of the first trigger and the one end of the first two-dimensional electron gas resistor, the first source being coupled to the gate and the one end of the first trigger; and a first lateral field-effect rectifier having one end coupled to the first gate, the other end of the first trigger, and the one end of the first two-dimensional electron gas resistor; the second sub-circuit comprising: a second trigger having one end coupled to the source and the first reference voltage; a second two-dimensional electron gas resistor having one end coupled to the other end of the second trigger; a second low-voltage high-electron-mobility transistor having a second gate, a second source, and a second drain, the second gate coupled to the other end of the second trigger and the one end of the second two-dimensional electron gas resistor, the second source coupled to the source and the first reference voltage; and a second lateral field-effect rectifier having one end coupled to the second gate, the other end of the second trigger, and the one end of the second two-dimensional electron gas resistor; wherein the other end of the first two-dimensional electron gas resistor, the other end of the second two-dimensional electron gas resistor, the other end of the first lateral field-effect rectifier, the other end of the second lateral field-effect rectifier, the first drain, and the second drain are coupled to each other.

[0006] These and other objects of the present invention will become more readily apparent to those skilled in the art after reading the following detailed description of the preferred embodiment which is illustrated in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] This specification includes accompanying drawings, which constitute a part of this specification and are intended to provide a further understanding of the present invention to those skilled in the art. These drawings depict some embodiments of the invention and, together with the description herein, illustrate the principles thereof. In these drawings:

[0008] Figure 1 is a schematic diagram of an electrostatic discharge protection circuit using a gallium nitride device according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of another electrostatic discharge protection circuit using a gallium nitride device according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of another electrostatic discharge protection circuit using a gallium nitride device according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of another electrostatic discharge protection circuit using a gallium nitride device according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of another electrostatic discharge protection circuit using a gallium nitride device according to an embodiment of the present invention;

[0013] Figure 6 is a schematic cross-sectional view of a gallium nitride capacitor according to an embodiment of the present invention;

[0014] Figure 7 is a schematic cross-sectional view of a metal-insulator-metal (MIM) capacitor according to an embodiment of the present invention;

[0015] Figure 8 is a schematic cross-sectional view of a gallium nitride resistor according to an embodiment of the present invention;

[0016] Figure 9 is a schematic cross-sectional view of a GaN lateral field effect rectifier according to an embodiment of the present invention; and

[0017] Figure 10 FIG. 1 is a schematic cross-sectional view of a low-voltage high electron mobility transistor (LV-HEMT) according to an embodiment of the present invention.

[0018] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0019]

Explanation of symbols

[0020] 2DEG Two-dimensional electron gas

[0021] 100 GaN substrate

[0022] 102 Aluminum Gallium Nitride Layer

[0023] 104 P-type gallium nitride layer

[0024] 106 Ion implanted insulation layer

[0025] 108 passivation layer

[0026] 110 anode metal layer

[0027] 112 cathode metal layer

[0028] B Electrostatic discharge protection circuit block

[0029] B1 First subcircuit

[0030] B2 Second subcircuit

[0031] C1 First capacitor

[0032] C2 Second capacitor

[0033] C A anode

[0034] C C cathode

[0035] D drain

[0036] D1 first drain

[0037] D2 Second drain

[0038] D A1 First anode

[0039] D A2 Second anode

[0040] D C cathode

[0041] FER First Lateral Field Effect Rectifier

[0042] FER1 first lateral field effect rectifier

[0043] FER2 Second lateral field effect rectifier

[0044] FER3 third lateral field effect rectifier

[0045] FER4 Fourth Lateral Field Effect Rectifier

[0046] G Gate

[0047] G1 first gate

[0048] G2 Second gate

[0049] I / O ports

[0050] L GD Gate to drain length

[0051] R resistor

[0052] R1 first resistor

[0053] R2 Second resistor

[0054] R H High potential end

[0055] R L Low potential end

[0056] S Source

[0057] S1 first source

[0058] S2 Second source

[0059] T Power High Electron Mobility Transistor

[0060] T1 First low voltage high electron mobility transistor

[0061] T2 Second low voltage high electron mobility transistor

[0062] V R1 First reference voltage

[0063] V R2 Second reference voltage DETAILED DESCRIPTION

[0064] Now the exemplary embodiments of the present invention will be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that those skilled in the art will understand and achieve the technical effects. It will be appreciated by those skilled in the art that the description herein is only by way of example and is not intended to limit the present application. Various embodiments of the present application and various features that do not conflict with each other in the embodiments may be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present application will be understandable to those skilled in the art and are intended to be included within the scope of the present application.

[0065] Those skilled in the art will readily appreciate that the meanings of “on,” “over,” and “above” in this application should be interpreted in a broad sense, such that “on” not only means “directly on” something but also includes being “on” something with intervening features or layers, and “on” or “above” not only means “on” or “above” something but also includes being “on” or “above” something with no intervening features or layers (i.e., directly on something). In addition, spatially relative terms such as “under,” “below,” “lower,” “over,” and “upper” may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings.

[0066] As used herein, the term "substrate" refers to the material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. The substrate referred to herein specifically refers to a gallium nitride (GaN) substrate, and semiconductor devices fabricated thereon are collectively referred to as GaN-based devices.

[0067] As used herein, the term "layer" refers to a material portion comprising an area with a thickness. A layer can extend over the entirety of a lower or upper structure, or can have a range that is less than the range of a lower or upper structure. In addition, a layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer can be located between the top surface and the bottom surface of a continuous structure or between any horizontal faces at the top surface and the bottom surface. A layer can extend horizontally, vertically and / or along an inclined surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and a contact layer (wherein contacts, interconnects and / or through-holes are formed) and one or more dielectric layers.

[0068] Those skilled in the art can generally understand terms, at least in part, from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "said" can also be understood to convey singular usage or to convey plural usage. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0069] Those skilled in the art will better understand that when words such as "comprise" and / or "contain" are used in this specification, they specify the existence of the stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0070] The present invention provides an electrostatic discharge (ESD) protection circuit based on gallium nitride (GaN) components. Compared to traditional silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs), GaN high electron mobility transistors (HEMTs) have lower threshold voltages and smaller gate-to-source on-resistance. These characteristics enable HEMTs to achieve lower gate drive requirements and higher current and switching frequencies. However, the HEMT's lower gate breakdown voltage can also lead to gate damage, as gate overshoot voltage surges can easily exceed the gate breakdown voltage. Therefore, in practice, a gate protection circuit is commonly used to protect GaN HEMTs from voltage surges generated during component switching or ESD. In the embodiments of the present invention, unless otherwise specified, the HEMTs used are normally-off enhancement-mode (E-HEMTs).

[0071] First, please refer to Figure 1 , which is a schematic diagram of an electrostatic discharge protection circuit using gallium nitride components according to an embodiment of the present invention, wherein various gallium nitride components constituting the electrostatic discharge protection circuit of the present invention are depicted. Figure 1 As shown, the electrostatic discharge protection circuit of the present invention includes a power high electron mobility transistor (power E-HEMT) T, which can be used for power amplification in amplifier circuits and is suitable for applications in radio frequency, microwave or millimeter wave fields. Figure 1 As shown, the power high electron mobility transistor T includes a gate G, a source S and a drain D, wherein the source S and the drain D are respectively coupled to a first reference voltage V R1 (such as ground voltage V SS ) and a second reference voltage V R2 (such as working voltage V DDBecause the power high electron mobility transistor (HEMT) T is made of gallium nitride (GaN), its gate terminal is susceptible to damage from voltage surges. To protect the gate G of the HEM transistor T, an ESD protection circuit block B is designed to be coupled between the gate G and source S of the HEM transistor T to provide ESD protection. Under normal operating voltage conditions, the ESD protection circuit block B does not operate, and the HEM transistor T operates normally. However, during component switching or ESD events, voltage surges may occur in the circuit. In these situations, the ESD protection circuit block B is designed to protect the HEM transistor T from these surges, preventing gate damage. In one embodiment, the gate G of the HEM transistor T can be directly coupled to an I / O terminal of an IC chip via the ESD protection circuit block B. A resistor R (e.g., a two-dimensional electron gas (2DEG) resistor, hereinafter referred to as the main resistor) can be provided between the ESD protection circuit block B and the gate G to further reduce the voltage applied to the gate G. One or more other circuits may be disposed between the electrostatic discharge protection circuit block B and the input / output terminal I / O, but the present invention is not limited thereto.

[0072] Refer again Figure 1 The electrostatic discharge protection circuit block B is composed of a lateral field effect rectifier (FER), a first 2DEG resistor R1, and a first low-voltage high electron mobility transistor (LV-HEMT) T1. In an embodiment, the lateral field effect rectifier FER serves as one of the triggers of the electrostatic discharge protection circuit and may include at least one lateral field effect rectifier element connected in series. The entire lateral field effect rectifier FER has a set trigger voltage. One end of the lateral field effect rectifier FER is coupled to the gate G of the power high electron mobility transistor T (possibly through the main resistor R) and the input / output terminal I / O, and the other end is coupled to one end of the first 2DEG resistor R1 and a first gate G1 of the first low-voltage high electron mobility transistor (LV-HEMT) T1. The first 2DEG resistor R1 serves as a voltage divider, one end of which is coupled to the other end of the lateral field effect rectifier FER and the first gate G1 of the first low-voltage high electron mobility transistor T1, and the other end of which is coupled to the first reference voltage V R1And the source S of the power high electron mobility transistor T. The first low voltage high electron mobility transistor T1 is designed as a switching element in a discharge path, which has a threshold voltage. The first low voltage high electron mobility transistor T1 further includes a first gate G1, a first source S1 and a first drain D1, wherein the first gate G1 is coupled to the other end of the lateral field effect rectifier FER and one end of the first 2DEG resistor R1, the first source S1 is coupled to the gate G of the power high electron mobility transistor T (via the main resistor R) and the input / output terminal I / O, and the first drain D1 is coupled to the first reference voltage V R1 and the source S of the power HEMT T. In operation, when the voltage of the first source S1 or the first drain D1 is greater than the voltage of the first gate G1 and the difference therebetween exceeds the threshold voltage of the first LV HEMT T1, the first LV HEMT T1 is turned on.

[0073] Refer again Figure 1 . In actual operation, when a positive voltage surge caused by electrostatic discharge enters the chip from the input / output terminal I / O, one end of the lateral field effect rectifier FER will be pulled up to the effective level. When the degree to which one end of the lateral field effect rectifier FER is pulled up is greater than that of the other end and the difference therebetween exceeds the trigger voltage set by the lateral field effect rectifier FER, the lateral field effect rectifier FER will be turned on. Thereafter, the lateral field effect rectifier FER will be continuously pulled up, causing the voltage at its other end to rise further, until the voltage at the other end exceeds the critical voltage of the first low-voltage high-electron-mobility transistor T1, so that the first low-voltage high-electron-mobility transistor T1 will be turned on, thereby forming a voltage from the input / output terminal I / O through the first low-voltage high-electron-mobility transistor T1 to the first reference voltage V R1 In this embodiment of the present invention, the first low-voltage high-electron-mobility transistor T1 is designed to be more durable, for example, with a larger area and the ability to withstand higher currents. This conduction path effectively serves as an electrostatic discharge channel for dissipating electrostatic surges. This is the operating mechanism of the electrostatic discharge protection circuit of the present invention.

[0074] Now please refer to Figure 2 , which is a schematic diagram of an electrostatic discharge protection circuit using gallium nitride components according to another embodiment of the present invention. The circuit components in this embodiment are Figure 1The embodiment of the present invention is similar to the embodiment of the present invention, except that a first lateral field effect rectifier FER1 is provided in the electrostatic discharge protection circuit block B of this embodiment. As shown in the figure, one end of the first lateral field effect rectifier FER1 in the electrostatic discharge protection circuit block B is coupled to the first gate G1 of the first low-voltage high-electron-mobility transistor T1, the other end of the lateral field effect rectifier FER, and one end of the first 2DEG resistor R1, and the other end of the first lateral field effect rectifier FER1 is coupled to the first reference voltage V R1 and the source S of the power high electron mobility transistor T. In this embodiment, the presence of the first lateral field effect rectifier FER1 can enhance the electrostatic discharge protection function of the electrostatic discharge protection circuit block B. The first lateral field effect rectifier FER1 is connected in series with the gate of the first low voltage high electron mobility transistor T1. It has a high transient current capacity, can absorb the high voltage spike generated by electrostatic discharge, and has a reverse blocking function. In addition, when the negative voltage surge is from the first reference voltage V R1 When the voltage of the first lateral field effect rectifier FER1 enters the terminal and is higher than the trigger voltage of the first lateral field effect rectifier FER1, the first lateral field effect rectifier FER1 will be turned on to protect the first low-voltage high electron mobility transistor T1 connected thereto.

[0075] above Figure 1 as well as Figure 2 The embodiment of the present invention is a protection circuit design for unidirectional electrostatic discharge surge. Figure 3 , which is a schematic diagram of an electrostatic discharge protection circuit using gallium nitride components according to an embodiment of the present invention. It illustrates various gallium nitride components that make up the electrostatic discharge protection circuit of the present invention and is divided into two sub-circuit blocks for forward voltage surges and reverse voltage surges, respectively.

[0076] like Figure 3 As shown, the power high electron mobility transistor T of this embodiment includes a gate G, a source S and a drain D, wherein the source S and the drain D are respectively coupled to a first reference voltage V R1 (such as ground voltage V SS ) and a second reference voltage V R2 (such as working voltage V DDTo protect the gate G of the power high electron mobility transistor T, an electrostatic discharge (ESD) protection circuit block B is designed in the circuit and coupled between the gate G and source S of the power high electron mobility transistor T to provide ESD protection. In one embodiment, the gate G of the power high electron mobility transistor T can be directly coupled to an input / output terminal (I / O) of an IC chip through the ESD protection circuit block B. A resistor R, such as a two-dimensional electron gas (2DEG) resistor, can be disposed between the ESD protection circuit block B and the gate G to further reduce the voltage applied to the gate G. One or more other circuits may also be disposed between the ESD protection circuit block B and the input / output terminal (I / O), without limitation.

[0077] Refer again Figure 3The electrostatic discharge protection circuit block B is divided into a first sub-circuit B1 and a second sub-circuit B2, each having a different trigger voltage. In an embodiment of the present invention, the first sub-circuit B1 and the second sub-circuit B2 are both coupled between the gate G and the source S of the power high electron mobility transistor T. The two are connected in series but in an anti-symmetrical arrangement. More specifically, the first sub-circuit B1 is composed of a third lateral rectifier FER3, a first 2DEG resistor R1, and a first low-voltage high electron mobility transistor T1. The third lateral rectifier FER3 serves as one of the triggers of the electrostatic discharge protection circuit and may include at least one lateral field-effect rectifier element connected in series. The entire third lateral rectifier FER3 has a set trigger voltage. One end of the third lateral rectifier FER3 is coupled to the gate G of the power high electron mobility transistor T (possibly through the main resistor R) and the input / output terminal I / O, and the other end of the third lateral rectifier FER3 is coupled to one end of the first 2DEG resistor R1 and a first gate G1 of the first low-voltage high electron mobility transistor T1. The first 2DEG resistor R1 acts as a voltage divider, with one end coupled to the other end of the third lateral rectifier FER3 and the first gate G1 of the first low-voltage high-electron-mobility transistor T1. The other end is coupled to a second 2DEG resistor R2 in the second sub-circuit B2. The first low-voltage high-electron-mobility transistor T1 is designed as a switching element in a discharge path and has a threshold voltage. The first low-voltage high-electron-mobility transistor T1 further includes a first gate G1, a first source S1, and a first drain D1. The first gate G1 is coupled to the other end of the third lateral rectifier FER3 and one end of the first 2DEG resistor R1. The first source S1 is coupled to the gate G of the power high-electron-mobility transistor T (possibly via the main resistor R) and the input / output terminal I / O. The first drain D1 is coupled to the second drain D2 of the second low-voltage high-electron-mobility transistor T2 in the second sub-circuit B2. In operation, when the voltage of the first source S1 or the first drain D1 is greater than the voltage of the first gate G1 and the difference therebetween exceeds the threshold voltage of the first low-voltage high-electron-mobility transistor T1 , the first low-voltage high-electron-mobility transistor T1 is turned on.

[0078] Refer again Figure 3 The structure of the second sub-circuit B2 is similar to that of the first sub-circuit B1, except that it is connected in series with the first sub-circuit B1 and is arranged in an inversely symmetrical manner. Figure 4As shown, the second sub-circuit B2 is composed of a fourth lateral rectifier FER4, a second 2DEG resistor R2, and a second low-voltage high electron mobility transistor T2. The fourth lateral rectifier FER4 serves as another trigger of the electrostatic discharge protection circuit and may include at least one lateral field effect rectifier element connected in series. The entire fourth lateral rectifier FER4 has a set trigger voltage. One end of the fourth lateral rectifier FER4 is coupled to the first reference voltage V R1 And the source S of the power high electron mobility transistor T, the other end of which is coupled to one end of the second 2DEG resistor R2 and the second gate G2 of the second low voltage high electron mobility transistor T2. The second 2DEG resistor R2 acts as a voltage divider, one end of which is coupled to the other end of the fourth horizontal rectifier FER4 and a second gate G2 of the second low voltage high electron mobility transistor T2, and the other end of which is coupled to the other end of the second 2DEG resistor R2 in the first sub-circuit B1. The second low voltage high electron mobility transistor T2 is designed as one of the switching elements in a discharge path, which has a threshold voltage. The second low voltage high electron mobility transistor T2 further includes a second gate G2, a second source S2 and a second drain D2, wherein the second gate G2 is coupled to one end of the second 2DEG resistor R2 and the other end of the fourth horizontal rectifier FER4, and the second source S2 is coupled to the first reference voltage V R1 The second drain D2 is coupled to the first drain D1 of the first low-voltage high-electron-mobility transistor T1 in the first sub-circuit B1. In operation, when the voltage at the second source S2 or the second drain D2 is greater than the voltage at the second gate G2, and the difference therebetween exceeds the threshold voltage of the second low-voltage high-electron-mobility transistor T2, the second low-voltage high-electron-mobility transistor T2 is turned on.

[0079] In actual operation, when a positive voltage surge caused by electrostatic discharge enters the chip from the I / O terminal, one end of the third horizontal rectifier FER3 is pulled up to an active voltage level. When the degree of pull-up of one end of the third horizontal rectifier FER3 is greater than that of the other end, and the difference between the two exceeds the trigger voltage of the third horizontal rectifier FER3, the third horizontal rectifier FER3 will turn on. The third horizontal rectifier FER3 will then continue to pull up, causing the voltage at its other end to rise further, until the voltage at the other end of the fourth horizontal rectifier FER4 is equal to the first reference voltage V R1 The difference between them exceeds the threshold voltage of the second low voltage high electron mobility transistor T2, so the second low voltage high electron mobility transistor T2 will be turned on, thereby forming a first reference voltage V from the input / output terminal I / O through the third horizontal rectifier FER3, the first 2DEG resistor R1, the second 2DEG resistor R2 and the second low voltage high electron mobility transistor T2.R1 Then, when the current flowing through the first conduction path is large enough to make the voltage difference between the two ends of the first 2DEG resistor R1 exceed the critical voltage of the first low-voltage high-electron-mobility transistor T1, the first low-voltage high-electron-mobility transistor T1 will be turned on, forming a first reference voltage V from the input / output terminal I / O through the first low-voltage high-electron-mobility transistor T1 and the second low-voltage high-electron-mobility transistor T2. R1 In this embodiment of the present invention, the first low-voltage high-electron-mobility transistor T1 and the second low-voltage high-electron-mobility transistor T2 are designed to be more durable, for example, with a larger area and the ability to withstand higher currents. Therefore, the second conductive path effectively serves as an electrostatic discharge channel for dissipating electrostatic surges. This is the operating mechanism of the electrostatic discharge protection circuit of the present invention.

[0080] On the other hand, when the negative voltage surges from the first reference voltage V R1 When the electrostatic surge enters the chip, the protection mechanism is completely opposite to the above mechanism. The fourth lateral rectifier FER4 is first pulled up and turned on, followed by the first low-voltage high-electron-mobility transistor T1, and finally the second low-voltage high-electron-mobility transistor T2. In this way, a second conduction path is established to discharge the electrostatic surge.

[0081] Now please refer to Figure 4 , which is a schematic diagram of an electrostatic discharge protection circuit using gallium nitride components according to another embodiment of the present invention. The circuit components in this embodiment are Figure 3 The embodiments are similar, differing only in that a first lateral field-effect rectifier FER1 and a second lateral field-effect rectifier FER2 are additionally provided in the first sub-circuit B1 and the second sub-circuit B2, respectively. As shown in the figure, one end of the first lateral field-effect rectifier FER1 in the first sub-circuit B1 is coupled to one end of the second lateral field-effect rectifier FER2 in the second sub-circuit B2, and the other end thereof is coupled to the gate of the first low-voltage high-electron-mobility transistor T1, the other end of the third lateral field-effect rectifier FER3, and one end of the first 2DEG resistor R1. One end of the second lateral field-effect rectifier FER2 in the second sub-circuit B2 is coupled to one end of the first lateral field-effect rectifier FER1 in the first sub-circuit B1, and the other end thereof is coupled to the second gate G2 of the second low-voltage high-electron-mobility transistor T2, the other end of the fourth lateral field-effect rectifier FER4, and one end of the second 2DEG resistor R2.

[0082] In this embodiment, the presence of the first lateral field effect rectifier FER1 and the second lateral field effect rectifier FER2 can enhance the protection function of the electrostatic discharge protection circuit block B. Taking the first sub-circuit B1 as an example, the first lateral field effect rectifier FER1 is connected in series with the gate of the first low-voltage high electron mobility transistor T1. It has a high transient current capacity, can absorb the high voltage spike generated by electrostatic discharge, and has a reverse blocking function. In addition, when the negative voltage surge is from the first reference voltage V R1 When a positive voltage surge enters the input / output terminal I / O and exceeds the trigger voltage of the first lateral field-effect rectifier FER1, the first lateral field-effect rectifier FER1 turns on to protect the first low-voltage high-electron-mobility transistor T1. The second lateral field-effect rectifier FER2 in the second sub-circuit B2 functions in the same manner as described above, but is arranged in an inversely symmetrical manner. When a positive voltage surge enters the input / output terminal I / O and exceeds the trigger voltage of the second lateral field-effect rectifier FER2, the second lateral field-effect rectifier FER2 turns on to protect the second low-voltage high-electron-mobility transistor T2.

[0083] Now please refer to Figure 5 , which is a schematic diagram of an electrostatic discharge protection circuit using gallium nitride components according to another embodiment of the present invention. The circuit components in this embodiment are Figure 4 The embodiments are similar, the only difference is that the two triggers in this embodiment are changed from lateral field effect rectifiers FER3 / FER4 to capacitors C1 / C2. 1 / C2 in the protection circuit of the present invention can achieve a similar effect as the lateral field effect rectifier FER3 / FER4. Its operating mechanism is the same as that described in the above embodiment and will not be elaborated herein.

[0084] After describing the circuit structure of the present invention's ESD protection circuit, the following figures and examples illustrate cross-sectional views of various GaN components used in the circuit. A key feature of the present invention is that all components in the circuit can be GaN devices, fabricated on the same GaN substrate and integrated using the same manufacturing process.

[0085] First, please refer to Figure 6 , which is a cross-sectional schematic diagram of a capacitor according to an embodiment of the present invention, which shows Figure 5 The detailed structure of the first capacitor C1 or the second capacitor C2. Figure 6As shown, the capacitors C1 / C2 of the present invention may be gallium nitride capacitors disposed on a gallium nitride substrate 100. The gallium nitride substrate 100 may also be a gallium nitride epitaxial layer formed on a silicon substrate, with a buffer layer, superlattice layer, and other layer structures formed therebetween, but the present invention is not limited thereto. Subsequent figures will use a gallium nitride substrate 100 as a representative example. In one embodiment, an aluminum gallium nitride (AlGaN) layer 102 is formed on the gallium nitride substrate 100. A heterojunction is formed between the AlGaN layer 102 and the gallium nitride substrate 100, with an energy gap discontinuity therebetween. Electrons generated in the AlGaN layer 102 due to the piezoelectric effect fall into the gallium nitride substrate 100, thereby generating a thin layer of highly mobile and conductive electrons at the interface between the two layers. This layer, known as a two-dimensional electron gas (2DEG), can serve as the channel of a transistor device. Furthermore, to produce an enhancement-mode GaN device with normally-off properties, a patterned P-type GaN layer 104 (e.g., GaN doped with P-type dopants such as carbon, iron, magnesium, or zinc) is formed on the AlGaN layer 102 to deplete the underlying two-dimensional electron gas (2DEG) to form a non-conductive depletion region.

[0086] Refer again Figure 6 In addition to the conductive region and the non-conductive region formed by the gallium nitride material, the first capacitor C1 or the second capacitor C2 also includes an anode C A formed on the P-type GaN layer 104 and a cathode C C The anode C is formed on the GaN substrate 100 and the AlGaN layer 102 on one side of the P-type GaN layer 104 to serve as the two electrodes of the capacitor. A With cathode C C The material may include a conductive material layer of a refractory metal or a related compound thereof, such as titanium (Ti), titanium nitride (TiN), tungsten titanium alloy (TiW) and tungsten (W), or nickel (Ni), gold (Au), copper (Cu), or an alloy thereof. In the embodiment of the present invention, the anode C A With cathode C C These are the conductor ends of the GaN capacitor, and the non-conductive area between them is the capacitor dielectric layer, such as the AlGaN layer 102 and the P-type GaN layer 104. When a voltage exists between the two conductors separated by the non-conductive area, an electric field will be generated on the non-conductive area, which will cause positive charges to concentrate on one conductor and negative charges to concentrate on the other conductor. For example, taking the first capacitor C1 as an example, when a positive voltage surge enters the chip from the I / O terminal, the cathode C C That is equivalent to the other end coupled to the input / output terminal I / O, the anode C A This is equivalent to the first reference voltage V R1The second capacitor C2 is set in reverse in the case of a negative voltage surge. In other embodiments, the anode C A With cathode C C The position on the gallium nitride substrate can also be swapped, but the present invention is not limited thereto. The capacitance value generated by the gallium nitride capacitor is preferably between 1 pF and 50 pF.

[0087] Now please refer to Figure 7 , which is a cross-sectional schematic diagram of a capacitor according to another embodiment of the present invention. In addition to the aforementioned gallium nitride capacitor, the first capacitor C1 or the second capacitor C2 of the present invention can also be a general metal-insulator-metal (MIM) capacitor. Figure 7 As shown, the first capacitor C1 or the second capacitor C2 is also fabricated on a gallium nitride substrate 100. Unlike the previous embodiment, which forms an aluminum gallium nitride layer 102 to create a two-dimensional electron device (2DEG), an ion-implanted insulating layer 106 is formed on the gallium nitride substrate 100 in this embodiment. This layer, for example, is a non-conductive layer formed by heavily doping the surface of the gallium nitride substrate 100 to prevent electrical coupling between the subsequent conductive layer formed thereon and the gallium nitride substrate 100. A passivation layer 108 is formed on the ion-implanted insulating layer 106. The passivation layer 108 may be made of one or more layers of silicon dioxide, silicon nitride (SiN), silicon oxynitride (SiON), undoped silicate glass (USG), or phospho-silicate glass (PSG). In this embodiment, an anode metal layer 110 and a cathode metal layer 112 may be formed within and on the passivation layer 108, respectively, to serve as the two electrodes of the capacitor. The materials of the anode metal layer 110 and the cathode metal layer 112 may include conductive material layers of refractory metals or related compounds thereof, such as titanium (Ti), titanium nitride (TiN), tungsten-titanium alloy (TiW) and tungsten (W), or may include nickel (Ni), gold (Au), copper (Cu) or their alloys. The passivation layer 108, the anode metal layer 110 and the cathode metal layer 112 may be integrated into the back-end semiconductor process. Similarly, in an embodiment of the present invention, the anode metal layer 110 and the cathode metal layer 112 are the conductors at both ends of the MIM capacitor, and the passivation layer 108 therebetween is the capacitor dielectric layer. When there is a voltage between the anode metal layer 110 and the cathode metal layer 112, an electric field will be generated in the passivation layer 108, causing positive charges to be concentrated on one conductor and negative charges to be concentrated on the other conductor. For example, taking the first capacitor C1 as an example, when a positive voltage surge enters the chip from the input / output terminal I / O, the cathode metal layer 112 is equivalent to the other end coupled to the input / output terminal I / O, and the anode metal layer 110 is equivalent to the first reference voltage V R1The second capacitor C2 is reversed in the event of a negative voltage surge. In other embodiments, the positions of the anode metal layer 110 and the cathode metal layer 112 on the gallium nitride substrate may be reversed, without limitation. The capacitance generated by this MIM capacitor is preferably between 1pF and 50pF.

[0088] Now please refer to Figure 8 , which is a cross-sectional schematic diagram of a gallium nitride resistor according to an embodiment of the present invention, depicting the detailed structure of the main resistor R, the first 2DEG resistor R1 and / or the second 2DEG resistor R2 in the above embodiment. Figure 8 As shown, the resistors R / R1 / R2 of the present invention are also arranged on the gallium nitride substrate 100. An aluminum gallium nitride layer 102 is formed on the gallium nitride substrate 100, thereby generating a two-dimensional electron gas 2DEG as a conductive channel. Unlike the previous embodiment, a P-type gallium nitride layer 104 pattern is not formed on the aluminum gallium nitride layer 102 to generate a non-conductive depletion region. The entire two-dimensional electron gas 2DEG serves as the main body of the resistor. A high potential terminal R is formed on the aluminum gallium nitride layer 102 and the gallium nitride substrate 100 at both ends of the resistor R / R1 / R2. H With a low potential terminal R L Taking the second 2DEG resistor R2 as an example, the high potential end R H That is, the terminal coupled to the input / output terminal I / O and the gate G of the power high electron mobility transistor T (via the main resistor R), the low potential terminal R L The other end is coupled to the second capacitor C2. The resistance value generated by the gallium nitride resistor is preferably between 50Ω and 100kΩ.

[0089] Now please refer to Figure 9 , which is a cross-sectional schematic diagram of a lateral field effect rectifier used as a trigger according to an embodiment of the present invention, illustrating the detailed structures of the lateral field effect rectifier FER and FER1-FER4 in the above embodiment. Figure 9 As shown, the lateral field effect rectifiers FER, FER1-FER4 of the present invention are also disposed on a gallium nitride substrate 100. An aluminum gallium nitride layer 102 is formed on the gallium nitride substrate 100, thereby generating a two-dimensional electron gas 2DEG as a conductive channel. A P-type gallium nitride layer 104 is also formed on the aluminum gallium nitride layer 102 to deplete the two-dimensional electron gas 2DEG directly below it to form a non-conductive depletion region. Furthermore, the lateral field effect rectifiers FER, FER1-FER4 further include a first anode D A1 formed on the P-type gallium nitride layer 104, and a second anode D A2 With a cathode D CThe first anode D is formed on the gallium nitride substrate 100 and the aluminum gallium nitride layer 102 on both sides of the P-type gallium nitride layer 104. A1 With the second anode D A2 They are coupled to each other to realize the rectification function of the diode with forward conduction and reverse blocking, and have the characteristics of low on-resistance and high reverse withstand voltage. A1 The width of the first anode D is preferably between 50 μm and 1000 μm. A1 , second anode D A2 and cathode D C The material may include a conductive material layer of a refractory metal or its related compounds, such as titanium (Ti), titanium nitride (TiN), tungsten titanium alloy (TiW) and tungsten (W), or nickel (Ni), gold (Au), copper (Cu) or their alloys. In the embodiment of the present invention, Figure 3 For example, when a positive voltage surge enters the chip from the I / O terminal, the cathode D C That is equivalent to the other end coupled to the input / output terminal I / O, the first anode D A1 With the second anode D A2 This is equivalent to the first reference voltage V R1 The fourth lateral field effect rectifier FER4 is set in reverse direction in the case of a negative voltage surge.

[0090] Now please refer to Figure 10 , which is a cross-sectional schematic diagram of a low voltage high electron mobility transistor (LV-HEMT) according to an embodiment of the present invention, illustrating the detailed structures of the first low voltage high electron mobility transistor T1 and the second low voltage high electron mobility transistor T2 in the above embodiment. Figure 10 As shown, the first low-voltage high-electron-mobility transistor T1 / the second low-voltage high-electron-mobility transistor T2 of the present invention are also disposed on a gallium nitride substrate 100. An aluminum gallium nitride layer 102 is formed on the gallium nitride substrate 100, thereby generating a two-dimensional electron gas (2DEG) that serves as a conductive channel. A p-type gallium nitride layer 104 is also patterned on the aluminum gallium nitride layer 102 to deplete the two-dimensional electron gas (2DEG) directly beneath it, forming a non-conductive depletion region that serves as the transistor channel. Furthermore, the lateral field-effect rectifier FER1 / FER2 further includes a gate G1 / G2 formed on the p-type gallium nitride layer 104, and a source S1 / S2 and a drain D1 / D2 formed on the gallium nitride substrate 100 and the aluminum gallium nitride layer 102, respectively, on either side of the p-type gallium nitride layer 104. In this embodiment, the width of the gate G1 / G2 (perpendicular to the page) is preferably greater than 1000 μm. In addition, for different operating voltages, the gate-to-drain length L of the HEMT transistor is GDDifferent sizes are also possible. For example, for high voltage components, the length L GD The preferred range is 15 μm to 20 μm. For medium voltage components, the length L GD The preferred range is 1.8 μm to 5 μm. For low voltage components, the length L GD Preferably, it is between 1μm and 1.8μm. Similarly, the materials of the gate G1 / G2, the source S1 / S2 and the drain D1 / D2 may include a conductive material layer of a refractory metal or its related compounds, such as titanium (Ti), titanium nitride (TiN), tungsten-titanium alloy (TiW), and tungsten (W), or include nickel (Ni), gold (Au), copper (Cu), or their alloys. In an embodiment of the present invention, taking the second low-voltage high electron mobility transistor T2 as an example, when a positive voltage surge enters the chip from the input / output terminal I / O, the second gate G2 will be pulled up to the effective level and turned on. Subsequently, when the first low-voltage high electron mobility transistor T1 coupled to the second drain D2 is also turned on, a voltage is established from the input / output terminal I / O through the first low-voltage high electron mobility transistor T1 and the second low-voltage high electron mobility transistor T2 to the first reference voltage V R1 The second conductive path is provided to discharge electrostatic surges.

[0091] Based on the aforementioned embodiments, those skilled in the art will appreciate that a major feature of the present invention is that all components of the ESD protection circuit can be GaN-based devices and / or manufactured using processes compatible with GaN devices, including resistors, capacitors, lateral field-effect rectifiers, and high-electron-mobility transistors (HEMTs). These components can be fabricated on the same GaN substrate and integrated using the same manufacturing process. For example, the main resistor R and 2DEG resistors R1 / R2, the flip-flops FER1-FER4 or C1 / C2, and the power HEMT T and low-voltage HEMT T1 / T2 can all share the same GaN substrate 100 and the same AlGaN layer 102. Furthermore, the flip-flops FER1-FER4 or C1 / C2, the power HEMT T, and the low-voltage HEMT T1 / T2 can also share the same P-type GaN layer 104. Such a design facilitates the integration of circuit design and manufacturing process of the power HEMT device, thereby reducing the cost and steps required for its production, which is an advantage of the present invention.

[0092] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An electrostatic discharge protection circuit using a gallium nitride device, comprising: A power high electron mobility transistor having a gate, a source and a drain, wherein the source and the drain are coupled to a first reference voltage and a second reference voltage respectively; Electrostatic discharge protection circuit block, including: The first sub-circuit comprises: a first trigger, one terminal of which is coupled to the gate; a first two-dimensional electron gas resistor, one end of which is coupled to the other end of the first trigger; a first low-voltage high electron mobility transistor having a first gate, a first source, and a first drain, wherein the first gate is coupled to the other end of the first trigger and the one end of the first two-dimensional electron gas resistor, and the first source is coupled to the gate and the one end of the first trigger; as well as a first lateral field effect rectifier, one end of which is coupled to the first gate, the other end of the first trigger, and the one end of the first two-dimensional electron gas resistor; The second sub-circuit comprises: A second trigger, one end of which is coupled to the source and the first reference voltage; a second two-dimensional electron gas resistor, one end of which is coupled to the other end of the second trigger; a second low-voltage high electron mobility transistor having a second gate, a second source, and a second drain, wherein the second gate is coupled to the other end of the second trigger and the one end of the second two-dimensional electron gas resistor, and the second drain is coupled to the source and the first reference voltage; as well as a second lateral field effect rectifier, one end of which is coupled to the second gate, the other end of the second trigger, and the one end of the second two-dimensional electron gas resistor; The other end of the first two-dimensional electron gas resistor, the other end of the second two-dimensional electron gas resistor, the other end of the first lateral field effect rectifier, the other end of the second lateral field effect rectifier, the first drain, and the second drain are coupled to each other.

2. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1 , wherein the first trigger is a gallium nitride capacitor, comprising: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the anode (A); and A cathode (C) is located on the gallium nitride substrate and the aluminum gallium nitride layer on one side of the P-type gallium nitride layer and is coupled to the one end and the other end of the first trigger.

3. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1 , wherein the second trigger is a gallium nitride capacitor, comprising: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the anode; as well as The cathode is located on the gallium nitride substrate and the aluminum gallium nitride layer at one side of the P-type gallium nitride layer and is coupled to the one end and the other end of the second trigger.

4. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1 , wherein the first trigger is a metal-insulator-metal capacitor comprising: GaN substrate; an ion-implanted insulating layer located on the gallium nitride substrate; a passivation layer located on the ion-implanted insulating layer; a gate metal layer located in the passivation layer; and The source / drain metal layer is located on the passivation layer and is coupled to the one end and the other end of the first trigger.

5. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1 , wherein the second trigger is a metal-insulator-metal capacitor comprising: GaN substrate; an ion-implanted insulating layer located on the gallium nitride substrate; a passivation layer located on the ion-implanted insulating layer; a gate metal layer located in the passivation layer; and The source / drain metal layer is located on the passivation layer and is coupled to the one end and the other end of the second trigger.

6. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1 , wherein the first trigger is at least one lateral field effect rectifier connected in series, each of the lateral field effect rectifiers comprising: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the first anode; The cathode and the second anode are respectively located on the gallium nitride substrate and the aluminum gallium nitride layer on both sides of the P-type gallium nitride layer, wherein the cathode and the second anode are respectively coupled to the one end and the other end of the first trigger, and the first anode is coupled to the second anode.

7. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1 , wherein the second trigger is at least one lateral field effect rectifier connected in series, each of the lateral field effect rectifiers comprising: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the first anode; The cathode and the second anode are respectively located on the gallium nitride substrate and the aluminum gallium nitride layer on both sides of the P-type gallium nitride layer, wherein the cathode and the second anode are respectively coupled to the one end and the other end of the second trigger, and the first anode is coupled to the second anode.

8. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1 , wherein the first lateral field effect rectifier comprises: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the first anode; The cathode and the second anode are respectively located on the gallium nitride substrate and the aluminum gallium nitride layer on both sides of the P-type gallium nitride layer, wherein the cathode and the second anode are respectively coupled to the one end and the other end of the first trigger, and the first anode is coupled to the second anode.

9. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1 , wherein the second lateral field effect rectifier comprises: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the first anode; The cathode and the second anode are respectively located on the gallium nitride substrate and the aluminum gallium nitride layer on both sides of the P-type gallium nitride layer, wherein the cathode and the second anode are respectively coupled to the one end and the other end of the first trigger, and the first anode is coupled to the second anode. 10 . The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1 , further comprising a main two-dimensional electron gas resistor having one end coupled to the gate and the other end coupled to the one end of the first trigger and the first source.

11. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 10, wherein the main two-dimensional electron gas resistor comprises: GaN substrate; an aluminum gallium nitride layer located on the gallium nitride substrate; and A high potential end and a low potential end are located on the gallium nitride substrate and the aluminum gallium nitride layer and are respectively coupled to the other end and the one end of the main two-dimensional electron gas resistor.

12. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1, wherein the first two-dimensional electron gas resistor comprises: GaN substrate; an aluminum gallium nitride layer located on the gallium nitride substrate; and A high potential end and a low potential end are located on the gallium nitride substrate and the aluminum gallium nitride layer and are respectively coupled to the one end and the other end of the first two-dimensional electron gas resistor.

13. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1 , wherein the second two-dimensional electron gas resistor comprises: GaN substrate; an aluminum gallium nitride layer located on the gallium nitride substrate; and A high potential end and a low potential end are located on the gallium nitride substrate and the aluminum gallium nitride layer and are respectively coupled to the one end and the other end of the first two-dimensional electron gas resistor.

14. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1, wherein the first low-voltage high electron mobility transistor comprises: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the first gate; and The first source and the first drain are respectively located on the gallium nitride substrate and the aluminum gallium nitride layer at two sides of the P-type gallium nitride layer.

15. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1, wherein the second low-voltage high electron mobility transistor comprises: GaN substrate; an aluminum gallium nitride layer, located on the gallium nitride substrate; A P-type gallium nitride layer, located on the aluminum gallium nitride layer and connected to the second gate; and The second source and the second drain are respectively located on the gallium nitride substrate and the aluminum gallium nitride layer at two sides of the P-type gallium nitride layer.

16. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1, wherein the first two-dimensional electron gas resistor, the first trigger, the first low-voltage high electron mobility transistor, the first lateral field-effect rectifier, the second two-dimensional electron gas resistor, the second trigger, the second low-voltage high electron mobility transistor, and the second lateral field-effect rectifier share a same gallium nitride substrate and a same aluminum gallium nitride layer.

17. The electrostatic discharge protection circuit using gallium nitride devices as claimed in claim 1, wherein the first trigger, the second trigger, the first low-voltage high-electron-mobility transistor, the first lateral field-effect rectifier, the second trigger, the second low-voltage high-electron-mobility transistor, and the second lateral field-effect rectifier share a same P-type gallium nitride layer.

18. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1 , wherein the first trigger has a threshold voltage, and when the voltage at one end of the first trigger is higher than the voltage at the other end of the first trigger and the voltage difference exceeds the threshold voltage of the first trigger, the first trigger is turned on; and the first low-voltage high-electron-mobility transistor has a threshold voltage, and when the voltage difference across the first two-dimensional electron gas resistor exceeds the threshold voltage of the first low-voltage high-electron-mobility transistor, the first low-voltage high-electron-mobility transistor is turned on.

19. The electrostatic discharge protection circuit using a gallium nitride device as claimed in claim 1 , wherein the second trigger has a threshold voltage, and when the voltage at one end of the second trigger is higher than the voltage at the other end of the second trigger and the voltage difference exceeds the threshold voltage of the second trigger, the second trigger is turned on; and the second low-voltage high-electron-mobility transistor has a threshold voltage, and when the voltage difference across the second two-dimensional electron gas resistor exceeds the threshold voltage of the second low-voltage high-electron-mobility transistor, the second low-voltage high-electron-mobility transistor is turned on.

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