A control structure suitable for a low power bluetooth receiving circuit

Abstract

The application discloses a control structure suitable for a low-power-consumption Bluetooth receiving circuit and belongs to the technical field of Bluetooth receiving circuit design, and comprises a main processor, a system bus, a baseband processing module, an APB interface, an APB-to-SPI module, an SPI selection module, an SPI module and a physical layer module; after the BLE chip is powered on, the main processor accesses the system bus through an AHB interface, and configures an initialization module, a radio frequency calibration module, a demodulation module and a modulation module in the physical layer module through the APB interface output by the system bus and after the APB-to-SPI module. The application adopts double-way SPI, can facilitate the main processor to configure the BLE physical layer in various aspects, and can meet the demand of BLE fast frequency hopping.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of Bluetooth receiving circuit design, and particularly relates to a control structure suitable for a low-power Bluetooth receiving circuit. BACKGROUND

[0002] In a complex 2.4 GHz ISM frequency band, a Bluetooth Low Energy (BLE) device needs to coexist with Wi-Fi, ZigBee and other multiple co-frequency or adjacent frequency devices, and is extremely susceptible to external radio frequency interference. In order to improve the reliability of the link, the BLE device adopts a frequency hopping technology (Frequency Hopping Spread Spectrum, FHSS) based on the spread spectrum idea, and quickly switches between multiple channels according to a predetermined sequence in the communication process, so as to disperse the interference in time and frequency dimensions, and reduce the bit error rate. Therefore, the BLE chip must have the ability of rapid frequency hopping.

[0003] In the actual design of the BLE chip, considering that a phase-locked loop (PLL) circuit of a radio frequency front end needs a locking time of tens of microseconds, the frequency control word of the PLL needs to be configured in advance, and a main processor in the BLE chip usually needs to process other tasks, and cannot configure the PLL in time, so as to meet the frequency hopping requirement of the BLE.

[0004] The application relates to a control structure between a main processor, a baseband processing module and a physical layer module, and particularly relates to a control structure realized in a BLE chip. SUMMARY

[0005] The application aims to provide a control structure suitable for a low-power Bluetooth receiving circuit, in different working stages of the BLE chip, the main processor and the baseband processing module configure the physical layer module through respective SPIs, which can meet the requirement of rapidly configuring the frequency control word of the PLL, and can conveniently perform other configurations on the physical layer module, so as to solve the problems in the background technology.

[0006] To achieve the above object, the application provides the following technical scheme: a control structure suitable for a low-power Bluetooth receiving circuit, which comprises a main processor, a system bus, a baseband processing module, an APB interface, an APB-to-SPI module, an SPI selection module, an SPI module and a physical layer module.

[0007] After the BLE chip is powered on, the main processor accesses the system bus through an AHB interface, and configures an initialization module, a radio frequency calibration module, a demodulation module and a modulation module in the physical layer module through the APB interface output by the system bus and after the APB-to-SPI module.

[0008] After the configuration is completed, the main processor switches the SPI channel in the SPI selection module from the APB to SPI path to the SPI interface output by the baseband processing module, and writes the subsequent PLL frequency control word corresponding to the BLE frequency hopping into the shared SRAM;

[0009] When the BLE protocol stack works, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance when frequency hopping, and configures the phase-locked loop PLL module in the physical layer module through the SPI interface.

[0010] Preferably, the control structure suitable for the low-power Bluetooth receiving circuit has the following specific processing procedure:

[0011] In the first step, after the BLE chip is powered on, the SPI selection module is powered on and the APB to SPI path is selected by default. At this time, the main processor initializes and configures the physical layer module through the SPI interface of the APB to SPI path.

[0012] In the second step, after the physical layer module completes the initialization and configuration, the main processor continues to configure the radio frequency calibration module in the physical layer module through the SPI interface. The radio frequency calibration module then starts the calibration of the radio frequency related components. The main processor queries the radio frequency calibration related state signal through the SPI interface. When the calibration completion signal is read, the third step is entered.

[0013] In the third step, the main processor configures the demodulation module in the physical layer module through the SPI interface. The configuration content includes but is not limited to turning on the receive clock and turning on the ADC. After the configuration is completed, the fourth step is entered.

[0014] In the fourth step, the main processor configures the modulation module in the physical layer module through the SPI interface. The configuration content includes but is not limited to configuring the modulation rate, the transmission power and the GFSK modulation frequency offset. After the configuration is completed, the fifth step is entered.

[0015] In the fifth step, the main processor switches the SPI channel of the SPI selection module to the SPI interface output by the baseband processing module, and enters the sixth step.

[0016] In the sixth step, the main processor writes the PLL frequency control word required when the BLE frequency hops into the shared SRAM, and notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM, and enters the seventh step.

[0017] In the seventh step, the main processor configures the baseband processor module according to the software program of the BLE protocol stack. The configuration content includes but is not limited to the BLE event type, the start time, the timeout time, the frequency hopping interval and the channel mapping table. After the configuration is completed, the eighth step is entered.

[0018] The eighth step, after the baseband processing module receives the start time parameter configured by the main processor, when the internal counter counts to the start time, the BLE event is started, the physical layer module is responsible for the modulation and demodulation of the wireless signal, the baseband processing module is responsible for the protocol analysis or generation, when the BLE frequency hopping, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance, and configures it into the phase-locked loop PLL module in the physical layer module through the SPI interface, because the frequency control word of the PLL is configured in advance, when the BLE chip frequency hopping, the PLL has been locked, and the ninth step is entered.

[0019] The ninth step, after the baseband processing module completes the processing of the BLE event, the processing data is stored in the shared SRAM, and the main processor is informed that the BLE event has ended through the interrupt signal, and the main processor performs subsequent processing based on the data stored in the shared SRAM.

[0020] Preferably, in the sixth step, the main processor informs the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM, at this time, the main processor informs the baseband processing module that the transmission starting path of the signal is the main processor, the AHB interface, the system bus, the AHB interface and the baseband processing module in turn.

[0021] Preferably, in the eighth step, the advance time of the baseband processing module reading the PLL frequency control word from the shared SRAM is 40-60 microseconds.

[0022] Compared with the prior art, the beneficial effects of the present application are:

[0023] The control structure suitable for the low-power Bluetooth receiving circuit of the present application adopts double SPI, which can not only facilitate the main processor to configure the BLE physical layer, but also meet the demand of BLE fast frequency hopping. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The implementation structure diagram of the control structure suitable for the low-power Bluetooth receiving circuit of the present application.

[0025] Figure 2 The specific processing flowchart of the control structure suitable for the low-power Bluetooth receiving circuit of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0027] As Figure 1 shown, a control structure suitable for a low-power Bluetooth receiving circuit of the application, after the chip is powered on, the main processor accesses the system bus through the AHB (Advanced High performance Bus, advanced high performance bus) interface, and outputs the APB (Advanced Peripheral Bus, advanced peripheral bus) interface through the system bus, and after the APB to SPI module, the initialization, radio frequency calibration, demodulation and modulation modules in the physical layer module are configured, after the configuration is completed, the main processor will switch the SPI channel of the SPI selection module from the APB to SPI to the SPI of the baseband processing module, and the main processor will write the corresponding PLL frequency control word of the subsequent BLE frequency hopping into the shared SRAM (Static Random-Access Memory, static random access memory); when the BLE protocol stack works, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance when frequency hopping, and configures the PLL in the physical layer module through the SPI interface.

[0028] As Figure 2 shown, a control structure suitable for a low-power Bluetooth receiving circuit of the application, the specific processing flow is as follows:

[0029] First, the BLE chip is powered on, the SPI selection module is powered on by default, and the APB to SPI is selected, at this time, the main processor configures the physical layer module through this SPI;

[0030] Second, after the initialization configuration is completed, the main processor continues to configure the radio frequency calibration module in the physical layer module through the SPI, and the radio frequency calibration module subsequently starts the calibration of the radio frequency related components, and the main processor can query the state signal related to the radio frequency calibration through the SPI. After reading the signal of completing the calibration, enter the third step;

[0031] Third, the main processor configures the demodulation module in the physical layer module through the SPI, such as turning on the receive clock, turning on the ADC (Analog to Digital Converter, analog to digital converter) and the like, and after the configuration is completed, enter the fourth step;

[0032] Fourth, the main processor configures the modulation module in the physical layer module through the SPI, such as configuring the modulation rate, the transmission power, the GFSK (Gauss Frequency Shift Keying, Gauss Frequency Shift Keying) modulation frequency offset and the like. After the configuration is completed, enter the fifth step;

[0033] Fifth step, the main processor switches the SPI channel of the SPI selection module to the SPI interface output by the baseband processing module, and enters the sixth step;

[0034] Sixth step, when the BLE frequency hopping, the main processor writes the PLL frequency control word to be configured into the shared SRAM, and informs the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM through AHB->system bus->AHB->baseband processing module, and enters the seventh step;

[0035] Seventh step, the main processor configures the baseband processor module according to the software program of the BLE protocol stack, configures the BLE event type, start time, timeout time, frequency hopping interval, channel mapping table and other parameters, and enters the eighth step;

[0036] Eighth step, after the baseband processing module receives the start time parameter configured by the main processor, waits for the internal counter to count to the start time, and then starts the BLE event, the physical layer module is responsible for the modulation and demodulation of the wireless signal, and the baseband processing module is responsible for the protocol analysis or generation, when the BLE frequency hopping, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance for tens of microseconds (usually 40 to 60 microseconds), and configures it to the PLL in the physical layer module through the SPI interface, since the frequency control word of the PLL is configured in advance, when the BLE chip frequency hopping, the PLL has been locked, and enters the ninth step;

[0037] Ninth step, after the baseband processing module completes the processing of the BLE event, stores the processing data into the shared SRAM, and informs the main processor that the BLE event has ended through the interrupt signal, and the main processor performs subsequent processing based on the data stored in the shared SRAM.

[0038] The application discloses a control structure suitable for a low-power Bluetooth receiving circuit, adopts double-way SPI, can conveniently configure the BLE physical layer by the main processor, and meets the demand of BLE fast frequency hopping.

[0039] Although the preferred embodiments of the application have been described, those skilled in the art can make other changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the application.

[0040] Obviously, those skilled in the art can make various modifications and variations to the application without departing from the spirit and scope of the application. Thus, if these modifications and variations of the application fall within the scope of the claims of the application and equivalent technologies thereof, the application also intends to include these modifications and variations.

Claims

1. A control method suitable for a low-power Bluetooth receiver circuit, characterized in that, The specific processing procedure is as follows: The first step is that after the BLE chip is powered on, the SPI selection module will default to selecting the APB to SPI path. At this time, the main processor will initialize and configure the physical layer module through the SPI interface of the APB to SPI path. The second step is that after the physical layer module completes the initialization configuration, the main processor continues to configure the RF calibration module in the physical layer module through the SPI interface. The RF calibration module then starts the calibration of the RF-related components. The main processor queries the status signals related to RF calibration through the SPI interface. When the calibration completion signal is read, the third step is entered. The third step is for the main processor to configure the demodulation module in the physical layer module through the SPI interface. The configuration includes enabling the receive clock and enabling the ADC. After the configuration is completed, proceed to the fourth step. The fourth step is for the main processor to configure the modulation module within the physical layer module via the SPI interface. The configuration includes setting the modulation rate, transmit power, and GFSK modulation frequency offset. After the configuration is complete, proceed to the fifth step. Fifth, the main processor switches the SPI path of the SPI selection module to the SPI interface output by the baseband processing module, and proceeds to the sixth step; Step 6: The main processor writes the PLL frequency control word that needs to be configured when BLE frequency hopping into the shared SRAM. The main processor then notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM and proceeds to step 7. Step 7: The main processor configures the baseband processor module according to the BLE protocol stack software program. The configuration includes BLE event type, start time, timeout time, frequency hopping interval and channel mapping table. After the configuration is completed, proceed to step 8. Step 8: After receiving the startup time parameters configured by the main processor, the baseband processing module enables the BLE event when the internal counter reaches the startup time. The physical layer module is responsible for the modulation and demodulation of the wireless signal, and the baseband processing module is responsible for protocol parsing or generation. When BLE frequency hopping occurs, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance and configures it into the phase-locked loop (PLL) module in the physical layer module through the SPI interface. Since the PLL frequency control word is configured in advance, the PLL is already locked when the BLE chip hops the frequency, and the process proceeds to step 9. In the ninth step, after the baseband processing module completes the processing of this BLE event, it stores the processed data in the shared SRAM and notifies the main processor via an interrupt signal that this BLE event has ended. The main processor then performs subsequent processing based on the data stored in the shared SRAM.

2. The control method for a low-power Bluetooth receiver circuit according to claim 1, characterized in that, In the sixth step, the main processor notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM. At this time, the transmission start path of the signal from the main processor to the baseband processing module is sequentially: main processor, AHB interface, system bus, AHB interface, and then sent to the baseband processing module.

3. The control method for a low-power Bluetooth receiver circuit according to claim 2, characterized in that, In the eighth step, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance by 40-60 microseconds.

4. A control system suitable for a low-power Bluetooth receiver circuit, the system performing the method as described in any one of claims 1-3, characterized in that, It includes a main processor, system bus, baseband processing module, APB interface, APB to SPI module, SPI selection module, SPI module and physical layer module; After the BLE chip is powered on, the main processor accesses the system bus through the AHB interface, and configures the initialization module, RF calibration module, demodulation module and modulation module in the physical layer module through the APB interface output by the system bus and after passing through the APB to SPI module. After configuration, the main processor will switch the SPI path in the SPI selection module from the APB to SPI path to the SPI interface output by the baseband processing module. At the same time, the main processor will write the PLL frequency control word corresponding to the subsequent BLE frequency hopping into the shared SRAM. Once the BLE protocol stack is operational, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance during frequency hopping and configures the PLL module within the physical layer module via the SPI interface.

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