QFN package structure and packaging method

Abstract

The application discloses a QFN packaging structure and a packaging method, and the packaging method comprises the following steps: providing a lead frame, the pin of the lead frame comprising a plane part and a side wall part, the pin side wall part being arranged towards the surface of the base island; a chip is arranged on the surface of the base island on the front of the lead frame; a plastic sealing part is arranged on the front of the lead frame and the chip, and the plastic sealing part covers the pin side wall part; after the plastic sealing, the connecting rib and the plastic sealing part are cut multiple times from the back of the lead frame, and a step type groove is formed on the outer side wing of the pin side wall part after the cutting; the step type groove is plated with tin to form a tin plating layer, the excess part of the plastic sealing part is cut off, and a QFN packaging structure is formed. The depth of the step type groove controls the height of the tin climbing of the pin side wall of the QFN packaging structure, the tin position on the pin side wall part is flexibly adjusted, the physical limitation of the electroplating process is not needed, the vertical covering height of the side surface solder can be accurately controlled, and effective solder climbing is formed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a QFN packaging structure and packaging method. Background Technology

[0002] In the field of QFN (Quad Flat No-lead) packaging, traditional processes use standard lead frames as the main structure. When a QFN packaged product is cut into individual pieces, the copper layer on the side of the pins is directly exposed. Since the melting point of copper (1083℃) is significantly higher than that of solder (typical SnAgCu solder is about 217℃), solder rejection often occurs on the side of the QFN packaged product pins during surface mount technology (SMT), seriously affecting soldering reliability.

[0003] To address the demand for high-reliability electronic products, the industry has proposed the Wettable Flank technology standard, requiring that the package sides possess excellent solderability. By adding solderability to the package sides, Wettable Flank technology makes solder joints easier to inspect and confirm during the soldering process, thereby improving overall soldering quality. The process flow of existing Wettable Flank technology solutions is as follows: Figure 1 As shown in the figure, 1a is a schematic diagram of the side structure of the lead frame 1. The surface of the lead frame 1 is provided with a base island 2 and a pin 3. The pin 3 has a connecting rib 102. 1b shows the process of mounting the chip 4 onto the lead frame 1 and then encapsulating it to form the encapsulated part 5. After encapsulation, a secondary cutting process is used, as detailed below. Figure 1 As shown in 1c, 1d and 1e: the first cut retains part of the connecting rib to keep the product in a whole strip shape. The exposed side of the groove after the first cut is locally electroplated with tin to form a tin plating layer 7. The final cut is completed using a narrow knife.

[0004] This process has two inherent flaws:

[0005] 1. It can only achieve limited soldering at certain positions on the side pins, and cannot form effective solder creep.

[0006] 2. Due to the physical limitations of the electroplating process, it is impossible to precisely control the vertical coverage height of the side solder.

[0007] With the increasing demands for device reliability in fields such as 5G communication and automotive electronics, existing technologies can no longer meet the requirements for higher solder airtightness in high-frequency applications, stronger mechanical bonding strength in automotive environments, and more precise solder control in the trend of miniaturized packaging.

[0008] Therefore, there is an urgent need for a new wettable flank solution that can overcome the limitations of traditional side soldering height. Summary of the Invention

[0009] To address the aforementioned issues, this invention provides a QFN package structure and packaging method. This package enables flexible adjustment of the solder position on the pin sidewalls, without being constrained by the physical limitations of the electroplating process. It can precisely control the vertical coverage height of the side solder, resulting in effective solder creep. It can meet the requirements of higher solder airtightness for high-frequency applications, stronger mechanical bonding strength for automotive environments, and more precise solder control in the trend of miniaturized packaging.

[0010] According to one aspect of the present invention, a packaging method for a QFN package structure is provided, which enables the pin sidewalls to have a high solder run-through height. The method includes the following steps:

[0011] S1. A lead frame is provided, the front of which has a base island and a plurality of pins, the pins surrounding the four sides of the base island; adjacent pins are connected by connecting ribs; each pin includes a planar portion and a sidewall portion, the sidewall portion of the pin being disposed toward the surface of the base island;

[0012] S2. A chip is provided, wherein the chip is disposed on the base island surface on the front side of the lead frame, and the chip is electrically connected to the planar portion of the pin;

[0013] S3. The molding part molds the front of the lead frame and the chip, and the molding part covers the sidewall of the pin. After molding, the connecting rib and the molding part are cut multiple times from the back of the lead frame. After cutting, a stepped groove is formed on the outer wing of the sidewall of the pin.

[0014] S4. Tin plating is performed inside the stepped groove to form a tin plating layer. Excess portion of the plastic encapsulation is removed to form a QFN package structure. The depth of the stepped groove controls the height of the tin climbing on the sidewall of the QFN package pins.

[0015] Preferably, in step S1, the planar portion and sidewall portion of a single pin are also connected by a connecting rib, with the planar portion and sidewall portion located on both sides of the connecting rib.

[0016] Preferably, the method for setting the pin sidewall towards the base island surface is as follows: stamping the connecting rib to press the sidewall towards the front of the base island, so that the sidewall, connecting rib and flat surface form an L-shaped pin.

[0017] Preferably, in step S3, the cutting method is as follows:

[0018] The first cut involves using a wide blade to cut the connecting ribs and plastic sealant at the edges, creating the first groove.

[0019] The second cut involves using a narrow blade to cut along the outer wing of the sidewall portion from inside the first groove, forming a second groove on the outer wing of the sidewall portion of the pin.

[0020] The first and second grooves form stepped grooves on the outer wing of the pin sidewall.

[0021] Preferably, the depth of the second groove is greater than half the height of the pin sidewall.

[0022] Preferably, in step S4, tin is plated on the outside of the pin within the stepped groove.

[0023] On the other hand, the present invention also discloses a QFN package structure manufactured using the above method, which includes:

[0024] A lead frame has a base island and multiple pins on its front side, with the pins surrounding the four sides of the base island; adjacent pins are connected by connecting ribs; each pin includes a planar portion and a sidewall portion, with the sidewall portion of the pin facing the surface of the base island.

[0025] The chip is disposed on the base island surface on the front side of the lead frame, and the chip is electrically connected to the planar portion of the pins;

[0026] The molding package encapsulates the front side of the lead frame and the chip, and the molding package covers the sidewalls of the leads;

[0027] The stepped structure is located on the outer wing of the pin sidewall, and the outer wing of the sidewall has a tin-plated layer.

[0028] Compared with the prior art, the beneficial effects of the present invention are:

[0029] This invention controls the solder climb height on the sidewall of the QFN package pins by adjusting the depth of the stepped groove, thus precisely controlling the vertical coverage height of the side solder and achieving effective solder climb. It breaks through the limitations of the side solder climb height in traditional package structures, enabling flexible adjustment of the solder position on the pin sidewall without being restricted by the physical limitations of the electroplating process. This meets the requirements of higher solder airtightness for high-frequency applications, stronger mechanical bonding strength for automotive environments, and more precise solder control for miniaturized packaging trends. Attached Figure Description

[0030] Figure 1 This is a process flow diagram of the existing Wettable Flank technology solution;

[0031] Figure 2 This is a schematic diagram of the strip-shaped lead frame in Embodiment 1 of the present invention;

[0032] Figure 3 This is a schematic diagram of the front structure of a single lead frame before cutting in Embodiment 1 of the present invention;

[0033] Figure 4 This is a schematic diagram of the cross-sectional structure of a single lead frame before cutting in Embodiment 1 of the present invention;

[0034] Figure 5 This is a schematic cross-sectional view of a single lead frame after cutting in Embodiment 1 of the present invention;

[0035] Figure 6 This is a schematic diagram of the QFN package structure in Embodiment 2 of the present invention;

[0036] Figure 7 This is a schematic diagram of the chip being mounted to the lead frame in Embodiment 2 of the present invention;

[0037] Figure 8 This is a schematic diagram of the encapsulated lead frame structure in Embodiment 2 of the present invention;

[0038] Figure 9 To Figure 8 A schematic diagram of the structure after the first cut;

[0039] Figure 10 To Figure 8 A schematic diagram of the structure after the second cut;

[0040] Figure 11 To Figure 10 A schematic diagram of the structure shown after tin plating;

[0041] Figure 12 For resection Figure 11 A schematic diagram of the excess plastic seal in the middle.

[0042] Labeling: 1. Lead frame, 101. Outer frame, 102. Connecting rib, 2. Base island, 3. Pin, 31. Planar part, 32. Side wall part, 320. Outer wing, 320. Chip, 4. Molded part, 5. Stepped structure, 6. Tin plating layer, 7. Stepped groove, 8. First groove, 80. Second groove, 81. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0044] Example 1

[0045] This embodiment discloses a lead frame 1 for a QFN package structure.

[0046] The fabrication method of lead frame 1 belongs to the prior art, and its molding process is mainly developed and the production process is as follows (taking mechanical template electroplating process as an example):

[0047] Frame design - Etching mold making - Raw material pre-cleaning - Press-dry film - Exposure - Development - Etching - Film removal - Press-dry film - Exposure - Development - Silver plating - Film removal - Stamping - Packaging.

[0048] In this embodiment, during the lead frame production process, the length of each pin 3 can be adjusted according to application requirements and connected by semi-etched connecting ribs. After the frame is silver-plated, a stamping process is added, and a matching stamping tool is used to bend the pins 3 perpendicular to the surface of the base island 2 according to the design. The semi-etched connecting ribs refer to the connecting ribs 102 between the flat part 31 and the side wall part 32 of the pin 3 adopting a semi-etched structure, which facilitates the implementation of the stamping and bending process.

[0049] Before cutting, multiple lead frames 1 are arranged in an array, and adjacent lead frames 1 are connected by an outer frame 101, such as... Figure 2 The structure shown is a schematic diagram of the strip-shaped lead frame 1. Figure 3 and Figure 4 This is a schematic diagram of the front and cross-sectional structure of a single lead frame 1 before cutting. The front of the lead frame 1 has a base island 2 and multiple pins 3, with the pins 3 surrounding the four sides of the base island 2; adjacent pins 3 are connected by connecting ribs 102. The surface of the base island 2 is used to mount the chip 4.

[0050] Pin 3 includes a planar portion 31 and a sidewall portion 32, with the sidewall portion 32 facing the surface of the base island 2. The length direction of the sidewall portion 32 is perpendicular to the surface of the base island 2. The method for aligning the sidewall portion 32 of pin 3 with the surface of the base island 2 is as follows: stamping is performed at the connecting rib 102 between the planar portion 31 and the sidewall portion 32, pressing the sidewall portion 32 toward the front of the base island 2, so that the sidewall portion 32, the connecting rib 102, and the planar portion 31 form an L-shaped pin 3.

[0051] In the L-shaped pin 3, the sidewall portion 32 has a relatively long length (height). After the QFN package structure is formed later, the sidewall portion 32 is located on the four sides of the QFN package structure. Therefore, the sidewall portion 32 has a relatively long length, which is also the basis for the later soldering height.

[0052] The height of the sidewall portion 32 can be customized according to different requirements of the QFN package structure, and its height should not exceed the sidewall height of the QFN package structure.

[0053] The connecting rib 102 between the flat part 31 and the side wall part 32 is partially etched. The partially etched position is located on the connecting rib 102 on the back of the lead frame 1, which facilitates stamping.

[0054] A cross-sectional schematic diagram of the cut single lead frame 1 is shown below. Figure 5 As shown. The bending of the sidewall portion 32 of pin 3 provides structural support for subsequent electroplating of the sidewall portion 32.

[0055] Example 2

[0056] Combination Figure 6 This embodiment discloses a QFN package structure that uses the lead frame 1 described in Embodiment 1.

[0057] The QFN package structure includes:

[0058] The lead frame 1 has a base island 2 and multiple pins 3 on its front side. The pins 3 surround the four sides of the base island 2. Adjacent pins 3 are connected by connecting ribs 102. The pins 3 include a flat portion 31 and a side wall portion 32. The side wall portion 32 of the pin 3 is arranged facing the surface of the base island 2.

[0059] Chip 4 is disposed on the surface of the base island 2 on the front side of the lead frame 1, and chip 4 is electrically connected to the planar portion 31 of the pin 3 via leads.

[0060] The molding package 5 encapsulates the front side of the lead frame 1 and the chip 4, and the molding package 5 covers the side wall portion 32 of the pin 3;

[0061] A stepped structure 6 is provided on the outer wing 320 of the sidewall portion 32 of the pin 3, and the outer wing 320 of the sidewall portion 32 has a tin-plated layer 7.

[0062] The stepped structure 6 allows for flexible adjustment of the tin position on the side wall 32 of pin 3, without being subject to the physical limitations of the electroplating process. It can precisely control the vertical coverage height of the side solder, forming an effective solder climb.

[0063] This embodiment also discloses a packaging method for the above-mentioned QFN package structure, which specifically includes the following steps:

[0064] S1, as in Example 1 Figure 5 The lead frame 1 shown has a base island 2 and a plurality of pins 3 on its front side, with the pins 3 surrounding the four sides of the base island 2; adjacent pins 3 are connected by connecting ribs 102; the pins 3 include a planar portion 31 and a sidewall portion 32, and the planar portion 31 and the sidewall portion 32 are also connected by connecting ribs 102.

[0065] The sidewall portion 32 of the pin 3 is oriented toward the surface of the base island 2; the sidewall portion 32, the connecting rib 102, and the planar portion 31 form an L-shaped pin 3. The length direction of the sidewall portion 32 is perpendicular to the surface of the base island 2.

[0066] The method for setting the side wall portion 32 of pin 3 toward the surface of base island 2 is as follows: stamping is performed on the connecting rib 102 between the flat portion 31 and the side wall portion 32, pressing the side wall portion 32 toward the front of base island 2, so that the side wall portion 32, the connecting rib 102, and the flat portion 31 form an L-shaped pin 3.

[0067] S2. A chip 4 is provided, which is disposed on the surface of the base island 2 on the front side of the lead frame 1. The chip 4 is electrically connected to the planar portion 31 of the pin 3 through leads, forming a configuration as shown in the figure. Figure 7 The diagram shown is a structural schematic.

[0068] S3, the molding compound 5 encapsulates the front side of the lead frame 1 and the chip 4, and the molding compound 5 covers the sidewall portion 32 of the pin 3, forming a shape as shown in the figure. Figure 8 The diagram shows the structure. After molding, the connecting rib 102 and the molding part 5 are cut multiple times from the back of the lead frame 1. After cutting, a stepped groove 8 is formed on the outer wing 320 of the side wall part 32 of the pin 3.

[0069] The specific cutting method is as follows:

[0070] In the first cut, a wide blade is used to cut the connecting rib 102 and the plastic sealing part 5 at the edge to form the first groove 80, as shown in the schematic diagram below. Figure 9 As shown; during the first cut, the connecting rib 102 between pins 3 should be cut to prevent internal short circuits in the product.

[0071] The second cut involves using a narrow blade to cut along the outer wing 320 of the sidewall portion 32 from within the first groove 80, forming a second groove 81 on the outer wing 320 of the sidewall portion 32 of the pin 3. The first groove 80 and the second groove 81 form a stepped groove 8 on the outer wing 320 of the sidewall portion 32 of the pin 3, as shown in the schematic diagram below. Figure 10 As shown.

[0072] In practice, the wide cutting edge is 300-700µm wide, and the narrow cutting edge is 200-300µm wide. The specific cutting depth is determined according to the packaging requirements. The depth of the second groove 81 is preferably greater than half the height of the sidewall 32 of the pin 3, and can be the same as the height of the sidewall 32. This height ensures the height of the subsequent tin plating layer 7 on the sidewall 32. The widths of the first groove 80 and the second groove 81 are also determined according to the packaging requirements.

[0073] S4. Tin plating is performed inside the stepped groove 8 to form a tin plating layer 7, the structural diagram of which is shown below. Figure 11 As shown.

[0074] Remove the excess portion of the plastic seal 5 to form a shape like... Figure 12 The QFN package structure shown.

[0075] In this embodiment, the height of the solder lining on the sidewall of the QFN package pin 3 can be flexibly controlled by setting the depth of the stepped groove 8, breaking through the limitation of the side solder lining height in the traditional package structure.

[0076] In specific implementation, tin can be plated on the outside of the pin 3 inside the stepped groove 8. This is because only the outer wing 320 of the side wall portion 32 of the pin 3 inside the stepped groove 8 is made of copper. During tin plating, only the copper area of ​​the outer wing 320 will react chemically with the electroplating solution and be plated with tin. The rest of the molding compound portion (stepped groove 8) will not react chemically with the electroplating solution. This is also the reason why the height of the side wall portion 32 of the pin 3 is the basis for the tin climbing height in this invention.

[0077] This invention enables flexible adjustment of the tin position on the sidewall portion 32 of pin 3, without being subject to the physical limitations of the electroplating process. It can precisely control the vertical coverage height of the side solder, forming an effective solder climb. It can meet the requirements of higher soldering airtightness for high-frequency applications, stronger mechanical bonding strength for automotive environments, and more precise solder control for miniaturized packaging trends.

[0078] The above descriptions are merely some embodiments of the present invention. It should be noted that those skilled in the art can make other modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A packaging method for a QFN package structure, characterized in that, The packaging method includes the following steps: S1. A lead frame is provided, the front of which has a base island and a plurality of pins, the pins surrounding the four sides of the base island; adjacent pins are connected by connecting ribs; each pin includes a planar portion and a sidewall portion, the sidewall portion of the pin being disposed toward the surface of the base island; The planar portion and sidewall portion of each pin are also connected by a connecting rib, with the planar portion and sidewall portion located on both sides of the connecting rib; The method for setting the pin sidewall toward the base island surface is as follows: stamping the connecting rib to press the sidewall toward the front of the base island, so that the sidewall, connecting rib and flat surface form an L-shaped pin; wherein, the connecting rib between the flat surface and the sidewall is partially etched, and the partially etched position is located on the connecting rib on the back of the lead frame. S2. A chip is provided, wherein the chip is disposed on the base island surface on the front side of the lead frame, and the chip is electrically connected to the planar portion of the pin; S3. The molding part molds the front of the lead frame and the chip, and the molding part covers the sidewall of the pin. After molding, the connecting rib and the molding part are cut multiple times from the back of the lead frame. After cutting, a stepped groove is formed on the outer wing of the sidewall of the pin. S4. Tin plating is performed inside the stepped groove to form a tin plating layer. Excess portion of the molding compound is removed to form a QFN package structure with stepped edges on all four sides. The depth of the stepped groove controls the height of the tin climbing on the sidewalls of the QFN package pins.

2. The packaging method according to claim 1, characterized in that, In step S3, the cutting method is as follows: The first cut involves using a wide blade to cut the connecting ribs and plastic sealant at the edges, creating the first groove. The second cut involves using a narrow blade to cut along the outer wing of the sidewall portion from inside the first groove, forming a second groove on the outer wing of the sidewall portion of the pin. The first and second grooves form stepped grooves on the outer wing of the pin sidewall.

3. The packaging method according to claim 2, characterized in that, The depth of the second groove is greater than half the height of the pin sidewall.

4. The packaging method according to claim 3, characterized in that, In step S4, tin is plated on the outside of the pins inside the stepped groove.

5. A QFN package structure, manufactured using the packaging method according to any one of claims 1-4, characterized in that, include: A lead frame has a base island and multiple pins on its front side, with the pins surrounding the four sides of the base island; adjacent pins are connected by connecting ribs; each pin includes a planar portion and a sidewall portion, with the sidewall portion of the pin facing the surface of the base island. The chip is disposed on the base island surface on the front side of the lead frame, and the chip is electrically connected to the planar portion of the pins; The molding package encapsulates the front side of the lead frame and the chip, and the molding package covers the sidewalls of the leads; The stepped structure is located on the outer wing of the pin sidewall, and the outer wing of the sidewall has a tin-plated layer.

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