Semiconductor devices and methods of forming stacked SIP structures with single-sided molding

Abstract

A semiconductor device has a first substrate and a plurality of first electrical components disposed over a first surface of the first substrate. The second substrate has a plurality of second electrical components. A second substrate is disposed over at least one of the first electrical components. A first encapsulant is deposited over the first substrate, the first electrical component, the second substrate, and the second electrical component. A first shielding material is disposed over the first encapsulant. A second encapsulant may be deposited over the second substrate and the second electrical component. A second shielding material may be disposed over the second encapsulant. An adhesive or a plurality of bumps may be disposed between the second substrate and at least one of the first electrical components. An epoxy material may be disposed between the second substrate and at least one of the first electrical components.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of forming a stacked SiP structure with single-sided molding. BACKGROUND

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a variety of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic operations, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, data management, networking, computing, entertainment and consumer products.

[0003] Multiple semiconductor dies and IPDs can be integrated into a system-in-a-package (SiP) module for higher density and extended electrical functionality in a small space. Within the SiP module, multiple first semiconductor dies and IPDs are disposed on a first surface of a substrate for structural support and electrical interconnection. A first encapsulant is deposited over the first semiconductor dies and IPDs on the first surface of the substrate. Multiple second semiconductor dies and IPDs are disposed on a second surface of the substrate opposite the first surface of the substrate for structural support and electrical interconnection. A second encapsulant is deposited over the second semiconductor dies and IPDs on the second surface of the substrate. The first electrical components and IPDs disposed on the first surface of the substrate and the second electrical components and IPDs disposed on the second surface of the substrate provide higher density in a small space and provide extended electrical functionality for the SiP module. However, depositing the first encapsulant over the first semiconductor dies and IPDs on the first surface of the substrate and depositing the second encapsulant over the second semiconductor dies and IPDs on the second surface of the substrate (referred to as double-sided molding (DSM)) increases the time and cost of the manufacturing process. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figures 1a-1c A semiconductor wafer is shown having multiple semiconductor dies separated by scribe lanes;

[0005] Figures 2a-2j A process of forming a stacked SiP structure with single-sided molding is shown;

[0006] Figures 3a-3g Another process of forming a stacked SiP structure with single-sided molding is shown;

[0007] Figures 4a-4d A process of forming a shielded SiP module is shown;

[0008] Figures 5a-5d A process of forming a stacked SiP structure with single-sided molding and using a Figures 4a-4d a process of a stacked SiP structure of a shielded SiP module; and

[0009] Figure 6 A printed circuit board (PCB) is shown in which different types of packages are disposed on a surface of the PCB. DETAILED DESCRIPTION

[0010] In the following description of the drawings, the application is described in one or more embodiments where identical numbers refer to identical or similar elements. While the application is described in terms of the best mode for achieving the objects of the application, it will be appreciated by those skilled in the art that the application is intended to cover any alternatives, modifications, and equivalents that can be included within the spirit and scope of the application as defined by the appended claims and their equivalents supported by the following disclosure and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural form of the word, and thus can refer to both a single semiconductor device and multiple semiconductor devices.

[0011] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming a plurality of dies on a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. The active electrical components such as transistors and diodes have a "current flow" ability. The passive electrical components such as capacitors, inductors and resistors create a relationship between voltage and current flow.

[0012] Back-end manufacturing refers to the process of cutting or singulating the finished wafer into individual semiconductor dies and packaging the semiconductor dies into a structural and protective module. To singulate the wafer, the wafer is marked and broken along non-functional areas called scribe lines or streets. The singulated semiconductor dies are then mounted onto a package substrate using die attach materials, and connected to other system components using wirebonds or flip-chip technology. The package substrate is typically an insulating material, and provides a structural and protective module for the semiconductor dies. The package substrate can be pre-coated with a layer of solder to facilitate wirebonding or flip-chip technology. The solder is reflowed during the die attach process to form an electrical and structural connection between the semiconductor die and the package substrate. The electrical connections are protected by a layer of encapsulation or other molding material.

[0013] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material used for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by non-active inter-die wafer areas or streets 106. The streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0014] Figure 1b A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog circuits or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memory, or other signal processing circuits. The semiconductor die 104 can also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0015] A conductive layer 112 is formed over the active surface 110 using a PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 operates as contact pads electrically connected to the circuitry on the active surface 110.

[0016] A conductive bump material is deposited over the conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or leadless solder. The bump material is joined to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed over under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. Interconnect structures can also use wirebonds, conductive paste, stud bumps, micro bumps, or other electrical interconnects.

[0017] In Figure 1c the semiconductor wafer 100 is singulated into individual semiconductor dies 104 through the scribe lanes 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or units (KGD / KGU) after singulation.

[0018] Figures 2a-2j A process of forming a stacked SiP structure with single-sided molding is shown; Figure 2a A cross-sectional view of an interconnect substrate or interposer 120 including one or more conductive layers 122 and one or more insulating layers 124 is shown. The conductive layers 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 122 can be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive layers 122 provide horizontal electrical interconnects across the substrate 120 as well as vertical electrical interconnects between the top surface 126 and the bottom surface 128 of the substrate 120. Portions of the conductive layers 122 can be electrically common or electrically isolated depending on the design and function of the semiconductor dies 104 and other electrical components. The insulating layers 124 include one or more layers of silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (AI2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The insulating layers 124 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layers 124 provide isolation between the conductive layers 122. There can be multiple conductive layers such as 122 separated by insulating layers 124.

[0019] In Figure 2b which multiple electrical components 130a-130e are disposed on the surface 126 of the interconnect substrate 120 and are electrically and mechanically connected to the conductive layer 122. The electrical components 130a-130e are each positioned over the substrate 120 using a pick and place operation. For example, the electrical component 130a can be a discrete electrical device or IPD, such as a diode, transistor, resistor, capacitor, and inductor, with terminals 132 disposed on the surface 126 of the interconnect substrate 120 and electrically and mechanically connected to the conductive layer 122 with solder or conductive paste 134. The electrical component 130b can be a discrete electrical device or IPD, such as a diode, transistor, resistor, capacitor, and inductor, with terminals 136 disposed on the surface 126 of the interconnect substrate 120 and electrically and mechanically connected to the conductive layer 122 with solder or conductive paste 138. The electrical component 130c can be a discrete electrical device or IPD, such as a diode, transistor, resistor, capacitor, and inductor, disposed on the surface 126 of the interconnect substrate 120 and electrically and mechanically connected to the conductive layer 122 with bumps 140. The electrical component 130d can be similar to the semiconductor die 104 from Figure 1c with the bumps 114 oriented toward the surface 126 of the substrate 120. The electrical component 130e can be a discrete electrical device or IPD, such as a diode, transistor, resistor, capacitor, and inductor, or a semiconductor die similar to the die 104. In one embodiment, the electrical component 130e is an e-bar interconnect structure having a base material 144 and a conductive via 146 formed through the base material and a bump 148 formed over the conductive via. The electrical component 130e is disposed on the surface 126 of the interconnect substrate 120 and is electrically and mechanically connected to the conductive layer 122 with a bump, solder, or conductive paste 150. Alternatively, the electrical components 130a-130e can include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs.

[0020] The electrical components 130a-130e are brought into contact with the surface 126 of the substrate 120 and into engagement with the conductive layer 122. Figure 2c The electrical components 130a-130e are shown electrically and mechanically connected to the conductive layer 122 of the substrate 120.

[0021] In Figure 2d which an adhesive 156, such as an epoxy, is deposited on the backside 108 of the electrical component 130d.

[0022] Figure 2eA cross-sectional view of an interconnect substrate or interposer 160 including one or more conductive layers 162 and one or more insulating layers 164 is shown. The conductive layers 162 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 162 can be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive layers 162 provide horizontal electrical interconnects across the interposer 160 and vertical electrical interconnects between the top surface 166 and the bottom surface 168 of the interposer 160. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layers 162 can be electrically common or electrically isolated. The insulating layers 164 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layers 164 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layers 164 provide isolation between the conductive layers 162. There can be multiple conductive layers such as 162 separated by insulating layers 164.

[0023] In Figure 2f , a pick-and-place operation is used to position the interposer 160 over the electrical components 130d-130e with the surface 168 oriented toward the electrical components. The surface 168 of the interposer 160 is brought into contact with the electrical components 130d and 130e and bonded to the adhesive layer 156. The bumps 148 are reflowed to make electrical and mechanical connections between the conductive layers 162 of the interposer 160 and the e-bar type electrical components 130e. Figure 2g An interposer 160 electrically and mechanically connected to electrical components 130d-130e is shown.

[0024] In Figure 2h , similar to Figure 2b-2c , multiple electrical components 170a-170b are disposed on the surface 166 of the interposer 160 and electrically and mechanically connected to the conductive layers 162. For example, the electrical component 170a can be made similar to the electrical component 130d from Figure 1csemiconductor die 104, where the bumps 114 are oriented toward the surface 166 of the interposer 160. The electrical components 170a can have different electrical functions than the electrical components 130d and / or the semiconductor die 104. The bumps 114 are reflowed to make electrical and mechanical connections to the conductive layer 162. The electrical components 170b can be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors, where the terminals 172 are disposed on the surface 166 of the interposer 160 and are electrically and mechanically connected to the conductive layer 162 with solder or conductive paste 174. Alternatively, the electrical components 170a-170b can include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs.

[0025] In another embodiment, the electrical components 170a-170b are disposed on the interposer 160 prior to mounting the interposer 160 to the electrical components 130d-130e.

[0026] In Figure 2i In one embodiment, the encapsulant or molding compound 178 is deposited over and around the electrical components 130a-130e, the electrical components 170a-170b, the interconnect substrate 120, and the interposer 160 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The encapsulant 178 can be a polymer composite, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant 178 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor devices from external factors and contaminants.

[0027] The electrical components 130a-130e and 170a-170b can include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included within the electrical components 130a-130e and 170a-170b provide electrical characteristics needed for high frequency applications, such as resonators, high pass filters, low pass filters, band pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 130a-130e and 170a-170b include digital circuits that switch at high frequencies, which can interfere with the operation of IPDs in the SiP module 192 or other IPDs in the vicinity.

[0028] To address the EMI, RFI, harmonic distortion, and inter-device interference, a shielding material 188 is deposited over the surfaces 180 and 182 of the encapsulant 178 and the surface 184 of the interconnect substrate 120, as shown in FIG. 2B. The shielding material 188 can be a conductive material, such as a conductive paste, a conductive film, or a conductive mesh. The shielding material 188 is electrically connected to the conductive layer 162 of the interposer 160 and the conductive layer 122 of the interconnect substrate 120. The shielding material 188 is electrically connected to the conductive layer 162 of the interposer 160 and the conductive layer 122 of the interconnect substrate 120. Figure 2jThe electromagnetic shielding material 188 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, the electromagnetic shielding material 188 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or inhibiting the effects of EMI, RFI, and other inter-device interference.

[0029] A conductive bump material is deposited over the conductive layer 122 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 190. In one embodiment, the bumps 190 are formed over UBMs having a wetting layer, barrier layer, and adhesion layer. The bumps 190 can also be compression bonded or thermocompression bonded to the conductive layer 122. The bumps 190 represent one type of interconnect structure that can be formed over the conductive layer 122. Interconnect structures can also use wirebonds, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0030] The electromagnetic shielding material 188 can also be formed around the bumps 190 over the surface 128 of the interconnect substrate 120.

[0031] As Figure 2j shown in FIG. 1, the SiP module 192 includes a plurality of electrical components 130a-130e disposed on the substrate 120 and electrical components 170a-170b disposed on the interposer 160 and stacked on the electrical components 130a-130e. The stacked electrical components and interposer are covered by a single-sided mold (i.e., encapsulant 178) and shielding material 188 to reduce or inhibit the effects of EMI, RFI, and other inter-device interference. Single-sided molding of the stacked SiP module 192 requires less manufacturing time and provides a low-cost, multi-functional system structure.

[0032] In another embodiment, the bumps 148 are removed from the electrical components 130d and 130e, as shown in FIG. 2. In this case, the conductive vias 194 can be formed through the electrical components 130d and the conductive layer 196 is formed on the backside 108 of the electrical components 130d. Alternatively, the electrical components 130d do not have conductive vias 194 or conductive layer 196, as shown in FIG. 3. Figure 2c Figure 3a Continuing, the interconnect substrate or interposer 200 is disposed over the electrical components 130d and 130e, as shown in FIG. 4. In this case, the bumps 148 are removed from the electrical component 130e. In one embodiment, the conductive vias 194 can be formed through the electrical component 130d and the conductive layer 196 is formed on the backside 108 of the electrical component 130d. Alternatively, the electrical component 130d does not have conductive vias 194 or conductive layer 196, as shown in FIG. 5. Figure 3d ​​

[0033] The interconnect substrate or interposer 200 includes one or more conductive layers 202 and one or more insulating layers 204. The conductive layers 202 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 202 can be formed using PVD, CVD, electrolytic plating, chemical plating processes, or other suitable metal deposition processes. The conductive layers 202 provide horizontal electrical interconnects across the interposer 200 and vertical electrical interconnects between the top surface 206 and the bottom surface 208 of the interposer 200. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layers 202 can be electrically common or electrically isolated. The insulating layers 204 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 204 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layers 204 provide isolation between the conductive layers 202. There can be multiple conductive layers such as 202 separated by insulating layers 204. Similar to the bumps 190, bumps 210 are formed on the surface 208 on the conductive layers 202.

[0034] A pick and place operation is used to position the interposer 200 over the electrical components 130d-130e with the surface 208 oriented toward the electrical components. The surface 208 of the interposer 200 is brought into contact with the electrical components 130d and 130e and bonded through the reflow of the bumps 210 to make electrical and mechanical connections with the conductive layers 196 of the electrical component 130d and the conductive vias 146 of the e-bar type electrical component 130e. In the case of the electrical component 130d not having conductive vias 194 and conductive layers 196, the bumps 210 that contact the back surface 108 of the electrical component 130d are dummy bumps that provide structural support for the interposer 200. Figure 3b The interposer 200 is shown electrically and mechanically connected to the electrical components 130d-130e.

[0035] Figure 3c More details from the block 212 of Figure 3b are shown. An epoxy material 214 is applied to the corners of the interposer 200 to hold the interposer in place. Figure 3c The case of the electrical component 130d with conductive vias 194 and conductive layers 196 is shown, Figure 3d Another embodiment from the block 212 of Figure 3b is shown. An epoxy material 216 is applied to the surface 108 of the electrical component 130d to hold the interposer 200 in place. Figure 3d The case of the electrical component 130d without conductive vias 194 and conductive layers 196 is shown. In Figure 3d In some embodiments, the bumps 210 over the electrical components 130d are dummy bumps to provide structural support for the interposer 200.

[0036] In some embodiments, the electrical components 130a-130e are semiconductor dies, such as the semiconductor die 104 from FIG. 1. Figure 3e In some embodiments, the electrical components 220a-220b are similar to the electrical components 130a-130e. Figure 2b-2c In some embodiments, the electrical components 220a-220b are disposed on the surface 206 of the interposer 200 and are electrically and mechanically connected to the conductive layer 202. For example, the electrical component 220a can be made similar to the semiconductor die 104 from FIG. 1, with the bumps 114 oriented toward the surface 206 of the interposer 200. The electrical component 220a can have a different electrical function than the electrical components 130d and / or the semiconductor die 104. The bumps 114 are reflowed to make electrical and mechanical connections to the conductive layer 202. The electrical component 220b can be a discrete electrical device or IPD, such as a diode, transistor, resistor, capacitor, and inductor, with terminals 222 disposed on the surface 206 of the interposer 200 and electrically and mechanically connected to the conductive layer 202 with solder or conductive paste 224. Alternatively, the electrical components 220a-220b can include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs. Figure 1c In another embodiment, the electrical components 220a-220b are disposed on the interposer 200 prior to mounting the interposer 200 to the electrical components 130d-130e.

[0037] In some embodiments, the electrical components 130a-130e are semiconductor dies, such as the semiconductor die 104 from FIG. 1.

[0038] In some embodiments, the electrical components 130a-130e are semiconductor dies, such as the semiconductor die 104 from FIG. 1. Figure 3f In some embodiments, the encapsulant or molding compound 228 is deposited over and around the electrical components 130a-130e, the electrical components 220a-220b, the interconnect substrate 120, and the interposer 200 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The encapsulant 228 can be a polymer composite, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant 228 is not electrically conductive, provides structural support, and environmentally protects the semiconductor devices from external factors and contaminants.

[0039] The electrical components 130a-130e and 220a-220b can contain IPD that is susceptible to or generates EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPD contained within the electrical components 130a-130e and 220a-220b provide electrical characteristics required for high frequency applications, such as resonators, high pass filters, low pass filters, band pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 130a-130e and 220a-220b contain digital circuits that operate at high frequencies that can interfere with the operation of the IPD in the SiP module 242 or other IPD in its vicinity.

[0040] To address the EMI, RFI, harmonic distortion, and inter-device interference, a shielding material 238 is deposited over the surfaces 230 and 232 of the encapsulant 228 and the surface 234 of the interconnect substrate 120, as shown in FIG. 2B. The electromagnetic shielding material 238 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, the electromagnetic shielding material 238 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon iron steel, foil, conductive resin, carbon black, aluminum flake, and other metals and composites that are capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Figure 3g

[0041] A conductive bump material is deposited over the conductive layer 122 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or leadless solder. The bump material is joined to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 240. In one embodiment, the bumps 240 are formed over a UBM having a wetting layer, a barrier layer, and an adhesion layer. The bumps 240 can also be compression bonded or thermocompression bonded to the conductive layer 122. The bumps 240 represent one type of interconnect structure that can be formed over the conductive layer 122. Interconnect structures can also use wirebonds, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0042] As shown in FIG. 2C, the SiP module 242 is attached to the interconnect substrate 120 using the bumps 240. The bumps 240 are formed over the conductive layer 122 and are joined to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bumps 240 are reflowed by heating the material above its melting point to form balls or bumps 240. In one embodiment, the bumps 240 are formed over a UBM having a wetting layer, a barrier layer, and an adhesion layer. The bumps 240 can also be compression bonded or thermocompression bonded to the conductive layer 122. The bumps 240 represent one type of interconnect structure that can be formed over the conductive layer 122. Interconnect structures can also use wirebonds, conductive paste, stud bumps, microbumps, or other electrical interconnects. Figure 3g ​As shown in FIG. 2, SiP module 242 includes a plurality of electrical components 130a-130e disposed on substrate 120 and electrical components 220a-220b disposed on interposer 200 and stacked on electrical components 130a-130e. The stacked electrical components and interposer are covered by a single-sided mold (i.e., encapsulant 228) and shielding material 238 to reduce or inhibit the effects of EMI, RFI, and other inter-device interference. Single-sided molding of stacked SiP module 242 requires less manufacturing time and provides a low-cost, multi-functional system architecture.

[0043] In another embodiment, Figure 4a A cross-sectional view of an interconnect substrate or interposer 250 including one or more conductive layers 252 and one or more insulating layers 254 is shown. Conductive layers 252 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Conductive layers 252 can be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layers 252 provide horizontal electrical interconnects across interposer 250 and vertical electrical interconnects between top surface 256 and bottom surface 258 of interposer 250. Depending on the design and functionality of semiconductor die 104 and other electrical components, portions of conductive layers 252 can be electrically common or electrically isolated. Insulating layers 254 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Insulating layers 254 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layers 254 provide isolation between conductive layers 252. There can be multiple conductive layers such as 252 separated by insulating layers 254.

[0044] In Figure 4b , similar to Figure 2b-2c , a plurality of electrical components 260a-260b are disposed on surface 256 of interposer 250 and electrically and mechanically connected to conductive layers 252. For example, electrical component 260a can be made similar to electrical component 130a from Figure 1csemiconductor die 104, where the bumps 114 are oriented toward the surface 256 of the interposer 250. The electrical components 260a can have different electrical functions than the electrical components 130d and / or the semiconductor die 104. The bumps 114 are reflowed to make electrical and mechanical connections to the conductive layer 252. The electrical components 260b can be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors, where the terminals 262 are disposed on the surface 256 of the interposer 250 and are electrically and mechanically connected to the conductive layer 252 with solder or conductive paste 264. Alternatively, the electrical components 260a-260b can include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, interconnect structures, or IPDs.

[0045] In Figure 4c , a sealant or molding compound 268 is deposited over and around the electrical components 260a-260b and the interposer 250 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 268 can be a polymer composite, such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The sealant 268 is not electrically conductive, provides structural support, and environmentally protects the semiconductor devices from external factors and contaminants.

[0046] The electrical components 260a-260b can contain IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs contained within the electrical components 260a-260b provide electrical characteristics needed for high frequency applications, such as resonators, high pass filters, low pass filters, band pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 260a-260b contain digital circuits that switch at high frequencies, which can interfere with the operation of IPDs in the SiP module 288 or other IPDs in its vicinity.

[0047] To address the EMI, RFI, harmonic distortion, and inter-device interference, a shielding material 278 is deposited over the surfaces 270 and 272 of the sealant 268 and the surface 274 of the interposer 250, as shown in Figure 4d The electromagnetic shielding material 278 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. Alternatively, the electromagnetic shielding material 278 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites that are capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference.

[0048] A conductive bump material is deposited over the conductive layer 252 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is joined to the conductive layer 252 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 280. In one embodiment, the bumps 280 are formed over a UBM having a wetting layer, barrier layer, and adhesion layer. The bumps 280 can also be compression bonded or thermocompression bonded to the conductive layer 252. The bumps 280 represent one type of interconnect structure that can be formed over the conductive layer 252. Interconnect structures can also use wirebonds, conductive paste, columnar bumps, microbumps, or other electrical interconnects.

[0049] An electromagnetic shielding material 278 can also be formed over the surface 258 of the interposer 250 around the bumps 280. Figure 4d The assembly shown in

[0050] From Figure 2c Continuing, a pick and place operation is used to position the SiP module 288 over the electrical components 130d-130e with the surface 258 oriented toward the electrical components as shown in Figure 5a In this case, the bumps 148 are removed from the electrical component 130e. In one embodiment, a conductive via 284 can be formed through the electrical component 130d and a conductive layer 286 is formed on the backside 108 of the electrical component 130d. Alternatively, similar to Figure 3d , the electrical component 130d does not have a conductive via 284 or conductive layer 286.

[0051] The surface 258 of the interposer 250 is brought into contact with the electrical components 130d and 130e and bonded by reflowing the bumps 280 for electrical and mechanical connection with the conductive layer 286 of the electrical component 130d and the conductive via 146 of the electrical component 130e. In the case where the electrical component 130d does not have a conductive via 284 or conductive layer 286, the bumps 280 that contact the backside 108 of the electrical component 130d are dummy bumps that provide structural support for the SiP module 288. Figure 5b The SiP module 288 is shown electrically and mechanically connected to the electrical components 130d-130e.

[0052] In Figure 5cIn an embodiment, the encapsulant or molding compound 290 is deposited over and around the electrical components 130a-130e, the interconnect substrate 120, and the SiP module 288 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The encapsulant 290 can be a polymer composite, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant 290 is not electrically conductive, provides structural support, and environmentally protects the semiconductor devices from external factors and contaminants.

[0053] The electrical components 130a-130e can contain IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, IPDs contained within the electrical components 130a-130e provide electrical characteristics required for high frequency applications, such as resonators, high pass filters, low pass filters, band pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 130a-130e contain digital circuits that operate as high frequency switches, which can interfere with the operation of IPDs in the SiP module 304 or other IPDs in the vicinity.

[0054] To address EMI, RFI, harmonic distortion, and inter-device interference, a shielding material 300 is deposited over the surfaces 292 and 294 of the encapsulant 290 and the surface 296 of the interconnect substrate 120, as shown in FIG. 3B. The electromagnetic shielding material 300 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Alternatively, the electromagnetic shielding material 300 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon iron steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The shielding material 300 further reduces or suppresses the effects of EMI, RFI, and other inter-device interference on the SiP module 288. Figure 5d

[0055] ​A conductive bump material is deposited over the conductive layer 122 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or leadless solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 302. In one embodiment, the bumps 302 are formed over UBMs having wetting, barrier, and adhesion layers. The bumps 302 can also be compression bonded or thermocompression bonded to the conductive layer 122. The bumps 302 represent one type of interconnect structure that can be formed over the conductive layer 122. Interconnect structures can also use wirebonds, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0056] As shown in FIG. 3, the SiP module 304 includes a plurality of electrical components 130a-130e disposed on the substrate 120 and the SiP module 288, where the electrical components 260a-260b are disposed on the interposer 250 and stacked on the electrical components 130a-130e. The stacked electrical components and interposer are covered by a single-sided mold (i.e., encapsulant 290) and a shielding material 300 to reduce or inhibit the effects of EMI, RFI, and other inter-device interference. The single-sided mold of the stacked SiP module 304 requires less manufacturing time and provides a low-cost, multi-functional system structure. Figure 5d

[0057] Figure 6 An electrical device 400 is shown having a chip carrier substrate or PCB 402, where a plurality of semiconductor packages are disposed on a surface of the PCB 402, including the SiP modules 192, 242, and 304. Depending on the application, the electrical device 400 can have one type of semiconductor package, or multiple types of semiconductor packages.

[0058] The electrical device 400 can be a stand-alone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electrical device 400 can be a subcomponent of a larger system. For example, the electrical device 400 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electrical device. Alternatively, the electrical device 400 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for products to be market accepted. Distances between semiconductor devices can be reduced to achieve higher densities.

[0059] In Figure 6 ​In particular, the PCB 402 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on or within the surface of the PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 404 provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces 404 also provide power and ground connections to each semiconductor package.

[0060] In some embodiments, the semiconductor device has two levels of packaging. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device can have a first level of packaging in which the die is mechanically and electrically disposed directly on the PCB. For illustrative purposes, several types of first level packaging are shown on the PCB 402, including wire bond packages 406 and flip chip 408. In addition, several types of second level packaging are shown disposed on the PCB 402, including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424, and wafer level chip scale package (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Any combination of semiconductor packages configured with any combination of first and second level packaging styles and other electrical components can be connected to the PCB 402 depending on system requirements. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electrical devices and systems. Because the semiconductor packages include complex functionality, less expensive components and streamlined manufacturing processes can be used to manufacture the electrical devices. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs to the consumer.

[0061] While one or more embodiments of the application have been illustrated and described, as noted above, one skilled in the art will readily devise numerous other variations of these embodiments that, without departing from the scope of the application as set forth in the appended claims.

Claims

1. A semiconductor device comprising: a first substrate; a plurality of first electrical components disposed above a first surface of the first substrate; a second substrate; a plurality of second electrical components disposed above the second substrate, wherein the second substrate is disposed above at least one of the first electrical components; a first encapsulant deposited above the first substrate, the first electrical components, the second substrate, and the second electrical components; and a first shielding material disposed above the first encapsulant.

2. The semiconductor device of claim 1, further comprising: a second encapsulant deposited above the second substrate and the second electrical components; and a second shielding material disposed above the second encapsulant.

3. The semiconductor device of claim 1, further comprising an adhesive disposed between the second substrate and at least one of the first electrical components.

4. The semiconductor device of claim 1, further comprising a plurality of bumps disposed between the second substrate and at least one of the first electrical components.

5. The semiconductor device of claim 1, further comprising an epoxy material disposed between the second substrate and at least one of the first electrical components.

6. A semiconductor device comprising: a first substrate; a first electrical component disposed above a first surface of the first substrate; a second substrate; a second electrical component disposed above the second substrate, wherein the second substrate is disposed above the first electrical component; and a first encapsulant deposited above the first substrate, the first electrical component, the second substrate, and the second electrical component.

7. The semiconductor device of claim 6, further comprising a shielding material disposed above the first encapsulant.

8. The semiconductor device of claim 6, further comprising: a second encapsulant deposited above the second substrate and the second electrical component; and a shielding material disposed above the second encapsulant.

9. The semiconductor device of claim 6, further comprising an adhesive disposed between the second substrate and the first electrical component.

10. The semiconductor device of claim 6, further comprising a plurality of bumps disposed between the second substrate and the first electrical component.

11. A method of manufacturing a semiconductor device, comprising: providing a first substrate; disposing a first electrical component above a first surface of the first substrate; providing a second substrate; disposing a second electrical component above the second substrate, wherein the second substrate is disposed above the first electrical component; and depositing a first encapsulant above the first substrate, the first electrical component, the second substrate, and the second electrical component.

12. The method of claim 11, further comprising disposing a shielding material above the first encapsulant.

13. The method of claim 11, further comprising: depositing a second encapsulant above the second substrate and the second electrical component; and disposing a shielding material above the second encapsulant.

14. The method of claim 11, further comprising disposing an adhesive between the second substrate and the first electrical component.

15. The method of claim 11, further comprising disposing a plurality of bumps between the second substrate and the first electrical component. ​ ​ ​ ​ ​ ​

Images