Electronic chip and method

Abstract

The embodiment of the invention relates to an electronic chip and a method. The present specification relates to an electronic chip bounded by an edge and comprising a semiconductor layer extending along a main plane, an interconnect structure over the semiconductor layer, and a seal ring arranged in the interconnect structure between the edge of the electronic chip and an electronic circuit region of the electronic chip. The sealing ring includes a plurality of cavities coupled together to form at least one continuous annular cavity around the electronic circuit region, and / or a plurality of conductive regions coupled together to form at least one conductive annular wall around the electronic circuit region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to French Application No. 24 04017, filed on April 18, 2024, which is hereby incorporated by reference herein. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic chips or integrated circuits and associated methods, in particular electronic chips comprising a sealing ring and associated methods. BACKGROUND

[0004] In the industry, most electronic devices are manufactured in series. Typically, multiple copies of an electronic device are manufactured simultaneously inside and on top of the same semiconductor substrate, e.g. the same semiconductor wafer. In particular, multiple electronic chips are typically manufactured inside and on top of the same semiconductor substrate, e.g. the same semiconductor wafer. The electronic chips can then be separated or diced, so that they can be used, for example, individually or in a more complete electronic device. This dicing is typically performed by cutting.

[0005] During such dicing, e.g. during cutting of the semiconductor wafer, cracks can appear on the edges of the electronic chips. Such cracks can cause malfunctions of the electronic circuits of the electronic chips.

[0006] Moreover, even if no cracks appear during manufacturing, certain cracks can appear during the lifetime of the chip, in particular on the edges of the chip, for example due to changes in temperature of the electronic chip.

[0007] To protect the electronic chips, in particular during manufacturing, dicing or even during their lifetime, the electronic chips can comprise a sealing ring on their periphery. The purpose of the sealing ring is to prevent cracks from propagating from the edges to the electronic circuit area or circuit area of the electronic chip. However, the sealing ring does not always prevent the formation and propagation of cracks in the electronic chip.

[0008] It would be desirable to be able to at least partially improve the electronic chips, in particular the protection of the electronic chips. SUMMARY

[0009] There is a need for an electronic chip that is better protected, in particular from cracks.

[0010] It would be advantageous to be able to perform a method of manufacturing such an electronic chip with conventional electronic chip manufacturing processes.

[0011] One embodiment overcomes all or part of the drawbacks of known electronic chips.

[0012] One embodiment provides a chip bounded by an edge, the electronic chip comprising: a semiconductor layer extending along a main plane; an interconnect structure located above the semiconductor layer; a sealing ring arranged in the interconnect structure between the edge of the electronic chip and an electronic circuitry region of the electronic chip, the sealing ring comprising: a plurality of cavities coupled together to form at least one continuous annular cavity around the electronic circuitry region; and / or a plurality of electrically conductive regions coupled together to form at least one electrically conductive annular wall around the electronic circuitry region.

[0013] The electronic circuitry region comprises electronic circuitry formed inside and on top of the semiconductor layer.

[0014] According to one embodiment, the interconnect structure comprises: a plurality of metallization levels, each metallization level comprising electrically conductive layers, the electrically conductive layers of two successive metallization levels being coupled together by electrically conductive vias and / or electrically conductive strips of the interconnect structure; and insulating layers, the electrically conductive layers, and the electrically conductive vias and / or electrically conductive strips being embedded in the insulating layers; the interconnect structure being coupled to the semiconductor layer, e.g. by another electrically conductive via and / or by an electrical contact.

[0015] According to one embodiment, each metallization level of the interconnect structure comprises electrically conductive elements of the electrically conductive layers, the electrically conductive elements being insulated from each other by insulating elements of the insulating layers.

[0016] According to one embodiment, the cavities and / or the electrically conductive regions extend at least as far as a first metallization level of the interconnect structure.

[0017] According to one embodiment, the cavities and / or the electrically conductive regions extend at least as far as an interface level between an electrically conductive via and an electrically conductive layer of two successive metallization levels of the interconnect structure, e.g. as far as an interface level between an electrically conductive via and electrically conductive layers of a first and a second metallization level of the interconnect structure.

[0018] According to one embodiment, the cavities and / or the electrically conductive regions extend as far as the semiconductor layer.

[0019] According to one embodiment, the cavities and / or the electrically conductive regions end at a non-zero distance from the semiconductor layer.

[0020] According to one embodiment, the electrically conductive regions are metallic regions, e.g. comprising tungsten, or made mainly of tungsten.

[0021] According to an embodiment, the seal ring comprises a seal element comprising electrically conductive annular plates in each metallization level of the interconnect structure, two electrically conductive annular plates of two successive metallization levels being coupled together in a direction perpendicular to the main plane by an electrically conductive annular strip.

[0022] According to an embodiment, the at least one continuous annular cavity comprises a first continuous annular cavity between the electronic circuit area and the seal element and / or a second continuous annular cavity between the seal element and the edge of the electronic die.

[0023] According to an embodiment, the at least one electrically conductive annular wall comprises a first electrically conductive annular wall between the electronic circuit area and the seal element and / or a second electrically conductive annular wall between the seal element and the edge of the electronic die.

[0024] According to an embodiment, the electronic die further comprises, in the electronic circuit area, other cavities coupled together and / or other electrically conductive areas coupled together between two adjacent electrically conductive elements of the interconnect structure.

[0025] An embodiment provides a method of manufacturing an electronic die, the method comprising: providing a structure comprising a semiconductor layer and a first metallization level of a future interconnect structure over the semiconductor layer, the structure comprising an electronic circuit area comprising an electronic circuit formed inside and on top of the semiconductor layer, and a seal ring area surrounding the electronic circuit area, and the first metallization level comprising electrically conductive elements of an electrically conductive layer insulated from each other by insulating elements of a first insulating layer; forming a first port in the seal ring area through the first insulating layer between two adjacent electrically conductive elements among the electrically conductive elements; widening the first port by etching to form an open cavity in the seal ring area coupled together around the electronic circuit area; forming a second insulating layer over the open cavity and the first insulating layer to close the open cavity, forming a cavity coupled together around the electronic circuit area, the cavity coupled together forming at least one continuous annular cavity around the electronic circuit area.

[0026] According to an embodiment, the method comprises, before forming the first port, depositing a protective layer over the first insulating layer and the electrically conductive elements, followed by forming an opening by etching in the protective layer, the first port being formed in alignment with the opening.

[0027] According to an embodiment, the method further comprises: forming at least two second ports by etching in the second insulating layer up to at least two cavities of the cavity in the seal ring area; and filling the second ports with an electrically conductive material, for example a metallic material, the filling of the second ports being performed to fill the cavity, form electrically conductive areas coupled together, and thus form at least one electrically conductive annular wall around the electronic circuit area.

[0028] According to an embodiment, the filling of the second ports also forms first electrically conductive vias coupled to the electrically conductive annular wall.

[0029] According to an embodiment, the method further comprises forming third ports by etching in the second insulating layer, each third port extending all the way to one of the electrically conductive elements, and filling the third ports with an electrically conductive material, e.g. a metallic material, forming second electrically conductive vias coupled to the electrically conductive elements.

[0030] According to an embodiment, the forming of the third ports is performed simultaneously with the forming of the second ports, and / or the filling of the third ports is performed simultaneously with the filling of the second ports.

[0031] According to an embodiment, the method further comprises forming other cavities and / or other electrically conductive areas coupled together in the electronic circuit area between two adjacent electrically conductive elements of the interconnect structure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The above features and advantages, and other features and advantages, will be described in detail in the remainder of the specification in relation to specific embodiments of the application given by way of example only and with reference to the following figures wherein:

[0033] Figure 1A is a simplified partial top view illustrating an example of an electronic chip;

[0034] Figure 1B is a simplified partial cross-sectional view illustrating an example of an embodiment of the electronic chip of Figure 1A

[0035] Figure 1C is another simplified partial cross-sectional view of the electronic chip of Figure 1B

[0036] Figure 2A is a simplified partial top view illustrating an example of an electronic chip according to an embodiment;

[0037] Figure 2B is a simplified partial cross-sectional view illustrating an example of an embodiment of the electronic chip of Figure 2A

[0038] Figure 2C is another simplified partial cross-sectional view of the electronic chip of Figure 2B

[0039] Figure 3A is a simplified partial top view illustrating an example of an electronic chip according to another embodiment;

[0040] Figure 3B is a simplified partial cross-sectional view illustrating an example of an embodiment of the electronic chip of Figure 3A ​​​​A simplified partial cross-sectional view of an example of an embodiment of an electronic chip;

[0041] Figure 3C yes Figure 3B Another simplified partial cross-sectional view of an electronic chip;

[0042] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G and Figure 4H is a cross-sectional view schematically and partially showing a structure obtained at the end of the steps of an example of a method for manufacturing an electronic chip according to an embodiment; and

[0043] Figure 5A and Figure 5B is schematically and partially shown in Figures 4A to 4H Cross-sectional view of the structure obtained at the end of the steps of a variant of the manufacturing method. DETAILED DESCRIPTION

[0044] Similar features are designated by similar reference numerals in the various figures. Specifically, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0045] For clarity, only those steps and elements that are helpful for understanding the described embodiments have been shown and described in detail. In particular, not all manufacturing steps and details of an electronic chip are described, as they can be formed using conventional electronic chip manufacturing methods. In particular, the electronic circuits of the electronic chip are not shown, as the embodiments are compatible with different electronic circuits in the electronic chip. In addition, not all manufacturing steps and details of the interconnect structure are described, as they can be formed using conventional interconnect structure manufacturing methods.

[0046] Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0047] In the following description, when absolute position qualifiers such as "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as "top", "bottom", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc. are mentioned, unless otherwise specified, they refer to the orientation of the figure.

[0048] The expressions "about", "approximately", "substantially" and "around" mean plus or minus 10% or 10°, preferably plus or minus 5% or 5°, unless otherwise stated.

[0049] In the following description, the terms "insulated" and "conductive" mean electrically insulated and electrically conductive, respectively, unless otherwise stated.

[0050] In the following description, when referring to a chip, it is meant an electronic chip, when referring to a via, it is meant a conductive via, and when referring to a substrate, it is meant a semiconductor substrate, unless otherwise stated.

[0051] In the following description of Figures 1A to 3C , an electronic chip that has been singulated is shown. However, in practice, the entire following description of the chip also applies when the chip has not yet been singulated and still forms part of, for example, a semiconductor wafer comprising a plurality of chips. In particular, in the case where the chip still forms part of a semiconductor wafer, the chip edge corresponds to the position of the chip edge after the singulation step. By edge, it is meant all edges or peripheral extremities of the chip.

[0052] Figure 1A is a simplified partial top view showing an example of an electronic chip 100. Figure 1B is a simplified partial cross-sectional view showing an example of an embodiment of the electronic chip 100 of Figure 1A . Figure 1C is another simplified partial cross-sectional view of the electronic chip of Figure 1B . Figure 1B The cross-sectional view of Figure 1A is obtained along the cross-section A-A shown in Figure 1C . Figure 1B The cross-sectional view of is obtained along the cross-section B-B shown in

[0053] . The chip 100 comprises a semiconductor layer 101, for example corresponding to a semiconductor substrate, for example made of silicon, or to a substrate of the silicon-on-insulator or SOI type. The electronic circuit of the chip 100 is arranged inside and / or on top of the semiconductor layer 101. The electronic circuit of the chip 100 is not shown in Figure 1A , 1B and 1C, but is all arranged in an electronic circuit region 105 or circuit region of the chip 100, delimited by a circumference 105L. In other words, the circuit region 105 comprises all the electronic circuit of the chip 100. The circuit region 105 of the chip 100 is, for example, a central region of the chip 100, as shown in the view of Figure 1A .

[0054] The chip 100 also comprises an interconnection structure 102 above the semiconductor layer 101, for example in contact with the semiconductor layer 101. This interconnection structure 102 is also denoted by the expression "back-end-of-line interconnection structure" or "BEOL" interconnection structure for brevity. The interconnection structure 102 comprises a plurality of metallization levels. Six metallization levels M1, M2, M3, M4, M5, M6 have been represented in the example, but this is not limiting as the number of metallization levels can vary. Figure 1B

[0055] Each metallization level comprises at least one portion 103C of electrically conductive layer 103, for example a metal layer, each portion 103C forming an electrically conductive element in the form of an electrically conductive track or wire. The electrically conductive tracks 103C of the different levels of the interconnection structure 102 are electrically coupled to each other by electrically conductive vias 106, for example metal vias, and / or are electrically coupled to the connection pads 104, and / or are electrically coupled to the electronic circuits of the chip 100. The electrically conductive tracks 103C of the various levels of the interconnection structure 102 are preferably located in the circuit region 105. Thus, the interconnection structure 102 is able to couple the electronic circuits of the chip 100 to each other and / or to couple the electronic circuits of the chip 100 to the connection pads 104. The connection pads 104, which can be simply referred to as "pads", are considered to form part of the interconnection structure 102. In the example, the pads 104 are arranged in an upper metallization level of the interconnection structure 102, this upper metallization level corresponding to the metallization level M6. In other words, the pads 104 are arranged on an upper surface 102A (first surface) of the interconnection structure 102, the lower surface 102B (second surface) of the interconnection structure, opposite the upper surface 102A, being in contact with the semiconductor layer 101. Figure 1B

[0056] The pads 104 are distributed in a substantially annular manner (here a square ring) in the circuit region 105 of the chip 100, more precisely in a region of the interconnection structure 102 contained in the circuit region 105 of the chip 100.

[0057] The pads 104 are configured to be in contact with electrically conductive elements located outside the chip 100, so that the chip 100 can exchange electrical signals with the outside. For example, each pad 104 is in direct contact with an electrically conductive track 103C of the upper metallization level M6, i.e. the metallization level farthest from the semiconductor layer 101. The interconnection structure 102 also comprises insulating layers, all of which are located between the metallization levels M1 to M6. Figure 1B Figure 1C ​​​Each insulating layer separates two successive metallization levels and can also be between portions of each conductive layer 103 at the same metallization level, the conductive layers 103 and vias 106 being embedded in the insulating layer 111. The entire insulating layer can be designated as an insulating layer. The insulating layer can be made of an oxide, for example silicon oxide, or of a high-k type dielectric material, i.e. a material having a dielectric constant K higher than that of silicon dioxide.

[0058] The chip 100 comprises a sealing region or sealing ring 107 at the periphery of the chip 100, i.e. between the circuit region 105 and the edge 110 of the chip 100. The sealing ring 107 thus surrounds the circuit region 105 of the chip 100. The sealing ring 107 is annular in a top view. The sealing ring 107 is arranged in the interconnect structure 102, at the periphery of the chip 100. The sealing ring 107 thus forms part of the interconnect structure 102, although it is not used to connect the electronic circuits of the chip 100 together and / or to the pads 104. Preferably, the chip 100 does not comprise electronic circuits in the sealing ring 107. In other words, the circuit region 105 of the chip 100 is laterally delimited in the interconnect structure 102 by the sealing ring 107.

[0059] A target function of the sealing ring 107 is to avoid the propagation of cracks from the edge 110 of the chip 100 towards the circuit region 105 of the chip 100.

[0060] Another target function of the sealing ring 107 can be to stop the propagation of moisture from the outside of the chip 100 and thus from the edge 110 of the chip 100 towards the electronic circuits of the circuit region 105 of the chip 100.

[0061] To perform one or more of these functions, the sealing ring 107 can comprise one or more sealing elements 108, each having an annular shape in a top view. One sealing element has already been shown in Figure 1A 、 Figure 1B and Figure 1C , although there can be multiple sealing elements, as shown below. When there are multiple sealing elements, they can be substantially concentric. One sealing element can be adapted to stop the propagation of cracks, another sealing element can be adapted to block the entry of moisture, and / or a sealing element can be adapted to perform both functions of stopping the propagation of cracks and blocking the entry of moisture. Each sealing element extends in height from the semiconductor layer 101 across all or part of the metallization levels M1-M6 of the interconnect structure 102, for example across one or more lower metallization levels of the interconnect structure 102. However, for moisture protection, it is preferable that the sealing element 108 extends all the way to the upper metallization level M6.

[0062] The shown sealing element 108 forms a closed loop around the circuit area 105 of the chip 100, or, in other words, the sealing element 108 completely encloses the circuit area 105 of the chip 100.

[0063] In Figure 1B In the shown embodiment, the sealing element 108 forms an annular wall comprising further portions 103A of the electrically conductive layers 103 of the interconnect structure 102. More specifically, the sealing element 108 comprises portions 103A of the electrically conductive layers 103 of each metallization level M1-M6 of the interconnect structure 102. Each portion 103A of the electrically conductive layers 103 forms an electrically conductive annular plate at each metallization level. For example, each electrically conductive annular plate 103A extends in a plane substantially parallel to the semiconductor layer 101. Successive electrically conductive annular plates 103A of the sealing element 108 are coupled together by one or more electrically conductive annular strips 112, which continuously extend between two successive electrically conductive annular plates 103A. In other words, the electrically conductive annular strips 112 connect two successive electrically conductive annular plates 103A in a Z-direction perpendicular to the XY-plane of the semiconductor layer 101.

[0064] As Figure 1B shown, successive electrically conductive annular plates 103A of the sealing element 108 can also be coupled together by electrically conductive vias 106 of the interconnect structure 102, enabling for example an increased mechanical resistance of the sealing element 108 to the propagation of cracks. The vias 106 can be cylindrical, as Figure 1C shown. As a variant, the vias can be elongated in the form of a band, or even form electrically conductive annular strips 112. The vias 106 and the electrically conductive annular strips 112 can be formed during the same manufacturing step.

[0065] The sealing element 108 can form a wall that prevents the propagation of humidity towards the circuit area 105 of the chip 100.

[0066] As Figure 1B shown, the sealing ring 108 can comprise dummy pads 104A, which are formed for example simultaneously with the pads 104. The dummy pads 104A are located on the electrically conductive annular plates 103A at the upper metallization level M6 of the interconnect structure 102. The dummy pads 104A can be arranged substantially in a ring, here it forms a square ring. There can be multiple dummy pads. The annular arrangement and the presence of one or more dummy pads are not mandatory.

[0067] For detecting cracks in the chip 100, the sealing ring 107 can comprise a crack sensor 116 or crack detector. The crack sensor 116 is arranged in the interconnect structure 102. In other words, the interconnect structure 102 comprises the crack sensor 116. As Figure 1A , Figure 1B andFigure 1C As shown, the crack sensor 116 can be disposed in a region of the interconnect structure 102 between the edge 110 of the chip 100 and the sealing element 108, which region does not include other sealing elements. Thus, if a crack occurs on the edge 110 of the chip 100 and propagates toward the circuit region 105, the crack can be detected by the crack sensor 116 before the sealing element 108. Other configurations are contemplated, as described below.

[0068] The crack sensor 116 corresponds to an electrically conductive structure, preferably an open loop, that forms an electrically conductive path. By testing the electrical conductivity between a first terminal or node 118 of the sensor 116 (e.g., a first end of the sensor 116) and a second terminal or node 119 of the sensor 116 (e.g., a second end of the sensor 116), a crack can be detected by the sensor 116.

[0069] In the example of the embodiment shown in Figure 1B and Figure 1C , the crack sensor 116 includes a plurality of metal stacks, each metal stack including other portions 103B of the electrically conductive layers 103 coupled by the electrically conductive vias 106 of the interconnect structure 102. More specifically, each metal stack extends in height in the Z-direction, which is perpendicular to the XY-plane of the semiconductor layer 101, through all or a portion of the metallization levels M1-M6 of the interconnect structure 102, in the example shown, all the way to the upper metallization level M6. Two metal stacks S1 and S2 of the crack sensor 116 have been shown as examples in Figure 1C , although there can be more than two.

[0070] Preferably, although this is not shown in Figure 1B and Figure 1C , in each metallization level, the portions 103B of the crack sensor 116 are discontinuous to form an electrical path extending upward and downward in the crack sensor 116 through the vias 106 of the crack sensor 116 that form a chain of vias. Preferably, the crack sensor 116 includes a plurality of portions 103B in each metallization level of the interconnect structure 102.

[0071] Although this is not shown in Figure 1A , Figure 1B and Figure 1CAlthough not shown, the sealing ring 107 may include multiple sealing elements similar to the sealing element 108 described above, such as an inner sealing element arranged around the circuit area 105 in the interconnect structure 102 and an outer sealing element arranged around the inner sealing element in the interconnect structure 102. The sealing ring 107 may then include an intermediate crack sensor, such as similar to the crack sensor 108 described previously, arranged in the interconnect structure 102 between the inner and outer sealing elements. The presence of the inner and outer sealing elements and the intermediate crack sensor between the inner and outer sealing elements enables detection of a crack that has propagated from the edge of the electronic chip across the outer sealing element.

[0072] Although this is not Figure 1A 、 Figure 1B and Figure 1C 1 , the seal ring 107 may include an internal crack sensor that is arranged around the circuit area 105 or on the edge of the circuit area 105 in the interconnect structure 102 and surrounded by the sealing element 108 or the internal sealing element. The internal crack sensor enables detection that a crack has propagated from the edge 110 of the chip 100 through the sealing element(s) and may have reached the circuit area 105.

[0073] More generally, any seal ring structure can be envisioned within an interconnect structure that is intended to limit the propagation of cracks into the circuit area of ​​an electronic chip, or even to block moisture. For example, the seal ring can include one or more sealing elements that do not necessarily extend all the way to the upper metallization level, or even multiple sealing elements that extend all the way to different metallization levels. For moisture protection, the sealing element preferably extends all the way to the upper metallization level. Furthermore, the seal ring can include one or more crack sensors that do not necessarily extend all the way to the upper metallization level, or even multiple crack sensors that extend all the way to different metallization levels.

[0074] In some cases, it has been observed by crack sensors, especially internal crack sensors, that cracks can propagate within the seal ring or even through it. Therefore, the seal ring is not always sufficient to stop cracks, which can propagate into the circuit area of ​​the electronic chip.

[0075] The inventors have provided an electronic chip that satisfies the aforementioned need for improvement and overcomes all or some of the disadvantages of previously described electronic chips. In particular, the inventors have provided an electronic chip with enhanced protection, particularly against cracks, and in particular, an electronic chip including a sealing ring with enhanced protection.

[0076] It would be advantageous to have a method for manufacturing such an electronic chip that could be implemented using conventional electronic chip manufacturing processes.

[0077] Embodiments of the electronic chip will be described below. The described embodiments are non-limiting, and those skilled in the art will appreciate different variations based on the teachings of this disclosure.

[0078] Figure 2A is a simplified partial top view illustrating an electronic chip 200 according to an embodiment. Figure 2B It shows Figure 2A Simplified partial cross-sectional view of an example of an embodiment of an electronic chip. Figure 2C yes Figure 2B Another simplified partial cross-sectional view of an electronic chip. Figure 2B A cross-sectional view along Figure 2A The cross-sectional plane AA indicated in FIG. Figure 2C A cross-sectional view along Figure 2B The cross-sectional plane BB indicated in is obtained.

[0079] Figure 2A 、 Figure 2B and Figure 2C The electronic chip 200 has many Figure 1A 、 1B The common features of the electronic chip 100 of 1C and only the differences between the two electronic chips 100 and 200 are described in detail in the following description.

[0080] Figure 2A 、 Figure 2B and Figure 2C Electronic chip 200 and Figure 1A 、 1B The main difference from the electronic chip 100 of 1C is that the sealing ring 207 further includes a plurality of cavities 231 , 231 ′ in the interconnect structure 202 .

[0081] The cavities 231 are coupled together to form a continuous annular cavity 230 that is located around the circuit area 105, preferably entirely around the circuit area 105, for example between the circuit area 105 and the sealing element 108. For example, the continuous annular cavity 230 can be positioned in the insulating layer 111 between the portion 103A and the portion 103C of the conductive track 103 of one or more metallization levels.

[0082] The insulating layer 111 may be made of an oxide (eg, silicon oxide), or a high-κ dielectric material (ie, a material having a higher dielectric constant κ than silicon dioxide).

[0083] The cavities 231' are coupled together, forming a continuous annular cavity 230' located around the circuit area 105, preferably entirely around the circuit area 105, for example between the edge 110 of the chip 200 and the sealing element 108.

[0084] The cavities can be referred to as "air gaps". By cavities, it is meant volumes filled with gas. Thus, the cavities are filled with a gas, for example air.

[0085] Such a continuous annular cavity makes it possible to form a crack absorption area, thus preventing the propagation of cracks across the sealing ring 207 towards the circuit area 105.

[0086] Advantageously, the cavities 231, 231' extend at least up to the interface between the via 106 and the electrical conducting layer 103 of two successive metallization levels, for example the first metallization level M1 and the second metallization level M2, in order to stop the progression of cracks that would form or propagate at this interface.

[0087] The cavities 231 have been shown as example cavities 231 extending up to the first metallization level M1, thus forming a continuous annular cavity 230 in the sealing ring 207 at the first metallization level M1. When indicating up to a metallization level, it is understood that this metallization level is to be included. Since cracks generally occur at the first metallization level, such a configuration can be sufficient to prevent cracks from propagating all the way to the circuit area 105 of the electronic chip 200. Furthermore, this makes it possible not to burden the electronic chip manufacturing method, since it can be based on an air gap forming process, which can already be provided at the first metallization level M1, for example in another area of the interconnection structure, for example in the circuit area 105.

[0088] However, this example is not limiting and it is possible to form cavities 231' extending up to the second metallization level M2 as shown, or even up to a higher metallization level, or even up to the upper metallization level (M6 in the example shown), thus forming a continuous annular cavity 230' in the sealing ring 207, which extends beyond the first metallization level M1.

[0089] Furthermore, the cavities 231, 231' have been shown to reach the semiconductor layer 101, which is not always necessary. As a variant, the cavities can be at a non-zero distance from the semiconductor layer 101, for example ending in the isolation layer 111, the cavities can form a structure that is more robust than the structure of the cavities 231, 231' ending at the semiconductor layer 101.

[0090] The other features described with respect to Figure 1A , Figure 1B and Figure 1C can be adapted toFigure 2A , Figure 2B and Figure 2C the electronic chip 200 of

[0091] In particular, in Figure 2A , Figure 2B and Figure 2C a single sealing element 108 has been shown, it is known that the sealing ring 207 can comprise a plurality of sealing elements in the interconnect structure 202. For example, the sealing ring 207 can comprise one or more sealing elements that do not extend all the way to the upper metallization level, or even a plurality of sealing elements that extend all the way to different metallization levels. For moisture protection, the sealing elements preferably extend all the way to the upper metallization level. Furthermore, in Figure 2A , Figure 2B and Figure 2C a crack sensor is not shown, but the sealing ring 207 of the chip 200 can comprise one or more crack sensors, similar to the crack sensors that have been described for Figure 1A , Figure 1B and Figure 1C Furthermore, the sealing ring 207 can comprise one or more crack sensors that do not extend all the way to the upper metallization level, or even a plurality of crack sensors that extend all the way to different metallization levels.

[0092] Figure 3A is a simplified partial top view showing an electronic chip 300 according to another embodiment. Figure 3B is a simplified partial cross-sectional view showing an example of an embodiment of the electronic chip of Figure 3A . Figure 3C is another simplified partial cross-sectional view of the electronic chip of Figure 3B . Figure 3B The cross-sectional view of Figure 3A is taken along the cross-section A-A shown in Figure 3C . The cross-sectional view of Figure 3B is taken along the cross-section B-B shown in .

[0093] Figure 3A , Figure 3B and Figure 3C The electronic chip 300 of Figure 2A , Figure 2B and Figure 2C has many features in common with the electronic chip 200 of

[0094] Figure 3A , Figure 3B and Figure 3C The electronic chip 300 of Figure 2A , Figure 2B and Figure 2CThe main difference with the electronic chip 200 of Figure 1 is that the cavities coupled together are filled with an electrically conductive material, preferably a metallic material, such as tungsten or copper, forming electrically conductive areas 331, 331' in the sealing ring 307. Like the cavities 231, 231', the electrically conductive areas 331, 331' are coupled together, forming an electrically conductive annular wall 330, 330' in the sealing ring 307 around the circuit area 105. Each electrically conductive area 331, 331' is preferably integral. The electrically conductive annular wall is preferably integral. It can also be said to be a continuous annular wall. When referring to an "integral" element, it is meant to remain integral together, without splitting, without break in shape and material.

[0095] Such an electrically conductive annular wall makes it possible to prevent the propagation of cracks. Indeed, in a sealing element comprising portions of electrically conductive layers coupled together by vias, the interface between the vias and the electrically conductive layers is potentially brittle and can be a source of cracking and / or of propagation of cracks. However, each electrically conductive area is made of a single electrically conductive material, and thus does not comprise an interface, and is thus not brittle, and the electrically conductive annular wall formed by the electrically conductive areas coupled together thus forms a continuous wall, which entirely surrounds the circuit area, and which is able to resist the propagation of cracks.

[0096] Advantageously, the electrically conductive areas 331, 331' extend at least as far as the interface between the via 106 and the electrically conductive layer 103 of two successive metallization levels, for example the first metallization level M1 and the second metallization level M2, in order to stop the progression of cracks formed or propagating at this interface.

[0097] The electrically conductive area 331 has been shown as an example, which is formed at the first metallization level M1, and thus forms the electrically conductive annular wall 330 in the sealing ring 307 at the first metallization level M1. Cracks generally occur at the first metallization level, such a configuration can be sufficient to prevent the propagation of cracks towards the circuit area 105 of the chip 300. Furthermore, it makes it possible not to burden the manufacturing method, which can be based on a metal-filled air gap formation process, which can already be provided in another area of the interconnection structure, for example in the circuit area 105, for example at the first metallization level M1.

[0098] But this example is not limiting, and it is possible to form electrically conductive areas 331' which extend as far as the second metallization level M2 as shown, or even as far as higher metallization levels, or even as far as the upper metallization level (M6 in the example shown), and thus form an electrically conductive annular wall 330' in the sealing ring 307 which extends beyond the first metallization level M1.

[0099] Furthermore, the conductive regions 331, 331' have been shown to reach the semiconductor layer 101, but this is not always necessary. As a variant, the conductive regions can be at a non-zero distance from the semiconductor layer 101, for example ending in the insulating layer 111, which can form a more robust structure than the conductive regions 331, 331' ending at the semiconductor layer 101.

[0100] against Figure 1A 、 Figure 1B and Figure 1C The other features described can be applied to Figure 3A 、 Figure 3B and Figure 3C electronic chip 300.

[0101] Specifically, in Figure 3A 、 Figure 3B and Figure 3C In FIG, a single sealing element 108 has been shown, it is known that the sealing ring 307 may include multiple sealing elements in the interconnect structure 302. For example, the sealing ring 307 may include one or more sealing elements that do not extend all the way to the upper metallization level, or even multiple sealing elements that extend all the way to different metallization levels. For moisture protection, the sealing element preferably extends all the way to the upper metallization level. In addition, in Figure 3A 、 Figure 3B and Figure 3C In the embodiment, no crack sensor is shown, but the sealing ring 307 of the chip 300 may include one or more crack sensors, similar to those already described for Figure 1A 、 Figure 1B and Figure 1C Furthermore, the sealing ring 307 may include one or more crack sensors that do not necessarily extend all the way to the upper metallization levels, or even multiple crack sensors that extend all the way to different metallization levels.

[0102] Figures 2A to 2C Examples and Figures 3A to 3C The embodiments may be combined. For example, the sealing ring may comprise a continuous annular cavity and a conductive annular wall, the continuous annular cavity and the conductive annular wall being, for example, substantially concentric.

[0103] Furthermore, in conjunction with one or more of the described embodiments, and similar to the embodiments described in the seal ring, the interconnect structure can include, in the circuit region, other cavities coupled together between adjacent conductive tracks of the interconnect structure forming another continuous cavity between the adjacent conductive tracks at least at the first metallization level of the interconnect structure. The interconnect structure can also include, in the circuit region, other cavities coupled together between adjacent conductive tracks of the interconnect structure filled with a metallic material, such as tungsten or copper, forming a continuous conductive region between the adjacent conductive tracks at least at the first metallization level of the interconnect structure.

[0104] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H are cross-sectional views schematically and partially showing a structure obtained at the end of the steps of an example of a method of manufacturing an electronic chip according to an embodiment. The obtained electronic chip is similar to the electronic chip 200 shown in Figure 2A , Figure 2B and Figure 2C , Figure 4H for example shows a portion of the electronic chip 200.

[0105] Figure 4A The structure shown in Figure 4A shows a portion of the interconnect structure including a seal ring region 407, intended to include a seal ring surrounding the circuit region 405. In the circuit region 405, electronic circuits are formed inside and on top of a semiconductor layer 401. The first metallization level 410 is arranged above the semiconductor layer 401. In certain embodiments, the semiconductor layer 401 corresponds to a semiconductor substrate made of silicon, for example, or to a semiconductor layer of a silicon-on-insulator (SOI) substrate.

[0106] The semiconductor layer 401 extends along a main XY plane.

[0107] An insulating layer 402, for example a metal pre-dielectric layer or PMD layer, is formed on the semiconductor layer 401. In certain embodiments, the PMD layer 402 includes silicon oxide, such as silicon dioxide (SiO2). In other embodiments, the PMD layer 402 includes a silicon phosphide glass, abbreviated as “PSG” (phosphosilicate glass), or a silicon boron phosphide glass, abbreviated as “BPSG” (borophosphosilicate glass). However, the PMD layer 402 can include a combination of multiple of these materials, or any other suitable material.

[0108] Conductive vias 403 are formed through the PMD layer 402 all the way to the semiconductor layer 401. The conductive vias 403 can be formed for Figures 1A to 1C The described cylindrical via 106 type of via, or an elongated via formed in the form of a strip or line, or even a conductive ring-shaped strip 112 is formed for Figures 1A to 1C The described conductive ring-shaped strip 112.

[0109] The first metallization level 410 comprises conductive elements 411, such as metal tracks or lines (elongated in the Y direction), which are insulated from each other by dielectric or insulating elements 412. These insulating elements 412 together form an insulating layer 413 (first insulating layer). The insulating layer 413 can be referred to as an intermetal dielectric layer or IMD layer. The conductive elements 411 are coupled to the vias 403, preferably positioned substantially in line with the vias 403.

[0110] The first metallization level 410 can be formed by a subtractive process, e.g. for aluminum conductive elements, or by a damascene process, e.g. for copper conductive elements.

[0111] An example of a subtractive process is described below. A conductive layer, e.g. made of aluminum, is deposited on the PMD layer 402 and the vias 403. Then, the conductive layer is etched by an etch mask, e.g. obtained by lithography, which etching forms openings through the conductive layer all the way to the PMD layer 402. The etch mask is dimensioned such that the remaining part of the conductive layer, forming the conductive elements 411, is positioned substantially in line with the vias 403. Then, the etch mask is removed. Then, a protective layer 414 can be deposited to at least cover the sidewalls of the conductive elements 411, which protective layer can be made of nitride, such as silicon nitride, or any other suitable material. Then, the IMD layer 413 is formed to at least fill the openings between the conductive elements 411, forming the insulating elements 412. The IMD layer 413 comprises, e.g., silicon oxide, such as silicon dioxide (SiO2), or any other dielectric material. Then, the excess of the IMD layer 413 above the conductive layer can be removed by planarization, such as CMP.

[0112] An example of a damascene process is described below. An IMD layer 413 is deposited on the PMD layer 402 and the via 403. The IMD layer can be similar to the IMD layers described above. The IMD 413 layer is then etched through an etch mask obtained, for example, by lithography, forming openings through the IMD layer 413. The etch mask is sized so that the openings in the IMD layer 413 are positioned to be substantially aligned with the via 403. The etch mask is then removed. A protective layer 414 can then be deposited in the openings of the IMD layer 413 so as to cover at least the sidewalls of the openings. The protective layer can be similar to the protective layers described above. A barrier layer can be formed in the openings so as to cover the sidewalls and the bottom of the openings. The barrier layer comprises a suitable conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, or a combination of multiple of these materials. A layer made of a conductive material, for example copper, is then formed to at least fill the openings between the insulating elements 412, forming conductive elements 411 with the barrier layer, when provided. Excess portions of the conductive layer over the insulating elements 412 can be removed by planarization, such as CMP.

[0113] In both techniques, the protective layer 414 is located on the sides of the conductive elements 411, and it can protect the conductive elements 411 during subsequent manufacturing steps, such as etching for forming cavities as described below.

[0114] As can be seen in Figure 4A , a protective layer 421 is formed on the first metallization level 410, i.e. on the conductive elements 411 and the IMD layer 413. The protective layer 421 can be similar to the protective layers 414 described above.

[0115] Figure 4B A structure obtained at the end of forming an etch mask 422 on the protective layer 421 is shown. The etch mask 422 can be obtained by a lithography technique, and it comprises openings 422A therethrough. A single opening 422A has been shown in Figure 4B , but there are typically multiple openings in at least the Y direction.

[0116] Figure 4C A structure obtained at the end of etching portions of the protective layer 421 through the openings 422A of the etch mask 422, the etched portions forming openings 421A in the protective layer 421. The etching is, for example, a dry etching of the type of plasma etching.

[0117] Figure 4DThe structure obtained at the end of the etching of the port 423 (first port) in the sealing ring area 407 between the conductive elements 411 throughout the IMD layer 413 up to the PMD layer 402 is shown. The etching is performed through the opening 422A of the etching mask 422 and the opening 421A of the protection layer 421. The port 423 can be formed by a suitable anisotropic etching, such as for example a dry etching of the plasma etching type. The diameter of the port 423 can substantially correspond to the diameter of the opening 421A in the protection layer 421.

[0118] The etching step described can be performed in a single step. Figure 4C and Figure 4D The etching step described can be performed in a single step.

[0119] The port 423 does not extend throughout the semiconductor layer 401, that is to say, it ends in the PMD layer 402.

[0120] The etching mask 422 is then removed.

[0121] Figure 4E The structure obtained at the end of the etching to widen the port 423 is shown, so as to form an open cavity 424 in the IMD layer 413 and the PMD layer 402 between the two conductive elements 411 and possibly between the two vias 403. The opening of the open cavity 424 corresponds to the opening 421A of the protection layer 421. The open cavity 424 can be formed by a suitable isotropic etching, advantageously the materials of the IMD layer 413 and the PMD layer 402 are selected with respect to the material of the protection layer 421 to avoid etching the protection layer 421. In certain embodiments, the isotropic etching is a wet etching, for example performed with hydrofluoric acid (HF) (for example in vapor form), hydrochloric acid (HC1), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), sodium hydroxide (NaOH), nitric acid (HNO3), buffered oxide etch (BOE), or a mixture of several of these products.

[0122] The diameter of the port 423 can enable to define the size of the open cavity 424. For example, the greater the diameter of the port 423, the greater the average diameter of the open cavity 424 can be. However, the diameter of the port 423 is generally limited by the next step, which comprises closing the opening 421A, and thus the open cavity 424, without sealing it for this purpose.

[0123] The protection layer 414 located on the sidewalls or sides of the conductive elements 411 can advantageously protect the conductive elements 411 during the anisotropic etching and / or the isotropic etching.

[0124] Figure 4FThe structure obtained at the end of the formation of an insulating layer 425 (second insulating layer), which can be referred to as an intermetal dielectric layer or IMD layer, on the protective layer 421 and on the opening of the open cavity 424, in order to close the open cavity, forming a closed cavity referred to as cavity 431, is shown. The IMD layer 425 can be formed by using similar materials and methods as for the IMD layer 413 as described above. By means of the openings 421A through the protective layer 421, the dielectric material of the IMD layer 425 can cover the inner surface of the cavity 431 before closing the open cavity 424, forming an inner coating 426 in the cavity 431.

[0125] Figure 4C , Figure 4D , Figure 4E , Figure 4F The cross-sections of Figures 4A, 4B, 4C and 4D respectively show a single opening 421A, a single port 423, a single open cavity 424 and a single cavity 431, but there are multiple openings 421A, multiple ports 423, and consequently multiple cavities 431 coupled together in the Y direction. Thus, the cavities 431 between the conductive elements 411 are coupled together, forming a continuously extending cavity. This can form a continuous annular cavity, such as the continuous annular cavity 230 described with respect to Figures 2A, 2B, 2C and 2D, because the cavities 431 are all coupled together along the periphery of the electronic chip surrounding the circuit region 405. Thus, the widening of the ports 423 is advantageously performed in such a way that the open cavities 424 can be coupled together, thus forming the coupled together cavities 431 between the conductive elements 411. Figure 2A , Figure 2B and Figure 2C The cross-sections of Figures 4A, 4B, 4C and 4D respectively show a single opening 421A, a single port 423, a single open cavity 424 and a single cavity 431, but there are multiple openings 421A, multiple ports 423, and consequently multiple cavities 431 coupled together in the Y direction. Thus, the cavities 431 between the conductive elements 411 are coupled together, forming a continuously extending cavity. This can form a continuous annular cavity, such as the continuous annular cavity 230 described with respect to Figures 2A, 2B, 2C and 2D, because the cavities 431 are all coupled together along the periphery of the electronic chip surrounding the circuit region 405. Thus, the widening of the ports 423 is advantageously performed in such a way that the open cavities 424 can be coupled together, thus forming the coupled together cavities 431 between the conductive elements 411.

[0126] Figure 4C , Figure 4D , Figure 4E and Figure 4F The cross-sections of Figures 4A, 4B, 4C and 4D respectively show a single opening 421A, a single port 423, a single open cavity 424 and a single cavity 431, but there are multiple openings 421A, multiple ports 423, and consequently multiple cavities 431 coupled together in the Y direction. Thus, the cavities 431 between the conductive elements 411 are coupled together, forming a continuously extending cavity. This can form a continuous annular cavity, such as the continuous annular cavity 230 described with respect to Figures 2A, 2B, 2C and 2D, because the cavities 431 are all coupled together along the periphery of the electronic chip surrounding the circuit region 405. Thus, the widening of the ports 423 is advantageously performed in such a way that the open cavities 424 can be coupled together, thus forming the coupled together cavities 431 between the conductive elements 411.

[0127] Figure 4G and Figure 4H show an example of the formation of a via 428 coupling a conductive element 411 of the first metallization level 410 (M1) to other conductive elements of a second metallization level (not shown).

[0128] Figure 4GThe structure obtained at the end of the formation of the etch mask 426 on the IMD layer 425, followed by the etching of the IMD layer 425 and of the protection layer 421 to form the port 427 through these layers 425, 421, in alignment with the conductive element 411 is shown.

[0129] The etch mask 426 can be obtained by photolithography techniques, and the opening 426A in the etch mask 426 can be formed in alignment with the conductive element 411 so that the port 427 is coupled to the conductive element 411, the etching being performed through the opening 426A of the etch mask 426.

[0130] Figure 4H The structure obtained at the end of the filling of the port 427 with a conductive material, preferably a metallic material, for example including tungsten with a previously formed barrier layer of Ti / TiN type, or including copper with a previously formed barrier layer of TaN / Ta type, is shown.

[0131] Figure 4H The portion of the cross section C-C shown in Fig. 4 can correspond to a portion of the cross section of the interconnect structure 202 of the electronic chip 200 along the direction of the arrow A-A. Figure 2A For example, the cavity 431 can correspond to one of the cavities 231 in the sealing ring 207 and in the interconnect structure 202 between the circuit region 105 and the sealing element 108. Figure 2B The conductive element 411 on the left-hand side of Fig. 4, as well as the vias 403, 428, can correspond to a portion of the interconnect structure in the circuit region 405, the left-hand side via 403 then being coupled to a contact of an electronic component on the semiconductor layer 401. Figure 4H The conductive element 411 on the right-hand side of Fig. 4, as well as the vias 403, 428, can correspond to a portion of the interconnect structure in the sealing ring region 407, and can correspond to a portion of the sealing element formed in the interconnect structure. Figure 4H The conductive element 411 on the right-hand side of Fig. 4, as well as the vias 403, 428, can correspond to a portion of the interconnect structure in the sealing ring region 407, and can correspond to a portion of the sealing element formed in the interconnect structure.

[0132] Then, a second metallization level can be formed by techniques similar to those used for forming the first metallization level 410, for example by a subtractive process or by a damascene process, as described with respect to Fig. 3. Figure 4A Then, other metallization levels can be formed in a similar manner.

[0133] If it is desired to obtain a cavity extending at least up to the second metallization level or even up to a higher metallization level, the steps described with respect to Fig. 3 can be repeated at least once. Figures 4A to 4H

[0134] Figures 4A to 4H ​​The described method can also be adapted to form, in the circuit region 405 of the chip, other cavities coupled together between adjacent conductive tracks of the interconnect structure, so as to form another continuous cavity between adjacent conductive tracks at least at the first metallization level of the interconnect structure.

[0135] Figure 5A and Figure 5B are schematic and partially show a structure obtained at the end of a variant of the manufacturing method of the Figures 4A to 4H electronic chip, for example similar to the Figure 3A , Figure 3B and Figure 3C chip 300, Figure 5B for example shows a portion of the electronic chip 300.

[0136] In particular, Figure 5A and Figure 5B show a variant of the Figure 4G and Figure 4H wherein the etching mask 526 comprises a first opening 526A aligned with the cavity 431 and a second opening 526B aligned with the conductive element 411. Thus, the etching of the IMD layer 425 and of the protection layer 421 through the etching mask 526 forms a port 527A (second port) and a port 527B (third port), the port 527A extending through these layers up to the cavity 431 and thus being coupled to the cavity 431, the port 527B extending through these layers up to the conductive element 411 and thus being coupled to the conductive element 411.

[0137] A single first opening 526A aligned with the cavity 431 has been shown in the figures, but, as mentioned previously, there are a plurality of cavities 431 in the Y direction and generally at least two first openings 526A aligned with two different cavities 431.

[0138] The ports 527A enable the re-opening of the cavities 431 for filling them with a conductive material and thus filling the continuously extending cavities or the continuous annular cavity, as described below. Preferably, each port 527A is centered on one of the openings 421A of the protection layer 421.

[0139] As mentioned previously, the ports 527A are preferably formed by etching the IMD layer 425 and the protection layer 421 through the etching mask 526, but they can also be formed by etching the IMD layer 425 and the protection layer 421 through a second etching mask 526B, as shown in the figures. Figure 5BFilling of the port 527A enables filling of the cavity 431 with the electrically conductive material, forming the electrically conductive region 531, and the port 527A forms a first via 528A once filled. A single electrically conductive region 531 has been shown in the figure, but as previously mentioned, there are multiple cavities 431 coupled together in the Y direction, and thus multiple electrically conductive regions 531 coupled together in the Y direction. Furthermore, there are typically also at least two first vias 528A in the Y direction.

[0140] Filling of the port 527B forms a second via 528B, which is coupled to the electrically conductive element 411 and participates in interconnecting the electrically conductive element 411 of the first metallization level 410 with an electrically conductive element of a second metallization level (not shown).

[0141] Filling is performed by a suitable deposition technique, such as an ALD technique, or by a PVD or CVD technique, or by electroplating.

[0142] Since the cavities 431 are coupled together in one or more directions in the XY plane, the electrically conductive regions 531 are also coupled together, forming a continuous electrically conductive wall. This can form an electrically conductive annular wall, such as the electrically conductive annular wall 330 described in relation to Figure 3A 、 Figure 3B and Figure 3C , since the electrically conductive regions 531 are all coupled together around the circuit region 505 along the periphery of the electronic chip.

[0143] Figure 5B Can correspond to the part cross-section of the cross-section C-C of the electronic chip 300 shown in Figure 3A . Thus, the electrically conductive regions 531 can correspond to the electrically conductive regions 331 in Figure 3B , in the sealing ring 307 and in the interconnect structure 302 between the circuit region 105 and the sealing element 108. Figure 5B The electrically conductive elements 411 on the left-hand side of the figure, as well as the vias 403, 528B, can correspond to the part of the interconnect structure in the circuit region 505, in which case the left-hand side via 403 can be a contact to an electronic component on the semiconductor layer 401. Figure 5B The electrically conductive elements 411 on the right-hand side of the figure, as well as the vias 403, 528A, 528B, can correspond to the part of the interconnect structure in the sealing ring region 507, and can correspond to the part of the sealing element formed in the interconnect structure.

[0144] Not all cavities 431 of the single continuously extending cavity have to be coupled to the first port 527A. In fact, since the cavities 431 of the single continuously extending cavity are coupled together, it can be sufficient to have only two ports 527A for filling the cavities 431 with the electrically conductive material, e.g. a first inlet port for the electrically conductive material and a first outlet port for the electrically conductive material. However, depending on the length of the continuously extending cavity, more than two ports 527A can be provided, enabling a correct filling thereof.

[0145] Then, a second metallization level can be formed by similar techniques as used for forming the first metallization level 410, e.g. by a subtractive process or by a damascene type process, as described with respect to Figure 4A . Then, further metallization levels can be formed in a similar way.

[0146] If it is desired to obtain an electrically conductive region extending at least up to the second metallization level or even up to a higher metallization level, the steps described with respect to Figures 4A to 4F , Figure 5A , Figure 5B may be repeated at least once.

[0147] The method described with respect to Figure 5A and Figure 5B may also be adapted to form, in the circuit region 505 of the chip, further cavities coupled together between adjacent electrically conductive tracks of the interconnect structure, and then fill these further coupled cavities with a metallic material in order to form a continuous electrically conductive region between the adjacent electrically conductive tracks at least at the first metallization level of the interconnect structure.

[0148] Various embodiments and variants have been described. The skilled person will understand that certain features of these various embodiments and variants can be combined, and will think of other variants.

[0149] Finally, the actual implementation of the described embodiments and variants is within the capabilities of the skilled person, based on the functional indications given above.

Claims

1. An electronic chip, bounded by an edge, comprising: a semiconductor layer, extending along a main plane; an interconnect structure, located above the semiconductor layer; and a sealing ring, arranged in the interconnect structure between the edge of the electronic chip and an electronic circuit region of the electronic chip, the sealing ring comprising: a plurality of cavities, coupled together to form at least one continuous annular cavity around the electronic circuit region; and / or a plurality of electrically conductive regions, coupled together to form at least one electrically conductive annular wall around the electronic circuit region.

2. The electronic chip according to claim 1, wherein the interconnect structure comprises: a plurality of metallization levels, each metallization level comprising an electrically conductive layer, the electrically conductive layers of two successive metallization levels being coupled together by electrically conductive vias and / or electrically conductive strips of the interconnect structure; and an insulating layer, the electrically conductive layers, and the electrically conductive vias and / or electrically conductive strips being embedded in the insulating layer; wherein the interconnect structure is coupled to the semiconductor layer by a further electrically conductive via and / or by an electrical contact.

3. The electronic chip according to claim 1, wherein the cavities and / or the electrically conductive regions extend at least to a first metallization level of the interconnect structure.

4. The electronic chip according to claim 1, wherein the cavities and / or the electrically conductive regions extend at least to an interface level between an electrically conductive via and an electrically conductive layer of two successive metallization levels of the interconnect structure.

5. The electronic chip according to claim 4, wherein the cavities and / or the electrically conductive regions extend at least to the interface level between the electrically conductive via and the electrically conductive layers of a first metallization level and a second metallization level of the interconnect structure.

6. The electronic chip according to claim 1, wherein the cavities and / or the electrically conductive regions extend to the semiconductor layer.

7. The electronic chip according to claim 1, wherein the cavities and / or the electrically conductive regions end at a non-zero distance from the semiconductor layer.

8. The electronic chip according to claim 1, wherein the electrically conductive regions are substantially tungsten.

9. The electronic chip according to claim 1, wherein the sealing ring comprises a sealing element comprising an electrically conductive annular plate in each metallization level of the interconnect structure, two electrically conductive annular plates of two successive metallization levels being coupled together in a direction perpendicular to the main plane by an electrically conductive annular strip.

10. The electronic chip according to claim 9, wherein the at least one continuous annular cavity comprises a first continuous annular cavity between the electronic circuit region and the sealing element and / or a second continuous annular cavity between the sealing element and the edge of the electronic chip. ​ ​ ​ 11. The electronic die of claim 9, wherein the at least one electrically conductive annular wall comprises a first electrically conductive annular wall between the electronic circuit region and the sealing element and / or a second electrically conductive annular wall between the sealing element and the edge of the electronic die.

12. The electronic chip of claim 1, further comprising: other cavities coupled together and / or other electrically conductive regions coupled together in the electronic circuit region between second two adjacent electrically conductive elements of the interconnect structure.

13. A method of manufacturing an electronic die, the method comprising: providing a structure comprising a semiconductor layer and a first metallization level of an interconnect structure over the semiconductor layer, the structure having an electronic circuit region comprising electronic circuitry formed inside and on top of the semiconductor layer and a sealing ring region surrounding the electronic circuit region, and the first metallization level comprising electrically conductive elements of an electrically conductive layer insulated from each other by insulating elements of a first insulating layer; forming a first port in the sealing ring region through the first insulating layer between first two adjacent electrically conductive elements of the electrically conductive layer; widening the first port by etching to form an open cavity in the sealing ring region coupled together around the electronic circuit region; and forming a second insulating layer over the open cavity and the first insulating layer to close the open cavity, thereby forming cavities coupled together around the electronic circuit region, the cavities coupled together forming at least one continuous annular cavity around the electronic circuit region.

14. The method of claim 13, further comprising: prior to forming the first port, depositing a protective layer over the first insulating layer and the electrically conductive elements, followed by forming an opening in the protective layer by etching in the protective layer, the first port being formed in alignment with the opening.

15. The method of claim 13, further comprising: forming at least two second ports by etching in the second insulating layer to at least two of the cavities in the sealing ring region; and filling the second ports with an electrically conductive material to fill the cavities, thereby forming electrically conductive regions coupled together, and thereby forming at least one electrically conductive annular wall around the electronic circuit region.

16. The method of claim 15, wherein the filling of the second ports also forms first electrically conductive vias coupled to the electrically conductive annular wall.

17. The method of claim 15, further comprising: forming third ports by etching in the second insulating layer, each third port extending to one of the electrically conductive elements; and filling the third ports with the electrically conductive material, thereby forming second electrically conductive vias coupled to the electrically conductive elements.

18. The method of claim 17, wherein the electrically conductive material is substantially tungsten.

19. The method of claim 17, wherein forming the third port is performed simultaneously with forming the second port, and / or filling the third port is performed simultaneously with filling the second port.

20. The method of claim 13, further comprising: other cavities and / or other conductive regions coupled together formed in the electronic circuitry region between two adjacent conductive elements of the interconnect structure.

19. The method of claim 17, wherein forming the third port is performed simultaneously with forming the second port, and / or filling the third port is performed simultaneously with filling the second port. other cavities and / or other conductive regions coupled together formed in the electronic circuitry region between two adjacent conductive elements of the interconnect structure.

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