Test key structure and test method thereof

Abstract

The invention discloses a test key structure and a test method thereof, and the test key structure comprises two conductive pads which are adjacently arranged, two vertical contact columns which are respectively arranged below the two conductive pads and are electrically connected with the two conductive pads, and a test conductive layer which is arranged below the two vertical contact columns and is electrically connected with the two conductive pads. And the test conductive layer is electrically connected with the two vertical contact columns, and the test conductive layer presents a snake-shaped arrangement pattern from a top view.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a test key structure with a contact pad and a test method thereof. Background Art

[0002] In the semiconductor manufacturing process, after electronic components and multiple circuit layers are formed on a substrate, a redistribution layer or contact pad is often formed on top of the stacked circuit layers to transfer these electronic components to other larger pins and connect to other electronic components or voltage sources.

[0003] With advances in semiconductor technology, the size of various components has become increasingly smaller, even leading to the development of semiconductor structures that bond two different wafers together using hybrid bonding technology. This trend has led to increasing component density and a gradual reduction in the size of top-surface contact pads. Furthermore, the formation of top-surface contact pads can damage underlying components during the formation process, and this damage is difficult to detect using standard semiconductor manufacturing processes. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a test key structure, including two conductive pads arranged adjacent to each other, wherein a first spacing distance is formed between the two conductive pads, two vertical contact pillars are respectively located below the two conductive pads and electrically connected to the two conductive pads, and a test conductive layer is located below the two vertical contact pillars and electrically connected to the two vertical contact pillars, wherein from a top view, the test conductive layer presents a serpentine arrangement pattern.

[0005] The present invention further provides a testing method for a test key structure, comprising providing a test key structure, the test key structure comprising two conductive pads arranged adjacent to each other, wherein the two conductive pads have a first spacing distance between them, two vertical contact pillars, respectively located below the two conductive pads and electrically connected to the two conductive pads, a test conductive layer, located below the two vertical contact pillars and electrically connected to the two vertical contact pillars, wherein from a top view, the test conductive layer presents a serpentine arrangement pattern, and an electrical testing step is performed on the two conductive pads.

[0006] The present application is characterized in providing a test key structure with conductive pads and a test method thereof. The applicant has found that when two adjacent conductive pads with a spacing distance are formed in a device region of a semiconductor, a crack is easily generated under the gap between the two conductive pads due to stress, and the crack is too fine to be detected in a general semiconductor manufacturing process. Therefore, the present application provides a test key structure with the same size as the conductive pads in the device region in a test key region beside the device region, and a serpentine circuit layer is further provided under the test key structure. Therefore, if a crack is generated between the test key structures in the test key region, the crack will cut off the serpentine circuit layer under the test key structure, causing the device of the test key to be open. In this way, the manufacturer can immediately find the defect of the device, adjust the manufacturing process parameters to improve the semiconductor device, and thus improve the yield of the overall semiconductor manufacturing process. BRIEF DESCRIPTION OF DRAWINGS

[0007] For the purpose of facilitating the understanding of the present application, the accompanying drawings and detailed description thereof can be referred to while reading the present application. The specific embodiments of the present application are explained in detail by the specific embodiments herein and with reference to the corresponding drawings, and the principles of the specific embodiments of the present application are explained to illustrate the effects of the specific embodiments of the present application. In addition, for the purpose of clarity, the features in the drawings can not be drawn to scale, and thus the sizes of some features in some drawings can be intentionally exaggerated or reduced.

[0008] Figure 1 A cross-sectional view of a semiconductor structure including contact pads near the top surface in a device region;

[0009] Figure 2 A top view of a device region and a test key region of a semiconductor structure;

[0010] Figure 3 A perspective view of a test key structure of the present application in a test key region;

[0011] Figure 4 A top view of a test key structure of the present application in a test key region;

[0012] Figure 5 A top view of a semiconductor structure including contact pads with the same size in a device region and a test key region.

[0013] Explanation of main element symbols

[0014] 10: oxide layer

[0015] 12: passivation layer

[0016] 14: mask layer

[0017] 100: semiconductor structure

[0018] 110: test key structure

[0019] 111: test key structure

[0020] 120: test conductive layer

[0021] 121: first conductive line

[0022] 122: second conductive line

[0023] B: barrier layer

[0024] C: crack

[0025] IMD: dielectric layer

[0026] Ln-1: conductive layer

[0027] Ln: conductive layer

[0028] Sub: substrate

[0029] P: conductive pad

[0030] P1: conductive pad pair

[0031] P2: conductive pad pair

[0032] R1: element region

[0033] R2: test key region

[0034] S: first interval distance

[0035] V: vertical contact pillar

[0036] W1: width

[0037] W2: pitch DETAILED DESCRIPTION

[0038] In order to enable the person skilled in the art to further understand the present application, the preferred embodiments of the present application are listed below, and the effects and contents of the present application are described in detail with reference to the accompanying drawings.

[0039] For the convenience of description, the drawings of the present application are only schematic to make it easier to understand the present application, and the detailed proportions can be adjusted according to the design requirements. The relative positions of the elements in the drawings described in the text are understood by those skilled in the art to refer to the relative positions of the objects, so they can be reversed to show the same components, which should be included in the scope disclosed in the specification, and this is described first.

[0040] Although the present application uses first, second, third, etc. words to describe elements, components, regions, layers, and / or sections, such words should be understood to be names being used for conve- nience, and should not necessarily be taken to imply any precedence or relation of one element, component, region, layer, or section to another element, component, region, layer, or section, unless otherwise specifically noted. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the application.

[0041] The terms "about" or "substantially" as used herein with reference to a given value or range means within 20% of the given value or range, such as within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It is noted that quantities provided in the specification are approximate unless otherwise indicated. Thus, where "about" or "substantially" is not otherwise indicated, it is to be understood that such terms are implicitly present.

[0042] The terms "coupled", "coupling", "electrically connected" as used herein encompass both direct and indirect electrical connection means. For example, if a first component is described as being coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means or connections.

[0043] Although the following describes the application by way of specific embodiments, the inventive principles of the application can also be applied to other embodiments. In addition, specific details are omitted in order not to obscure the spirit of the application, which will be apparent from the detailed description.

[0044] Reference is made to Figure 1 and Figure 2According to an embodiment of the present application, a substrate Sub is first provided, and a device region Rl is defined on the substrate Sub. A plurality of electronic devices and circuit layers are formed within the device region Rl. The electronic devices can be, for example, transistors, capacitors, inductors, resistors, memories, power amplifiers, or other logic circuits, but the present application is not limited thereto. Circuit layers are then formed above the electronic devices. The function of the circuit layers is to electrically connect the electronic devices to other layers above. Subsequently, other electronic devices or voltage sources can be electrically connected to the electronic devices through conductive pads. The circuit layers are usually multi-layered and include horizontally extending conductive layers (often referred to as metal layers) and vertical conductive pillars (often referred to as vias). Other related techniques of electronic devices and circuit layers are known in the art and will not be described in detail herein.

[0045] After the multi-layered circuit layers are formed, contact pads are usually formed on the top of the circuit layers. The function of the contact pads is to provide larger size pads for connecting other electronic devices. Please refer to Figure 1 , Figure 1 A cross-sectional view of a semiconductor structure near the top surface of a device region including contact pads is shown. As shown in Figure 1 , within the device region Rl, conductive layer Ln-1 represents the second-to-last layer of the multi-layered circuit layers (i.e., the second layer from the top of the multi-layered circuit layers), conductive layer Ln represents the last layer of the multi-layered circuit layers (i.e., the top layer of the multi-layered circuit layers), and vertical conductive pillar V represents the vertical conductive pillar connecting conductive layer Ln-1 and conductive layer Ln. The materials of conductive layer Ln-1, conductive layer Ln, and vertical conductive pillar V can be, for example, metals such as tungsten, cobalt, copper, aluminum, gold, silver, etc., but the present application is not limited thereto. In addition, conductive layer Ln-1, conductive layer Ln, and vertical conductive pillar V are located within dielectric layers, such as dielectric layer IMD shown in Figure 1 . The materials of the dielectric layers can be, for example, silicon oxide, silicon nitride, or silicon oxynitride, but the present application is not limited thereto. The outer side of the connection between conductive layer Ln-1, conductive layer Ln, and vertical conductive pillar V can optionally include a barrier layer B. The material of the barrier layer B can be, for example, titanium / titanium nitride, etc. The barrier layer B can help the metal material to be better formed within the dielectric layer IMD.

[0046] It is worth noting that, as Figure 1 A cross-sectional view of a semiconductor structure near the top surface of a device region is shown. Therefore, the lower side of conductive layer Ln-1 can include other circuit layers and electronic devices, but for the sake of simplicity of the drawing, the circuit layers (including conductive layers and vertical conductive pillars) and electronic devices of the lower side are omitted and not shown herein.

[0047] Next, a contact pad structure is formed on the conductive layer Ln. The contact pad structure includes a contact pad P located within the oxide layer 10. Furthermore, a passivation layer 12 and a mask layer 14 may be located above the oxide layer 10. In this embodiment, the contact pad P is made of, for example, aluminum, the oxide layer 10 is made of, for example, silicon oxide, the passivation layer 12 is made of, for example, borophosphosilicate glass (PSG), and the mask layer 14 is made of, for example, silicon nitride, but the present invention is not limited thereto. From a cross-sectional view, the contact pad P may have a U-shaped cross-section, wherein the bottom surface of the contact pad P directly contacts and is electrically connected to the underlying conductive layer Ln. In this embodiment, a portion of the contact pad P is located on the oxide layer 10 and covers the top surface of the oxide layer 10. The passivation layer 12 and the mask layer 14 are located on the oxide layer 10. In this embodiment, a portion of the passivation layer 12 and the mask layer 14 cover the sidewalls and a portion of the top surface of the contact pad P, but the present invention is not limited thereto.

[0048] In subsequent steps, the contact pad P may contact other electronic components or signal sources, for example, an electrical signal may be connected to provide power to the electronic component to drive the electronic component, etc. For the sake of simplicity, the structure above the contact pad P is not shown.

[0049] With the advancement of semiconductor technology, the above Figure 1 The size of the semiconductor structure shown is also getting smaller and smaller. The applicant has found that when the contact pads P are arranged in pairs and at a certain distance, it is more likely to cause cracks in other material layers underneath during the manufacturing process, presumably due to stress accumulation. In more detail, as Figure 1 As shown, during the fabrication process, a crack C may be generated. The crack C is primarily located between two adjacent contact pads P and extends downward from the mask layer 14, the passivation layer 12, and the oxide layer 10. If the crack C is deep enough, it may even extend downward to the dielectric layer IMD and even cause a break in the conductive layer Ln-1.

[0050] The crack C is not easily found in the semiconductor manufacturing process, and is not easily found in wafer acceptance test (WAT). In some cases, a manufacturer uses a set of manufacturing process parameters to manufacture a semiconductor device, and even though the crack C is generated, the crack C does not cause the underlying circuit layer to be broken because the position of the circuit layer does not overlap the crack C, and thus the electrical property of the semiconductor device is not affected. The manufacturer can mistakenly believe that the set of manufacturing process parameters does not generate the crack C. However, if the manufacturer uses the same set of manufacturing process parameters to manufacture another semiconductor device, the crack C can also be generated. Because the shape of the circuit layer of the another semiconductor device can be different from that of the previous semiconductor device, the crack C can overlap the circuit layer of the another semiconductor device, and thus the circuit layer can be cut off by the crack C. Therefore, not only the circuit layer is damaged, but the manufacturer also cannot easily find the cause of the damage of the semiconductor device.

[0051] Therefore, to solve the above problems, the present application provides a test key structure, which is characterized by providing a pair of contact pads with the same size as that in the device region, and a snake-shaped test conductive layer is disposed under the pair of contact pads to simulate the generation of a crack in the device region. When the crack is generated, the crack can be found immediately through the snake-shaped test conductive layer. The details are described in the following paragraphs.

[0052] Please refer to Figure 2 , Figure 3 and Figure 4 . Figure 2 a top view of a semiconductor structure showing a device region and a test key region, Figure 3 a perspective view of a test key structure of the present application in a test key region, Figure 4 a top view of a test key structure of the present application in a test key region. As shown in Figure 2 a semiconductor structure 100 includes a device region Rl and a test key region R2 on a substrate Sub, wherein the device formed in the device region Rl will be the device actually needed to be used after the manufacturing process is completed, that is, the formation region of the semiconductor structure shown in Figure 1 the test key region R2, for example, a peripheral region beside the device region or a dummy region, wherein the test key can be formed. Figure 2 In the figure, other devices in the device region Rl and the test key region R2 are omitted for simplicity of the figure.

[0053] As shown in Figure 3 and Figure 4As shown, in one embodiment of the present application, a test key structure 110 is provided in the test key region R2. The test key structure 110 includes two pairs of conductive pads P, and each of the conductive pads P is directly contacted by a conductive layer Ln, and the conductive layer Ln is directly contacted by a vertical contact pillar V, and the vertical contact pillar V is directly contacted by a serpentine test conductive layer 120. The vertical contact pillar V directly contacts and electrically connects the serpentine test conductive layer 120 and the conductive layer Ln, and the conductive layer Ln directly contacts and electrically connects the conductive pad P and the vertical contact pillar V. Here, the conductive pad P, the conductive layer Ln and the vertical contact pillar V in the test key structure 110 are the same as the conductive pad P, the conductive layer Ln and the vertical contact pillar V in the semiconductor structure in the element region Rl, and thus the same features are denoted by the same reference numerals, and the same features will not be described again. However, it is worth noting that the conductive pad P, the conductive layer Ln, the vertical contact pillar V and the serpentine test conductive layer 120 in the test key structure 110 are formed in the test key region R2, not in the element region Rl.

[0054] In addition, in the present embodiment, the two pairs of contact pads P have the same area, and the distance between the two pairs of contact pads P is defined as S, wherein S can be equal to, less than or equal to 3.5 microns, or approximately equal to 6 microns. Alternatively, the two pairs of contact pads P have different areas, and the distance S between the two pairs of contact pads P is approximately equal to 4.5 microns. According to the experimental results of the applicant, it is found that the probability of cracks between the contact pads P is higher under the above condition range, and thus it is necessary to pay attention to whether cracks are generated between the contact pads P in the manufacturing process. However, it can be understood that the above condition range is only one example of the present application, and the present application is not limited thereto, that is, if the distance between the pairs of contact pads P is other values, it also belongs to the scope of the present application.

[0055] In addition, please continue to refer to Figure 3 and Figure 4 In the present embodiment, the vertical contact pillar V is electrically connected to both ends (the first end and the last end) of the serpentine test conductive layer 120, and the serpentine test conductive layer 120 includes a plurality of first conductive lines 121 arranged in a first direction (for example, the X direction) and a plurality of second conductive lines 122 arranged in a second direction (for example, the Y direction). Figure 4 Figure 4 In addition, in the present embodiment, the two pairs of contact pads P have the same area, and the distance between the two pairs of contact pads P is defined as S, wherein S can be equal to, less than or equal to 3.5 microns, or approximately equal to 6 microns. Alternatively, the two pairs of contact pads P have different areas, and the distance S between the two pairs of contact pads P is approximately equal to 4.5 microns. According to the experimental results of the applicant, it is found that the probability of cracks between the contact pads P is higher under the above condition range, and thus it is necessary to pay attention to whether cracks are generated between the contact pads P in the manufacturing process. However, it can be understood that the above condition range is only one example of the present application, and the present application is not limited thereto, that is, if the distance between the pairs of contact pads P is other values, it also belongs to the scope of the present application.

[0055] In addition, please continue to refer to Figure 3 and Figure 4 In the present embodiment, the vertical contact pillar V is electrically connected to both ends (the first end and the last end) of the serpentine test conductive layer 120, and the serpentine test conductive layer 120 includes a plurality of first conductive lines 121 arranged in a first direction (for example, the X direction) and a plurality of second conductive lines 122 arranged in a second direction (for example, the Y direction). Figure 4 Figure 4The second conductive lines 122 (in the Y direction) are connected in series, with the two ends of each second conductive line 122 connected in series to the ends of two first conductive lines 121, thereby forming a repeating "S" shape or serpentine shape. The width of a first conductive line 121 is defined as W1, and the spacing between two adjacent first conductive lines 121 is defined as W2. In this embodiment, W1 is preferably greater than W2. This allows the serpentine-shaped test conductive layer 120 to have a higher pattern density. When cracks occur, the probability of the cracks overlapping the serpentine-shaped test conductive layer 120 is greater. However, the present invention is not limited to this. The actual dimensions of the serpentine-shaped test conductive layer 120, the length and width of each first conductive line 121 and second conductive line 122, the spacing between the first conductive lines 121, and the arrangement of the second conductive lines 122 can all be adjusted according to actual needs.

[0056] In addition, the extending direction of the gap between the two conducting pads P is preferably perpendicular to the extending direction of the first conducting line 121 of the serpentine testing conducting layer 120. Figure 3 or Figure 4 For example, the gaps between the conductive pads P are arranged along the Y direction, while the first conductive lines 121 of the serpentine test conductive layer 120 are preferably arranged along the X direction. Thus, when cracks form between the conductive pads P, the cracks are likely to form along the Y direction. This creates a high probability of overlapping with the first conductive lines 121 of the serpentine test conductive layer 120, thereby cutting off the first conductive lines 121 and achieving a detection effect.

[0057] During actual testing, the vertical contact studs V electrically connect the two ends of the serpentine test conductive layer 120. When a voltage is applied to the vertical contact studs V at both ends, the serpentine test conductive layer 120 forms a circuit. If a signal detector is connected to the circuit, a normal signal can be detected. For example, when measuring the resistance of the circuit, a predetermined resistance value within a normal range can be obtained. However, if a crack C forms during the manufacturing process, causing the underlying serpentine test conductive layer 120 to be severed, a normal signal cannot be measured. For example, when measuring resistance, the resistance value will typically be higher than the normal range. This typically indicates that the circuit formed by the serpentine test conductive layer 120 has been affected or interrupted by the crack.

[0058] If the circuit of the serpentine test conductive layer 120 within the test key region R2 is interrupted during testing, this indicates that cracks have likely formed between the conductive pads P. Since the device region R1 also contains pairs of conductive pads of the same size, cracks may also form between the pairs of conductive pads P within the device region R1. In this case, the manufacturer can review the manufacturing process and adjust the process parameters to prevent cracks from affecting the semiconductor device. Therefore, the method of the present invention can immediately detect the formation of cracks between pairs of conductive pads.

[0059] Figure 5 A schematic top view of a semiconductor structure with contact pads of the same size in the device region and the test key region is shown. Figure 5 As shown, in some embodiments, the component region R1 may include more than one pair of conductive pads, but may include two or more pairs of conductive pads, and the two pairs of conductive pads are defined as P1 and P2, respectively. The areas of the two conductive pads in the two groups of conductive pads P1 and P2 may be the same or different, and the spacing between the two conductive pads may also be adjusted as needed. In order to simulate whether cracks will occur between the conductive pad pair P1 or P2 in the component region R1 in the test key region R2, conductive pad pairs P1 and P2 of the same size are also formed in the test key region R2, and a serpentine test conductive layer 120 is provided under the conductive pad pair P1 and P2 in the test key region R2. In other words, Figure 5 The conductive pad pair P1 located within the test key region R2 can be considered as a test key structure 110, and the other conductive pad pair P2 located within the test key region R2 can be considered as another test key structure 111. In other words, in this embodiment, multiple different test keys can be provided within the test key region R2, and each test key can be the same size as one of the conductive pad pairs P1 or P2 within the device region R1. It is understood that the present invention also encompasses the provision of more test keys (more than two) within the test key region R2, which is also within the scope of the present invention.

[0060] also, Figure 5 For the sake of simplicity in the drawings, other components except the conductive pad pairs located in the device region R1 and the test key region R2 are omitted.

[0061] In summary, the present invention provides a test key structure 110 comprising two adjacent conductive pads P, wherein a first spacing distance S is provided between the two conductive pads P, two vertical contact pillars V, respectively located below the two conductive pads P and electrically connected to the two conductive pads P, and a test conductive layer 120, located below the two vertical contact pillars V and electrically connected to the two vertical contact pillars V. From a top view, the test conductive layer 120 exhibits a serpentine arrangement pattern.

[0062] In some embodiments of the present invention, the serpentine arrangement pattern includes a plurality of first conductive lines 121 arranged along a first direction (e.g., X direction) and parallel to each other, and a plurality of second conductive lines 122 arranged along a second direction (e.g., Y direction) and parallel to each other, wherein each second conductive line 122 connects each first conductive line 121 to form a continuous conductive line pattern.

[0063] In some embodiments of the present invention, a gap distance W2 between the mutually parallel first conductive lines 121 is smaller than a width W1 of each first conductive line 121 .

[0064] In some embodiments of the present application, the two vertical contact posts V contact the test conductive layer 120 at a first end and a second end.

[0065] In some embodiments of the present application, two conductive layers Ln are further included between the two conductive pads P and the two vertical contact posts V, wherein the conductive layers Ln electrically connect the conductive pads P and the vertical contact posts V.

[0066] In some embodiments of the present application, an oxide layer 10 is further included between the two conductive pads P.

[0067] In some embodiments of the present application, a crack C is further included in the oxide layer 10, and the crack C passes through the test conductive layer 120.

[0068] In some embodiments of the present application, a passivation layer 12 is further included on the oxide layer 10, and part of the passivation layer 12 covers a side edge and a top surface (as shown) of the conductive pads P. Figure 1

[0069] In some embodiments of the present application, the first interval distance S between the two conductive pads P is less than or equal to 3.5 microns.

[0070] In some embodiments of the present application, the first interval distance S between the two conductive pads P is about 6 microns.

[0071] In some embodiments of the present application, the first interval distance S between the two conductive pads P is about 4.5 microns.

[0072] In some embodiments of the present application, the material of the two conductive pads P comprises aluminum.

[0073] In some embodiments of the present application, the test key structure 110 is located in the test key area R2, and the test key area R2 is located beside the component area Rl.

[0074] In some embodiments of the present application, the areas of the two conductive pads P are the same.

[0075] In some embodiments of the present application, the areas of the two conductive pads P are different.

[0076] In some embodiments of the present application, another test key structure (for example, the test key structure 111 in Figure 5 is further included, and the another test key structure 111 comprises two second conductive pads arranged adjacently, wherein a second interval distance is between the two second conductive pads, and the second interval distance is different from the first interval distance. Figure 5 ​In some embodiments, the distance between the conductive pads of the pair P1 and the distance between the conductive pads of the pair P2 can be different.

[0077] The present application also provides a test method for testing a test key structure. The test method includes providing a test key structure 110, the test key structure 110 including two conductive pads P arranged adjacent to each other with a first distance S between the two conductive pads P, two vertical contact pillars V arranged below the two conductive pads P and electrically connected to the two conductive pads P, and a test conductive layer 120 arranged below the two vertical contact pillars V and electrically connected to the two vertical contact pillars V. The test conductive layer 120 has a serpentine arrangement pattern when viewed from a top view. The test method further includes performing an electrical test on the two conductive pads P.

[0078] In some embodiments, the electrical test includes applying a voltage to a circuit formed by the two conductive pads P, the two vertical contact pillars V, and the test conductive layer 120, and measuring whether a resistance value of the circuit is greater than a predetermined value.

[0079] In some embodiments, if the measured resistance value is greater than the predetermined value, a manufacturing process adjustment is performed (indicating that the circuit has a possible open circuit).

[0080] The present application features a test key structure with conductive pads and a test method thereof. The present application has found that when two conductive pads are formed adjacent to each other with a distance between them in a device region of a semiconductor, a crack can be formed under the gap between the two conductive pads due to stress, which is too small to be detected in a general semiconductor manufacturing process. Therefore, the present application provides a test key structure with the same size as the conductive pads in the device region in a test key region adjacent to the device region, and a serpentine circuit layer is further provided below the test key structure. If a crack is formed between the test key structures in the test key region, the crack will cut off the serpentine circuit layer below, causing an open circuit of the test key. Thus, the manufacturer can immediately find the defect of the device, adjust the manufacturing process parameters to improve the semiconductor device, and thus improve the yield of the overall semiconductor manufacturing process.

[0081] The above description is only some preferred embodiments of the present application. Any equivalent changes and modifications made according to the claims of the present application should be covered by the present application.

Claims

1. A test key structure, characterized by : two conductive pads arranged adjacent to each other with a first spacing distance between the two conductive pads; two vertical contact posts respectively located below and electrically connected to the two conductive pads; a test conductive layer located below and electrically connected to the two vertical contact posts, wherein the test conductive layer presents a snake-like arrangement pattern from a top view.

2. The test key structure of claim 1, wherein the snake-like arrangement pattern comprises: a plurality of first conductive lines arranged along a first direction and parallel to each other; a plurality of second conductive lines arranged along a second direction and parallel to each other, wherein each of the second conductive lines connects each of the first conductive lines and forms a continuous conductive line pattern.

3. The test key structure of claim 2, wherein a gap distance between each of the parallel first conductive lines is less than a width of each of the first conductive lines.

4. The test key structure of claim 1, wherein the two vertical contact posts respectively contact a first end and a last end of the test conductive layer.

5. The test key structure of claim 1, further comprising two conductive layers respectively located between the two conductive pads and the two vertical contact posts, wherein the conductive layers electrically connect the conductive pads and the vertical contact posts.

6. The test key structure of claim 1, further comprising an oxide layer located between the two conductive pads.

7. The test key structure of claim 6, further comprising a crack located in the oxide layer and passing through the test conductive layer.

8. The test key structure of claim 6, further comprising a passivation layer located on the oxide layer and partially covering side edges and a top surface of the conductive pads.

9. The test key structure of claim 1, wherein the first spacing distance between the two conductive pads is less than or equal to 3.5 microns.

10. The test key structure of claim 1, wherein the first spacing distance between the two conductive pads is approximately equal to 6 microns.

11. The test key structure of claim 1, wherein the first spacing distance between the two conductive pads is approximately equal to 4.5 microns.

12. The test key structure of claim 1, wherein the test key structure is located in a test key region, and the test key region is located adjacent to a device region.

13. The test key structure of claim 1, wherein the two conductive pads have the same area.

14. The test key structure of claim 1, wherein the two conductive pads have different areas.

15. The test key structure of claim 1, further comprising another test key structure, and the another test key structure comprises two second conductive pads arranged adjacent to each other with a second spacing distance between the two second conductive pads, and the second spacing distance is different from the first spacing distance.

16. A test method of testing a key structure, characterized by : A test key structure is provided, the test key structure comprising: two conductive pads arranged adjacent to each other with a first spacing distance between the two conductive pads; two vertical contact posts respectively located below and electrically connected to the two conductive pads; a test conductive layer located below and electrically connected to the two vertical contact posts, wherein the test conductive layer presents a snake-like arrangement pattern from a top view; and ​ performing an electrical test on the two conductive pads.

17. The testing method of claim 16, wherein the electrical test comprises: applying a voltage to a circuit formed by the two conductive pads, the two vertical contact posts, and the test conductive layer; and measuring whether the resistance of the circuit is greater than a predetermined value.

18. The testing method of claim 17, wherein if the measured resistance is greater than the predetermined value, then performing a manufacturing process adjustment.

19. The testing method of claim 16, wherein the serpentine arrangement comprises: a plurality of first conductive lines arranged in a first direction and parallel to each other; and a plurality of second conductive lines arranged in a second direction and parallel to each other, wherein each of the second conductive lines connects each of the first conductive lines and forms a continuous conductive line pattern.

20. The testing method of claim 19, wherein the gap distance between each of the parallel conductive lines is less than the width of each of the first conductive lines.

Images