Signal conversion device and signal conversion method

Abstract

The invention discloses an apparatus for signal conversion and a signal conversion method. An apparatus as discussed herein may be configured to include a delay line analog-to-digital converter operable to convert an analog error voltage into a digital error voltage signal. In addition, the apparatus may be configured to include an accumulator function module and a digital-to-analog converter. The accumulator function module is operable to generate a digital value representative of the analog input voltage, the digital value being adjusted based on samples of a digital error voltage signal generated by the delay line analog-to-digital converter. The digital-to-analog converter is operable to convert a digital value received from the accumulator function to a second analog voltage, the analog error voltage being a difference between the input voltage and the second analog voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an apparatus and a signal conversion method for signal conversion, and more particularly, to a self-calibrating delay line flash ADC and tracking circuitry. BACKGROUND

[0002] A conventional tracking ADC (analog-to-digital converter) can be used to convert an input voltage into a corresponding digital signal indicative of the magnitude of the input voltage. Typically, the conventional tracking ADC is operable to compare an analog input voltage to a digital output thereof that is digitally-to-analog (D / A) converted.

[0003] For example, the conventional tracking ADC can be configured to include a digital-to-analog converter. The digital-to-analog converter receives a digital output of the conventional tracking ADC. Based on the received digital output, the digital-to-analog converter converts the digital output into a corresponding analog signal representative of the digital output. The conventional tracking ADC can be configured to also include a difference function that produces an error signal representative of a difference between the analog input voltage (positively converted) and the corresponding analog signal generated by the digital-to-analog converter. The conventional tracking ADC includes an analog-to-digital converter function that converts the analog error signal into a corresponding digitized version of the error signal. Based on the digitized error signal, the conventional tracking ADC produces a corresponding digital output representative of the input voltage.

[0004] The above-described loop associated with the conventional tracking analog-to-digital converter ensures that the digital output representative of the input voltage is very accurate. SUMMARY

[0005] Implementations of clean energy (or green technology) are very important to reduce the impact of humans on the environment. Generally, clean energy includes any method and material that is constantly evolving to reduce the overall toxicity of energy consumption on the environment.

[0006] The present disclosure includes the observation that it is generally required to convert raw energy (e.g., raw energy received from green or non-green energy) into an appropriate form (e.g., a desired AC voltage, a DC voltage, etc.) before it can be used to power an end device such as a server, a computer, a mobile communication device, a wireless base station, etc. In some cases, the energy is stored in a corresponding one or more battery resources. Alternatively, the energy is received from a voltage generator or a voltage source.

[0007] Regardless of whether the energy is received from green or non-green energy, it is desirable to most efficiently utilize (e.g., store and subsequently distribute) the raw energy provided by such energy sources to reduce our impact on the environment. The present disclosure helps to reduce our carbon footprint and provide better utilization of energy via more efficient energy conversion.

[0008] As previously discussed, a conventional tracking ADC can be configured to subtract an input analog signal from an analog output signal of a DAC to create an analog error voltage. The DAC stores a previous cycle value of the ADC output - the error voltage is digitized by a comparator that determines whether to add or subtract a step from the DAC for the next cycle.

[0009] Note that conventional tracking ADCs have limitations. For example, a tracking ADC can be used as a current sensor ADC (also referred to as an ISADC), but has the following advantages / disadvantages

[0010] • Advantages of a tracking ADC:

[0011] o Low power

[0012] o High sampling rate

[0013] o Single cycle conversion

[0014] • Disadvantages of a tracking ADC

[0015] o But can only digitize low bandwidth signals

[0016] o Step speed of tracking loop can only be as fast as the step controlled by the resolution / range of the error quantizer

[0017] The present disclosure also includes the observation that as power inductor values continue to shrink and switching frequencies of corresponding power converters in new power converter products continue to increase, it is desirable to design current sensor ADCs that track higher speed transients. Further, new applications of LLC type resonant converters can require ISADCs to track 1 Mhz sinusoidal waveform currents. Additionally, LLC regulator topologies can require accurate detection of when the switching current crosses zero in order to have the advantage of higher efficiency due to a “Zero Volt Switching” control method.

[0018] Conventional tracking ADCs will have problems in tracking signals with fast slew rates. To track faster slew rates, a larger error quantizer (e.g., the function that converts the generated analog error signal to a corresponding digital error signal) is required. Existing versions of ISADCs (also referred to as current sense analog-to-digital converters) can include multiple comparators for converting the respective error signals to digitized error signals, which requires multiple preamplifiers and multiple latches, which undesirably occupies a large area and consumes a high amount of power. Additionally, multiple comparators in a conventional tracking ADC can create a large load at the output of the tracking loop, which degrades the bandwidth (set-up time of Verror) of the tracking loop. The technical solutions including the circuitry and methods as discussed herein solve one or more of these disadvantages.

[0019] More specifically, an apparatus or system as discussed herein includes delay line analog-to-digital converter circuitry, signal generator circuitry, and calibration circuitry. The signal generator circuitry (e.g., a voltage-to-time converter or other suitable entity) can be coupled to the delay line analog-to-digital converter circuitry. The signal generator circuitry can be configured to generate a control signal for controlling operation of the delay line analog-to-digital converter circuitry based on an analog voltage received by the signal generator circuitry for conversion to a digital signal. Moreover, the calibration circuitry as discussed herein can be configured to calibrate the signal generator circuitry based on calibration feedback (e.g., by monitoring the delay line analog-to-digital converter circuitry and / or the signal generator circuitry) to ensure accurate operation of converting instances of the received analog voltage to corresponding samples of the digital signal.

[0020] In one example, the delay line analog-to-digital converter circuitry includes a first delay line analog-to-digital converter circuit and a second delay line analog-to-digital converter circuit arranged in parallel to convert the received analog voltage to corresponding samples of a digital output signal.

[0021] According to another example discussed herein, the delay line analog-to-digital converter circuitry can be configured to include a first delay line analog-to-digital converter operable to generate positive polarity error values associated with converting the received analog voltage to a digital signal and a second delay line analog-to-digital converter operable to generate negative polarity error values associated with converting the received analog voltage to a digital signal.

[0022] Moreover, as discussed herein, the received analog voltage can be supplied by a selector circuit (e.g., a multiplexer circuit coupled to the signal generator) in which different types of analog voltage signals are input to the signal generator circuitry for conversion to corresponding samples of a digital signal. One or more different types of analog voltage signals can be used to support calibration as discussed herein.

[0023] In yet another example, a first delay line analog-to-digital converter circuit of the delay line analog-to-digital converter circuitry is operable to generate a first portion of the corresponding samples during a first operating condition in which the analog voltage is greater than a threshold level (e.g., 0 volts or other suitable value); and a second delay line analog-to-digital converter circuit of the delay line analog-to-digital converter circuitry is operable to generate a second portion of the corresponding samples during a second operating condition in which the analog voltage is less than the threshold level.

[0024] It is also noted that the control signals as discussed herein can be configured to include a first control signal and a second control signal. The first control signal can be configured to control a start operation of the first delay line analog-to-digital converter circuit; the second control signal can be configured to control a stop operation of the first delay line analog-to-digital converter circuit. The second control signal can be configured to control a start operation of the second delay line analog-to-digital converter circuit; the first control signal can be configured to control a stop operation of the second delay line analog-to-digital converter circuit.

[0025] According to further examples as discussed herein, the apparatus can be configured to include selector circuitry operable to select between a first output signal generated by the first delay line analog-to-digital converter circuit and a second output signal generated by the second delay line analog-to-digital converter circuit. The calibration circuitry can be configured to use the first signal and the second signal as a basis for the calibration signal generator circuit and / or the delay line analog-to-digital converter circuitry.

[0026] Further examples as discussed herein include implementing the delay line analog-to-digital converter circuitry in a tracking analog-to-digital converter circuit. The calibration circuitry can be configured to include a gain calibration loop, wherein a gain associated with the delay line analog-to-digital converter circuitry is configured to match a gain setting of a tracking loop associated with the tracking analog-to-digital converter circuit.

[0027] Further, it is noted that the signal generator circuit, e.g. a voltage-to-time converter, can be configured to include an amplifier operable to receive an analog voltage. The calibration circuitry as discussed herein can be configured to include an offset calibration circuit operable to monitor a control signal output from the signal generator and input to the delay line analog-to-digital converter circuitry. The offset calibration circuit can be further configured to generate an offset adjustment control signal based on the monitored control signal input to the delay line analog-to-digital converter circuitry. The offset adjustment control signal adjusts an offset associated with the amplifier. In one example, the offset calibration circuit is an offset delay locked loop circuit or other suitable entity operable to produce the offset adjustment control signal supplied to the amplifier.

[0028] In another example, the signal generator circuit, e.g., a voltage-to-time converter, can include an amplifier operable to receive the analog voltage. The calibration circuitry can be configured to include a gain calibration circuit operable to monitor an output of the delay line analog-to-digital converter circuitry. The gain calibration circuit can be configured to generate a gain adjustment control signal based on the output of the delay line analog-to-digital converter circuitry, where the generated gain adjustment control signal adjusts a gain associated with the amplifier that subsequently converts other samples of the received analog voltage to the control signal. The gain calibration circuit can be configured as a gain delay locked loop circuit or other suitable entity.

[0029] In another example, the signal generator circuit as described herein is a voltage-to-time converter operable to generate a start signal and a stop signal supplied to the delay line analog-to-digital converter circuitry, where a magnitude of a duration between the start signal and the stop signal depends on or proportionally tracks a magnitude of the received analog voltage. The calibration circuitry can be configured to calibrate the voltage-to-time converter based on the calibration feedback in a manner as previously discussed.

[0030] Further, an apparatus as discussed herein can be configured to include a selector circuit (e.g., relative to a pre-stage of a voltage-to-time converter) for selecting an analog voltage input to the signal generator among a plurality of analog inputs. For example, the selector circuit can be configured to select among: i) a first analog gain reference voltage, ii) a second analog gain reference voltage, iii) an offset reference voltage, and iv) an analog error voltage. Signals including i) the first analog gain reference voltage, ii) the second analog gain reference voltage, iii) the offset reference voltage, etc. can be used for calibration purposes.

[0031] An analog voltage received and converted to a digital signal as discussed herein can be: i) a first analog gain reference voltage, ii) a second analog gain reference voltage, iii) an offset reference voltage, or iv) an analog error voltage. In one example, the calibration circuitry is operable to generate a calibration adjustment signal, e.g., calibration feedback, discussed herein, based on analog-to-digital conversion of the first analog gain reference voltage, the second analog gain reference voltage, and the offset reference voltage at different times during an analog-to-digital converter cycle.

[0032] Further, the selector circuit (e.g., with respect to a pre-stage of the voltage-to-time converter) can be configured to interleave conversion of a received analog voltage, e.g., an analog error voltage (or other signal of interest), among conversion of the first analog gain reference voltage, conversion of the second analog gain reference voltage, and conversion of the offset reference voltage. In other words, conversion of the first analog gain reference voltage, the second analog gain reference voltage, and the offset reference voltage support calibration of the signal generator circuit for purposes of subsequently providing analog-to-digital conversion of the signal of interest (e.g., the error voltage or other suitable voltage for conversion). In such examples, the analog-to-digital converter circuit and / or the signal generator circuit as discussed herein can be calibrated constantly (e.g., within a cycle) between instances of converting the analog error voltage to respective samples of a digital signal. The continuous or repeated function of periodically calibrating the analog-to-digital converter (including the signal generator and / or delay line analog-to-digital converter circuitry) ensures that respective samples of the digital signal representing the analog error voltage are as accurate as possible.

[0033] Further, examples of the apparatus include a synchronizer circuit. The synchronizer circuit as discussed herein is operable to adjust a clock signal applied to D flip-flops disposed in the delay line analog-to-digital converter circuitry.

[0034] Further, examples herein include a method comprising: receiving an analog voltage; generating, via a signal generator circuit, e.g., a voltage-to-time converter or other suitable entity, a control signal for controlling operation of a delay line analog-to-digital converter circuitry based on the analog voltage received by the signal generator circuit, the delay line analog-to-digital converter circuitry being operable to convert the analog voltage to a digital signal; and calibrating the signal generator circuit based on calibration feedback generated by the delay line analog-to-digital converter circuitry converting a sample of the analog voltage to the digital signal.

[0035] According to further examples, the calibration circuitry can be configured to include a gain calibration circuit and an offset calibration circuit. The gain calibration circuit can include a first set of charge pumps to generate a gain calibration signal supplied to the signal generator circuit. The offset calibration circuit can include a second set of charge pumps to generate an offset calibration signal supplied to the signal generator circuit. The apparatus as discussed herein can further include i) first pulse width calibration circuitry operable to adjust a pulse width of a first pulse width modulated signal applied to the first set of charge pumps to calibrate the first set of charge pumps and the first phase frequency detector based on an output of the delay line analog-to-digital converter circuitry, and ii) second pulse width calibration circuitry operable to adjust a pulse width of a second pulse width modulated signal applied to the second set of charge pumps to calibrate the second set of charge pumps and the second phase frequency detector based on the output of the delay line analog-to-digital converter circuitry.

[0036] Additionally, the delay line ADC circuitry may include a first D flip-flop and a second D flip-flop. The first D flip-flop in the first delay line ADC circuitry and the second D flip-flop in the second delay line ADC circuitry may be implemented with a negative setup time to provide overlap with respect to generating a digital output signal of the delay line ADC circuitry near a threshold level.

[0037] These and other more specific examples are disclosed in greater detail below.

[0038] As discussed herein, the techniques herein are well suited for use in the field of analog-to-digital conversion, such as implementing corresponding delay line analog-to-digital converters. However, it should be noted that the examples herein are not limited to use in such applications, and the techniques discussed herein are also well suited for other applications.

[0039] Additionally, it is noted that while each of the various features, techniques, configurations, etc. herein may be discussed at various locations throughout this disclosure, it is intended that each of the concepts may optionally be implemented independently of one another or in combination with one another, where appropriate. Thus, one or more of the present inventions described herein may be implemented and viewed in many different ways.

[0040] Furthermore, it is noted that this preliminary discussion of examples herein (a brief description of the examples) is not intended to specify every example and / or progressively novel aspect of the present disclosure or the claimed invention. Rather, this brief description merely presents general examples and corresponding points of novelty relative to conventional techniques. For additional details and / or possible viewpoints (arrangements) of the present invention, the reader is referred to the Detailed Description of the Disclosure (which is a summary of the examples) and the corresponding figures, as further discussed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is an example diagram of a tracking ADC system as discussed herein.

[0042] Figure 2 is an example diagram illustrating a more detailed tracking ADC system including calibration circuitry as discussed herein.

[0043] Figure 3 is an example diagram illustrating a tracking ADC circuit as discussed herein.

[0044] Figure 4A and Figure 4B is an example diagram illustrating a voltage-to-time converter (signal generator), delay line ADC circuitry, and corresponding calibration circuitry as discussed herein.

[0045] Figure 5Ais an example top-level diagram showing a delay line ADC as discussed herein.

[0046] Figure 5B is an example timing diagram showing signals associated with a delay line ADC as discussed herein.

[0047] Figure 6 is an example diagram showing a current-starved inverter as discussed herein.

[0048] Figure 7 is an example diagram showing equations associated with a current-starved inverter implemented in an analog-to-digital converter as discussed herein.

[0049] Figure 8 is an example diagram showing a voltage-to-time converter as discussed herein.

[0050] Figure 9 is a timing diagram showing calibration and analog signal conversion of a delay-locked loop as discussed herein.

[0051] Figure 10 is an example diagram showing taps associated with a calibration gain as discussed herein.

[0052] Figure 11 is an example diagram showing an implementation of a selector circuit for calibration in signal conversion within a corresponding tracking loop as discussed herein.

[0053] Figure 12 is an example diagram of a charge pump as discussed herein.

[0054] Figure 13 is an example diagram showing a raw phase frequency detector as discussed herein.

[0055] Figure 14 is an example timing diagram associated with a raw phase frequency detector as discussed herein.

[0056] Figure 15 is an example diagram of a programmable phase frequency detector as discussed herein.

[0057] Figure 16 is an example timing diagram of a programmable phase frequency detector as discussed herein.

[0058] Figure 17 is an example simulation diagram associated with range adjustment of UP and DOWN pulses as discussed herein.

[0059] Figure 18 is an example timing diagram showing calibration for error removal as discussed herein.

[0060] Figure 19is an example detailed diagram of a tracking ADC as discussed herein.

[0061] Figure 20 is an example timing diagram associated with the auxiliary DAC as discussed herein.

[0062] Figure 21A 、 Figure 21B and Figure 21C is an example diagram illustrating a delay line ADC including circuitry as discussed herein.

[0063] Figure 22 is an example diagram illustrating a method according to examples herein.

[0064] The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred examples thereof, as illustrated in the accompanying drawings, in which like reference numerals refer to like parts throughout the different views. The drawings are not necessarily drawn to scale, emphasis instead being placed upon illustrating examples, principles, concepts, etc. DETAILED DESCRIPTION

[0065] Now, more specifically, Figure 1 is an example overview diagram showing a tracking ADC implementing a delay line ADC as discussed herein.

[0066] Typically, in this example, Figure 1 The tracking ADC system 100 shown in FIG. 1 converts an input voltage signal 121 (eg, an analog input voltage signal) into a corresponding digital output signal 139 . The digital output signal 139 tracks the magnitude of the input voltage signal 121 .

[0067] More specifically, to convert the input voltage signal 121 into the output signal 139, the analog input voltage 121 is subtracted from the DAC output signal 126 (which is an analog representation of the digital output 139) generated by the digital-to-analog converter 150 via the differencing function 124. The output signal 126 is a stored version of the ADC output 139 from the previous cycle. The differencing function 124 generates an analog error voltage signal 125, which is the analog input signal 121 (e.g., "Vin") minus the DAC output signal 126. The delay line ADC 110 converts the analog error voltage signal 125 (also referred to as vsig) into a digital error signal 127. The delay line ADC 110 outputs the digital error signal 127 to the sampling function 130.

[0068] The sample function module 130 outputs samples of the digital error signal 127 as a digital error signal 127-1 to an accumulator function module 135. The accumulator function module 135 includes an adder 115 and a storage resource 116 (storing a previous sample of the digital output 139). Upon receiving a new sample 127-1 (e.g., an error correction value, which as discussed herein can be a positive or negative value), the accumulator function module 135 adds the previous sample of the digital output 139 to the current sample 127-1 and outputs from the accumulator function 135 module to produce a new digital output 139.

[0069] In this way, the delay line ADC 110 outputs a digital error signal 127 (a positive or negative error value) which is added via the accumulator function module 135 to the previous cycle output 139 of the ADC to create a new output 139 of the ADC.

[0070] As further shown, the continually updated digital output 139 is fed to a digital to analog converter 150 for conversion again to the output signal 126.

[0071] In this example, if the tracking ADC system 100 were to implement a comparator-based analog to digital converter function (rather than the delay line ADC 110), the corresponding ADC would thus be limited to increment / decrement its output 127 by the range and resolution of the loop comparators. For a single comparator, the step size would be limited to + / - 1 code, while for multiple loop comparators, the step size is set by the number of comparators and the resolution of the comparator threshold spacing.

[0072] However, the tracking analog to digital converter system 100 as discussed herein advantageously implements a delay line analog to digital converter 110 to provide an improved and more accurate circuitry over conventional techniques.

[0073] Thus, in one example, the delay line analog to digital converter 110 is operable to convert an analog error voltage (125 or signal) to a digital error voltage signal 127; the accumulator function module 135 is operable to produce a digital value 139 representing the analog input voltage 121, wherein the digital value 139 is adjusted based on samples of the digital error voltage signal 127 generated by the delay line analog to digital converter 110; and the digital to analog converter 150 is operable to convert the digital value 139 received from the accumulator function module 135 to a second analog voltage 126, the analog error voltage 125 being the difference between the input voltage 121 and the second analog voltage 126.

[0074] Figure 2 is an example diagram showing a tracking ADC circuit implementing a calibration function as discussed herein.

[0075] In this example, the tracking ADC system 100 includes a voltage-to-time converter 210, a calibration circuit 221, and a calibration circuit 222. The tracking ADC system 100 operates in a similar manner as previously discussed. Additionally, however, the calibration circuit 221 provides a first calibration control feedback 106 (e.g., an offset adjustment signal) to the voltage-to-time converter 210. The calibration circuit 222 provides a calibration control feedback 107 (e.g., a gain adjustment signal) to the voltage-to-time converter 210.

[0076] As the name implies, the voltage-to-time converter 210 is operable to receive the analog error voltage signal 125 from the difference function module 124. As previously discussed, the delay line ADC 110 is operable to convert the analog error voltage signal 125 into a corresponding digital error signal 127. In this example, the voltage-to-time converter 210 generates one or more corresponding control signals 105 to control the operation of the delay line ADC 110 and the timing of the conversion of the analog error voltage signal 125 into the digital error signal 127.

[0077] Further, the tracking ADC system 100 can also be configured to include the calibration circuit 221 to provide offset calibration associated with the voltage-to-time converter 210 based on the feedback 106. The tracking ADC system 100 also includes the calibration circuit 222 to provide gain calibration associated with the voltage-to-time converter 210 based on the feedback 107. Figure 4A and Figure 4B Further details of the calibration circuitry are shown in FIGS. 1-3.

[0078] Referring again to Figure 2 As further discussed herein, it is noted that the calibration of the voltage-to-time converter 210 and the delay line ADC 110 (via the feedback 107 and the feedback 106) supports more accurate conversion of the analog error signal 125 into the digital error signal 127.

[0079] Accordingly, an apparatus or system as discussed herein includes delay line analog-to-digital converter circuitry 110, signal generator circuitry such as voltage-to-time converter 210, and calibration circuitry 221 / 222. The signal generator circuitry (e.g., voltage-to-time converter or other suitable entity) can be coupled to the delay line analog-to-digital converter circuitry 110. The signal generator circuitry 210 can be configured to generate control signals 105 (e.g., start signals and stop signals, etc.) for controlling operation of the delay line analog-to-digital converter circuitry 110 based on a calibration signal or analog voltage 125 received by the signal generator circuitry for conversion to digital signals 127. Moreover, the calibration circuitry 221 / 222 can be configured to calibrate the signal generator circuitry based on calibration feedback (e.g., calibration feedback 106 and calibration feedback 107 such as adjustment signals) to ensure accurate operation of converting instances of the received analog voltage 125 to corresponding samples of the digital signals 127.

[0080] Further examples as discussed herein include implementing delay line analog-to-digital converter circuitry 110 in a tracking analog-to-digital converter circuit 100. The delay line analog-to-digital converter circuitry 110 can be configured to convert an analog voltage 125 received by the voltage-to-time converter 210 to a first digital signal 127 indicative of a magnitude of the analog voltage 125. It is also noted that the analog voltage 125 can be a first analog voltage. The first analog voltage received by the signal generator (voltage-to-time converter 210) can be an analog error voltage representing a difference between the analog input voltage 121 and a second analog voltage 126 generated by the digital-to-analog converter 150. The second analog voltage 126 can be derived by the digital-to-analog converter 150 from a second digital signal 139, where the second digital signal 139 is derived from the first digital signal 127. In this case, the second digital signal 139 is indicative of a magnitude of the analog input voltage 121.

[0081] As further discussed herein, the selector 410 can be configured to apply any one of the analog voltage 125, reference voltage VR1, reference voltage VR2, reference voltage VR3, etc. signals. Additional details of using these signals are discussed below.

[0082] Figure 3 is an example overall diagram illustrating a tracking ADC implementing a delay line ADC operable to support current sensing as discussed herein.

[0083] In this example, the tracking ADC 100 includes respective novel implementations of the delay line ADC circuit 110 as compared to conventional techniques.

[0084] For example, the error sensing tracking and compensation loop associated with the tracking ADC system 100 includes voltage source 405, resistor Rl, resistor R2, amplifier 411, amplifier 412, voltage source 414, transistor T411, transistor T412, resistor R3, resistor R4, delay line digital-to-analog converter 110, digital-to-analog converter 150, buffer 431, buffer 432, converter function module 310 (e.g., a thermometer to binary converter function module), accumulator function module 135, etc.

[0085] Generally, the digital-to-analog converter 150 in this example controls the sink of current (also referred to as output current) relative to the error sensing circuitry. As shown, the error sensing circuitry receives an input signal 121, e.g., the difference between a signal ISEN (also referred to as Vin) at node Nl and a signal IREF (also referred to as a ground reference) at node N2. The voltage across node Nl and node N2 represents a differential voltage converted by an analog-to-digital converter as discussed herein. For example, the digital output signal 139 is a digital value indicative of the magnitude of the corresponding input voltage or signal received across node Nl and node N2.

[0086] As further shown, the delay line ADC 110 receives the error signal 125 as a differential signal, e.g., the difference between a signal von and a signal vop, which represents a sample of a differential voltage (error voltage 125).

[0087] Further, in this example, the delay line ADC 110 produces a corresponding error signal 127-0, e.g., a digital signal. In one example, the error signal 127-0 is encoded according to a thermometer code. The system as discussed herein also includes a converter 310 operable to convert the error signal 127-0 via the thermometer code to a corresponding error signal 127 encoded according to a standard binary code, for example. As previously discussed, the error signal 127 is supplied to the accumulator function module 135.

[0088] Ideally, the error signal 127-0 and the error signal 127 are zero if the digital-to-analog converter 150 is set to the appropriate setting via the digital output signal 139. In this case, the current from the voltage source 405 through Rl is equal to the current from the voltage source 405 through R2. However, when the current through resistor Rl and resistor R2 is not balanced, the delay line ADC 110 produces a corresponding non-zero error signal 127-0. The error signal 127-0 and the error signal 127 can be a positive or negative value generated by the delay line analog-to-digital converter circuitry 110. In response to the size of the sample of the error signal 127, the accumulator function module 135 adjusts the digital output signal 139 up or down so that the error signal 127 is biased toward zero over multiple sampling periods. This supports accurate conversion of the analog input voltage signal 121 (e.g., the voltage across nodes Nl and N2) to the digital output signal 139.

[0089] Thus, in one example:

[0090] • The input buffer drives current into the tracking loop.

[0091] • The input voltage 121 is converted to an input current and subtracted from the DAC code.

[0092] • The difference between the input current and the DAC current is amplified through regulated cascodes to an error voltage (vop-von) that is digitized as the error signal 127.

[0093] In one example, the advantages of the novel tracking ADC 100 with the delay line ADC 110 as discussed herein are as follows:

[0094] • The 5-bit delay line ADC 110 can be replaced with an equivalent of 32 comparators instead of the otherwise implemented comparator bank of 9 comparators while still saving area and power and increasing the bandwidth of the tracking loop.

[0095] • The delay line ADC 110 can implement a larger range and smaller resolution of the error voltage for better transient tracking.

[0096] • The delay line ADC 110 can digitize a + / - 16mV range with 1mV resolution

[0097] • The delay line ADC 110 can be designed to have low input impedance to maximize the tracking loop bandwidth.

[0098] • The conversion time of the delay line ADC 110 = 2.5ns, which is the smallest possible clock segment, enabling the ISADC to run at the fastest speed (7.5ns setup time)

[0099] • Area comparison:

[0100] o DLFLASH, equivalent to 32 comparators: 13336 um 2 .

[0101] o 9 comparator groups: 19888 um 2 .

[0102] • Equivalent power at same speed

[0103] o Delay line converts at 2.5 ns and uses 1.3 mA.

[0104] o Equivalent 32 comparators would use 6.5 mA of current.

[0105] Figure 4A and Figure 4B is an example overview showing block diagrams associated with a delay line ADC and corresponding calibration functionality as discussed herein.

[0106] In this example, with reference to Figure 4A and Figure 4B and other drawings, the tracking ADC includes a selector functionality module 410, delay line analog-to-digital converters 110 (e.g., including delay line analog-to-digital converter 110-1 and delay line analog-to-digital converter 110-2), a voltage-to-time converter 210 (controller for the delay line ADC 110), a calibration circuit 221, and a calibration circuit 222.

[0107] The controller 140-2 or other suitable entity generates one or more control signals, e.g., including the signal dl_sig_sel (see also Figure 9 ), for controlling the switches SO, SI, S2, and S3.

[0108] As the name implies, and as previously discussed, the selector functionality module 410 controls which of a plurality of different voltages is input to the voltage-to-time converter 210. For example, in accordance with Figure 9The signal dl_sig_sel, shown in the middle, selects the switch and control select function module 410 to switch between inputting a reference voltage VR1 (e.g., 16 millivolts DC or other suitable value), a reference voltage VR2 (e.g., a ground reference voltage or 0 millivolts during a suitable value), a reference voltage VR3 (e.g., 16 millivolts DC or other suitable value), and an analog error voltage 125 (any signal of interest). In other words, the control selector function module 410 changes which one of the different reference voltages VR1 (channel 1 associated with switch S1), VR2 (channel 3 associated with switch S3), VR3 (channel 2 associated with switch S2), or the analog error voltage 125 (e.g., channel 0 associated with switch S0) is input to the voltage-to-time converter 210 for conversion to a corresponding output digital error signal 127 (e.g., a multi-bit value generated by the Q outputs of the first set of D flip-flops D11, D12,..., D1N or the second set of D flip-flops D21, D22,..., D2N).

[0109] As further shown, the voltage-to-time converter 210 includes an amplifier Al. The amplifier Al includes an inverting input to receive a differential voltage associated with the channel selected by the selector function module 410 at input Vinn and a non-inverting input to receive input Vinp.

[0110] As previously discussed, the selector function module 410 controls which one of the different reference voltages VR1, VR2, VR3, or the analog error voltage 125 is input to the voltage-to-time converter 210.

[0111] Further, the positive output of the amplifier Al produces a signal Kl to drive a current-starved inverter Zl. The negative output of the amplifier Al produces a signal K2 to drive a current-starved inverter Z2. The current-starved inverter Zl receives a clock signal clk_200_n as an input.

[0112] Additionally, the output K3 of the transconductance amplifier A2 provides offset calibration of the amplifier Al. As further shown, the voltage-to-time converter 210 also receives a clock signal CLK that is input to each of the current-starved inverter Zl and the current-starved inverter Z2. The current-starved inverter Z2 receives a clock signal clk_200_n as an input.

[0113] The current-starved inverter Zl produces an output signal voutp (voltage) that is stored in a capacitor C3 and supplied to an inverter I3.

[0114] The current-starved inverter Z2 produces an output signal voutn that is stored in capacitor C4 and supplied to inverter I4.

[0115] As further shown, inverter I3 receives signal voutp and inverts it to produce a corresponding control signal 105-1 that is applied to node N41. Signal 105-1 at node N41 is a start signal for delay line ADC 110-1. Signal 105-1 at node N41 is a stop signal for delay line ADC 110-2.

[0116] Inverter I4 receives signal voutn and inverts it to produce an output control signal that is applied to node N42. Signal 105-2 at node N42 is a start signal for delay line ADC 110-2. Signal 105-2 at node N42 is a stop signal for delay line ADC 110-1.

[0117] Referring to Figure 4B Delay line ADCs 110-1 and 110-2 each include a sequence of multiple D flip-flops connected in series to produce a respective digital error signal 127-0. The digital output of each delay line analog-to-digital converter circuitry 110 represents a corresponding magnitude of the differential voltage selected by selector function module 410.

[0118] For example, delay line ADC 110-1 (top delay line ADC) includes flip-flop D11, flip-flop D12,..., and flip-flop D1N. Each of the D flip-flops in delay line ADC 110-1 is clocked by the stop signal 105-2 at node N42. The signal (e.g., clock pulse or signal edge) at node N41 passes through each of the delay elements (labeled delta) according to aspects of the manner associated with each delay element, which provides an input to the respective D input of the respective D flip-flop. Overall, in one example, for a given input voltage to voltage-to-time converter 210, delay line ADC 110-1 produces a top 18 bits (e.g., positive output value), e.g., top digital output bits 17:0 such as vout_top<17..0>. Clock signal clk_200 (inversion of clock signal clk_200_n) resets each of the D flip-flops in analog-to-digital converter circuit 110-1.

[0119] The delay line ADC 110-2 (bottom delay line ADC) includes a flip-flop D21, a flip-flop D22,... and a flip-flop D2N. Each D flip-flop in the delay line ADC 110-2 is clocked by the stop signal at node N41. The signal at node N42 is passed through each of the delay elements (labeled delta), which provide input to the respective D input of the respective flip-flop. Overall, for a given input voltage to the voltage-to-time converter 210, the delay line ADC 110-2 produces a bottom 18 bits (for negative output values), e.g., a bottom digital output bit 17:0 such as vout_bot<17..0>. The clock signal clk_200 (inversion of the clock signal clk_200_n) resets each D flip-flop in the analog-to-digital converter circuit 110-2.

[0120] Thus, Figure 4A The input voltages (vinn and vinp) supplied to the voltage-to-time converter 210 are converted by the voltage-to-time converter 210 into a time difference represented by the delay between the start rising edge and the stop rising edge at the respective nodes N41 and N42. This delay is quantified by the delay line analog-to-digital converter circuitry to produce respective digital outputs representing the magnitude of the differential input voltage input to the amplifier Al at the nodes vinn and vinp. Thus, the delay line analog-to-digital converter circuitry 110 converts the differential voltage vinn and vinp into respective sampled digital output signals 139 produced by the respective delay line analog-to-digital converter system 110.

[0121] In one example, note that the top delay line and the bottom delay line fold around the 0 mV error (reference voltage VR2). As previously discussed, the start signal and the stop signal input to the respective delay line ADC 110-1 and 110-2 are exchanged (at node N41 and node N42). Additionally, the bottom delay line ADC 110-2 will digitize the negative range associated with the delay line ADC 110, while the top delay line ADC 110-1 will digitize the positive range associated with the delay line ADC 110. Thus, the delay line analog-to-digital converter circuit 110-1 produces positive digital output values 127 when the magnitude of the differential voltage received by the amplifier Al is positive; the delay line analog-to-digital converter circuit 110-2 produces negative digital output values 127 when the magnitude of the differential voltage received by the amplifier Al is negative.

[0122] As further shown, and as previously discussed, Figure 4A and Figure 4B The circuitry shown in FIGS. 1-2 can be configured to include a plurality of delay locked loops (e.g., calibration circuit 221 and calibration circuit 222) that control the resolution of the delay line ADC 110 over process, voltage, temperature, and aging.

[0123] As further discussed herein, a delay locked loop (DLL) controls error from both the voltage-to-time converter 210 and each of the delay line ADCs associated with the delay line ADC 110.

[0124] Further, as described by other figures discussed herein, the delay line ADC 110 and corresponding circuitry describes how to alternate converting a real input signal (e.g., an analog error voltage signal 125 or other signal) and calibrating gain associated with the current starved inverter and offset associated with the amplifier Al, for example, when the rest of the tracking loop is stable.

[0125] In one example, the delay line analog-to-digital converter circuitry includes a first delay line analog-to-digital converter circuit 110-1 and a second delay line analog-to-digital converter circuit 110-2 arranged in parallel to convert a received analog voltage (e.g., a differential voltage as indicated by vinn and vinp) into corresponding samples of a digital output signal.

[0126] As further discussed herein, the received analog voltage (vinn and vinp) can be supplied by a selector circuit 410 (e.g., a multiplexer circuit), where different types of analog voltage signals are input to the signal generator circuit (voltage-to-time converter 210) for conversion into respective samples of the digital signal 127-0.

[0127] In yet another example, as previously discussed, the first delay line analog-to-digital converter circuit 110-1 of the delay line analog-to-digital converter circuitry 110 is operable to generate a first portion of corresponding samples for a first operating condition in which the analog voltage is greater than a threshold level (e.g., for positive values); and the second delay line analog-to-digital converter circuit 110-2 of the delay line analog-to-digital converter circuitry 110 is operable to generate a second portion of corresponding samples during a second operating condition in which the received analog voltage at the input of the amplifier Al is less than the threshold level (for negative values).

[0128] Additionally, note that as discussed herein, the control signals can be configured to include a first control signal (e.g., a voltage at node N41) and a second control signal (e.g., a voltage at node N42). The first control signal can be configured to control a start operation of the first delay line analog-to-digital converter circuit 110-1; the second control signal can be configured to control a stop operation of the first delay line analog-to-digital converter circuit 110-1. The second control signal can be configured to control a start operation of the second delay line analog-to-digital converter circuit 110-2; the first control signal can be configured to control a stop operation of the second delay line analog-to-digital converter circuit 110-2.

[0129] According to other examples discussed herein, the apparatus can be configured to include a selector circuit system 410 operable to select between a first output signal X1 generated by the first delay line ADC circuit 110-1 and a second output signal X2 generated by the second delay line ADC circuit 110-2. The calibration circuit 222 can be configured to use the first signal X1 and the second signal X2 as a basis for calibrating the signal generator circuit system and / or the delay line ADC circuit system.

[0130] According to another example, the calibration circuit 222 may be configured to include a gain calibration loop, wherein the gain associated with the delay line ADC circuitry 110 is configured to match a gain setting of a tracking loop associated with the tracking ADC circuitry.

[0131] Furthermore, it is noted that the signal generator circuit (voltage-to-time converter 210) can be configured to include an amplifier A1 operable to receive an analog voltage (differential voltages vinn and vinp). The calibration circuitry discussed herein can be configured to include an offset calibration circuit 221 operable to monitor control signals input to the delay line ADC circuitry 110 at nodes N41 and N42. The offset calibration circuit 221 can also be configured to generate an offset adjustment control signal J1 based on the control signals input to the delay line ADC circuitry monitored at nodes N41 and N42. The offset adjustment control signal J1 adjusts the offset associated with amplifier A1. For example, transconductance amplifier A2 receives calibration signal J1 and converts it into an output signal supplied by transconductance amplifier A2 to correct the offset associated with amplifier A1.

[0132] In one example, the offset calibration circuit 221 is an offset delay locked loop circuit operable to generate an offset adjustment control signal J1 and a corresponding output signal of a transconductance amplifier A2 that is supplied to the amplifier A1 .

[0133] In another example, as previously discussed, the signal generator circuit (voltage-to-time converter 210) may include an amplifier A1 operable to receive an analog voltage (eg, the difference between vinn and vinp). Figure 4BThe calibration circuitry shown in FIG. 2 can be configured to include a gain calibration circuit 222 operable to monitor digital samples output from the delay line analog-to-digital converter circuitry 110. The gain calibration circuit 222 can be configured to generate a gain adjustment control signal G1 (at node N49) based on the output digital samples of the delay line analog-to-digital converter circuitry, where the generated gain adjustment control signal G1 (e.g., a voltage stored in capacitor C1) adjusts the gain associated with the amplifier that subsequently converts other samples of the received analog voltage into a control signal. Again, note that the gain adjustment control signal G1 can be generated based on the output digital samples of the delay line analog-to-digital converter circuitry 110-1 and / or 110-2. Figure 4B As shown in FIG. 2, the gain calibration circuit 222 can be configured to include a gain delay locked loop circuit.

[0134] According to another example as discussed herein, the delay line analog-to-digital converter circuit 110 can be configured to include a first delay line analog-to-digital converter 110-1 operable to generate positive polarity error values associated with converting the received analog voltage (vinn and vinp) into a digital signal and a second delay line analog-to-digital converter 110-2 operable to generate negative polarity error values associated with converting the received analog voltage into a digital signal.

[0135] In another example, the signal generator circuit is a voltage-to-time converter 210 operable to produce a start signal (voltage at node N41) and a stop signal (voltage at node N42) supplied to the delay line analog-to-digital converter circuit 110-1, where the magnitude of the duration between the start signal and the stop signal depends on the magnitude of the analog voltage received at the input of the amplifier Al. The calibration circuit 221 can be configured to calibrate the voltage-to-time converter 210 based on calibration feedback (e.g., voltages monitored at nodes N41 and N42) in a manner as previously discussed.

[0136] Further, the apparatus as discussed herein can be configured to include a selector circuit 410 operable to select among a plurality of analog inputs that are inputted to the signal generator as the analog voltage. For example, the selector circuit can be configured to select among: i) a first analog gain reference voltage VR1, ii) a second analog gain reference voltage VR3, iii) an offset reference voltage VR2, and iv) the analog error voltage 125.

[0137] As discussed herein, the analog voltage 121 received and converted into the digital signal 127 produced by the delay line analog-to-digital converter circuitry 110 can be: i) a first analog gain reference voltage, ii) a second analog gain reference voltage, iii) an offset reference voltage, or iv) an analog error voltage. In one example, the calibration circuitry (221 and / or 222) is operable to generate calibration feedback (e.g., gain adjustment control signal G1, offset adjustment signal J1, etc.) based on analog-to-digital conversion of the first analog gain reference voltage, the second analog gain reference voltage, and the offset reference voltage made at different times during an analog-to-digital conversion cycle.

[0138] Note that the calibration circuitry can be configured to include a gain calibration circuit 222 and an offset calibration circuit 221. As discussed herein, the gain calibration circuit 222 can be operable to generate a gain calibration signal G1 supplied to the signal generator circuit 210 based on analog-to-digital conversion of a first analog gain reference voltage made at a first time during an analog-to-digital conversion cycle and analog-to-digital conversion of a second analog gain reference voltage made at a second time during the analog-to-digital conversion cycle. The offset calibration circuit 221 can be operable to generate an offset calibration signal J1 supplied to the signal generator circuit 210 based on analog-to-digital conversion of an offset reference voltage made at a third time during the analog-to-digital conversion cycle. Figure 4A and Figure 4B As shown in FIGS. 4A and 4B, the gain calibration circuit 222 can include a first set of charge pumps CP1 and CP2 to generate a gain calibration signal G1 supplied to the signal generator circuit 210. The gain calibration signal G1 calibrates a gain associated with the signal generator circuit 210. The offset calibration circuit 221 can include a second set of charge pumps CP3 and CP4 to generate an offset calibration signal J1 supplied to the signal generator circuit 210. The offset calibration signal J1 calibrates an offset associated with the signal generator circuit 210. As discussed herein, the apparatus can also include: i) a first pulse width calibration circuitry 440-2 operable to adjust a pulse width of first pulse width modulation signals PWM1 and PWM2 applied to the first set of charge pumps CP1 and CP2 to calibrate the first set of charge pumps and a corresponding first phase frequency detector (also referred to as 222) based on an output of the delay line analog-to-digital converter circuitry in a calibration mode, and ii) a second pulse width calibration circuitry 440-1 operable to adjust a pulse width of second pulse width modulation signals PWM3 and PWM4 applied to the second set of charge pumps CP3 and CP4 to calibrate the second set of charge pumps and a second phase frequency detector (also referred to as 221) based on an output of the delay line analog-to-digital converter circuitry 110 in the calibration mode. The first pulse width calibration circuitry operates to adjust a pulse width of first pulse width modulation signals applied to the first set of charge pumps and the phase frequency detector to calibrate the first set of charge pumps and the phase frequency detector based on an output of the delay line analog-to-digital converter circuitry;

[0139] In one example, wherein the adjustment of the pulse width of the first pulse width modulation signals reduces charge pump errors and phase frequency detector errors associated with the first set of charge pumps and the phase frequency detector; the adjustment of the pulse width of the second pulse width modulation signals reduces charge pump errors and phase frequency detector errors associated with the second set of charge pumps and the phase frequency detector.

[0140] Figure 5A is an example diagram of a delay line ADC as discussed herein.

[0141] Delay line operation

[0142] Figure 5A A schematic diagram of respective delay line analog-to-digital converters 110-1 and 110-2 is shown in FIG. 11. As previously discussed, the respective delay line analog-to-digital converters convert the time domain signals received from nodes N41 and N42 into corresponding digital codes, e.g., error signals 127.

[0143] Each delay line analog-to-digital converter includes a chain of delay cells represented by buffers with a delay value of δ seconds. The delay value delays the propagation of the respective 1 or 0 input to the delay line analog-to-digital converter from node N41 or node N42.

[0144] Each output of the buffers is connected to a flip-flop clocked by the stop signal.

[0145] The delay line operates by digitizing the difference between the start-up rising edge delay and the stop rising edge delay to convert the respective input voltage received at vinn and vinp into a respective digitized error signal 127 stored in the D flip-flops of the delay line analog-to-digital converter circuitry 110.

[0146] Each flip-flop in the chain of D flip-flops in each of the different delay line analog-to-digital converter circuitry 110 acts as a comparator that outputs a 1 if the start signal in the delayed version is faster than the stop signal.

[0147] The delay line outputs a thermometer encoded signal of tsig / δ.

[0148] Figure 5B is a timing diagram associated with generating respective control signals from the voltage-to-time converter output to control the operation of a delay line ADC as discussed herein.

[0149] As shown in this example, the voltage-to-time converter 210 produces a rising edge of the start control signal from node N41 to occur at time T51. The voltage-to-time converter 210 produces a rising edge of the stop signal from node N42 to occur at time T52. The time difference between times T51 and T52 is tsig.

[0150] The logic 1 associated with the start signal from node N41 is passed through the delay line analog-to-digital converter 110-1 to produce a logic 1 at the output of the delay line analog-to-digital converter 110-1 at time T53. Figure 5A ​The series of delay elements shown in the middle are transferred. The delay time associated with each of the delay elements is the value δ. At time T51, the delay line analog-to-digital converter 110, depending on the signal polarity of the received error signal 125, sets the bits of the D flip-flops of the delay line analog-to-digital converter circuit 110-1 or 110-2 based on vout<0> = 1, vout<1> = 1, vout<2> = 1,..., vout<tsig / δ-1> = 0, vout<tsig / δ> = 0,..., vout <n-3>= 1, vout <n-2>= 0, vout <n-1>= 0 (e.g., Q output of D flip-flop D11, D12,..., D1N or Q output of D flip-flop D21, D22,..., D2N) to generate a corresponding error signal 127.

[0151] Thus, Figure 5A A delay line analog-to-digital converter is shown in FIG. 2, and the corresponding voltage-to-time converter 210 converts a received analog input voltage into a corresponding digital error signal 127 (digital output signal) based on the above-described setting of bits used to convert the respective analog voltage into a digital value (e.g., Q output of D flip-flop D11, D12,..., D1N or Q output of D flip-flop D21, D22,..., D2N).

[0152] Of course, since the size of tsig varies depending on the size of the input voltage supplied at nodes vinn and vinp, e.g., one of the reference voltages VR1, VR2, VR3 or the analog error voltage 125 selected by the selector 410, the delay line analog-to-digital converter 110 generates a corresponding digital error signal 127 that is proportional to the input voltage vinn and vinp.

[0153] Figure 6 is an example diagram showing a so-called current-starved inverter as discussed herein.

[0154] As previously discussed, the voltage-to-time converter 210 can be configured to include one or more current-starved inverters Z1 and Z2. Figure 6 is an example of a current-starved inverter Z1 that receives a clock CLK as an input signal to generate a corresponding output signal voutp. The current-starved inverter Z2 is identical to the current-starved inverter Z1, the current-starved inverter Z2 receives a clock CLK (clk_200_n) as an input signal to generate a corresponding output signal voutn.

[0155] The control voltage V G (e.g., signal K1) modulates the current through the inverter, and thus the propagation delay (tpn) between the input falling clock edge of the signal CLK (clk_200_n) and the output falling clock edge of the signal CLK (note that the rising edges are not affected).

[0156] Transistor M D The inverter is provided with a minimum amount of current, which results in better linearity but a smaller range.

[0157] As discussed herein, the delay-locked loop (e.g., gain or offset) associated with the calibration circuit 221 / 222 uses a transistor M D The gain is modulated over process corner / temperature / age.

[0158] The differential CSI stage employs two CSI (current starved inverter) stages, e.g., Z1 and Z2, whose difference, where the differential voltage input is around the input common mode voltage.

[0159] The CSI input common mode must operate at the best point to maximize the range.

[0160] The signal tsig becomes the difference of two falling edges (voutp and voutn) from the repetitive CSI stage, which makes the linearity better since the shape of the edges is the same.

[0161] The differential CSI stage has twice the range for the same linearity performance and the same control voltage operating region.

[0162] The slew rate formula for the current starved inverter output:

[0163] - (dV_out) / dt = (i_(d_N) + i_(d_D)) / C_L

[0164] As previously discussed, the gain calibration circuit 222 generates a corresponding adjustment signal Gl to control the slew rate associated with the current starved inverters Z1 and Z2. Adjustment of the slew rate ensures that the input voltage at the amplifier Al is properly converted to the corresponding digital output voltage from the delay line analog-to-digital converter circuitry 110. For example, the slew rate adjustment supported by the gain adjustment signal Gl ensures that the delay line analog-to-digital converter circuitry 110 produces the appropriate digital output values for each of the calibration voltages VR1, VR2, and VR3. Calibration of the circuitry for these reference voltages ensures that the conversion of the analog signal 125 (VSIG) is as accurate as possible.

[0165] Figure 7 is an example diagram illustrating an equation associated with a current starved inverter as discussed herein.

[0166] Figure 8 is an example diagram illustrating an implementation of a voltage-to-time converter as discussed herein.

[0167] The voltage-to-time converter 210 can be configured to have a low input impedance front end open loop amplifier to maximize the bandwidth of the tracking loop with a nominal gain of about 6 or other suitable value. The impedance can be minimized by selecting the smallest size devices for Mp1 and Mp2, since their mismatch generated offset will be canceled by the adjustment signal generated by the transconductance amplifier A2 associated with the offset delay locked loop (calibration circuit 221).

[0168] The current to the inverters Z1 and Z2 can be modulated with the differential output of the front end.​

[0169] In addition, the VTC 210 also converts the voltage from the 3.3V domain to the 1.2V domain.

[0170] If needed, the range / resolution of the flash delay line ADC can be increased by reducing the gain of the open loop front end amplifier. Bandwidth requirement for the CSI stage front end: must meet the requirement due to the DLL (Delay Locked Loop) switching between signal and calibration max.

[0171] 5τ < 5ns (for 100Mhz VSADC) -> f 3dB > 1 / (2*π*(1ns)) > 159Mhz

[0172] MP3 and MP4 differential pairs adjust the total offset of the delay line flash by adjusting the offset of the CSI input.

[0173] Iadjust is used to correct the offset of the entire VTC + delay line chain.

[0174] The input pmos differential pair has the most impact on the offset.

[0175] The total offset is 250ps, which is the range that needs to be accommodated by the offset loop.

[0176] Dynamic flip-flop

[0177] It is also noted that for the flip-flops in the delay line ADC circuitry 110, so-called dynamic flip-flops can be implemented.

[0178] Dynamic flip-flops can provide negative setup time, where the clock can arrive slightly before the data.

[0179] This is a desirable feature to capture the 0mV error voltage crossing and avoid dead zone of the ADC.

[0180] The flip-flops are placed at the zero crossing to have higher resolution around 0 error voltage. When start and stop are perfectly aligned with each other, both the first flip-flops of the top delay line and the bottom delay line will output 1. All other flip-flops will output 0.

[0181] In summary, the four flip-flops can provide information about the error voltage being close to 0 in steady state and determine how to step the tracking ADC.

[0182] Encoding of the DLADC (delay line ADC 110)

[0183] The encoding of the delay line ADC 110 is shown in Table 1.

[0184] The top delay line (delay line ADC 110-1) and the bottom delay line (delay line ADC 110-2) have separate output buses.

[0185] The flip-flops are added 0 input signals, so there is no dead zone area around zero.

[0186] There will be redundancy in the vout_top<0> and vout_bot<0> outputs, as they both capture the intermediate crossing.

[0187] The flip-flops used have a slightly negative setup time (-2.8 ps), which varies with process and mismatch, but is always negative.

[0188] The added bits should give us more flexibility in how the ADC can step.

[0189] The step size of the ISADC can be changed based on the four combinations of vout_top<0> and vout_bot<0>.

[0190] If they are both 1, it means the signal was between 0 mV + / - setup time of the flip-flop (between -150 uV and 150 uV)

[0191] Table 1

[0192]

[0193]

[0194] The delay line ADC circuitry 110 as discussed herein can include a first D flip-flop and a second D flip-flop as previously discussed. The first D flip-flop in the first delay line ADC circuit 110-1 and the second D flip-flop in the second delay line ADC circuit 110-2 can be implemented to have a negative setup time to provide overlap with respect to producing a digital output signal of the delay line ADC circuitry 110 around a threshold level of 0 volts.

[0195] Figure 9 is an example diagram showing calibration and converter operation of an interleaved delay line ADC as discussed herein.

[0196] Calibration sequence using a delay locked loop

[0197] Ideally, the clock signal and the output of the last buffer in the delay line ADC should be perfectly aligned when the input is at the maximum value.

[0198] The delay locked loop switches between the calibration phase and normal operation, where the tracking loop output is digitized. Figure 9 A timing diagram illustrating a dlflash calibration scheme associated with the operation of the delay line analog-to-digital converter circuitry 110 is shown. Figure 11 Further details of the selector 410 are shown in .

[0199] Refer again Figure 9 and Figure 11 When the analog error voltage signal 125 is selected, the input vinp of the amplifier A1 is the same as the signal vop.

[0200] As previously mentioned Figure 4A and Figure 4B As discussed, the offset calibration circuit 221 includes switches S51, S52, S53, and S54 controlled by the controller 140-1. The gain calibration circuit 222 includes switches S41, S42, S43, and S44 controlled by the controller 140-2.

[0201] Via selector 410 , amplifier A1 of voltage-to-time converter 210 and input vinn of the corresponding delay line analog-to-digital converter (eg, signal von when analog error voltage signal 125 is selected) are swapped or time-varying between:

[0202] - Top gain calibration (reference voltage VR1), wherein the switch S1 (channel 1) of the selector 410 is activated to the on state and all other switches S0, S2, S3 are off; for the top gain calibration, the switches S41, S42, S53, S54 are all set to the closed state (on); for the top gain calibration, the switches S43, S44, S51, S52 are all set to the open state (off);

[0203] - Signal conversion (analog error voltage signal 125 or vsig), wherein, between time T1 and time T2, switch S0 (channel 0) of selector 410 is activated to the on state (closed state) and all other switches S1, S2, S3 are off (open); between time T1 and time T2, switches S43, S44, S53, S54 are all set to the closed state (on); between time T1 and time T2, switches S41, S42, S51, S52 are all set to the open state (off);

[0204] - offset calibration (reference voltage VR2), wherein, between time T2 and time T3, switch S3 (channel 3) of the selector 410 is activated to the on state and all other switches S0, S1 and S2 are off; between time T2 and time T3, switches S43, S44, S51, S52 are all set to the closed state (on); between time T2 and time T3, switches S41, S42, S53, S54 are all set to the open state (off);

[0205] - signal conversion (analog error voltage signal 125 or vsig), wherein between time T3 and time T4, switch SO (channel 0) of the selector 410 is activated to the on state (closed state) and all other switches SI, S2, S3 are turned off (open); between time T3 and time T4, switches S43, S44, S53, S54 are all set to the closed state (on); between time T3 and time T4, switches S41, S42, S51, S52 are all set to the open state (off);

[0206] - bottom gain calibration (reference voltage VR3), wherein between time T4 and time T5, switch S2 (channel 2) of the selector 410 is activated to the on state and all other switches SO, SI, S3 are turned off; between time T4 and time T5, switches S41, S42, S53, S54 are all set to the closed state (on); between time T4 and time T5, switches S43, S44, S51, S52 are all set to the open state (off);

[0207] - signal conversion (analog error voltage signal 125 or vsig), wherein between time T5 and time T6, switch SO (channel 0) of the selector 410 is activated to the on state (closed state) and all other switches SI, S2, S3 are turned off (open); between time T5 and time T6, switches S43, S44, S53, S54 are all set to the closed state (on); between time T5 and time T6, switches S41, S42, S51, S52 are all set to the open state (off);

[0208] - offset calibration (reference voltage VR2), wherein between time T6 and time T7, switch S3 (channel 3) of the selector 410 is activated to the on state and all other switches SO, SI, and S2 are turned off; between time T6 and time T7, switches S43, S44, S51, S52 are all set to the closed state (on); between time T6 and time T7, switches S41, S42, S53, S54 are all set to the open state (off);

[0209] The top gain state and the bottom gain state as discussed above and the corresponding calibration circuit 222 support calibration of the gain associated with the voltage-to-time converter 210 and the corresponding delay line analog-to-digital converter 110. The offset state as discussed above and the corresponding calibration circuit 221 support calibration of the offset associated with the voltage-to-time converter 210 and the corresponding delay line analog-to-digital converter 110.

[0210] As Figure 9 As previously discussed, the calibration circuit 221 generates a corresponding offset calibration signal J1 supplied to the transconductance amplifier A2 based on feedback to the monitoring nodes N41 and N42 during a calibration phase. The transconductance amplifier A2 converts the received offset calibration signal J1 to an adjustment signal K3 applied to the amplifier Al. The signal K3 adjusts the output of the VTC front-end amplifier (the output of the amplifier Al ) to compensate for the offset of the VTC 210 and the delay line 110. Figure 4A The calibration circuit 221 provides offset calibration to the amplifier Al in the corresponding circuitry.

[0211] As previously discussed, the calibration circuit 221 generates a corresponding offset calibration signal J1 supplied to the transconductance amplifier A2 based on feedback to the monitoring nodes N41 and N42 during a calibration phase. The transconductance amplifier A2 converts the received offset calibration signal J1 to an adjustment signal K3 applied to the amplifier Al. The signal K3 adjusts the output of the VTC front-end amplifier (the output of the amplifier Al ) to compensate for the offset of the VTC 210 and the delay line 110. Figure 9 As further shown in FIG. 2, the calibration circuit 222 generates a corresponding gain calibration signal G1 (gain adjustment control signal) supplied to each of the current-starved inverters Z1 and Z2. The gain calibration signal G1 (e.g., feedback) controls the output slew rate of the current-starved inverters Z1 and Z2 that generate the respective output signals voutp and voutn. This provides gain calibration for the voltage-to-time converter 210 and the corresponding circuitry in FIG. 2. Figure 4A The calibration circuit 222 provides gain calibration for the voltage-to-time converter 210 and the corresponding circuitry in FIG. 2.

[0212] In one example, during gain calibration using the calibration circuit 222, the input of the voltage-to-time converter 210 is connected to 4mV or -4mV (also referred to as a reference voltage VR1 or a reference voltage VR3, which can be any suitable voltage), and the phase error between the stop of one delay line and the 4-buffer delayed version of the alternative delay line is reduced. The charge pumps (CP1 and CP2) store the average of the gains of the top and bottom delay lines in the capacitor CI.

[0213] During offset calibration, the input of the DLFLASH is shorted and the differential outputs of the VTC 210 are compared, and the transconductance amplifier A2 adjusts the output of the VTC front-end amplifier (the output of the amplifier Al ) in a differential manner to compensate for the offset of the VTC 210 and the delay line 110.

[0214] The delay line analog-to-digital converter 110 can be configured to operate twice within one ADC clock cycle - the first time is error digitization associated with the received signal 125, and the second time is gain and offset calibration.

[0215] The calibration can be configured to occur when the tracking loop is stable to a new DAC code, and thus does not slow down the total ISADC conversion time.

[0216] Thus, at a 100 Mhz ADC clock rate, 2.5 ns is allocated to the DLFLASH, while 7.5 ns is allocated to the ADC tracking loop for settling. For example, the input voltage VSIG settles to a new value for conversion between times T82 and T85, while offset calibration occurs between times T2 and T3. The input voltage VSIG settles to a new value for conversion between times T86 and T90, while gain calibration occurs between times T4 and T5.

[0217] Upon generation of the start and stop signals, the dl_sig_sw signal goes high. Upon the dl_sig_sw going high, the input to the DLFLASH is switched to the next value.

[0218] As shown in Figure 9 The selector circuit 410 can be configured to interleave conversion of the received analog voltage (e.g., the inputs vinn and vinp of the amplifier Al), such as the analog error voltage 125, among conversion of the first analog gain reference voltage VR1, conversion of the second analog gain reference voltage VR2, and conversion of the offset reference voltage VR3. In other words, conversion of the first analog gain reference voltage, the second analog gain reference voltage, and the offset reference voltage support calibration of the signal generator circuit in a manner as previously discussed. In such examples, the analog-to-digital converter circuit and / or the signal generator circuit as discussed herein can be constantly calibrated between instances of converting the analog error voltage into respective samples of a digital signal. The constant or repeated function of calibrating the analog-to-digital converter, including the signal generator and / or delay line analog-to-digital converter circuitry, ensures that respective samples of the digital signal output from the analog-to-digital converter circuitry 110 as accurately as possible represent the analog error voltage.

[0219] Figure 10 is an example diagram illustrating implementation of a multiplexer (selector) and corresponding connections for calibration associated with a delay line ADC as discussed herein.

[0220] In this example, gain calibration is performed for δsig = tstart - tstop = + / - (N-2)*δLSB

[0221] For signal = +4*δLSB, nodes G1 and G2 are tapped into the PFD [for top gain calibration].

[0222] For signal = -4*δLSB, nodes B1 and B2 are tapped into the PFD [for bottom gain calibration]

[0223] Figure 11 is an example diagram illustrating implementation of a multiplexer (selector) and corresponding connections for calibration associated with a delay line ADC as discussed herein.

[0224] Figure 11 Connections for calibration of the DLFLASH circuitry as discussed herein are shown. These connections are generated within the ADC tracking loop and provide +4mV (reference voltage VR1), -4mV (reference voltage VR3) for gain calibration. Because the current sources that generate these references are based on the same bandgap voltage divided by resistors designed to match the reference, amplification, and input resistors and generate current for the IDAC; and since the references track the input common mode of the DLFLASH, the references include the gain error of the tracking loop and the DLFLASH is calibrated according to this same gain error, which means that no further trimming of the DLFLASH is needed.

[0225] For offset calibration, the inputs of the DLFLASH are simply shorted. Figure 9 "dl_sig_sel” in Figure 11 is the same as "SELECT” in

[0226] In this example, for each analog-to-digital conversion within a cycle, the selector 410 selects one of the switches SO, SI, S2, and S3 to provide the corresponding voltage to the node vinn of the amplifier Al of the voltage-to-time converter 210. For the selection of different states as the respective conversion cycle, see Figure 9 .

[0227] Figure 12 is an example diagram showing a charge pump as discussed herein.

[0228] Figure 12 The charge pump used is shown in

[0229] Charge pump

[0230] Charge pump design has its unique design challenges. For example, the charge pump can introduce errors into the delay-locked loop if the following conditions exist:

[0231] - Mismatch between UP current and DOWN current. Channel length modulation.

[0232] - Switch sharing charge

[0233] - The charge pump used has a feedback loop for matching the UP current and the DOWN current and controlling channel length modulation.

[0234] The switches between the UP current and the DOWN current can introduce errors due to their mismatch.

[0235] Mismatch in the switches creates large errors in the delay locked loop.

[0236] Small switch size minimizes charge injection.

[0237] Phase error as a function of PFD (Phase Frequency Detector) pulse width variation due to charge injection and current mismatch:

[0238]

[0239] Even with good design, transistor mismatch creates residual errors.

[0240] - Phase frequency detector + charge pump mismatch introduces phase error into the DLL loop: σ = 17.5 ps

[0241] - For gain DLL: phase error contribution will be σ / 16 cells / 20 ps resolution = 5.4% standard deviation of gain error

[0242] - For offset DLL: phase error will contribute about 1 code of standard deviation of offset error

[0243] - Calibration loop to remove mismatch errors of charge pump and phase frequency detector.

[0244] Figure 13 is an example diagram showing a raw phase frequency detector as discussed herein.

[0245] Figure 13 One version of the PFD (Phase Frequency Detector) logic is shown in Figure 14 .

[0246] As shown in Figure 15 , a tunable delay is introduced into the reset path of each flip-flop in order to program the individual pulse widths of the UP and DOWN pulses.

[0247] Figure 16 is an example timing diagram showing the operation of a programmable phase frequency detector as discussed herein.

[0248] The UP and DOWN pulses change in opposite directions sequentially. Figure 17 The difference between the UP and DOWN pulses is shown over the entire range of adjustment. There are 128 possible adjustments.

[0249] The offset is updated based on when only the DL FLASH bits vout_bot<0> and vout_top<0> are equal to 1 during offset calibration.

[0250] Offset calibration is complete only when vout_bot<0> and vout_top<0> are 1.

[0251] The gain is updated based on when the DL FLASH outputs 5 and -5 during gain calibration.

[0252] In a practical implementation, a large average is taken and then the pulse width is adjusted.

[0253] Since the loop is slow, once the pulse width adjustment converges, these values are stored in memory for reloading during start-up.

[0254] Figure 17 is an example timing diagram showing curves of pulse width settings (y-axis) as discussed herein versus digital correction control codes (x-axis).

[0255] In this example, the plot 1700 shows curves of UP pulse widths 1701, DOWN pulse widths 1702, and corresponding pulse width differences 1703 for different pulse width settings versus corresponding control codes. Pulses with different 1703 represent the difference between UP pulses with 1701 and DOWN pulses with 1702.

[0256] - Figure 18 The calibration timing for removing PFD+CP error is shown in Table 1.

[0257] - During calibration, a large average of the DL FLASH is taken to generate the gain calibration signal and the offset calibration signal.

[0258] - At the end of the averaging, the gain control signal and the offset control signal are updated

[0259] - After the gain control signal and the offset control signal are updated, the DLL needs at least 5us of wait time to settle before another average can be taken.

[0260] Figure 18 is an example timing diagram of calibration as discussed herein.

[0261] Calibration timing for removing PFD+CP error

[0262] The charge pump error removal loop described is a slow loop for removing mismatches, critical for ensuring no additional trimming is needed for all devices and only 16 cells are needed to digitize 16mV. This technique ensures that the DLFLASH can convert in 2.5ns for all devices. After startup, the loop stabilizes the PFD pulse widths, after which these values can be stored to memory and reloaded for subsequent startups, making the startup time fast.

[0263] Other details of implementations

[0264] Biasing the VTC

[0265] The optimal bias point for the CSI changes primarily with temperature and nmos process corner

[0266] As shown in Figure 7 The optimal operating region changes

[0267] The faster process corners have lower gain from the output of the CSI stage, which is desirable because the resolution of the delay line will also decrease, and vice versa for the slower process corners

[0268] Since the NMOS devices control the current through the CSI stage, the adjustment current at the front end is supplied by a V gs / R type CTAT bias, where I out = V gs / R, and the NMOS devices can track the process corner together, and thus the CSI will be close to its optimal point

[0269]

[0270] Tracking the timing of the ADC

[0271] The tracking ADC can operate at 100Mhz due to the use of an auxiliary DAC to provide a fast feedback path. This idea is McKinley's past patent. The size and range / resolution of the auxiliary DAC is the same as the DLFLASH ADC. It updates immediately after the delay line flash conversion occurs and provides a fast analog feedback path. This function provides an additional clock cycle for the digital feedback loop to update the accumulator and calculate the next DAC code.

[0272] In the delay line analog-to-digital converter 110, each flip-flop is a dynamic flip-flop paired with a standard library flip-flop clocked by an opposite phase clock to form a synchronizer to reduce the probability of metastability. Figure 19 The auxiliary DAC and its feedback path and synchronizer are shown in

[0273] Figure 20 is an example timing diagram showing the operation of the tracking ADC as discussed herein.

[0274] In one embodiment, as shown in Figure 20 there is an auxiliary DAC that updates the tracking loop as previously described to the immediate value calculated by the DLFLASH (analog to digital converter circuit 110) while the main DAC updates after one cycle. Both the auxiliary DAC and the main digital to analog converter can be configured to have a time of 7.5 ns or other suitable amount to settle.

[0275] Figure 21A , Figure 21B and Figure 21C are example delay line ADCs including a synchronizer as discussed herein.

[0276] Further, note that examples of apparatuses as discussed herein can be configured to include a synchronizer circuit 2100. The synchronizer circuit as discussed herein is used to adjust the clock signal applied to D flip-flops disposed in a delay line analog to digital converter circuitry.

[0277] • The delay line schematic is shown in combination with Figure 21A , Figure 21B and Figure 21C Each dynamic flip-flop is paired with a standard flip-flop that is clocked by the opposite clock cycle to form a synchronizer pair.

[0278] • clk_200 can force a stop clock signal. The synchronizer is clocked based on a delayed clk_200 that occurs

[0279] • The delay line has 16 unary cells to convert time into a digital code

[0280] • δ ~ = 20 ps -> resolution of the delay line

[0281] Figure 22 is an example diagram showing a method as discussed herein.

[0282] As shown in flowchart 2200 (method), in process operation 2210, a voltage-to-time converter 210 (also referred to as a signal generator) receives an analog voltage between nodes vinn and vinp of an amplifier Al.

[0283] In process operation 2220, the voltage-to-time converter 210 generates control signals 105 for controlling operation of the delay line analog-to-digital converter circuitry 110 based on the analog voltage received between nodes vinn and vinp by the voltage-to-time converter circuit 210 (the signal generator circuit) at nodes voutp and voutn. As previously discussed, the delay line analog-to-digital converter circuitry 110 is operable to convert samples of the analog voltage received between nodes vinn and vinp into digital signals.

[0284] In process operation 2230, the calibration circuitry (e.g., the offset calibration circuit 221 and / or the gain calibration circuit 222) calibrates the signal generator circuit (the voltage-to-time converter 210) based on calibration feedback generated by the delay line analog-to-digital converter circuitry 110 converting the analog voltage into digital signals (e.g., the gain calibration circuit 222 for generating the output 499 of the gain adjustment control signal Gl, or the offset calibration circuit 211 for generating the monitor voltages at nodes N41 and N42 of the offset adjustment control signal Jl).

[0285] Again, note that the techniques herein are well suited for use in circuit applications (e.g., circuit applications implementing compensation in power converters). However, it should be noted that the examples herein are not limited to use in such applications, and the techniques discussed herein are well suited for other applications as well.

[0286] Based on the description set forth herein, numerous specific details have been set forth in order to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter can be practiced without these specific details. In other instances, methods, apparatuses, systems, etc. known to those of ordinary skill have not been described in detail in order to avoid obscuring the claimed subject matter. Some portions of the detailed description have been presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the data processing arts to convey the substance of their work to others. An algorithm is here, and generally, is considered to be a self-consistent sequence of operations or similar processing leading to a desired result. In this context, operations or processing involve physical manipulation of physical quantities. Typically, although not necessarily, such quantities can take the form of electrical, magnetic, or optical signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as apparent from the following discussion, it is appreciated that throughout this specification discussions utilizing terms such as "processing," "computing," "calculating," "determining" or the like refer to the action or processes of a computing platform, such as a computer or a similar electronic computing device, that manipulates or transforms data represented as physical electronic quantities within the computing platform's registers and other information storage, transmission or display devices.

[0287] While the application has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the application as defined by the appended claims. Such variations are intended to be covered by the scope of this application. Thus, the foregoing description of examples of this application is not intended to be limiting. Rather, any limitations to the application are presented in the following claims.

Claims

1. An apparatus for signal conversion, comprising: a delay line analog-to-digital converter circuitry; a signal generator circuit coupled to the delay line analog-to-digital converter circuitry, the signal generator circuit operable to generate a control signal based on an analog voltage received by the signal generator circuit to control operation of the delay line analog-to-digital converter circuitry; and a calibration circuitry operable to calibrate the signal generator circuit based on calibration feedback.

2. The apparatus of claim 1, wherein, the delay line analog-to-digital converter circuitry comprises a first delay line analog-to-digital converter circuit and a second delay line analog-to-digital converter circuit arranged in parallel to convert the received analog voltage into corresponding samples of a digital output signal.

3. The apparatus of claim 2, wherein, the first delay line analog-to-digital converter circuit is operable to generate a first portion of the corresponding samples under a first condition that a magnitude of the analog voltage is greater than a threshold level; and wherein the second delay line analog-to-digital converter circuit is operable to generate a second portion of the corresponding samples under a second condition that the magnitude of the analog voltage is less than the threshold level.

4. The apparatus of claim 2, wherein, the control signal comprises a first control signal and a second control signal; wherein the first control signal is operable to control a start operation of the first delay line analog-to-digital converter circuit; wherein the second control signal is operable to control a stop operation of the first delay line analog-to-digital converter circuit; wherein the second control signal is operable to control a start operation of the second delay line analog-to-digital converter circuit; and wherein the first control signal is operable to control a stop operation of the second delay line analog-to-digital converter circuit.

5. The apparatus of claim 2, further comprising: a selector circuitry arranged at an output of the delay line analog-to-digital converter circuitry, the selector circuitry operable to select between a first signal generated by the first delay line analog-to-digital converter circuit and a second signal generated by the second delay line analog-to-digital converter circuit.

6. The apparatus of claim 1, wherein, the delay line analog-to-digital converter circuitry is implemented in a tracking analog-to-digital converter circuit, the delay line analog-to-digital converter circuitry operable to convert the analog voltage into a first digital signal indicative of a magnitude of the analog voltage.

7. The apparatus of claim 6, wherein, the analog voltage is a first analog voltage; and wherein the first analog voltage is an analog error voltage representing a difference between an analog input voltage and a second analog voltage, the second analog voltage derived from a second digital signal by a digital-to-analog converter, the second digital signal derived from the first digital signal.

8. The apparatus of claim 7, wherein, the second digital signal is indicative of a magnitude of the analog input voltage.

9. The apparatus of claim 6, wherein, the calibration circuitry comprises a gain calibration loop, a gain associated with the delay line analog-to-digital converter circuitry is configured to match a gain setting of a tracking loop associated with the tracking analog-to-digital converter circuit.

10. The apparatus of claim 1, wherein, the signal generator circuit comprises an amplifier operable to receive the analog voltage; wherein the calibration circuitry comprises an offset calibration circuit operable to monitor a control signal input to the delay line analog-to-digital converter circuitry; and The offset calibration circuit is operable to generate an offset adjustment control signal based on a monitored control signal input to the delay line analog-to-digital converter circuitry, the offset adjustment control signal being operable to adjust an offset associated with the amplifier.

11. The apparatus of claim 10, wherein, The offset calibration circuit is an offset delay locked loop circuit.

12. The apparatus of claim 1, wherein, The signal generator circuit includes an amplifier operable to receive the analog voltage; wherein the calibration circuitry includes a gain calibration circuit operable to monitor an output of the delay line analog-to-digital converter circuitry; and Wherein the gain calibration circuit is operable to generate a gain adjustment control signal based on the output, the gain adjustment control signal being operable to adjust a gain associated with the amplifier that converts the received analog voltage into the control signal.

13. The apparatus of claim 12, wherein, The gain calibration circuit is a gain delay locked loop circuit.

14. The apparatus of claim 1, wherein, The delay line analog-to-digital converter circuit system includes: a first delay line analog-to-digital converter operable to generate a positive error value associated with converting the analog voltage into a digital signal; and A second delay line analog-to-digital converter is operable to generate a negative error value associated with converting the analog voltage into the digital signal.

15. The apparatus of claim 1, wherein, the signal generator circuit being a voltage-to-time converter operable to generate a start signal and a stop signal supplied to the delay line analog-to-digital converter circuitry, the magnitude of the duration between the start signal and the stop signal being dependent on the magnitude of the received analog voltage; wherein the calibration circuitry is operable to calibrate the voltage-to-time converter based on the calibration feedback; and The calibration feedback is received by monitoring the control signal and a digital signal output from the delay line analog-to-digital converter circuit system.

16. The apparatus according to claim 1, further comprising: A selector circuit is operable to select among a plurality of inputs including: i) a first analog gain reference voltage, ii) a second analog gain reference voltage, iii) an offset reference voltage, and iv) an analog error voltage.

17. The apparatus of claim 16, wherein, The calibration circuitry is operable to generate the calibration feedback based on sample conversions of the first analog gain reference voltage, the second analog gain reference voltage, and the offset reference voltage taken at different times during an analog-to-digital conversion cycle.

18. The apparatus of claim 17, wherein, The selector circuit is operable to interleave conversions of the analog error voltage among conversions of the first analog gain reference voltage, conversions of the second analog gain reference voltage, and conversions of the offset reference voltage.

19. The apparatus according to claim 1, further comprising: A synchronizer circuit is operable to adjust a clock signal applied to a D flip-flop disposed in the delay line analog-to-digital converter circuitry.

20. The apparatus of claim 1, wherein, The calibration circuit system includes a gain calibration circuit and an offset calibration circuit; wherein the offset calibration circuit includes a first set of charge pumps to generate an offset calibration signal supplied to the signal generator circuit; wherein the gain calibration circuit includes a second set of charge pumps to generate a gain calibration signal that is supplied to the signal generator circuit; the apparatus further comprising: a first pulse width calibration circuitry operable to adjust a pulse width of a first pulse width modulated signal applied to the first set of charge pumps and phase frequency detector to calibrate the first set of charge pumps and phase frequency detector based on an output of the delay line analog-to-digital converter circuitry; and wherein the adjustment of the pulse width of the first pulse width modulated signal reduces charge pump errors and phase frequency detector errors associated with the first set of charge pumps and phase frequency detector; and a second pulse width calibration circuitry operable to adjust a pulse width of a second pulse width modulated signal applied to the second set of charge pumps and phase frequency detector to calibrate the second set of charge pumps and phase frequency detector based on an output of the delay line analog-to-digital converter circuitry; and wherein the adjustment of the pulse width of the second pulse width modulated signal reduces charge pump errors and phase frequency detector errors associated with the second set of charge pumps and phase frequency detector.

21. The apparatus of claim 3, wherein, the first D flip-flop in the first delay line analog-to-digital converter circuit and the second D flip-flop in the second delay line analog-to-digital converter circuit are implemented with negative setup times to provide overlap with respect to generating the digital output signal around the threshold level.

22. A signal conversion method comprising: receiving an analog voltage; generating, via a signal generator circuit, a control signal to control operation of a delay line analog-to-digital converter circuitry based on the analog voltage received by the signal generator circuit, the delay line analog-to-digital converter circuitry operable to convert samples of the analog voltage into a digital signal; and calibrating the signal generator circuit based on calibration feedback generated by the delay line analog-to-digital converter circuitry converting samples of the analog voltage into a digital signal.

23. An apparatus for signal conversion comprising: a delay line analog-to-digital converter operable to convert an analog error voltage into a digital error voltage signal; an accumulator function module operable to generate a digital value representative of an analog input voltage, the digital value adjusted based on samples of the digital error voltage signal generated by the delay line analog-to-digital converter; and a digital-to-analog converter operable to convert the digital value received from the accumulator function module into a second analog voltage, the analog error voltage being a difference between the analog input voltage and the second analog voltage.

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