Power semiconductor device and power converter including the same, and method of manufacturing power

Abstract

Embodiments relate to a power semiconductor device, a power semiconductor module, a power converter and a manufacturing method thereof. A power semiconductor device according to an embodiment may include a substrate, a first conductivity type first epitaxial layer disposed on the substrate, a first conductivity type 2-1 epitaxial layer disposed on the first conductivity type first epitaxial layer, a first conductivity type 2-2 epitaxial layer disposed on the first conductivity type 2-1 epitaxial layer, and a second conductivity type second epitaxial layer disposed on the first conductivity type 2-2 epitaxial layer. The second conduction type well is partially arranged in the first conduction type 2-1 epitaxial layer, the second conduction type ion implantation area and the source electrode area are located above the second conduction type well, and the source electrode is arranged on the source electrode area. The semiconductor device includes a second conductivity type ion implantation region, a first conductivity type 2-2 epitaxial layer disposed on the first conductivity type 2-2 epitaxial layer, a gate insulating layer disposed in the trench region in which the second conductivity type ion implantation region and a portion of the first conductivity type 2-2 epitaxial layer are removed, a trench gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the trench gate, and a gate electrode electrically connected to the trench gate.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a power semiconductor device, a power semiconductor module, a power converter, and a manufacturing method thereof. BACKGROUND

[0002] A power semiconductor is one of key elements that determine efficiency, speed, durability, and reliability of a power electronics system.

[0003] With recent development of the power electronics industry, silicon (Si) power semiconductors previously used have reached their physical limits. In order to replace the silicon power semiconductors, WBG (Wide Band Gap) power semiconductors, such as silicon carbide (SiC) power semiconductors and gallium nitride (GaN) power semiconductors, are being actively researched.

[0004] The band gap energy of a WBG power semiconductor device is about three times that of a Si power semiconductor device, and thus, the WBG power semiconductor device has characteristics of low intrinsic carrier concentration, high breakdown electric field (about 4 to 20 times), high thermal conductivity (about 3 to 13 times), and large electron saturation rate (about 2 to 2.5 times) compared to the Si power semiconductor.

[0005] Since these characteristics make operation in a high-temperature and high-voltage environment feasible, the WBG power semiconductor device has high switching speed and low switching loss. Among them, a gallium nitride (GaN) power semiconductor device can be used in a low-voltage system, and a silicon carbide (SiC) power semiconductor device can be applied to a high-voltage system.

[0006] A SiC MOSFET power semiconductor in the related art generally has a vertical diffusion structure and is referred to as a VDMOSFET, which can also be simply referred to as a double-diffusion DMOSFET. In addition, the SiC MOSFET can be classified into a planar MOSFET and a trench MOSFET according to the direction of a channel.

[0007] Among them, the trench MOSFET is a structure in which a channel is formed on the sidewall of a trench. To this end, a gate insulating film is formed on the sidewall of the trench, and a gate electrode is formed in the trench.

[0008] The SiC MOSFET has high R ON Therefore, a trench MOSFET is proposed to reduce R ON The advantage of the trench MOSFET is that the channel density is increased by forming a channel on the sidewall of a trench.

[0009] However, because the trench MOSFET has a larger electric field in the trench gate oxide having a shorter drift distance than the P-base (P-well), and the electric field is concentrated at the edge of the trench, there is a problem that gate oxide breakdown occurs quickly and BV (breakdown voltage) decreases.

[0010] For example, the breakdown field strength of the SiC trench MOSFET is 10 times that of the Si MOSFET, and thus the SiC semiconductor device is used at a voltage that is 10 times closer to the voltage of the Si device. For this reason, an electric field that is 10 times stronger than the electric field of the silicon device is applied to the gate insulating film formed in the trench, and there is a problem that the gate insulating film at the trench corner is easily damaged.

[0011] Internal technology is researching a process of forming a p-type well (P-base) deeper than the gate trench to prevent concentration of the electric field at the trench corner, but in order to form such a deep p-type well, there is a problem that ion implantation energy exceeds the general process level.

[0012] In addition, since high-energy ion implantation causes serious ion implantation outside the target area, there is a problem that the cell pitch decreases due to difficulty in controlling lateral straggling. SUMMARY

[0013] One of the technical objects of the power semiconductor device according to the embodiment, the power converter including the same, and the manufacturing method of the power semiconductor device is to prevent concentration of the electric field at the trench corner and prevent the problem of the decrease in the cell pitch due to lateral straggling.

[0014] The technical problem of the embodiment is not limited to the technical problem described in this section, and includes a technical problem that can be understood through the description of the invention.

[0015] The power semiconductor device according to the embodiment can include a substrate, a first conductive type first epitaxial layer disposed on the substrate, a first conductive type second epitaxial layer disposed on the first conductive type first epitaxial layer, a second conductive type well partially formed in the first conductive type second epitaxial layer, a second conductive type ion implantation region and a source region located above the second conductive type well, a source electrode disposed on the source region, a gate insulating layer formed in a trench region in which the second conductive type ion implantation region and a portion of the first conductive type second epitaxial layer are removed, a trench gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the trench gate, and a gate electrode electrically connected to the trench gate.

[0016] The first-conductivity-type second epitaxial layer can include a first-conductivity-type 2-1 epitaxial layer disposed on the first-conductivity-type first epitaxial layer, and a first-conductivity-type 2-2 epitaxial layer disposed on the first-conductivity-type 2-1 epitaxial layer.

[0017] The second-conductivity-type well can be partially formed in the first-conductivity-type 2-1 epitaxial layer.

[0018] The gate insulating layer can be in contact with an upper surface of the second-conductivity-type well.

[0019] The trench gate can be arranged to be vertically aligned with the second-conductivity-type well.

[0020] The second-conductivity-type well can be placed lower than the trench gate.

[0021] A power semiconductor device according to an embodiment can include a substrate 110, a first-conductivity-type first epitaxial layer 111 disposed on the substrate 110, a first-conductivity-type 2-1 epitaxial layer 112a disposed on the first-conductivity-type first epitaxial layer 111, a first-conductivity-type 2-2 epitaxial layer 112b disposed on the first-conductivity-type 2-1 epitaxial layer 112a, a second-conductivity-type well 121 partially formed in the first-conductivity-type 2-1 epitaxial layer 112a, a second-conductivity-type ion implantation region 122 and a source region 115 above the second-conductivity-type well 121, a source electrode 142 disposed on the source region 115, a gate insulating layer 131 formed in a trench region T in which the second-conductivity-type ion implantation region 122 and a portion of the first-conductivity-type 2-2 epitaxial layer 112b are removed, a trench gate 132 disposed on the gate insulating layer 131, an interlayer insulating layer 150 disposed on the trench gate 132, and a gate electrode electrically connected to the trench gate 132.

[0022] An upper surface of the second-conductivity-type well 121 can be equal to or lower than the first-conductivity-type 2-1 epitaxial layer 112a.

[0023] A doping concentration of the second-conductivity-type well 121 formed in the first-conductivity-type 2-1 epitaxial layer 112a can be higher than a doping concentration of the second-conductivity-type ion implantation region 122.

[0024] A power converter according to an embodiment can include any of the above-described power semiconductor devices.

[0025] The method of manufacturing a power semiconductor device according to an embodiment can include growing a first-conductivity-type first epitaxial layer 111 on a substrate 110, growing a first-conductivity-type second-1 epitaxial layer 112a on the first-conductivity-type first epitaxial layer 111, partially forming a second-conductivity-type well 121 by implanting ions into the first-conductivity-type second-1 epitaxial layer 112a, growing a first-conductivity-type second-2 epitaxial layer 112b on the first-conductivity-type second-1 epitaxial layer 112a, forming a second-conductivity-type ion-implanted region 122 and a source region 115 by implanting ions into the first-conductivity-type second-2 epitaxial layer 112b, forming a trench region T by removing a portion of the second-conductivity-type ion-implanted region 122 and the first-conductivity-type second-2 epitaxial layer 112b, forming a gate insulating layer 131 and a trench gate 132 in the trench region T, forming an interlayer insulating layer 150 on the trench gate 132, and forming a gate electrode electrically connected to the trench gate 132.

[0026] An upper surface of the second-conductivity-type well 121 can be equal to or lower than the first-conductivity-type second-1 epitaxial layer 112a.

[0027] A doping concentration of the second-conductivity-type well 121 formed in the first-conductivity-type second-1 epitaxial layer 112a can be higher than a doping concentration of the second-conductivity-type ion-implanted region 122.

[0028] In the step of forming the trench region T by removing a portion of the second-conductivity-type ion-implanted region 122 and the first-conductivity-type second-2 epitaxial layer 112b, a portion of the second-conductivity-type well 121 can be exposed.

[0029] The gate insulating layer 131 can contact the second-conductivity-type well 121.

[0030] A hard mask pattern for forming the trench region can correspond to an opening region of a hard mask pattern for forming the second-conductivity-type well 121 by ion implantation.

[0031] The trench region can be arranged to be vertically aligned with the second-conductivity-type well 121.

[0032] The trench gate 132 and the second-conductivity-type well 121 can be vertically aligned.

[0033] [Technical Effects]

[0034] In the power semiconductor device according to the embodiment, the power converter including the same, and the manufacturing method of the power semiconductor device, the second-conductivity-type well 121 can be provided under the trench gate 132 to disperse an electric field concentrated at a bottom corner of the trench gate. If the electric field at the bottom corner of the trench gate is not dispersed, a breakdown voltage can be significantly reduced or a gate reliability problem can occur, which can reduce a lifetime of the semiconductor device.

[0035] Further, according to the embodiment, since the second-conductivity-type well 121 can be formed without using high-energy ion implantation, the embodiment can prevent a pitch reduction problem due to lateral dispersion of dopants and at the same time can form the second-conductivity-type well 121 in a region deeper than the trench. Therefore, there is a technical effect of preventing gate insulating layer breakdown by dispersing an electric field concentrated at a bottom corner of a gate trench.

[0036] In addition, in the embodiment, a doping concentration of the second-conductivity-type well 121 formed in the first-conductivity-type 2-1 epitaxial layer 112a can be higher than a doping concentration of the second-conductivity-type ion implantation region 122. For example, according to the embodiment, there is a technical effect capable of implementing a concentration gradient in which the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 changes more abruptly than the doping concentration of the second-conductivity-type ion implantation region 122 formed adjacent to the trench gate 132.

[0037] For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 17 19 3 16 17 3 , but is not limited thereto.

[0038] According to the embodiment, since the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 is formed to be higher than the doping concentration of the second-conductivity-type ion implantation region 122, a depletion layer can be expanded in a direction of the substrate 110. Therefore, there is a technical effect of increasing a breakdown voltage. In addition, according to the embodiment, since the doping concentration of the second-conductivity-type ion implantation region 122 formed around the trench gate 132 is formed to be lower than the doping concentration of the second-conductivity-type well 121, there is a complex technical effect of reducing a threshold voltage and increasing a current density.

[0039] Technical effects of the embodiment are not limited to the technical effects described in this section and include technical effects that can be understood by the description of the present invention. BRIEF DESCRIPTION OF DRAWINGS ​​​​​

[0040] Figure 1 is an exemplary configuration diagram of a power converter 1000 according to an embodiment.

[0041] Figure 2 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0042] Figure 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0043] Figures 4 to 10 is a cross-sectional view of a manufacturing process of a power semiconductor device 100 according to an embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, the present application according to an embodiment for solving the above problems will be described in greater detail with reference to the accompanying drawings.

[0045] The suffix "module" or "part" of the elements used in the following description is given simply as a consideration for ease of writing the specification, and does not itself give any particularly important meaning or role. Therefore, "module" and "unit" can be used interchangeably.

[0046] The terms including ordinal numbers, such as first, second, etc., can be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

[0047] The singular expression includes the plural expression, unless the context clearly dictates otherwise.

[0048] In this application, terms such as "include", "have" or "comprise" are intended to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification. These terms should be understood as not precluding the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0049] [EMBODIMENT]

[0050] Figure 1 is an exemplary configuration diagram of a power converter 1000 according to an embodiment.

[0051] The power converter 1000 according to an embodiment can receive DC power from a battery or a fuel cell, convert the DC power into AC power, and provide the AC power to a predetermined load. For example, the power converter 1000 according to an embodiment can include an inverter, and can receive DC power from a battery, convert the DC power into three-phase AC power, and provide the AC power to a motor M, which can provide power to an electric vehicle, a fuel cell vehicle, or the like.

[0052] The power converter 1000 according to the embodiment can include power semiconductor devices 100. The power semiconductor devices 100 can be MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but are not limited thereto, and can include IGBTs (Insulated Gate Bipolar Transistors).

[0053] For example, the power converter 1000 can include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, 100f and a plurality of diodes (not shown). Each of the plurality of diodes can be embedded in each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and the diodes can also be separately provided.

[0054] The embodiment can convert DC power into AC power through on-off control of the plurality of power semiconductor devices 100a to 100f. For example, the power converter 1000 according to the embodiment turns on the first power semiconductor device 100a and turns off the second power semiconductor device 100b to supply positive polarity power to the motor M for a first time period of one cycle, and can turn off the first power semiconductor device 100a and turn on the second power semiconductor device 100b to supply negative polarity power to the motor M for a second time period of one cycle.

[0055] In the embodiment, a group of power semiconductor devices arranged in series on a high voltage line and a low voltage line on the input side can be referred to as an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b form a first arm 12a, the third power semiconductor device 100c and the fourth power semiconductor device 100d form a second arm 12b, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f can form a third arm 12c.

[0056] In the arm, the upper power semiconductor device and the lower power semiconductor device can be controlled not to be turned on at the same time. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b can not be turned on at the same time, but can be alternately turned on and turned off.

[0057] Each of the power semiconductor devices 100a to 100f can receive a high power in the off state. For example, if the second power semiconductor device 100b is turned off while the first power semiconductor device 100a is turned on, the input voltage can be applied to the second power semiconductor device 100b as it is. The voltage input to the second power semiconductor device 100b can be a relatively high voltage, and the withstand voltage of each of the power semiconductor devices 100a to 100f can be designed to be high to withstand the high voltage.

[0058] Each of the power semiconductor devices 100a to 100f can conduct a high current in an on state. The motor M is driven with a relatively high current, and this high current can be supplied to the motor M through the on power semiconductor devices.

[0059] A high voltage applied to each of the power semiconductor devices 100a to 100f can cause a high switching loss. A high current conduction of the power semiconductor devices 100a to 100f can cause a high conduction loss. In order to dissipate heat generated by such losses, the power semiconductor devices 100a to 100f can be packaged as a power semiconductor module including a heat dissipation device.

[0060] The power semiconductor devices 100 of the embodiment can be silicon carbide (SiC) power semiconductor devices, can operate in a high temperature and high voltage environment, and can have a high switching speed and a low switching loss.

[0061] Meanwhile, the power converter 1000 according to the embodiment can include a plurality of power semiconductor modules.

[0062] For example, the plurality of power semiconductor devices 100a to 100f shown in FIG. 1 can be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm can be packaged into one power semiconductor module. Figure 1 The plurality of power semiconductor devices 100a to 100f shown in FIG. 1 can be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm can be packaged into one power semiconductor module.

[0063] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f shown in FIG. 1 can be packaged as one power semiconductor module. Figure 1

[0064] In addition, there can be additional power semiconductor devices placed in parallel with each of the power semiconductor devices 100a to 100f to increase current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module can be more than six.

[0065] The power converter 1000 according to the embodiment can include diode-type power semiconductor devices in addition to the transistor-type power semiconductor devices 100a to 100f. For example, a first diode (not shown) can be provided in parallel with the first power semiconductor device 100a, and a second diode (not shown) can be provided in parallel with the second power semiconductor device 100b. Also, these diodes can be packaged together in one power semiconductor module. In addition, the diodes can be provided in the form of internal diodes in each of the power semiconductor devices.

[0066] Next, the power semiconductor devices constituting each arm can be packaged into one power semiconductor module.​

[0067] For example, the first power semiconductor device 100a and the second power semiconductor device 100b constituting the first arm can be packaged into a first power semiconductor module, the third power semiconductor device 100c and the fourth power semiconductor device 100d constituting the second arm can be packaged into a second power semiconductor module, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f constituting the third arm can be packaged into a third power semiconductor module.

[0068] In addition, in order to increase current capacity, there can be an additional power semiconductor device placed in parallel with each power semiconductor device 100a to 100f. In this case, the number of power semiconductor devices included in each power semiconductor module is two, but there can be more power semiconductor devices. In addition, each arm can include a diode-type power semiconductor device (not shown) in addition to the transistor-type power semiconductor devices 100a to 100f, and these diodes can also be packaged together in one power semiconductor module. In addition, a diode can be provided in the form of an internal diode in each power semiconductor device.

[0069] Next, Figure 2 is a cross-sectional view of one of the power semiconductor devices 100 according to an embodiment.

[0070] The power semiconductor device 100 according to an embodiment can include a source electrode 130, a gate electrode 175 disposed above a predetermined semiconductor epitaxial layer 120, and a drain electrode 105 disposed below the semiconductor epitaxial layer 120.

[0071] In the form of a MOSFET, the source electrode 130 or the gate electrode 175 can include an Al-based metal. The drain electrode 105 can be a Ti / Ni / Ag layer including a Ti layer, a Ni layer, and an Ag layer, and can include a metal, NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0072] One technical object of an embodiment is to prevent concentration of an electric field at a trench corner and to prevent a problem of a cell pitch reduction due to lateral spread.

[0073] Hereinafter, a power semiconductor device 100 according to an embodiment for solving the above technical problem will be described.

[0074] Figure 3 is a cross-sectional view of a power semiconductor device 100 according to an embodiment.

[0075] First, referring to Figure 3The power semiconductor device 100 according to the embodiment can include at least one of the drain electrode 105, the substrate 110, the first-conductivity-type first epitaxial layer 111, the first-conductivity-type second epitaxial layer 112, the second-conductivity-type well 121, the second-conductivity-type ion-implanted region 122, the first-conductivity-type source region 115, the source contact 141, the second-conductivity-type contact region 123, the source electrode 142, the gate insulating layer 131, the gate electrode 132, and the interlayer insulating layer 150.

[0076] The first-conductivity-type second epitaxial layer 112 can include a first-conductivity-type 2-1 epitaxial layer 112a and a first-conductivity-type 2-2 epitaxial layer 112b.

[0077] The first-conductivity-type can be N-type and the second-conductivity-type can be P-type, but is not limited thereto. The substrate 110, the first-conductivity-type first epitaxial layer 111, and the first-conductivity-type second epitaxial layer 112 can include SiC (silicon carbide), but is not limited thereto.

[0078] In detail, the power semiconductor device 100 according to the embodiment can include the substrate 110, the first-conductivity-type first epitaxial layer 111 disposed on the substrate 110, the first-conductivity-type 2-1 epitaxial layer 112a disposed on the first-conductivity-type first epitaxial layer 111, and the first-conductivity-type 2-2 epitaxial layer 112b disposed on the first-conductivity-type 2-1 epitaxial layer 112a.

[0079] In addition, the embodiment can include the second-conductivity-type well 121 formed in the first-conductivity-type 2-1 epitaxial layer 112a.

[0080] An upper surface of the second-conductivity-type well 121 can be equal to or lower than the first-conductivity-type 2-1 epitaxial layer 112a.

[0081] In addition, the embodiment can include the second-conductivity-type ion-implanted region 122 located above the second-conductivity-type well 121, and the source region 115 and the second-conductivity-type contact region 123 disposed on the second-conductivity-type ion-implanted region 122.

[0082] In addition, the embodiment can include the source electrode 142 disposed on the source region 115 and the second-conductivity-type contact region 123, the gate insulating layer 131 (a portion of the second-conductivity-type ion-implanted region 122 and the first-conductivity-type 2-2 epitaxial layer 112b are removed from the trench region T) formed on a bottom and a sidewall of a trench region T (see Figure 8 ), the trench gate 132 disposed on the gate insulating layer 131, the interlayer insulating layer 150 disposed on the trench gate 132, and the gate electrode (not shown) electrically connected to the trench gate 132.

[0083] In the power semiconductor device according to the embodiment, the power converter including the same, and the manufacturing method of the power semiconductor device, the second-conductivity-type well 121 can be provided under the trench gate 132 to disperse an electric field concentrated at a bottom corner of the trench gate. If the electric field at the bottom corner of the trench gate is not dispersed, a breakdown voltage can be significantly reduced or a gate reliability problem can occur, which can reduce a lifetime of the semiconductor device.

[0084] Further, according to the embodiment, since the second-conductivity-type well 121 can be formed without using high-energy ion implantation, a problem of pitch reduction due to lateral diffusion of dopants is prevented, and at the same time, the second-conductivity-type well 121 is formed in a region deeper than the trench, so there is a technical effect of preventing gate insulating layer breakdown by dispersing an electric field concentrated at a bottom corner of the gate trench.

[0085] On the other hand, in the related art, high-energy ion implantation requires the introduction of a high-cost dedicated device, and despite such a dedicated device, the yield is poor. Further, since lateral diffusion that occurs significantly in high-energy ion implantation is difficult to control, there is a problem of pitch reduction.

[0086] Lateral diffusion can refer to an unintended increase in ion implantation in a lateral direction, and when lateral diffusion occurs, since a moving width of electrons is narrowed, there is a problem of Ron increase.

[0087] Further, in the related art, if a subsequent thermal oxidation process is performed on the trench sidewall after ion implantation of the trench sidewall, an oxide that can occur by unexpected growth in terms of thickness and characteristics can occur, which can affect Vth, Ron, gate oxide lifetime, etc.

[0088] In addition, in the embodiment, a doping concentration of the second-conductivity-type well 121 formed in the first-conductivity-type 2-1 epitaxial layer 112a can be higher than a doping concentration of the second-conductivity-type ion implantation region 122. For example, according to the embodiment, there is a technical effect in which a concentration gradient can be implemented in which the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 changes more abruptly than the doping concentration of the second-conductivity-type ion implantation region 122 formed adjacent to the trench gate 132.

[0089] For example, the doping concentration of the second-conductivity-type well 121 can be 2×10 17 to 2×10 19 / cm 3 , and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1×10 16 to 1×10 17 / cm 3 , but is not limited thereto.

[0090] According to the embodiment, since the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 can be formed higher than the doping concentration of the second-conductivity-type ion-implanted region 122, a depletion layer can be expanded in the direction of the substrate 110. Thus, there is a technical effect of increasing the breakdown voltage. In addition, according to the embodiment, the doping concentration of the second-conductivity-type ion-implanted region 122 formed around the trench gate 132 can be formed lower than the doping concentration of the second-conductivity-type well 121, there is a complex technical effect of reducing the threshold voltage and increasing the current density.

[0091] Hereinafter, a manufacturing process of the power semiconductor device 100 according to the embodiment will be described with reference to Figures 4 to 10 Figure 3

[0092] First, referring to Figure 4 A first-conductivity-type first epitaxial layer 111 and a first-conductivity-type 2-1 epitaxial layer 112a can be sequentially grown on the substrate 110. The first-conductivity-type first epitaxial layer 111 can include a first-conductivity-type buffer layer (not shown) and a first-conductivity-type drift layer (not shown).

[0093] The substrate 110, the first-conductivity-type first epitaxial layer 111, and the 2-1 epitaxial layer 112a can include a 4H-SiC material, but are not limited thereto. For example, the substrate 110, the first-conductivity-type first epitaxial layer 111, and the 2-1 epitaxial layer 112a can include a 3C-SiC or a 6H-SiC.

[0094] Next, a second-conductivity-type well 121 can be formed in the first-conductivity-type 2-1 epitaxial layer 112a by ion implantation.

[0095] For example, a first hard mask pattern (not shown) can be formed using an ion implantation mask and the second-conductivity-type well 121 can be formed by ion implantation to the first hard mask pattern. The second-conductivity-type well 121 can be a P-type body, but is not limited thereto. The first hard mask pattern can include a polysilicon pattern and an oxide pattern, but is not limited thereto.

[0096] P-type dopant ions can be implanted into the second-conductivity-type well 121. For example, Al or boron can be implanted, but is not limited thereto.

[0097] ​​According to the embodiment, the second-conductivity-type well 121 is formed in the first-conductivity-type second-1 epitaxial layer 112a without using high-energy ion implantation, thereby preventing a problem of pitch reduction due to lateral diffusion of dopants and simultaneously forming the second-conductivity-type well 121 in a region deeper than the trench. Thus, there is a technical effect of preventing breakdown of the gate insulating layer by dispersing an electric field concentrated at a bottom corner of the gate trench.

[0098] Next, referring to FIG. 2B, Figure 5 The first-conductivity-type second-2 epitaxial layer 112b can be grown again on the first-conductivity-type second-1 epitaxial layer 112a.

[0099] According to the embodiment, the second-conductivity-type well 121 is formed in the first-conductivity-type second-1 epitaxial layer 112a without using high-energy ion implantation, thereby preventing a problem of pitch reduction due to lateral diffusion of dopants and simultaneously forming the second-conductivity-type well 121 in a region deeper than the trench gate 132 formed later. Thus, it is possible to disperse an electric field concentrated at a bottom corner of the gate trench, thereby having a technical effect of preventing breakdown of the gate insulating layer.

[0100] Next, referring to FIG. 2B, Figure 6 Al or boron plasma can be implanted into the first-conductivity-type second-2 epitaxial layer 112b to form the second-conductivity-type ion implantation region 122.

[0101] The doping concentration of the second-conductivity-type well 121 formed in the first-conductivity-type second-1 epitaxial layer 112a according to the embodiment can be higher than the doping concentration of the second-conductivity-type ion implantation region 122.

[0102] For example, according to the embodiment, there is a technical effect in which the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 can change more abruptly than the doping concentration of the second-conductivity-type ion implantation region 122 formed adjacent to the trench gate 132, which can achieve a concentration gradient.

[0103] For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 17 For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 19 For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 3 For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 16 For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 17 For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 3 For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto.

[0104] According to the embodiment, because the doping concentration of the second-conductivity-type well 121 to be formed under the trench gate 132 is formed higher than the doping concentration of the second-conductivity-type ion-implanted region 122, there is a technical effect that a depletion layer expands in the direction of the substrate 110, and there is a technical effect that a breakdown voltage is increased.

[0105] According to the embodiment, the doping concentration of the second-conductivity-type ion-implanted region 122 to be formed around the trench gate 132 is formed lower than the doping concentration of the second-conductivity-type well 121, there is a complex technical effect that a threshold voltage is reduced and a current density is increased.

[0106] Next, referring to Figure 7 , by using an ion implantation mask having a second hard mask pattern (not shown), ions can be implanted into the second-conductivity-type ion-implanted region 122 to form the first-conductivity-type source region 115. For example, N-type dopants such as nitrogen or phosphorus can be ion-implanted at a concentration of about 1 x 1019 18 cm -3 to about 7 x 1019 19 cm -3 to form the first-conductivity-type source region 115 by using a self-alignment method.

[0107] In addition, the second-conductivity-type contact region 123 can be formed using a third hard mask pattern (not shown) as an ion implantation mask. The second-conductivity-type contact region 123 can be used to maintain a zero potential of the second-conductivity-type ion-implanted region 122, and can be used as a body diode.

[0108] Next, referring to Figure 8 , because a fourth hard mask pattern (not shown) can be used as an etching mask, the first-conductivity-type source region 115, the second-conductivity-type ion-implanted region 122, and the first-conductivity-type 2-2 epitaxial layer 112b can be partially removed to form a trench region T.

[0109] The fourth hard mask pattern can be a reverse pattern of the first hard mask pattern.

[0110] For example, the fourth hard mask pattern used to form the trench region T can correspond to an opening region of the first hard mask pattern used for ion implantation.

[0111] Therefore, in the embodiment, the trench region T can be formed to be aligned to the second-conductivity-type well 121. Therefore, the trench gate 132 and the second-conductivity-type well 121 formed later can be vertically aligned.

[0112] Next, referring to Figure 9 , a gate insulating layer 131 can be formed in the trench region T, and a trench gate 132 can be formed on the gate insulating layer 131.

[0113] According to an embodiment, the second-conductivity-type well 121 can be provided under the trench gate 132 to disperse an electric field concentrated at a bottom corner of the trench gate.

[0114] In particular, according to an embodiment, the second-conductivity-type well 121 can be formed without using high-energy ion implantation, a problem of pitch reduction due to lateral dispersion of dopants can be prevented, and at the same time, the second-conductivity-type well 121 is formed in a region deeper than the trench. Thus, an electric field concentrated at a bottom corner of a gate trench can be dispersed, and thus, there is a technical effect of preventing destruction of a gate insulating layer.

[0115] The gate insulating layer 131 can be a thermal oxide film or an oxide film deposited using LPCVD or the like, but is not limited thereto. The trench gate 132 can be formed of polysilicon, but is not limited thereto.

[0116] Then, the source contact 141 can be formed. For example, the source contact 141 can be formed using Ti or Ni, but is not limited thereto.

[0117] In addition, the drain electrode 105 can be formed on the substrate 110 using Ti / Al.

[0118] Next, referring to FIG. 2, Figure 10 The interlayer insulating layer 150 can be formed on the trench gate 132 and the gate insulating layer 131, and the source electrode 142 and a gate electrode (not shown) can be formed on the interlayer insulating layer 150 and the source contact 141.

[0119] The interlayer insulating layer 150 can be formed of an oxide film or a nitride film, but is not limited thereto.

[0120] The source electrode 142 can be formed of Al or the like, but is not limited thereto. In addition, the source electrode 142 can further include a barrier metal layer.

[0121] In the power semiconductor device according to an embodiment, the power converter including the same, and the manufacturing method of the power semiconductor device, the second-conductivity-type well 121 can be provided under the trench gate 132 to disperse an electric field concentrated at a bottom corner of the trench gate. If the electric field at the bottom corner of the trench gate is not dispersed, a breakdown voltage can be significantly reduced or a problem of gate reliability can occur, which can reduce the life of the semiconductor device.

[0122] Further, according to the embodiment, the second-conductivity-type well 121 can be formed without using high-energy ion implantation, thereby preventing a problem of pitch reduction due to lateral dispersion of dopants, and at the same time, the second-conductivity-type well 121 is formed in a region deeper than the trench. Thus, there is a technical effect of preventing gate insulating layer breakdown by dispersing an electric field concentrated at a bottom corner of the gate trench.

[0123] In addition, in the embodiment, a doping concentration of the second-conductivity-type well 121 formed in the first-conductivity-type second-1 epitaxial layer 112a can be higher than a doping concentration of the second-conductivity-type ion implantation region 122. For example, according to the embodiment, there is a technical effect in which a concentration gradient can be achieved in which the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 changes more abruptly than the doping concentration of the second-conductivity-type ion implantation region 122 formed adjacent to the trench gate 132.

[0124] For example, the doping concentration of the second-conductivity-type well 121 can be 2 x 1018 / cm3 to 2 x 1020 / cm3, and the doping concentration of the second-conductivity-type ion implantation region 122 can be 1 x 1018 / cm3 to 1 x 1020 / cm3, but is not limited thereto. 17 19 3 16 17 3

[0125] According to the embodiment, since the doping concentration of the second-conductivity-type well 121 formed under the trench gate 132 can be formed to be higher than the doping concentration of the second-conductivity-type ion implantation region 122, a depletion layer is expanded in the direction of the substrate 110, so that there is a technical effect of increasing a breakdown voltage. In addition, according to the embodiment, since the doping concentration of the second-conductivity-type ion implantation region 122 formed around the trench gate 132 is formed to be lower than the doping concentration of the second-conductivity-type well 121, there is a complex technical effect of lowering a threshold voltage and increasing a current density.

[0126] In the foregoing, the present application has been described with reference to the embodiments, but it will be readily appreciated by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present application, as set forth in the appended claims.​​​​​​

Claims

1. A power semiconductor device, comprising: a substrate; a first-conductivity-type first epitaxial layer provided on the substrate; a first-conductivity-type second epitaxial layer provided on the first-conductivity-type first epitaxial layer; a second-conductivity-type well partially provided in the first-conductivity-type second epitaxial layer; a second-conductivity-type ion-implanted region and a source region provided above the second-conductivity-type well; a source electrode provided on the source region; a gate insulating layer provided in a trench region in which the second-conductivity-type ion-implanted region and a portion of the first-conductivity-type second epitaxial layer are removed; a trench gate provided on the gate insulating layer; an interlayer insulating layer provided on the trench gate; and a gate electrode electrically connected to the trench gate. The first-conductivity-type second epitaxial layer includes a first-conductivity-type 2-1 epitaxial layer provided on the first-conductivity-type first epitaxial layer, and a first-conductivity-type 2-2 epitaxial layer provided on the first-conductivity-type 2-1 epitaxial layer.

2. The power semiconductor device of claim 1, wherein, The second-conductivity-type well is partially provided in the first-conductivity-type 2-1 epitaxial layer.

3. The power semiconductor device of claim 2, wherein, An upper surface of the second-conductivity-type well is equal to or lower than the first-conductivity-type 2-1 epitaxial layer.

4. The power semiconductor device of claim 3, wherein, A doping concentration of the second-conductivity-type well in the first-conductivity-type 2-1 epitaxial layer is higher than a doping concentration of the second-conductivity-type ion-implanted region.

5. The power semiconductor device of claim 3, wherein, The gate insulating layer is in contact with an upper surface of the second-conductivity-type well.

6. The power semiconductor device of claim 3, wherein, The trench gate is arranged in vertical alignment with the second-conductivity-type well.

7. The power semiconductor device of claim 3, wherein, The second-conductivity-type well is provided lower than the trench gate.

8. The power semiconductor device of claim 3, wherein, 9. A power converter comprising the power semiconductor device according to any one of claims 1 to 8.

10. A manufacturing method of a power semiconductor device, comprising: growing a first-conductivity-type first epitaxial layer on a substrate; growing a first-conductivity-type 2-1 epitaxial layer on the first-conductivity-type epitaxial layer; partially forming a second-conductivity-type well by ion-implanting into the first-conductivity-type 2-1 epitaxial layer; growing a first-conductivity-type 2-2 epitaxial layer on the first-conductivity-type 2-1 epitaxial layer; forming a second-conductivity-type ion-implanted region and a source region by ion-implanting into the first-conductivity-type 2-2 epitaxial layer; forming a trench region by removing the second-conductivity-type ion-implanted region and a portion of the first-conductivity-type 2-2 epitaxial layer; forming a gate insulating layer and a trench gate in the trench region; forming an interlayer insulating layer on the trench gate; and forming a gate electrode electrically connected to the trench gate. An upper surface of the second-conductivity-type well is equal to or lower than the first-conductivity-type 2-1 epitaxial layer. A doping concentration of the second-conductivity-type well formed in the first-conductivity-type 2-1 epitaxial layer is higher than a doping concentration of the second-conductivity-type ion-implanted region.

11. The method of manufacturing a power semiconductor device according to claim 10, wherein, ​ 12. The method of manufacturing a power semiconductor device according to claim 10, wherein, ​ 13. The method of manufacturing a power semiconductor device according to claim 10, wherein, In the step of forming the trench region by removing the second conductive type ion implantation region and a portion of the first conductive type 2-2 epitaxial layer, a portion of the second conductive type well is exposed.

14. The method of manufacturing a power semiconductor device according to claim 10, wherein, The gate insulating layer is configured to contact the second conductive type well.

15. The method of manufacturing a power semiconductor device according to claim 10, wherein, The hard mask pattern for forming the trench region is configured to correspond to an opening region of a hard mask pattern for forming the second conductive type well by ion implantation.

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