Etching method and plasma processing apparatus

Abstract

In one exemplary embodiment, an etching method includes: a step of forming a recess overlapping an opening of a mask by etching a silicon layer; a step of forming a protective layer on at least a side wall of the recess; and a step of etching a bottom portion of the recess. The step of forming the protective layer includes: a layer forming step of forming a precursor layer at least on a sidewall of the recess; and a modification step of modifying the precursor layer into a protective layer. The step of etching the bottom of the recess includes: a first step of supplying a pulse of high-frequency electric power from a high-frequency power source; and a second step of supplying a pulse of bias electric power from a bias power supply to a support part supporting the substrate, wherein a period during which the first step is performed and a period during which the second step is performed do not overlap with each other.

Description

TECHNICAL FIELD

[0001] An exemplary embodiment of the present application relates to an etching method and a plasma processing apparatus. BACKGROUND

[0002] Patent Literature 1 relates to a method and an apparatus for reducing roughness using an integrated atomic layer deposition method and an etching method. In Patent Literature 1, a technique of etching a first material layer of a substrate after a conformal layer is deposited on a pattern / mask layer of the substrate by an ALD method is disclosed.

[0003] PRIOR ART DOCUMENTS PATENT LITERATURE Patent Literature 1: Japanese Patent Application Laid-Open No. 2021-504974 SUMMARY

[0004] PROBLEMS TO BE SOLVED BY THE INVENTION For example, sometimes a pattern (a density pattern) including openings of a plurality of sizes is provided on a mask located on an etching object. In this case, there is a tendency that the deeper a trench provided on the etching object is made, the more the depth of the trench is deviated (i.e., the more the etching amount is deviated). In addition to this, there is a tendency that the more a trench is provided via a small opening, the more a shape abnormality such as occurrence of bowing is likely to occur. Therefore, the present application provides an etching method and a plasma processing apparatus capable of suppressing both of occurrence of bowing and deviation of an etching amount corresponding to the size of an opening.

[0005] MEANS FOR SOLVING THE PROBLEMS In one exemplary embodiment, an etching method includes: a step of preparing a substrate including a mask having a density pattern and a silicon layer located below the mask; a step of forming a recess overlapping with an opening of the mask by etching the silicon layer using a first plasma generated from a first processing gas; a step of forming a protective layer at least on a sidewall of the recess; and a step of etching a bottom of the recess using a second plasma generated from a second processing gas, the step of forming the protective layer includes: a layer forming step of forming a precursor layer at least on the sidewall of the recess; and a modification step of modifying the precursor layer to the protective layer using a third processing gas, the step of etching the bottom of the recess includes: a first step of supplying a pulse of high-frequency electric power from a high-frequency power supply; and a second step of supplying a pulse of bias electric power from a bias power source to a support portion that supports the substrate, the period in which the first step is performed and the period in which the second step is performed do not overlap each other.

[0006] Effects of Invention According to one illustrative embodiment, an etching method and a plasma processing apparatus that can suppress both generation of arc bending and deviation of etching amount corresponding to the size of an opening can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a diagram for explaining a structure example of a plasma processing system of one illustrative embodiment.

[0008] Figure 2 is a diagram for explaining a structure example of an inductively coupled plasma processing apparatus of one illustrative embodiment.

[0009] Figure 3 is a flowchart of an etching method of one illustrative embodiment.

[0010] Figure 4 is a cross-sectional view of a substrate that is one example of a method that can be applied Figure 3

[0011] Figure 5 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment.

[0012] Figure 6 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment.

[0013] Figure 7 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment.

[0014] Figure 8 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment.

[0015] Figure 9 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment.

[0016] Figure 10 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment.

[0017] Figure 11 is a cross-sectional view that represents one step of an etching method of one illustrative embodiment. DETAILED DESCRIPTION ​

[0018] Next, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like elements are denoted by like reference numerals.

[0019] Figure 1 is a diagram for explaining a configuration example of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control section 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support section 11, and a plasma generating section 12. The plasma processing chamber 10 has a plasma processing space. In addition, the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply section 20 described later, and the gas exhaust port is connected to an exhaust system 40 described later. The substrate support section 11 is disposed in the plasma processing space, and has a substrate support surface for supporting a substrate.

[0020] The plasma generating section 12 is capable of generating plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space can be a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), an electron-cyclotron-resonance plasma (ECR), a helicon wave plasma (HWP), a surface wave plasma (SWP), or the like. In addition, various types of plasma generating sections including an AC (Alternating Current) plasma generating section and a DC (Direct Current) plasma generating section can be used. In one embodiment, an AC signal (AC electric power) used in the AC plasma generating section has a frequency in the range of 100 kHz to 10 GHz. Thus, the AC signal includes an RF (Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0021] The control section 2 can process a computer executable command for causing the plasma processing apparatus 1 to execute various steps described in the present application. The control section 2 can control each element of the plasma processing apparatus 1 to execute various steps described herein. In one embodiment, a part or all of the control section 2 can be included in the plasma processing apparatus 1. The control section 2 can include a processing section 2al, a storage section 2a2, and a communication interface 2a3. The control section 2 is implemented by, for example, a computer 2a. The processing section 2al can read a program from the storage section 2a2, and execute various control actions by executing the read program. The program can be pre-stored in the storage section 2a2, or can be acquired via a medium as needed. The acquired program is stored in the storage section 2a2, and read from the storage section 2a2 by the processing section 2al and executed. The medium can be various storage media readable by the computer 2a, or can be a communication line connected to the communication interface 2a3. The processing section 2al can be a CPU (Central Processing Unit). The storage section 2a2 can include a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 can communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0022] Next, a configuration example of an inductively coupled plasma processing apparatus as one example of the plasma processing apparatus 1 will be described. Figure 2 is a view for describing a configuration example of an inductively coupled plasma processing apparatus.

[0023] The inductively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply section 20, a power source 30, and an exhaust system 40. The plasma processing chamber 10 includes a dielectric window 101. In addition, the plasma processing apparatus 1 includes a substrate support section 11, a gas introduction section, and an antenna 14. The substrate support section 11 is disposed inside the plasma processing chamber 10. The antenna 14 is disposed on or above the plasma processing chamber 10 (i.e., on or above the dielectric window 101). The plasma processing chamber 10 has a plasma processing space 10s defined by the dielectric window 101, a side wall 102 of the plasma processing chamber 10, and the substrate support section 11. The plasma processing chamber 10 is grounded.

[0024] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting a substrate W and a ring-shaped region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The ring-shaped region 111b of the main body portion 111 encloses the central region 111a of the main body portion 111 in plan view. The substrate W is arranged on the central region 111a of the main body portion 111, and the ring assembly 112 is arranged on the ring-shaped region 111b of the main body portion 111 so as to enclose the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also referred to as a substrate support surface for supporting the substrate W, and the ring-shaped region 111b is also referred to as a ring support surface for supporting the ring assembly 112.

[0025] In one embodiment, the main body portion 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes an electrically conductive member. The electrically conductive member of the base 1110 can function as a biasing electrode. The electrostatic chuck 1111 is arranged on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b arranged in the ceramic member 1111a. The ceramic member 1111a has the central region 111a. In one embodiment, the ceramic member 1111a also has the ring-shaped region 111b. Further, other members surrounding the electrostatic chuck 1111, such as a ring-shaped electrostatic chuck, a ring-shaped insulating member, etc., can have the ring-shaped region 111b. In this case, the ring assembly 112 can be arranged on the ring-shaped electrostatic chuck or the ring-shaped insulating member, or can be arranged on both the electrostatic chuck 1111 and the ring-shaped insulating member. In addition, at least one RF / DC electrode coupled to the RF power source 31 and / or the DC power source 32 described later can be arranged in the ceramic member 1111a. In this case, the at least one RF / DC electrode can function as a biasing electrode. Further, the electrically conductive member of the base 1110 and the at least one RF / DC electrode can function as a plurality of biasing electrodes. In addition, the electrostatic electrode 1111b can function as a biasing electrode. Therefore, the substrate support portion 11 includes at least one biasing electrode.

[0026] The ring assembly 112 includes one or more ring-shaped members. In one embodiment, the one or more ring-shaped members include one or more edge rings and at least one cover ring. The edge rings are formed of an electrically conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0027] Further, the substrate support 11 can include a temperature adjustment module for adjusting at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module can include a heater, a heat transfer medium, the flow path 1110a, or a combination thereof. A heat transfer fluid such as a salt water or a gas can be flowed in the flow path 1110a. In one embodiment, the flow path 1110a is formed within the susceptor 1110, and one or more heaters are disposed within the ceramic member 1111a of the electrostatic chuck 1111. Further, the substrate support 11 can include a heat transfer gas supply portion capable of supplying a heat transfer gas to a gap between a back surface of the substrate W and the central region 111a.

[0028] The gas introduction portion is capable of introducing at least one process gas from the gas supply portion 20 into the plasma processing space 10s. In one embodiment, the gas introduction portion includes a central gas injector (CGI) 13. The central gas injector 13 is disposed above the substrate support 11 and is mounted to a central opening portion formed in the dielectric window 101. The central gas injector 13 has at least one gas supply port 13a, at least one gas flow path 13b, and at least one gas introduction port 13c. Process gas supplied to the gas supply port 13a is capable of being introduced into the plasma processing space 10s from the gas introduction port 13c through the gas flow path 13b. Further, the gas introduction portion can include one or more side gas injectors (SGI) mounted to one or more opening portions formed in the side wall 102 in addition to or instead of the central gas injector 13.

[0029] The gas supply portion 20 can include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply portion 20 is capable of supplying at least one process gas from each corresponding gas source 21 to the gas introduction portion via each corresponding flow controller 22. Each flow controller 22 can include, for example, a mass flow controller or a pressure-controlled flow controller. Further, the gas supply portion 20 can include at least one flow modulation device for modulating or pulsing the flow of at least one process gas.

[0030] The power supply 30 includes an RF power source 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power source 31 is a high frequency power source capable of supplying at least one RF signal (also referred to as RF electric power, high frequency electric power) to the at least one bias electrode and the antenna 14. Thereby, a plasma can be formed from at least one process gas supplied to the plasma processing space 10s. Thus, the RF power source 31 can function as at least a part of the plasma generation section 12. Further, by supplying a bias RF signal to the at least one bias electrode, a bias potential can be generated at the substrate W to attract ions in the formed plasma to the substrate W.

[0031] In one embodiment, the RF power source 31 includes a first RF generation section 31a and a second RF generation section 31b. The first RF generation section 31a is a high frequency power source capable of generating a source RF signal (also referred to as source RF electric power, source high frequency electric power) for plasma generation, coupled to the antenna 14 via at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency in the range of 0.1 kHz to 150 MHz. In one embodiment, it can be that the first RF generation section 31a is capable of generating a plurality of source RF signals having different frequencies. The generated source RF signal(s) is / are supplied to the antenna 14.

[0032] The second RF generation section 31b is a bias power source capable of generating a bias RF signal (also referred to as bias RF electric power, bias electric power), coupled to the at least one bias electrode via at least one impedance matching circuit. The frequency of the bias RF signal can be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 0.1 kHz to 60 MHz. In one embodiment, it can be that the second RF generation section 31b is capable of generating a plurality of bias RF signals having different frequencies. The generated bias RF signal(s) is / are supplied to the at least one bias electrode. Further, in various embodiments, at least one of the source RF signal and the bias RF signal can be pulsed. In this case, the first RF generation section 31a can supply pulses of source high frequency electric power to the antenna 14, and the second RF generation section 31b can supply pulses of bias electric power to the substrate support section 11.

[0033] Further, the power supply 30 can include a DC power source 32 coupled to the plasma processing chamber 10. The DC power source 32 includes a bias DC generation section 32a. In one embodiment, the bias DC generation section 32a is connected to the at least one bias electrode and is capable of generating a bias DC signal. The generated bias DC signal is applied to the at least one bias electrode. Further, the power supply 30 can include a DC power source 32 coupled to the plasma processing chamber 10. The DC power source 32 includes a bias DC generation section 32a. In one embodiment, the bias DC generation section 32a is connected to the at least one bias electrode and is capable of generating a bias DC signal. The generated bias DC signal is applied to the at least one bias electrode.

[0034] In various embodiments, the bias DC signal can be pulsed. In this case, a sequence of voltage pulses is applied to the at least one bias electrode. The voltage pulses can have a pulse waveform of a shape of a rectangle, a trapezoid, a triangle, or a combination thereof. In one embodiment, a waveform generation section for generating a sequence of voltage pulses from a DC signal is connected between the bias DC generation section 32a and the at least one bias electrode. Thus, the bias DC generation section 32a and the waveform generation section constitute a voltage pulse generation section. The voltage pulses can have a positive polarity, or can have a negative polarity. In addition, the sequence of voltage pulses can contain one or more positive polarity voltage pulses and one or more negative polarity voltage pulses in one cycle. Further, it can be that the bias DC generation section 32a is provided in addition to the RF power source 31, or it can be that the bias DC generation section 32a is provided instead of the second RF generation section 31b.

[0035] The antenna 14 includes one or more coils. In one embodiment, the antenna 14 can include an outer coil and an inner coil which are arranged on the same axis. In this case, the RF power source 31 and the DC power source 32 can each be connected to both the outer coil and the inner coil, or can be connected to either one of the outer coil and the inner coil. In the former case, it can be that the same RF generation section is connected to both the outer coil and the inner coil, or it can be that different RF generation sections are connected to the outer coil and the inner coil, respectively.

[0036] The exhaust system 40 can be connected to a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10, for example. The exhaust system 40 can include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space 10s can be adjusted with the pressure regulating valve. The vacuum pump can include a turbo molecular pump, a dry pump, or a combination thereof.

[0037] Figure 3 is a flowchart of an etching method of an exemplary embodiment. Figure 3 The etching method MT1 (hereinafter referred to as "method MT1") shown can be executed by the plasma processing apparatus 1 of the above-described embodiment. The method MT1 can be applied to the substrate W. Thus, the method MT1 is at least a part of a processing method of the substrate W.

[0038] Figure 4 is a cross-sectional view of a substrate which is one example of a method which can be applied Figure 3 to the method. As shown in Figure 4 one embodiment, the substrate W has a mask M, a silicon layer Fl located below the mask M, and a base region UR located below the silicon layer Fl.

[0039] The mask M has at least one opening OP. The at least one opening OP can be a hole or a slit. The at least one opening OP can be formed by development. The development can be performed by the plasma processing apparatus 1 or by a development device different from the plasma processing apparatus 1. The opening OP includes a first opening OP1 and a second opening OP2. The width Dl of the first opening OP1 is smaller than the width D2 of the second opening OP2. The width Dl and the width D2 each become narrower as they approach the silicon layer Fl, but are not limited thereto. The minimum width of the width Dl is, for example, 5 nm or more and 20 nm or less. The minimum width of the width D2 is, for example, 10 nm or more and 30 nm or less. In one embodiment, a portion where the first opening OP1 is provided is sometimes referred to as a dense pattern, and a portion where the second opening OP2 is provided is sometimes referred to as a sparse pattern. Therefore, the mask M can also be referred to as a mask having a dense and sparse pattern.

[0040] In one embodiment, the mask M has a first region Rl on the silicon layer Fl and a second region R2 on the first region Rl. The first region Rl contains, for example, an oxidized material. The oxidized material can be a metal oxide or a silicon oxide (SiO X ). x is a positive real number. The thickness of the first region Rl is not particularly limited and is, for example, 30 nm or more and 100 nm or less. Nitrogen or the like can also be contained in the first region Rl. The second region R2 contains, for example, silicon. The silicon can be amorphous silicon or polycrystal silicon. The thickness of the second region R2 is not particularly limited and is, for example, 30 nm or more and 100 nm or less.

[0041] The silicon layer Fl is an etching target in the etching method MTl and contains silicon. The silicon of the silicon layer Fl can be amorphous silicon, polycrystal silicon, or single crystal silicon. The thickness of the silicon layer Fl is, for example, 200 nm or more and 500 nm or less, but is not limited thereto.

[0042] Hereinafter, for the method MTl, a case where the method MTl is applied to the substrate W using the plasma processing apparatus 1 of the above-described embodiment will be described with reference to Figure 4 , except that Figures 5 to 11 . Figures 5 to 11 Each is a cross-sectional view of one step of the etching method of one illustrative embodiment. In a case where the plasma processing apparatus 1 is used, the method MTl can be executed in the plasma processing apparatus 1 by control of each portion of the plasma processing apparatus 1 by the control portion 2. In the method MTl, as shown in Figure 2 , the substrate W disposed on the substrate support portion 11 in the plasma processing chamber 10 is processed.

[0043] As shown in Figure 3As shown, method MT1 may include steps ST1 to ST8 . Steps ST1 to ST8 may be performed sequentially and may be performed in the same plasma processing chamber 10 .

[0044] (Step ST1) In step ST1, prepare Figure 4 The substrate W is shown. The substrate W can be supported by the substrate support 11 within the plasma processing chamber 10. The opening OP can be formed during step ST1 or before step ST1. A natural oxide film NO is formed on the surface of the silicon layer F1 of the substrate W. The natural oxide film NO is a surface oxide film of the silicon layer F1, and is formed, for example, when the opening OP is formed or when the substrate W is transported into the plasma processing chamber 10.

[0045] (Step ST2) In step ST2, as Figure 5 As shown, the natural oxide film NO is removed. In step ST2, the natural oxide film NO is etched, for example, using plasma generated from a fluorine-containing gas. Fluorine-containing gases include, for example, hydrogen fluoride gas (HF gas), fluorocarbon gas, and hydrofluorocarbon gas. Fluorocarbon gas includes, for example, C4F6 gas, C4F8 gas, C3F8 gas, and CF4 gas. Hydrofluorocarbon gas includes, for example, CHF3 gas, CH2F2 gas, and the like. In one example, first, a fluorine-containing gas is supplied from the gas supply unit 20 into the plasma processing space 10s. Next, a pulse of source high-frequency electric power is supplied from the first RF generating unit 31a to the antenna 14, and a pulse of bias electric power is supplied from the second RF generating unit 31b to the substrate support unit 11. As a result, electrons accelerated in the plasma processing space 10s collide with the fluorine-containing gas, generating plasma from the fluorine-containing gas. Then, the natural oxide film NO is etched using this plasma. The supply of the fluorine-containing gas can be stopped at the end of step ST2.

[0046] (Step ST3) In step ST3, as Figure 6As shown, a recess Re overlapping the opening OP of the mask M is formed by etching (first etching) of the silicon layer Fl using a first plasma generated from a processing gas (first processing gas). In step ST3, partial etching of the silicon layer Fl is performed. The etching of the silicon layer Fl is anisotropic etching using the mask M, but is not limited thereto. The first processing gas can include a halogen-containing gas such as Cl2. The first processing gas can further include an inert gas such as argon or nitrogen, and can further include an oxygen-containing gas or the like. The first plasma is, for example, an inductively coupled plasma, but is not limited thereto. In one example, first, the first processing gas is supplied from the gas supply portion 20 into the plasma processing space 10s. Next, a step of supplying a pulse of source high-frequency electric power from the first RF generation portion 31a to the antenna 14 (first step) and a step of supplying a pulse of bias electric power from the second RF generation portion 31b to the substrate support portion 11 (second step) are performed. By performing the above first step and the above second step, the first plasma is generated. Thereby, electrons accelerated in the plasma processing space 10s collide with the first processing gas, and the first plasma is generated from the first processing gas. Then, the silicon layer Fl is etched with the first plasma. The supply of the first processing gas can be stopped at the end of step ST3.

[0047] In step ST3, the above first step and the above second step can not be performed at the same time. In other words, a period (first period) in which a pulse of source high-frequency electric power is supplied from the first RF generation portion 31a to the antenna 14 and a period (second period) in which a pulse of bias electric power is supplied from the second RF generation portion 31b to the substrate support portion 11 can not overlap each other. In one example, the above first step and the above second step are sequentially and continuously performed. In this case, the first period and the second period continuously overlap each other. In step ST3, the length of the first period and the length of the second period can be the same as each other, or can be different from each other. In one example, the first period can be 1.5 times or more, can be 2 times or more, can be 3 times or less, or can be 2.5 times or less than the second period. Further, the above first step and the above second step can be sequentially performed without a gap, but are not limited thereto. For example, there can be a gap time (interval) from the above first step to switching to the above second step. In other words, there can be a short blank period between the above first period and the above second period.

[0048] In step ST3, the first and second steps can be performed alternately and continuously, but this is not limited to this. For example, after the second step is completed, the first step can be performed again after a specified interval. In this case, step ST3 includes a step (a third step) in which neither the source high-frequency electric power pulse nor the bias electric power pulse is supplied. In one example, within a certain unit time period (one cycle), the first, second, and third steps are performed sequentially and continuously. In other words, the unit time period in one example consists of the first and second consecutive time periods, and a time period (also referred to as a third time period or an offset time period) during which the third step is performed. The third time period can be longer or shorter than at least one of the first and second time periods, or can be the same as at least one of the first and second time periods. In one example, the third time period is approximately the same as the first time period.

[0049] The recess Re includes a first recess Re1 that overlaps with the first opening OP1 and a second recess Re2 that overlaps with the second opening OP2. The width w1 of the first recess Re1 corresponds to the minimum width D1 of the first opening OP1, while the width w2 of the second recess Re2 corresponds to the minimum width D2 of the second opening OP2. The depths of the first recess Re1 and the second recess Re2 are each, for example, not less than 30% and not more than 60% of the thickness of the silicon layer F1. In one example, the depth of the second recess Re2 is greater than that of the first recess Re1 due to variations in etching depth depending on the width of the opening OP of the mask M (microloading effect), but this is not limiting. The depths of the first recess Re1 and the second recess Re2 may also be the same.

[0050] (Steps ST4 to ST6) In steps ST4 to ST6, if Figure 8 、 Figure 9 As shown in FIG. 1 , a protective layer PL is formed at least on the sidewall SW of the recess Re. Figure 7As shown, in step ST4, a precursor layer PCL is formed at least on the sidewalls SW of the recess Re (layer formation step). In step ST4, the precursor layer PCL is formed using plasma generated from the process gas supplied into the plasma processing chamber 10. The precursor layer PCL may cover the entire sidewalls SW or only a portion of the sidewalls SW. The precursor layer PCL may be formed not only on the sidewalls SW of the recess Re, but also on the bottom BT of the recess Re, on the side surfaces of the mask M, or on the top surface of the mask M. In one example, the precursor layer PCL is formed using chemical vapor deposition (CVD), but this is not limited to this. The CVD method may be thermal CVD or plasma CVD. By using CVD, the precursor layer PCL can be easily formed in the desired area (i.e., on the sidewalls SW of the recess Re). In other words, compared with the atomic layer deposition method (ALD method), it is possible to make it less likely that the precursor layer PCL is formed on the bottom portion BT of the recessed portion Re (particularly, on the bottom portion BT of the first recessed portion Re1 ).

[0051] The process gas used in step ST4 can include at least one of a silicon-containing gas such as SiH4 or SiCl4, a diluent gas such as argon, helium, or nitrogen, and a halogen-containing gas such as HBr. The silicon-containing gas can serve as the source gas for the precursor layer PCL. Therefore, the precursor layer PCL is a layer primarily composed of silicon. If the process gas includes a halogen-containing gas, the precursor layer PCL will contain halogen. For example, if the process gas includes HBr, the precursor layer PCL will contain Br. The supply of the process gas can be stopped at the end of step ST4.

[0052] Then, in step ST5, Figure 8 As shown, the precursor layer PCL is modified into the protective layer PL using an oxygen-containing gas as a process gas (third process gas) (modification step). In step ST5, the oxygen-containing gas is supplied from the gas supply unit 20 into the plasma processing space 10s. This oxidizes (ashes) the precursor layer PCL, forming the protective layer PL as a silicon oxide film. The ashing of the precursor layer PCL can be performed simply by supplying the oxygen-containing gas into the plasma processing space 10s, or using plasma generated from the oxygen-containing gas. The oxygen-containing gas may contain, for example, at least one of oxygen, carbon dioxide, carbon monoxide, and carbonyl sulfide.

[0053] If step ST4 and step ST5 have not been performed for the prescribed number of times (step ST6: No), step ST4 and step ST5 are performed again in sequence. Thus, after the precursor layer PCL is deposited on the protective layer PL, the precursor layer PCL is ashed. Then, as shown in FIG. Figure 9As shown, a portion of the protective layer PL is removed. Thereby, the bottom BT of the recess Re can be exposed. In step ST7, another portion of the protective layer PL can be thinned. In step ST7, the portion of the protective layer PL on the bottom BT of the recess Re is removed by plasma generated from a fluorine-containing gas, for example, by the same method as in step ST2. The fluorine-containing gas used in step ST7 is the same as the fluorine-containing gas used in step ST2, for example, but is not limited thereto. The supply of the fluorine-containing gas can be stopped at the end of step ST7.

[0054] (Step ST7) In step ST7, as shown, Figure 10 a portion of the protective layer PL is removed. Thereby, the bottom BT of the recess Re can be exposed. In step ST7, another portion of the protective layer PL can be thinned. In step ST7, the portion of the protective layer PL on the bottom BT of the recess Re is removed by plasma generated from a fluorine-containing gas, for example, by the same method as in step ST2. The fluorine-containing gas used in step ST7 is the same as the fluorine-containing gas used in step ST2, for example, but is not limited thereto. The supply of the fluorine-containing gas can be stopped at the end of step ST7.

[0055] (Step ST8) In step ST8, as shown, Figure 11 the bottom BT of the recess Re is etched (second etching) using a second plasma generated from a processing gas (second processing gas). In step ST8, the bottom BT of the recess Re is etched by the etching of the silicon layer Fl using the second plasma. Thereby, the bottom BT of the recess Re reaches the base region UR or the vicinity of the base region UR. The etching of the bottom BT is anisotropic etching using the mask M, but is not limited thereto. In step ST8, the sidewall SW of the recess Re is covered with the protective layer PL. Therefore, the aspect ratio of the etching amount of the bottom BT with respect to the sidewall SW becomes extremely high. Therefore, not only the bottom BT of the second recess Re2 but also the bottom BT of the first recess Re1 can reach the base region UR or the vicinity of the base region UR. That is, the micro-loading effect is less likely to occur. For example, the total etching amount of the first recess Re1 is 96.5% or more, 97% or more, 98% or more, or 99% or more of the total etching amount of the second recess Re2.

[0056] The second processing gas can be the same as the first processing gas described above, or can be different from the first processing gas described above. In the case where the second processing gas is different from the first processing gas, for example, the first processing gas contains Cl2gas as the halogen-containing gas, and the second processing gas contains Cl2gas and HBr gas as the halogen-containing gas. In this case, the flow rate of the Cl2gas in the second processing gas is, for example, 2 times or more, 3 times or more, or 4 times or more the flow rate of the HBr gas, and is 5 times or less. The second processing gas can further include an inert gas such as argon or nitrogen, or the like, and can further include an oxygen-containing gas or the like. The second plasma is, for example, an inductively coupled plasma, but is not limited thereto.

[0057] In one example, first, the second processing gas is supplied from the gas supply portion 20 into the plasma processing space 10s. Next, the second plasma is generated by implementing the first step described above and the second step described above. Thereby, the electrons accelerated in the plasma processing space 10s collide with the second processing gas, and the second plasma is generated from the second processing gas. Then, the silicon layer Fl is etched using the second plasma.

[0058] The period of the first step described above in the step ST8 can be the same as the period of the first step described above in the step ST3, or can be different from the period of the first step described above in the step ST3. Similarly, the period of the second step described above in the step ST8 can be the same as the period of the second step described above in the step ST3, or can be different from the period of the second step described above in the step ST3. In one example, the period of the first step described above in the step ST8 is longer than the period of the first step described above in the step ST3, and the period of the second step described above in the step ST8 is shorter than the period of the second step described above in the step ST3. The total period of the first step described above and the second step described above in the step ST8 can be the same as the total period of the first step described above and the second step described above in the step ST3, or can be different from the total period of the first step described above and the second step described above in the step ST3. In one example, the total period of the first step described above and the second step described above in the step ST8 can be longer than the total period of the first step described above and the second step described above in the step ST3. In addition, in the step ST8, the third step described above can be implemented in addition to the first step described above and the second step described above, similarly to the step ST3. In this case, the period of the third step described above in the step ST8 can be the same as the period of the third step described above in the step ST3, or can be different from the period of the third step described above in the step ST3. The supply of the second processing gas can be stopped at the end of the step ST8.

[0059] In step ST3, the control section 2 controls the gas supply section 20 and the plasma generating section 12 while the substrate W is supported on the substrate support section 11, and forms the recess Re by etching the silicon layer Fl using the first plasma generated from the first processing gas. In steps ST4 to ST6, the control section 2 controls at least one of the gas supply section 20 and the plasma generating section 12, and forms the protective layer PL at least on the side wall SW of the recess Re. At this time, the control section 2 controls the gas supply section 20 and the plasma generating section 12 so that the precursor layer PCL is modified to the protective layer PL using the third processing gas described above after the precursor layer PCL is formed at least on the side wall SW of the recess Re. In step ST8, the bottom portion BT of the recess Re is etched using the second plasma generated from the second processing gas. At this time, the control section 2 controls the high-frequency power supply and the bias power supply so that the pulse of the source high-frequency electric power is supplied in the first period, and the pulse of the bias electric power is supplied to the substrate support section 11 in the second period which does not overlap with the first period.

[0060] Next, one example of the effect of the illustrative embodiment will be described with reference to Reference Examples described below. In Reference Example 1, the etching of the silicon layer Fl is performed by one time. That is, in Reference Example 1, steps ST4 to ST8 are not performed. In Reference Example 1, the total etching amount of the first recess Re1 is about 90% or so of the total etching amount of the second recess Re2. Therefore, in the case where the thickness of the silicon layer Fl is about 200 nm, the difference between the total etching amount of the first recess Re1 and the total etching amount of the second recess Re2 will be 20 nm or more in Reference Example 1. In Reference Example 2, instead of not performing steps ST4 to ST7, ashing with oxygen is performed between step ST3 and step ST8. In Reference Example 2, the total etching amount of the first recess Re1 is about 95% or so of the total etching amount of the second recess Re2. Therefore, in the case where the thickness of the silicon layer Fl is about 200 nm, the difference between the total etching amount of the first recess Re1 and the total etching amount of the second recess Re2 will be 10 nm or more in Reference Example 2.

[0061] According to Embodiment 1 in which the steps ST1 to ST8 of the method MT1 are implemented, both the occurrence of bowing and the deviation of the etching amount corresponding to the size of the opening can be suppressed. Specifically, in Embodiment 1, after the partial etching of the silicon layer F1 in the step ST3, the protective layer PL is formed at least on the side wall SW of the recess Re in the steps ST4 to ST6. Then, in the step ST8, the etching of the silicon layer F1 is performed again, and the bottom BT of the recess Re is etched. Thereby, not only the bottom BT of the second recess Re2 but also the bottom BT of the first recess Re1 can reach the base region UR or the vicinity of the base region UR. That is, the micro-loading effect is less likely to occur. Therefore, in Embodiment 1, the total etching amount of the first recess Re1 can exceed 99% of the total etching amount of the second recess Re2. In other words, even in the case where the thickness of the silicon layer F1 is about 200 nm, the difference between the total etching amount of the first recess Re1 and the total etching amount of the second recess Re2 can be suppressed to within several nm. Further, in the step ST8 described above, since the protective layer PL is present, the side wall SW of the recess Re is less likely to be etched, and thus bowing is less likely to occur in Embodiment 1.

[0062] In one embodiment, in the step ST4, the precursor layer PCL can be formed by a CVD method. In this case, the precursor layer PCL can be formed well at least on the side wall SW of the recess Re.

[0063] In one embodiment, the processing gas including a silicon-containing gas and a halogen-containing gas can be used to form the precursor layer PCL.

[0064] In one embodiment, in the step of forming the protective layer PL, the step ST4 and the step ST5 can be alternately repeated. In this case, the occurrence of bowing can be well suppressed.

[0065] In one embodiment, the method MT1 can include a step ST7 of removing the protective layer PL on the bottom BT before the step ST8. In this case, the occurrence of bowing can be well suppressed.

[0066] The above describes various exemplary embodiments, but is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and changes can be made. In addition, elements in different embodiments can be combined to form other embodiments.

[0067] Here, various exemplary embodiments included in the present application are described in [E1] to [E10] below.

[0068] [E1] An etching method, characterized by comprising: a step of preparing a substrate including a mask having a dense-and-dilute pattern and a silicon layer located below the mask; a step of forming a recess overlapping with an opening of the mask by etching the silicon layer using a first plasma generated from a first processing gas; a step of forming a protective layer at least on a sidewall of the recess; and a step of etching a bottom of the recess using a second plasma generated from a second processing gas, the step of forming the protective layer includes: a layer forming step of forming a precursor layer at least on the sidewall of the recess; and a modification step of modifying the precursor layer to the protective layer using a third processing gas, the step of etching the bottom of the recess includes: a first step of supplying a pulse of high-frequency electric power from a high-frequency power supply source; and a second step of supplying a pulse of bias electric power to a support portion supporting the substrate from a bias power supply, a period in which the first step is implemented and a period in which the second step is implemented do not overlap with each other.

[0069] [E2] The etching method according to [E1], wherein in the layer forming step, the precursor layer is formed by a CVD method.

[0070] [E3] The etching method according to [E1] or [E2], wherein the precursor layer is formed using a processing gas including a silicon-containing gas and a halogen-containing gas.

[0071] [E4] The etching method according to any one of [E1] to [E3], wherein in the step of forming the protective layer, the layer forming step and the modification step are alternately repeated.

[0072] [E5] The etching method according to any one of [E1] to [E4], wherein the step of etching the bottom of the recess includes a third step of not supplying both the pulse of the source high-frequency electric power and the pulse of the bias electric power.

[0073] [E6] The etching method according to any one of [E1] to [E5], wherein each of the first plasma and the second plasma is an inductively coupled plasma.

[0074] [E7] The etching method according to any one of [E1] to [E6], wherein the second processing gas is different from the first processing gas.

[0075] [E8] The etching method according to any one of [E1] to [E7], wherein the third processing gas is an oxygen-containing gas.

[0076] [E9] The etching method according to any one of [E1] to [E8], further comprising, before the step of etching the bottom of the recess, a step of removing the protective layer on the bottom.

[0077] [E10] A plasma processing apparatus, comprising: a chamber; a substrate support section provided in the chamber; a gas supply section capable of supplying a processing gas into the chamber; a plasma generation section capable of generating a plasma from the processing gas in the chamber; and a control section, the plasma generation section has a high-frequency power source for supplying a pulse of source high-frequency electric power and a bias power source for supplying a pulse of bias electric power to the substrate support section, the control section is capable of controlling the gas supply section and the plasma generation section in a state where the substrate support section supports a substrate including a mask having a dense-and-dilute pattern and a silicon layer under the mask, forming a recess overlapping with an opening of the mask by etching the silicon layer using a first plasma generated from a first processing gas, forming a protective layer at least on a side wall of the recess, etching a bottom of the recess using a second plasma generated from a second processing gas, in forming the protective layer, the control section is capable of controlling the gas supply section and the plasma generation section such that, after forming a precursor layer at least on the side wall of the recess, the precursor layer is modified into the protective layer using a third processing gas, in etching the bottom of the recess, the control section is capable of controlling the high-frequency power source and the bias power source such that a pulse of the source high-frequency electric power is supplied for a first period and a pulse of the bias electric power is supplied to the substrate support section for a second period that does not overlap with the first period.

[0078] It should be understood from the above description that various embodiments of the present application are described in the present specification for the purpose of illustration and can be variously changed without departing from the scope and spirit of the present application. Therefore, the various embodiments disclosed in the present specification are not intended to limit the present application, and the true scope and spirit of the present application are represented by the appended claims.

[0079] Reference numerals 1…plasma processing apparatus, 2…control section, 10…plasma processing chamber, 11…substrate support section, 12…plasma generation section, 20…gas supply section, F1…silicon layer, M…mask, NO…natural oxide film, OP…opening, OP1…first opening, OP2…second opening, PCL…precursor layer, PL…protective layer, Re…recess, Re1…first recess, Re2…second recess, SW…side wall, W…substrate.

Claims

1. An etching method characterized by, comprising: a step of preparing a substrate including a mask having a dense-and-dilute pattern and a silicon layer located below the mask; a step of forming a recess overlapping with an opening of the mask by etching the silicon layer using a first plasma generated from a first processing gas; a step of forming a protective layer at least on a sidewall of the recess; and a step of etching a bottom of the recess using a second plasma generated from a second processing gas, the step of forming the protective layer includes: a layer forming step of forming a precursor layer at least on the sidewall of the recess; and a modification step of modifying the precursor layer to the protective layer using a third processing gas, the step of etching the bottom of the recess includes: a first step of supplying a pulse of high-frequency electric power from a high-frequency power supply; and a second step of supplying a pulse of bias electric power to a support portion supporting the substrate from a bias power supply, a period in which the first step is performed and a period in which the second step is performed do not overlap with each other.

2. The etching method according to claim 1, wherein: in the layer forming step, the precursor layer is formed by a CVD method.

3. The etching method according to claim 1 or 2, wherein: the precursor layer is formed using a processing gas including a silicon-containing gas and a halogen-containing gas.

4. The etching method according to claim 1 or 2, wherein: in the step of forming the protective layer, the layer forming step and the modification step are alternately repeated.

5. The etching method according to claim 1 or 2, wherein: the step of etching the bottom of the recess includes a third step of not supplying both the pulse of the source high-frequency electric power and the pulse of the bias electric power.

6. The etching method according to claim 1 or 2, wherein: each of the first plasma and the second plasma is an inductively coupled plasma.

7. The etching method according to claim 1 or 2, wherein: the second processing gas is different from the first processing gas.

8. The etching method according to claim 1 or 2, wherein: the third processing gas is an oxygen-containing gas. further comprising:

9. The etching method according to claim 1 or 2, wherein a step of removing the protective layer located on the bottom before the step of etching the bottom of the recess. comprising:

10. A plasma processing apparatus, characterized by, a chamber; a substrate support portion provided in the chamber; a gas supply portion capable of supplying a processing gas into the chamber; a plasma generation portion capable of generating a plasma from the processing gas in the chamber; and a control portion, the plasma generation portion has: a high-frequency power supply for supplying a pulse of high-frequency electric power; and a bias power supply for supplying a pulse of bias electric power to the substrate support portion, the control portion is capable of controlling the gas supply portion and the plasma generation portion in a state where the substrate support portion supports a substrate including a mask having a dense-and-dilute pattern and a silicon layer located below the mask, a recess overlapping with an opening of the mask is formed by etching the silicon layer using a first plasma generated from a first processing gas, ​ ​ ​ forming a protective layer at least on a side wall of the recess, etching a bottom of the recess using a second plasma generated from a second processing gas, when forming the protective layer, the control section is capable of controlling the gas supply section and the plasma generation section so that after forming a precursor layer at least on the side wall of the recess, the precursor layer is modified to the protective layer using a third processing gas, when etching the bottom of the recess, the control section is capable of controlling the high-frequency power supply and the bias power supply so that pulses of the source high-frequency electric power are supplied for a first period, and pulses of the bias electric power are supplied to the substrate support section for a second period which does not overlap with the first period.

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