Preparation method and system of stable sub-state based on graph state and electronic equipment

Abstract

The invention discloses a graph-state-based stable sub-state preparation method and system and electronic equipment, and the method comprises the steps: obtaining and preprocessing a stable sub-generator, and obtaining a complete stable sub-generator; generating an initial check matrix according to the complete stabilizer generator; converting the initial check matrix into a graph-state check matrix, and recording a conversion operation performed in the conversion process; constructing a graph state preparation circuit according to the check matrix of the graph state; constructing a stable sub-state reduction circuit according to the conversion operation; combining the graph state preparation circuit and the stable sub-state reduction circuit into a total circuit; and obtaining an initialized quantum state, and enabling the initialized quantum state to execute the total circuit to obtain a stable sub-state. According to the invention, the graph state is used as a medium, the complexity of circuit design is reduced, the calculation efficiency is improved, and the method is suitable for a large-scale quantum system. Meanwhile, through the accurate mapping relation between the stable sub-state and the graph state, the approximate error is avoided.

Description

Technical Field

[0001] This invention relates to the field of quantum technology, and in particular to a method for preparing a graph-based stable substate, a system for preparing a graph-based stable substate, and an electronic device. Background Technology

[0002] Stabilizer states are a core resource in quantum information science, playing an irreplaceable role in several key areas. For example, in quantum error correction, many important quantum error-correcting codes, such as [[n, k, d]] quantum error-correcting codes, are largely constructed based on stabilizer states. Stabilizer states effectively resist quantum noise and decoherence effects. By measuring stabilizer generators, errors in qubits can be detected and corrected, ensuring the accuracy of quantum information during transmission and storage. This is crucial for achieving reliable quantum communication and large-scale quantum computing. Stabilizer states also hold significant importance in quantum simulation. For instance, in quantum chemistry, the ground state energy of a molecular system can be obtained by solving for the minimum expectation value of the Hamiltonian, and stabilizer states are ideal candidate solutions to this problem. By preparing and manipulating stabilizer states, complex quantum systems can be accurately simulated, providing powerful tools for new material development, drug design, and other fields. In quantum computing, stabilizer state encoding can improve the reliability and fault tolerance of computation, enabling quantum algorithms to operate correctly in noisy environments.

[0003] However, the methods for preparing stable quantum states in related technologies have some limitations. Current methods rely on variational quantum classical hybrid algorithms to approximate the preparation of the target state through parameterized quantum circuits. This method has significant drawbacks: 1. It requires training and optimization of the complete quantum state using a classical simulator, and the computational cost increases exponentially with the number of qubits, making it difficult to adapt to large-scale systems and resulting in high computational complexity. 2. The approximation characteristics of variational algorithms lead to the accumulation of preparation errors, especially in many-body systems, where the fidelity decreases significantly with the increase of system size. Summary of the Invention

[0004] The present invention is proposed to solve at least one of the above-mentioned problems. According to a first aspect of the present invention, a method for preparing a graph-based stable substate is provided, the method comprising:

[0005] Obtain and preprocess stable sub-generators to obtain complete stable sub-generators.

[0006] Based on the complete stable sub-generator, an initial parity-check matrix is ​​generated.

[0007] The initial parity check matrix is ​​converted into a graphical parity check matrix, and the conversion operations performed during the conversion process are recorded.

[0008] Based on the verification matrix of the pattern, construct the pattern preparation circuit.

[0009] Based on the aforementioned conversion operation, a stable substate restoration circuit is constructed.

[0010] The pattern preparation circuit and the stable sub-state restoration circuit are combined into a total circuit.

[0011] An initial quantum state is obtained, and the initial quantum state is made to execute the overall circuit to obtain a stable substate.

[0012] The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. The parity-check matrix of the graphical state is characterized by the X matrix being an identity matrix, and all qubits in the initialized quantum state are in a state where... state.

[0013] In one embodiment of the present invention, the step of converting the initial parity-check matrix into a graph-state parity-check matrix includes:

[0014] The X matrix is ​​converted into an upper triangular matrix or a lower triangular matrix, and the upper triangular matrix or the lower triangular matrix is ​​converted into the identity matrix.

[0015] Set the diagonal of the Z matrix to zero.

[0016] Set all phase indices to zero.

[0017] In one embodiment of the present invention, the step of converting the X matrix into an upper triangular matrix includes:

[0018] Traverse the X matrix row by row and determine Is it equal to 1?

[0019] like and Then through ,make .

[0020] like and Then through ,make 1, and return the judgment. The steps to determine if it equals 1.

[0021] like And none Then execute The door is opened, and the judgment is returned. The steps to determine if it equals 1.

[0022] The step of converting the upper triangular matrix into the identity matrix includes:

[0023] Traverse the upper triangular matrix row by row and determine... Is it equal to 1?

[0024] like Then through ,Will Set to 0.

[0025] The step of setting the diagonal of the Z matrix to zero includes:

[0026] Traverse the Z matrix row by row and determine Is it equal to 1?

[0027] like Then execute The door will Set to 0.

[0028] The step of setting all phase indices to zero includes:

[0029] Iterate through the phase indices row by row to determine... Is it 1?

[0030] like Then execute The door will Set to 0.

[0031] In one embodiment of the present invention, the include:

[0032] The phase index of the j-th row is determined using the following formula:

[0033]

[0034] The first XOR to the first Line up.

[0035] The include:

[0036] The first commutation matrix Line and number OK.

[0037] The execution The steps for opening a door include:

[0038] The phase index of the i-th row is updated sequentially using the following formula:

[0039]

[0040] Swap the a-th column of matrix Z with the a-th column of matrix X.

[0041] The execution The steps for opening a door include:

[0042] The phase index of the i-th row is updated sequentially using the following formula:

[0043]

[0044] The matrix elements are updated sequentially using the following formula. :

[0045]

[0046] The execution The steps for opening a door include:

[0047] The phase index of the i-th row is updated sequentially using the following formula:

[0048]

[0049] in, This represents the H gate on the a-th qubit. This represents the S-gate on the a-th qubit. This represents the Z-gate on the a-th qubit. This represents the element in the i-th row and j-th column of matrix X. This represents the element in the i-th row and j-th column of the Z matrix. Represents the i-th phase index. , , , , where n represents the number of qubits.

[0050] In one embodiment of the present invention, the step of constructing a pattern preparation circuit based on the pattern verification matrix includes:

[0051] An H-gate is applied independently to each qubit.

[0052] Based on the adjacency matrix in the parity check matrix of the pattern, a CZ gate is applied to obtain the pattern preparation circuit.

[0053] In one embodiment of the present invention, the conversion operation includes: , H-gate, S-gate, and Z-gate; the step of constructing a stable substate restoration circuit based on the transition operation includes:

[0054] The H gate, S gate, and Z gate in the conversion operation are combined in reverse order to generate the stable substate restoration circuit.

[0055] In one embodiment of the present invention, the step of merging the pattern preparation circuit and the stable sub-state restoration circuit into a total circuit includes:

[0056] Construct the inverse circuit of the pattern preparation circuit to obtain the first inverse circuit.

[0057] Construct the inverse circuit of the stable substate restoration circuit to obtain the second inverse circuit.

[0058] The first inverse circuit and the second inverse circuit are connected in series in sequence to obtain the total circuit.

[0059] In one embodiment of the present invention, the step of obtaining and preprocessing stable sub-generators includes:

[0060] Determine whether the number of stable generators is equal to the number of qubits in the stable state to be prepared.

[0061] If equal, the stable sub-generator is taken as the complete stable sub-generator.

[0062] If they are not equal, the stable sub-generators are padded to obtain the complete stable sub-generators.

[0063] According to a second aspect of the present invention, a graph-based stable substate preparation system is provided, comprising: a preprocessing module, an initialization module, a transformation module, a graph preparation circuit construction module, a stable substate reduction circuit construction module, a total circuit construction module, and a stable substate preparation module.

[0064] The preprocessing module is used to acquire and preprocess stable sub-generators to obtain complete stable sub-generators.

[0065] The initialization module is used to generate an initial verification matrix based on the complete stable sub-generator.

[0066] The transformation module is used to convert the initial parity check matrix into a graphical parity check matrix and record the transformation operations performed during the transformation process.

[0067] The pattern preparation circuit construction module is used to construct a pattern preparation circuit based on the check matrix of the pattern.

[0068] The stable substate restoration circuit construction module is used to construct a stable substate restoration circuit according to the conversion operation.

[0069] The overall circuit construction module is used to combine the pattern preparation circuit and the stable sub-state restoration circuit into an overall circuit.

[0070] The stable substate preparation module is used to obtain an initial quantum state and make the initial quantum state execute the overall circuit to obtain a stable substate.

[0071] The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. The parity-check matrix of the graphical state is characterized by the X matrix being an identity matrix, and all qubits in the initialized quantum state are in a state where... state.

[0072] According to a third aspect of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein when the computer program is executed by the processor, it implements any of the above-described methods for preparing stable substates based on graph states.

[0073] According to embodiments of the present invention, a method, system, and electronic device for preparing stable substates based on graph states are provided. The method for preparing stable substates based on graph states uses graph states as an intermediary, reducing the complexity of circuit design, thereby reducing computational complexity and improving the efficiency of quantum information processing, making this application adaptable to large-scale quantum systems. Furthermore, by establishing a precise mapping relationship between stable substates and graph states, approximation errors are avoided, achieving 100% theoretical fidelity. Simultaneously, preprocessing the stable substate generators improves the accuracy and reliability of stable substate preparation. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 This is a schematic flowchart of a method for preparing a graph-based stable substate according to an embodiment of the present invention.

[0076] Figure 2 A schematic diagram of a quantum circuit provided in an embodiment of the present invention;

[0077] Figure 3 A schematic diagram of a quantum circuit provided for another embodiment of the present invention;

[0078] Figure 4 This is a schematic diagram of the structure of a graph-based stable substate preparation system provided in an embodiment of the present invention;

[0079] Figure 5 This is a hardware structure block diagram of a computer terminal for a method of preparing stable substates based on graph states, as provided in an embodiment of the present invention. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of the present invention.

[0081] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0082] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0083] To fully understand this invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by this invention. Optional embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0084] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0085] To improve the efficiency of quantum information processing, the first aspect of this invention provides a method for preparing stable substates based on graph states, such as... Figure 1 As shown, the method for preparing stable substates based on graph states includes:

[0086] S1: Obtain and preprocess stable sub-generators to obtain complete stable sub-generators.

[0087] It should be noted that a stable substate can be defined by a set of stable sub-generators. A stable sub-generator can be represented as a single... binary matrix:

[0088]

[0089] in, row representation One generator, Indicates the The phase index of each generator corresponds to the phase. And for the first One generator:

[0090] If the first Position ,but It is 1 if it is true, otherwise it is 0.

[0091] If the first Position ,but It is 1 if it is true, otherwise it is 0.

[0092] If the first Position ,but All are 1, otherwise all are 0.

[0093] S2, Generate the initial parity-check matrix based on the complete stable sub-generators.

[0094] S3 converts the initial parity check matrix into a graphical parity check matrix and records the conversion operations performed during the conversion process.

[0095] It's important to note that graph states are a class of quantum states closely related to graph theory. The entanglement structure between their qubits is described by an undirected graph, playing a crucial role in distributed quantum computing. Taking Measurement Based Quantum Computing (MBQC) as an example, graph states serve as initial states, and through a series of carefully designed single-qubit measurement operations, arbitrary quantum computing tasks can be realized. This computational model exhibits high parallelism and scalability, providing a highly promising approach for building large-scale quantum computing systems. Furthermore, the preparation and manipulation of graph states are relatively simple, requiring only H-gates and CZ-gates, and are highly compatible with current mainstream quantum hardware platforms such as superconducting and ion traps, demonstrating good hardware feasibility.

[0096] For example, the graph state consists of a vertex set V and an undirected, unweighted edge set E. Each vertex in vertex set V corresponds to a qubit, while the edge set E determines the interaction relationships between the qubits. After the initial parity-check matrix is ​​transformed into the parity-check matrix of the graph state, each generator can be represented as: ,in, As the vertex, Represents vertices The edge neighborhood of the graph. The parity check matrix of the graph can be represented as: ,in, It is an adjacency matrix. It is the identity matrix. It is a column vector of phases, usually... .

[0097] S4. Construct the pattern preparation circuit based on the parity check matrix in the pattern.

[0098] As an example, the generation process of a patterned fabrication circuit may include initialization and entanglement generation.

[0099] S5, construct a stable sub-state restoration circuit based on the conversion operation.

[0100] As an example, a stable substate restoration circuit can be constructed based on the column operations of the transformation operation.

[0101] S6 combines the pattern preparation circuit and the stable sub-state restoration circuit into a total circuit.

[0102] S7: Obtain an initial quantum state and make the initial quantum state execute the total circuit to obtain a stable quantum state.

[0103] The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. A characteristic of the graphical parity-check matrix is ​​that the X matrix is ​​an identity matrix, and all qubits in the initialized quantum state are in a state of... state.

[0104] The graph-based stable substate preparation method of this invention uses graph states as an intermediary, reducing the complexity of circuit design and thus computational complexity, improving the efficiency of quantum information processing, and making this application adaptable to large-scale quantum systems. Furthermore, by establishing a precise mapping relationship between stable substates and graph states, approximation errors are avoided, achieving 100% theoretical fidelity. Simultaneously, preprocessing the stable substate generators enhances the accuracy and reliability of stable substate preparation.

[0105] In some embodiments, the step of converting the initial parity-check matrix into a graphical parity-check matrix includes:

[0106] S31 converts the X matrix into an upper triangular matrix or a lower triangular matrix, and converts the upper triangular matrix or the lower triangular matrix into an identity matrix.

[0107] S32 sets the diagonal of the Z matrix to zero.

[0108] S33 sets all phase indices to zero.

[0109] Specifically, the steps to convert the X matrix into an upper triangular matrix include:

[0110] S3111, traverse matrix X row by row and determine... Is it equal to 1?

[0111] S3112, if and Then through ,make .

[0112] S3113, if and Then through ,make 1, and return the judgment. The steps to determine if it equals 1.

[0113] S3114, if And none Then execute The door is opened, and the judgment is returned. The steps to determine if it equals 1.

[0114] The steps to convert an upper triangular matrix into an identity matrix include:

[0115] S3121, traverse the upper triangular matrix row by row and determine... Is it equal to 1?

[0116] S3122, if Then through ,Will Set to 0.

[0117] The steps to set the diagonal of the Z matrix to zero include:

[0118] S321, Traverse the Z matrix row by row and determine... Is it equal to 1?

[0119] S322, if Then execute The door will Set to 0.

[0120] The steps to set all phase indices to zero include:

[0121] S331, traverse the phase index row by row to determine Is it 1?

[0122] S332, if Then execute The door will Set to 0.

[0123] More specifically, include:

[0124] The phase index of the j-th row is determined using the following formula:

[0125]

[0126] The first XOR to the first Line up.

[0127] Including: the first commutation matrix Line and number OK.

[0128] implement The steps for opening a door include:

[0129] The phase index of the i-th row is updated sequentially using the following formula:

[0130]

[0131] Swap the a-th column of matrix Z with the a-th column of matrix X.

[0132] implement The steps for opening a door include:

[0133] The phase index of the i-th row is updated sequentially using the following formula:

[0134]

[0135] The matrix elements are updated sequentially using the following formula. :

[0136]

[0137] implement The steps for opening a door include:

[0138] The phase index of the i-th row is updated sequentially using the following formula:

[0139]

[0140] in, This represents the H gate on the a-th qubit. This represents the S-gate on the a-th qubit. This represents the Z-gate on the a-th qubit. This represents the element in the i-th row and j-th column of matrix X. This represents the element in the i-th row and j-th column of the Z matrix. Represents the i-th phase index. , , , , where n represents the number of qubits.

[0141] It should be noted that the initial parity-check matrix is ​​ultimately processed into... In the form of.

[0142] In this embodiment, through a series of transformation operations, the initial parity check matrix is ​​converted into a graph state parity check matrix, and the subsequent graph state preparation circuit and stable substate restoration circuit design are connected, which greatly reduces the complexity and operational error of stable substate preparation.

[0143] In some embodiments, the step of constructing a pattern fabrication circuit based on the pattern parity matrix includes:

[0144] S41, apply the H gate independently to each qubit.

[0145] Accordingly, this step can be denoted as initialization.

[0146] As an example, apply to all qubits Gate, preparation This state is the basis for the subsequent generation of entangled states. The matrix representation of the gate is as follows Apply to all qubits Gate operations can be represented by tensor products, i.e. ,in It is the number of qubits.

[0147] S42, based on the adjacency matrix in the parity check matrix of the pattern, apply the CZ gate to obtain the pattern preparation circuit.

[0148] Accordingly, this step can be denoted as entanglement generation.

[0149] As an example, based on the adjacency matrix Apply to each edge (i,j) A gate can introduce entanglement between two qubits; specifically, when the control bit is in a certain state... When the target bit is in phase flip, the control bit will be in phase flip. At that time, the target bit remains unchanged. In this invention, based on the adjacency matrix... The element value determines whether to apply to the first element. The and the first Applying one quantum bit Door, if Then it means the first The and the first Entanglement exists between individual qubits, requiring the application of... Door; if This indicates that there is no entanglement between them, and no action is required. Door. The matrix representation of the gate is as follows The entanglement generation operation can be represented as ,in It is the edge set of a graph. This means that an application is performed on the two qubits corresponding to each edge in the graph. This introduces entanglement between these qubits by creating a gate.

[0150] It should be noted that by combining the initialization and entanglement generation steps, the pattern state preparation circuit is obtained. Specifically, the operation sequence is as follows: first, initialization is performed, placing all qubits in... The graph state is then generated, and entanglement is introduced between the qubits. Therefore, the graph state generation circuit can be represented as follows: (The evolution of a quantum state is mathematically described by the action of a unitary matrix; that is, when a quantum state...) Apply first Operation, then apply During the operation, matrix multiplication can be represented as follows: ).

[0151] In this embodiment, the circuit design described above enables efficient fabrication of the desired graph state, providing a foundation for subsequent quantum computing operations. Compared to traditional graph state fabrication methods, the method of this invention reduces the number of quantum gates used by optimizing operational steps and utilizing information from the adjacency matrix, thereby reducing circuit complexity and noise impact, and improving the efficiency and fidelity of graph state fabrication.

[0152] In some embodiments, the conversion operation includes: , The steps for constructing a stable substate restoration circuit based on the conversion operation include: combining the H gate, S gate, and Z gate in the conversion operation in reverse order to generate a stable substate restoration circuit.

[0153] It should be noted that after the pattern is prepared by the pattern preparation circuit, it is necessary to restore the pattern to a stable sub-state in order to perform subsequent measurements or other operations.

[0154] As an example, the process of converting the initial parity-check matrix into a graphical parity-check matrix is ​​documented, including each conversion operation, such as row swapping. Seeking a balance and single-bit gate operations ( To restore a graph state to a stable substate, the inverse operations of these operations need to be performed in reverse order, and only column operations need to be performed. The inverse operation of the gate is obtained, while the inverse of the row operation (row swap, row summation) is achieved through a linear transformation, without the need to add extra gate operations to the physical circuit, finally resulting in a stable substate restoration circuit. The specific mechanism is as follows:

[0155] Seeking a balance The inverse of the XOR operation is itself, achieved through a linear combination of row operation matrices, without the need for quantum gates.

[0156] Line swap Its inverse operation is itself, which is achieved by swapping row indices and does not require quantum gates.

[0157] H-gate: The inverse operation is itself. .

[0158] The S-gate, its inverse operation is transpose-conjugate. .

[0159] Z-gate: The inverse operation is itself. .

[0160] In this embodiment, the circuit design described above enables the efficient fabrication of the required stable substate reduction circuit, providing a foundation for subsequent quantum computing operations.

[0161] In some embodiments, the step of merging the pattern preparation circuit and the stable substate restoration circuit into a total circuit includes:

[0162] S61, construct the inverse circuit of the pattern preparation circuit to obtain the first inverse circuit.

[0163] S62, construct the inverse circuit of the stable substate reduction circuit to obtain the second inverse circuit.

[0164] S63, connect the first inverse circuit and the second inverse circuit in series to obtain the total circuit.

[0165] Specifically, in quantum circuits, combinations of different operations can be represented using matrix multiplication. When attempting to convert a stable substate into a graphical state and then back to a stable substate from the graphical state, these two processes occur sequentially. First, using a circuit... Will Convert to a graphical state; then, use a circuit. The graph state is manipulated to reduce it to a stable substate. These two operations act sequentially on the quantum state, mathematically equivalent to a matrix. and Multiply in sequence, that is And the total circuit It is the whole from The inverse operation of the process from the graph state to the stable substate, i.e. .

[0166] This circuit design allows for accurate reconstruction of a graphical state into a stable substate. Furthermore, because each step of the conversion process is recorded, the accuracy and repeatability of the reconstruction are guaranteed. This is crucial for error correction and measurement operations in quantum computing, as accurate reconstruction of the stable substate is essential for correct subsequent measurements and analyses, leading to reliable computational results.

[0167] In this embodiment, the quantum circuit design of the present invention achieves efficient conversion between stable substates and graph states through a graph state preparation circuit and a stable substate reduction circuit, providing important technical support for the practical application of quantum computing. This circuit design not only reduces the number of quantum gates used and lowers circuit complexity, but also improves the fidelity and efficiency of quantum state conversion, exhibiting significant technical advantages compared to existing technologies.

[0168] In some embodiments, the step of obtaining and preprocessing stable sub-generators includes:

[0169] S11, determine whether the number of stable generators is equal to the number of qubits in the stable state to be prepared.

[0170] S12, if equal to, treat the stable generator as the complete stable generator.

[0171] S13, if not equal to, complete the stable generator to obtain the complete stable generator.

[0172] As an example, when the number of qubits is n, but the number of stable generators is less than n, it can be expanded to n by applying existing generator completion techniques, thereby forming a standard parity check matrix.

[0173] In this embodiment, by performing a padding operation on the stable sub-generators, the preprocessed stable sub-generators can form a standard parity check matrix, ensuring the full rank of the parity check matrix.

[0174] Next, this invention uses a set of generators Taking an example, the process of converting a three-qubit stable substate to a graphical state and the circuit construction of this invention are explained:

[0175] A1, the transformation process from a stable substate to a graphical state:

[0176] The initial form of the check matrix is:

[0177] Transformation to a graphical parity check matrix: through operations Transformation into a graphical parity check matrix: Conversion operation The order is: rowsum(0,1), rowuswap(1,2), H(2), rowsum(2,1), rowsum(2,0), S(0), Z(0), Z(1), Z(2).

[0178] A2, Construction of the overall circuit:

[0179] Pattern preparation circuit Applying H-gates to all qubits to prepare State; based on the adjacency matrix Add CZ(0,1) and CZ(0,2).

[0180] Stable substate reduction circuit :according to The column operations H(2), S(0), Z(0), Z(1), and Z(2) are added with their inverse circuits, i.e. .

[0181] Overall circuit: See Figure 2 .

[0182] Next, this invention uses a set of generators Taking an example, the process of converting a four-qubit stable sub-state to a graphical state and the circuit construction of this invention are explained:

[0183] B1, the transition process from a stable substate to a graphical state:

[0184] The initial form of the check matrix is:

[0185] Transformation to a graphical parity check matrix: through operations Transformation into a graphical parity check matrix: Conversion operation The order is: rowsum(0,1), rowuswap(1,2), rowusum(1,3), H(2), H(3), rowsum(3,1), rowsum(2,1), rowsum(2,0), S(0), Z(0), S(1), Z(1), Z(3).

[0186] B2, Construction of the overall circuit:

[0187] Pattern preparation circuit Applying H-gates to all qubits to prepare State; based on the adjacency matrix Add CZ(0,1), CZ(0,2), and CZ(1,3).

[0188] Stable substate reduction circuit :according to The column operations H(2), H(3), S(0), Z(0), S(1), Z(1), Z(3) are added with their inverse circuits, i.e. .

[0189] Overall circuit: See Figure 3 .

[0190] In addition, the present invention also provides a system for preparing stable substates based on graph states, such as Figure 4 As shown, the graph-based stable substate preparation system includes: a preprocessing module 10, an initialization module 20, a transformation module 30, a graph preparation circuit construction module 40, a stable substate restoration circuit construction module 50, a total circuit construction module 60, and a stable substate preparation module 70.

[0191] The preprocessing module 10 is used to acquire and preprocess stable sub-generators to obtain complete stable sub-generators.

[0192] The initialization module 20 is used to generate an initial verification matrix based on the complete stable subgenerator.

[0193] The transformation module 30 is used to transform the initial parity check matrix into a graphical parity check matrix and record the transformation operations performed during the transformation process.

[0194] The pattern preparation circuit construction module 40 is used to construct a pattern preparation circuit based on the check matrix of the pattern.

[0195] The stable substate restoration circuit construction module 50 is used to construct a stable substate restoration circuit according to the conversion operation.

[0196] The total circuit construction module 60 is used to combine the pattern preparation circuit and the stable sub-state restoration circuit into a total circuit.

[0197] The stable substate preparation module 70 is used to obtain an initial quantum state and make the initial quantum state execute the overall circuit to obtain a stable substate.

[0198] The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. The parity-check matrix of the graphical state is characterized by the X matrix being an identity matrix, and all qubits in the initialized quantum state are in a state where... state.

[0199] For other specific embodiments of the graph-based stable substate preparation system of the present invention, please refer to the specific embodiments of the graph-based stable substate preparation method of the above embodiments of the present invention.

[0200] The graph-based stable substate preparation system of this invention reduces the complexity of circuit design by using graph states as an intermediary, thereby reducing computational complexity and improving the efficiency of quantum information processing, making this application adaptable to large-scale quantum systems. Furthermore, by establishing a precise mapping relationship between stable substates and graph states, approximation errors are avoided, achieving 100% theoretical fidelity. Simultaneously, preprocessing the stable substate generators improves the accuracy and reliability of stable substate preparation.

[0201] The following detailed explanation uses a computer terminal as an example. Figure 5 This is a hardware structure block diagram of a computer terminal for a method of preparing stable substates based on graph states, provided in an embodiment of the present invention. Figure 5 As shown, a computer terminal may include one or more ( Figure 5 Only one is shown in the diagram. A processor 501 (processor 501 may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 502 for storing data are also shown. Optionally, the computer terminal may further include a transmission device 503 for communication functions and an input / output device 504. Those skilled in the art will understand that... Figure 5 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown.

[0202] The memory 502 can be used to store software programs and modules for application software, such as the program instructions / modules corresponding to the graph-based stable substate preparation method in this embodiment. The processor 501 executes various functional applications and data processing by running the software programs and modules stored in the memory 502, thereby implementing the above-described method. The memory 502 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 502 may further include memory remotely located relative to the processor 501, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0203] The transmission device 503 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 503 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 503 may be a Radio Frequency (RF) module, used for wireless communication with the Internet. Embodiments of this application also provide a computer-readable storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments, wherein the computer includes an electronic device.

[0204] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer may include an electronic device.

[0205] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0206] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0207] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0208] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0209] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0210] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0211] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0212] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules according to the embodiments of this application. This application can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0213] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0214] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A method for preparing stable substates based on graph states, characterized in that, The preparation method includes: Obtain and preprocess stable sub-generators to obtain complete stable sub-generators; Based on the complete stable sub-generator, generate the initial verification matrix; The initial parity check matrix is ​​converted into a graphical parity check matrix, and the conversion operations performed during the conversion process are recorded. Based on the verification matrix of the graph, construct the graph preparation circuit; Based on the aforementioned conversion operation, a stable sub-state restoration circuit is constructed; The pattern preparation circuit and the stable sub-state restoration circuit are combined into a total circuit; An initial quantum state is obtained, and the initial quantum state is made to execute the overall circuit to obtain a stable substate; The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. The parity-check matrix of the graphical state is characterized by the X matrix being an identity matrix, and all qubits in the initialized quantum state are in a state where... state.

2. The method for preparing stable substates based on graph states according to claim 1, characterized in that, The step of converting the initial parity-check matrix into a graphical parity-check matrix includes: Convert the X matrix into an upper triangular matrix or a lower triangular matrix, and convert the upper triangular matrix or the lower triangular matrix into the identity matrix; Set the diagonal of the Z matrix to zero; Set all phase indices to zero.

3. The method for preparing stable substates based on graph states according to claim 2, characterized in that, The step of converting the X matrix into an upper triangular matrix includes: Traverse the X matrix row by row and determine Is it equal to 1? like and Then through ,make ; like and Then through ,make 1, and return the judgment. The steps to determine if it equals 1; like And none Then execute The door is opened, and the judgment is returned. The steps to determine if it equals 1; The step of converting the upper triangular matrix into the identity matrix includes: Traverse the upper triangular matrix row by row and determine... Is it equal to 1? like Then through ,Will Set to 0; The step of setting the diagonal of the Z matrix to zero includes: Traverse the Z matrix row by row and determine Is it equal to 1? like Then execute The door will Set to 0; The step of setting all phase indices to zero includes: Iterate through the phase indices row by row to determine... Is it 1? like Then execute The door will Set to 0.

4. The method for preparing stable substates based on graph states according to claim 3, characterized in that, The include: The phase index of the j-th row is determined using the following formula: The first XOR to the first Line up; The include: The first commutation matrix Line and number OK; The execution The steps for opening a door include: The phase index of the i-th row is updated sequentially using the following formula: Swap the a-th column of matrix Z with the a-th column of matrix X; The execution The steps for opening a door include: The phase index of the i-th row is updated sequentially using the following formula: The matrix elements are updated sequentially using the following formula. : The execution The steps for opening a door include: The phase index of the i-th row is updated sequentially using the following formula: in, This represents the H gate on the a-th qubit. This represents the S-gate on the a-th qubit. This represents the Z-gate on the a-th qubit. This represents the element in the i-th row and j-th column of matrix X. This represents the element in the i-th row and j-th column of the Z matrix. Represents the i-th phase index. , , , , where n represents the number of qubits.

5. The method for preparing stable substates based on graph states according to claim 1, characterized in that, The step of constructing the pattern preparation circuit based on the pattern verification matrix includes: Apply an H-gate independently to each qubit; Based on the adjacency matrix in the parity check matrix of the pattern, a CZ gate is applied to obtain the pattern preparation circuit.

6. The method for preparing stable substates based on graph states according to claim 3, characterized in that, The conversion operation includes: , H-gate, S-gate, and Z-gate; The step of constructing a stable sub-state restoration circuit based on the conversion operation includes: The H gate, S gate, and Z gate in the conversion operation are combined in reverse order to generate the stable substate restoration circuit.

7. The method for preparing stable substates based on graph states according to claim 1, characterized in that, The step of merging the pattern preparation circuit and the stable sub-state restoration circuit into a total circuit includes: Construct the inverse circuit of the pattern preparation circuit to obtain the first inverse circuit; Construct the inverse circuit of the stable substate restoration circuit to obtain the second inverse circuit; The first inverse circuit and the second inverse circuit are connected in series in sequence to obtain the total circuit.

8. The method for preparing stable substates based on graph states according to claim 1, characterized in that, The steps for obtaining and preprocessing stable sub-generators include: Determine whether the number of stable generators is equal to the number of qubits in the stable state to be prepared; If they are equal, the stable sub-generator is taken as the complete stable sub-generator; If they are not equal, the stable sub-generators are padded to obtain the complete stable sub-generators.

9. A system for preparing stable substates based on graph states, characterized in that, The system includes: The preprocessing module is used to acquire and preprocess stable sub-generators to obtain complete stable sub-generators; An initialization module is used to generate an initial verification matrix based on the complete stable sub-generators; The transformation module is used to convert the initial parity check matrix into a graphical parity check matrix and record the transformation operations performed during the transformation process. The pattern preparation circuit construction module is used to construct a pattern preparation circuit based on the check matrix of the pattern. A stable substate restoration circuit construction module is used to construct a stable substate restoration circuit based on the conversion operation; The overall circuit construction module is used to combine the pattern preparation circuit and the stable sub-state restoration circuit into an overall circuit; A stable substate preparation module is used to obtain an initial quantum state and make the initial quantum state execute the overall circuit to obtain a stable substate. The initial parity-check matrix consists of a Z matrix, an X matrix, and a phase index. The parity-check matrix of the graphical state is characterized by the X matrix being an identity matrix, and all qubits in the initialized quantum state are in a state where... state.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the computer program is executed by the processor, it implements the method for preparing a graph-based stable substate according to any one of claims 1-8.

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